[net-next-2.6.git] / include / linux / dmar.h

/*
 * Copyright (c) 2006, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
 * Place - Suite 330, Boston, MA 02111-1307 USA.
 *
 * Copyright (C) Ashok Raj <ashok.raj@intel.com>
 * Copyright (C) Shaohua Li <shaohua.li@intel.com>
 */

#ifndef __DMAR_H__
#define __DMAR_H__

#include <linux/acpi.h>
#include <linux/types.h>
#include <linux/msi.h>
#include <linux/irqreturn.h>

struct intel_iommu;
#if defined(CONFIG_DMAR) || defined(CONFIG_INTR_REMAP)
struct dmar_drhd_unit {
	struct list_head list;		/* list of drhd units	*/
	struct  acpi_dmar_header *hdr;	/* ACPI header		*/
	u64	reg_base_addr;		/* register base address*/
	struct	pci_dev **devices; 	/* target device array	*/
	int	devices_cnt;		/* target device count	*/
	u16	segment;		/* PCI domain		*/
	u8	ignored:1; 		/* ignore drhd		*/
	u8	include_all:1;
	struct intel_iommu *iommu;
};

extern struct list_head dmar_drhd_units;

#define for_each_drhd_unit(drhd) \
	list_for_each_entry(drhd, &dmar_drhd_units, list)

#define for_each_active_iommu(i, drhd)					\
	list_for_each_entry(drhd, &dmar_drhd_units, list)		\
		if (i=drhd->iommu, drhd->ignored) {} else

#define for_each_iommu(i, drhd)						\
	list_for_each_entry(drhd, &dmar_drhd_units, list)		\
		if (i=drhd->iommu, 0) {} else 

extern int dmar_table_init(void);
extern int dmar_dev_scope_init(void);

/* Intel IOMMU detection */
extern void detect_intel_iommu(void);
extern int enable_drhd_fault_handling(void);

extern int parse_ioapics_under_ir(void);
extern int alloc_iommu(struct dmar_drhd_unit *);
#else
static inline void detect_intel_iommu(void)
{
	return;
}

static inline int dmar_table_init(void)
{
	return -ENODEV;
}
static inline int enable_drhd_fault_handling(void)
{
	return -1;
}
#endif /* !CONFIG_DMAR && !CONFIG_INTR_REMAP */

struct irte {
	union {
		struct {
			__u64	present 	: 1,
				fpd		: 1,
				dst_mode	: 1,
				redir_hint	: 1,
				trigger_mode	: 1,
				dlvry_mode	: 3,
				avail		: 4,
				__reserved_1	: 4,
				vector		: 8,
				__reserved_2	: 8,
				dest_id		: 32;
		};
		__u64 low;
	};

	union {
		struct {
			__u64	sid		: 16,
				sq		: 2,
				svt		: 2,
				__reserved_3	: 44;
		};
		__u64 high;
	};
};
#ifdef CONFIG_INTR_REMAP
extern int intr_remapping_enabled;
extern int intr_remapping_supported(void);
extern int enable_intr_remapping(int);
extern void disable_intr_remapping(void);
extern int reenable_intr_remapping(int);

extern int get_irte(int irq, struct irte *entry);
extern int modify_irte(int irq, struct irte *irte_modified);
extern int alloc_irte(struct intel_iommu *iommu, int irq, u16 count);
extern int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index,
   			u16 sub_handle);
extern int map_irq_to_irte_handle(int irq, u16 *sub_handle);
extern int free_irte(int irq);

extern int irq_remapped(int irq);
extern struct intel_iommu *map_dev_to_ir(struct pci_dev *dev);
extern struct intel_iommu *map_ioapic_to_ir(int apic);
extern struct intel_iommu *map_hpet_to_ir(u8 id);
extern int set_ioapic_sid(struct irte *irte, int apic);
extern int set_hpet_sid(struct irte *irte, u8 id);
extern int set_msi_sid(struct irte *irte, struct pci_dev *dev);
#else
static inline int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
{
	return -1;
}
static inline int modify_irte(int irq, struct irte *irte_modified)
{
	return -1;
}
static inline int free_irte(int irq)
{
	return -1;
}
static inline int map_irq_to_irte_handle(int irq, u16 *sub_handle)
{
	return -1;
}
static inline int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index,
			       u16 sub_handle)
{
	return -1;
}
static inline struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
{
	return NULL;
}
static inline struct intel_iommu *map_ioapic_to_ir(int apic)
{
	return NULL;
}
static inline struct intel_iommu *map_hpet_to_ir(unsigned int hpet_id)
{
	return NULL;
}
static inline int set_ioapic_sid(struct irte *irte, int apic)
{
	return 0;
}
static inline int set_hpet_sid(struct irte *irte, u8 id)
{
	return -1;
}
static inline int set_msi_sid(struct irte *irte, struct pci_dev *dev)
{
	return 0;
}

#define irq_remapped(irq)		(0)
#define enable_intr_remapping(mode)	(-1)
#define disable_intr_remapping()	(0)
#define reenable_intr_remapping(mode)	(0)
#define intr_remapping_enabled		(0)
#endif

/* Can't use the common MSI interrupt functions
 * since DMAR is not a pci device
 */
struct irq_data;
extern void dmar_msi_unmask(struct irq_data *data);
extern void dmar_msi_mask(struct irq_data *data);
extern void dmar_msi_read(int irq, struct msi_msg *msg);
extern void dmar_msi_write(int irq, struct msi_msg *msg);
extern int dmar_set_interrupt(struct intel_iommu *iommu);
extern irqreturn_t dmar_fault(int irq, void *dev_id);
extern int arch_setup_dmar_msi(unsigned int irq);

#ifdef CONFIG_DMAR
extern int iommu_detected, no_iommu;
extern struct list_head dmar_rmrr_units;
struct dmar_rmrr_unit {
	struct list_head list;		/* list of rmrr units	*/
	struct acpi_dmar_header *hdr;	/* ACPI header		*/
	u64	base_address;		/* reserved base address*/
	u64	end_address;		/* reserved end address */
	struct pci_dev **devices;	/* target devices */
	int	devices_cnt;		/* target device count */
};

#define for_each_rmrr_units(rmrr) \
	list_for_each_entry(rmrr, &dmar_rmrr_units, list)

struct dmar_atsr_unit {
	struct list_head list;		/* list of ATSR units */
	struct acpi_dmar_header *hdr;	/* ACPI header */
	struct pci_dev **devices;	/* target devices */
	int devices_cnt;		/* target device count */
	u8 include_all:1;		/* include all ports */
};

extern int intel_iommu_init(void);
#else /* !CONFIG_DMAR: */
static inline int intel_iommu_init(void) { return -ENODEV; }
#endif /* CONFIG_DMAR */

#endif /* __DMAR_H__ */
Commit	Line	Data
10e5247f KA	1	/*
	2	* Copyright (c) 2006, Intel Corporation.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*
	13	* You should have received a copy of the GNU General Public License along with
	14	* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
	15	* Place - Suite 330, Boston, MA 02111-1307 USA.
	16	*
	17	* Copyright (C) Ashok Raj <ashok.raj@intel.com>
	18	* Copyright (C) Shaohua Li <shaohua.li@intel.com>
	19	*/
	20
	21	#ifndef __DMAR_H__
	22	#define __DMAR_H__
	23
	24	#include <linux/acpi.h>
	25	#include <linux/types.h>
ba395927	26	#include <linux/msi.h>
1531a6a6	27	#include <linux/irqreturn.h>
10e5247f	28
ba395927	29	struct intel_iommu;
29b61be6	30	#if defined(CONFIG_DMAR) \|\| defined(CONFIG_INTR_REMAP)
2ae21010 SS	31	struct dmar_drhd_unit {
	32	struct list_head list; /* list of drhd units */
	33	struct acpi_dmar_header hdr; / ACPI header */
	34	u64 reg_base_addr; /* register base address*/
	35	struct pci_dev *devices; / target device array */
	36	int devices_cnt; /* target device count */
276dbf99	37	u16 segment; /* PCI domain */
2ae21010 SS	38	u8 ignored:1; /* ignore drhd */
	39	u8 include_all:1;
	40	struct intel_iommu *iommu;
	41	};
	42
	43	extern struct list_head dmar_drhd_units;
	44
	45	#define for_each_drhd_unit(drhd) \
	46	list_for_each_entry(drhd, &dmar_drhd_units, list)
	47
8f912ba4 DW	48	#define for_each_active_iommu(i, drhd) \
	49	list_for_each_entry(drhd, &dmar_drhd_units, list) \
	50	if (i=drhd->iommu, drhd->ignored) {} else
	51
	52	#define for_each_iommu(i, drhd) \
	53	list_for_each_entry(drhd, &dmar_drhd_units, list) \
	54	if (i=drhd->iommu, 0) {} else
	55
2ae21010	56	extern int dmar_table_init(void);
2ae21010 SS	57	extern int dmar_dev_scope_init(void);
	58
	59	/* Intel IOMMU detection */
	60	extern void detect_intel_iommu(void);
9d783ba0	61	extern int enable_drhd_fault_handling(void);
2ae21010	62
2ae21010 SS	63	extern int parse_ioapics_under_ir(void);
	64	extern int alloc_iommu(struct dmar_drhd_unit *);
	65	#else
	66	static inline void detect_intel_iommu(void)
	67	{
	68	return;
	69	}
	70
	71	static inline int dmar_table_init(void)
	72	{
	73	return -ENODEV;
	74	}
29b61be6 SS	75	static inline int enable_drhd_fault_handling(void)
	76	{
	77	return -1;
	78	}
2ae21010 SS	79	#endif /* !CONFIG_DMAR && !CONFIG_INTR_REMAP */
2ae21010 SS	80
2ae21010 SS	81	struct irte {
	82	union {
	83	struct {
	84	__u64 present : 1,
	85	fpd : 1,
	86	dst_mode : 1,
	87	redir_hint : 1,
	88	trigger_mode : 1,
	89	dlvry_mode : 3,
	90	avail : 4,
	91	__reserved_1 : 4,
	92	vector : 8,
	93	__reserved_2 : 8,
	94	dest_id : 32;
	95	};
	96	__u64 low;
	97	};
	98
	99	union {
	100	struct {
	101	__u64 sid : 16,
	102	sq : 2,
	103	svt : 2,
	104	__reserved_3 : 44;
	105	};
	106	__u64 high;
	107	};
	108	};
29b61be6 SS	109	#ifdef CONFIG_INTR_REMAP
29b61be6 SS	110	extern int intr_remapping_enabled;
93758238	111	extern int intr_remapping_supported(void);
29b61be6	112	extern int enable_intr_remapping(int);
b24696bc FY	113	extern void disable_intr_remapping(void);
b24696bc FY	114	extern int reenable_intr_remapping(int);
29b61be6	115
b6fcb33a SS	116	extern int get_irte(int irq, struct irte *entry);
	117	extern int modify_irte(int irq, struct irte *irte_modified);
	118	extern int alloc_irte(struct intel_iommu *iommu, int irq, u16 count);
	119	extern int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index,
	120	u16 sub_handle);
	121	extern int map_irq_to_irte_handle(int irq, u16 *sub_handle);
b6fcb33a SS	122	extern int free_irte(int irq);
	123
	124	extern int irq_remapped(int irq);
75c46fa6	125	extern struct intel_iommu map_dev_to_ir(struct pci_dev dev);
89027d35	126	extern struct intel_iommu *map_ioapic_to_ir(int apic);
20f3097b	127	extern struct intel_iommu *map_hpet_to_ir(u8 id);
f007e99c	128	extern int set_ioapic_sid(struct irte *irte, int apic);
20f3097b	129	extern int set_hpet_sid(struct irte *irte, u8 id);
f007e99c	130	extern int set_msi_sid(struct irte irte, struct pci_dev dev);
2ae21010	131	#else
29b61be6 SS	132	static inline int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
	133	{
	134	return -1;
	135	}
	136	static inline int modify_irte(int irq, struct irte *irte_modified)
	137	{
	138	return -1;
	139	}
	140	static inline int free_irte(int irq)
	141	{
	142	return -1;
	143	}
	144	static inline int map_irq_to_irte_handle(int irq, u16 *sub_handle)
	145	{
	146	return -1;
	147	}
	148	static inline int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index,
	149	u16 sub_handle)
	150	{
	151	return -1;
	152	}
	153	static inline struct intel_iommu map_dev_to_ir(struct pci_dev dev)
	154	{
	155	return NULL;
	156	}
	157	static inline struct intel_iommu *map_ioapic_to_ir(int apic)
	158	{
	159	return NULL;
	160	}
20f3097b SS	161	static inline struct intel_iommu *map_hpet_to_ir(unsigned int hpet_id)
	162	{
	163	return NULL;
	164	}
f007e99c WH	165	static inline int set_ioapic_sid(struct irte *irte, int apic)
	166	{
	167	return 0;
	168	}
20f3097b SS	169	static inline int set_hpet_sid(struct irte *irte, u8 id)
	170	{
	171	return -1;
	172	}
f007e99c WH	173	static inline int set_msi_sid(struct irte irte, struct pci_dev dev)
	174	{
	175	return 0;
	176	}
	177
b6fcb33a	178	#define irq_remapped(irq) (0)
2ae21010	179	#define enable_intr_remapping(mode) (-1)
fc1edaf9 SS	180	#define disable_intr_remapping() (0)
fc1edaf9 SS	181	#define reenable_intr_remapping(mode) (0)
2ae21010 SS	182	#define intr_remapping_enabled (0)
	183	#endif
	184
3460a6d9 KA	185	/* Can't use the common MSI interrupt functions
	186	* since DMAR is not a pci device
	187	*/
5c2837fb TG	188	struct irq_data;
	189	extern void dmar_msi_unmask(struct irq_data *data);
	190	extern void dmar_msi_mask(struct irq_data *data);
3460a6d9 KA	191	extern void dmar_msi_read(int irq, struct msi_msg *msg);
	192	extern void dmar_msi_write(int irq, struct msi_msg *msg);
	193	extern int dmar_set_interrupt(struct intel_iommu *iommu);
1531a6a6	194	extern irqreturn_t dmar_fault(int irq, void *dev_id);
3460a6d9 KA	195	extern int arch_setup_dmar_msi(unsigned int irq);
3460a6d9 KA	196
9d783ba0	197	#ifdef CONFIG_DMAR
2ae21010	198	extern int iommu_detected, no_iommu;
10e5247f	199	extern struct list_head dmar_rmrr_units;
10e5247f KA	200	struct dmar_rmrr_unit {
10e5247f KA	201	struct list_head list; /* list of rmrr units */
1886e8a9	202	struct acpi_dmar_header hdr; / ACPI header */
10e5247f KA	203	u64 base_address; /* reserved base address*/
	204	u64 end_address; /* reserved end address */
	205	struct pci_dev *devices; / target devices */
	206	int devices_cnt; /* target device count */
	207	};
	208
ba395927 KA	209	#define for_each_rmrr_units(rmrr) \
ba395927 KA	210	list_for_each_entry(rmrr, &dmar_rmrr_units, list)
aa5d2b51 YZ	211
	212	struct dmar_atsr_unit {
	213	struct list_head list; /* list of ATSR units */
	214	struct acpi_dmar_header hdr; / ACPI header */
	215	struct pci_dev *devices; / target devices */
	216	int devices_cnt; /* target device count */
	217	u8 include_all:1; /* include all ports */
	218	};
	219
2ae21010	220	extern int intel_iommu_init(void);
9d5ce73a FT	221	#else /* !CONFIG_DMAR: */
	222	static inline int intel_iommu_init(void) { return -ENODEV; }
	223	#endif /* CONFIG_DMAR */
	224
10e5247f	225	#endif /* __DMAR_H__ */