[net-next-2.6.git] / drivers / watchdog / pnx4008_wdt.c

/*
 * drivers/char/watchdog/pnx4008_wdt.c
 *
 * Watchdog driver for PNX4008 board
 *
 * Authors: Dmitry Chigirev <source@mvista.com>,
 * 	    Vitaly Wool <vitalywool@gmail.com>
 * Based on sa1100 driver,
 * Copyright (C) 2000 Oleg Drokin <green@crimea.edu>
 *
 * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
 * the terms of the GNU General Public License version 2. This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 */

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/miscdevice.h>
#include <linux/watchdog.h>
#include <linux/init.h>
#include <linux/bitops.h>
#include <linux/ioport.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/spinlock.h>
#include <linux/uaccess.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <mach/hardware.h>

#define MODULE_NAME "PNX4008-WDT: "

/* WatchDog Timer - Chapter 23 Page 207 */

#define DEFAULT_HEARTBEAT 19
#define MAX_HEARTBEAT     60

/* Watchdog timer register set definition */
#define WDTIM_INT(p)     ((p) + 0x0)
#define WDTIM_CTRL(p)    ((p) + 0x4)
#define WDTIM_COUNTER(p) ((p) + 0x8)
#define WDTIM_MCTRL(p)   ((p) + 0xC)
#define WDTIM_MATCH0(p)  ((p) + 0x10)
#define WDTIM_EMR(p)     ((p) + 0x14)
#define WDTIM_PULSE(p)   ((p) + 0x18)
#define WDTIM_RES(p)     ((p) + 0x1C)

/* WDTIM_INT bit definitions */
#define MATCH_INT      1

/* WDTIM_CTRL bit definitions */
#define COUNT_ENAB     1
#define RESET_COUNT    (1 << 1)
#define DEBUG_EN       (1 << 2)

/* WDTIM_MCTRL bit definitions */
#define MR0_INT        1
#undef  RESET_COUNT0
#define RESET_COUNT0   (1 << 2)
#define STOP_COUNT0    (1 << 2)
#define M_RES1         (1 << 3)
#define M_RES2         (1 << 4)
#define RESFRC1        (1 << 5)
#define RESFRC2        (1 << 6)

/* WDTIM_EMR bit definitions */
#define EXT_MATCH0      1
#define MATCH_OUTPUT_HIGH (2 << 4)	/*a MATCH_CTRL setting */

/* WDTIM_RES bit definitions */
#define WDOG_RESET      1	/* read only */

#define WDOG_COUNTER_RATE 13000000	/*the counter clock is 13 MHz fixed */

static int nowayout = WATCHDOG_NOWAYOUT;
static int heartbeat = DEFAULT_HEARTBEAT;

static DEFINE_SPINLOCK(io_lock);
static unsigned long wdt_status;
#define WDT_IN_USE        0
#define WDT_OK_TO_CLOSE   1
#define WDT_REGION_INITED 2
#define WDT_DEVICE_INITED 3

static unsigned long boot_status;

static struct resource	*wdt_mem;
static void __iomem	*wdt_base;
struct clk		*wdt_clk;

static void wdt_enable(void)
{
	spin_lock(&io_lock);

	/* stop counter, initiate counter reset */
	__raw_writel(RESET_COUNT, WDTIM_CTRL(wdt_base));
	/*wait for reset to complete. 100% guarantee event */
	while (__raw_readl(WDTIM_COUNTER(wdt_base)))
		cpu_relax();
	/* internal and external reset, stop after that */
	__raw_writel(M_RES2 | STOP_COUNT0 | RESET_COUNT0,
		WDTIM_MCTRL(wdt_base));
	/* configure match output */
	__raw_writel(MATCH_OUTPUT_HIGH, WDTIM_EMR(wdt_base));
	/* clear interrupt, just in case */
	__raw_writel(MATCH_INT, WDTIM_INT(wdt_base));
	/* the longest pulse period 65541/(13*10^6) seconds ~ 5 ms. */
	__raw_writel(0xFFFF, WDTIM_PULSE(wdt_base));
	__raw_writel(heartbeat * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base));
	/*enable counter, stop when debugger active */
	__raw_writel(COUNT_ENAB | DEBUG_EN, WDTIM_CTRL(wdt_base));

	spin_unlock(&io_lock);
}

static void wdt_disable(void)
{
	spin_lock(&io_lock);

	__raw_writel(0, WDTIM_CTRL(wdt_base));	/*stop counter */

	spin_unlock(&io_lock);
}

static int pnx4008_wdt_open(struct inode *inode, struct file *file)
{
	int ret;

	if (test_and_set_bit(WDT_IN_USE, &wdt_status))
		return -EBUSY;

	clear_bit(WDT_OK_TO_CLOSE, &wdt_status);

	ret = clk_enable(wdt_clk);
	if (ret) {
		clear_bit(WDT_IN_USE, &wdt_status);
		return ret;
	}

	wdt_enable();

	return nonseekable_open(inode, file);
}

static ssize_t pnx4008_wdt_write(struct file *file, const char *data,
					size_t len, loff_t *ppos)
{
	if (len) {
		if (!nowayout) {
			size_t i;

			clear_bit(WDT_OK_TO_CLOSE, &wdt_status);

			for (i = 0; i != len; i++) {
				char c;

				if (get_user(c, data + i))
					return -EFAULT;
				if (c == 'V')
					set_bit(WDT_OK_TO_CLOSE, &wdt_status);
			}
		}
		wdt_enable();
	}

	return len;
}

static const struct watchdog_info ident = {
	.options = WDIOF_CARDRESET | WDIOF_MAGICCLOSE |
	    WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
	.identity = "PNX4008 Watchdog",
};

static long pnx4008_wdt_ioctl(struct file *file, unsigned int cmd,
				unsigned long arg)
{
	int ret = -ENOTTY;
	int time;

	switch (cmd) {
	case WDIOC_GETSUPPORT:
		ret = copy_to_user((struct watchdog_info *)arg, &ident,
				   sizeof(ident)) ? -EFAULT : 0;
		break;

	case WDIOC_GETSTATUS:
		ret = put_user(0, (int *)arg);
		break;

	case WDIOC_GETBOOTSTATUS:
		ret = put_user(boot_status, (int *)arg);
		break;

	case WDIOC_KEEPALIVE:
		wdt_enable();
		ret = 0;
		break;

	case WDIOC_SETTIMEOUT:
		ret = get_user(time, (int *)arg);
		if (ret)
			break;

		if (time <= 0 || time > MAX_HEARTBEAT) {
			ret = -EINVAL;
			break;
		}

		heartbeat = time;
		wdt_enable();
		/* Fall through */

	case WDIOC_GETTIMEOUT:
		ret = put_user(heartbeat, (int *)arg);
		break;
	}
	return ret;
}

static int pnx4008_wdt_release(struct inode *inode, struct file *file)
{
	if (!test_bit(WDT_OK_TO_CLOSE, &wdt_status))
		printk(KERN_WARNING "WATCHDOG: Device closed unexpectdly\n");

	wdt_disable();
	clk_disable(wdt_clk);
	clear_bit(WDT_IN_USE, &wdt_status);
	clear_bit(WDT_OK_TO_CLOSE, &wdt_status);

	return 0;
}

static const struct file_operations pnx4008_wdt_fops = {
	.owner = THIS_MODULE,
	.llseek = no_llseek,
	.write = pnx4008_wdt_write,
	.unlocked_ioctl = pnx4008_wdt_ioctl,
	.open = pnx4008_wdt_open,
	.release = pnx4008_wdt_release,
};

static struct miscdevice pnx4008_wdt_miscdev = {
	.minor = WATCHDOG_MINOR,
	.name = "watchdog",
	.fops = &pnx4008_wdt_fops,
};

static int __devinit pnx4008_wdt_probe(struct platform_device *pdev)
{
	int ret = 0, size;
	struct resource *res;

	if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT)
		heartbeat = DEFAULT_HEARTBEAT;

	printk(KERN_INFO MODULE_NAME
		"PNX4008 Watchdog Timer: heartbeat %d sec\n", heartbeat);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (res == NULL) {
		printk(KERN_INFO MODULE_NAME
			"failed to get memory region resouce\n");
		return -ENOENT;
	}

	size = resource_size(res);
	wdt_mem = request_mem_region(res->start, size, pdev->name);

	if (wdt_mem == NULL) {
		printk(KERN_INFO MODULE_NAME "failed to get memory region\n");
		return -ENOENT;
	}
	wdt_base = (void __iomem *)IO_ADDRESS(res->start);

	wdt_clk = clk_get(&pdev->dev, NULL);
	if (IS_ERR(wdt_clk)) {
		ret = PTR_ERR(wdt_clk);
		release_resource(wdt_mem);
		kfree(wdt_mem);
		goto out;
	}

	ret = clk_enable(wdt_clk);
	if (ret) {
		release_resource(wdt_mem);
		kfree(wdt_mem);
		goto out;
	}

	ret = misc_register(&pnx4008_wdt_miscdev);
	if (ret < 0) {
		printk(KERN_ERR MODULE_NAME "cannot register misc device\n");
		release_resource(wdt_mem);
		kfree(wdt_mem);
		clk_disable(wdt_clk);
		clk_put(wdt_clk);
	} else {
		boot_status = (__raw_readl(WDTIM_RES(wdt_base)) & WDOG_RESET) ?
		    WDIOF_CARDRESET : 0;
		wdt_disable();		/*disable for now */
		clk_disable(wdt_clk);
		set_bit(WDT_DEVICE_INITED, &wdt_status);
	}

out:
	return ret;
}

static int __devexit pnx4008_wdt_remove(struct platform_device *pdev)
{
	misc_deregister(&pnx4008_wdt_miscdev);

	clk_disable(wdt_clk);
	clk_put(wdt_clk);

	if (wdt_mem) {
		release_resource(wdt_mem);
		kfree(wdt_mem);
		wdt_mem = NULL;
	}
	return 0;
}

static struct platform_driver platform_wdt_driver = {
	.driver = {
		.name = "pnx4008-watchdog",
		.owner	= THIS_MODULE,
	},
	.probe = pnx4008_wdt_probe,
	.remove = __devexit_p(pnx4008_wdt_remove),
};

static int __init pnx4008_wdt_init(void)
{
	return platform_driver_register(&platform_wdt_driver);
}

static void __exit pnx4008_wdt_exit(void)
{
	platform_driver_unregister(&platform_wdt_driver);
}

module_init(pnx4008_wdt_init);
module_exit(pnx4008_wdt_exit);

MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
MODULE_DESCRIPTION("PNX4008 Watchdog Driver");

module_param(heartbeat, int, 0);
MODULE_PARM_DESC(heartbeat,
		 "Watchdog heartbeat period in seconds from 1 to "
		 __MODULE_STRING(MAX_HEARTBEAT) ", default "
		 __MODULE_STRING(DEFAULT_HEARTBEAT));

module_param(nowayout, int, 0);
MODULE_PARM_DESC(nowayout,
		 "Set to 1 to keep watchdog running after device release");

MODULE_LICENSE("GPL");
MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
MODULE_ALIAS("platform:pnx4008-watchdog");
Commit	Line	Data
9325fa36 VW	1	/*
	2	* drivers/char/watchdog/pnx4008_wdt.c
	3	*
	4	* Watchdog driver for PNX4008 board
	5	*
	6	* Authors: Dmitry Chigirev <source@mvista.com>,
	7	* Vitaly Wool <vitalywool@gmail.com>
	8	* Based on sa1100 driver,
	9	* Copyright (C) 2000 Oleg Drokin <green@crimea.edu>
	10	*
	11	* 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
	12	* the terms of the GNU General Public License version 2. This program
	13	* is licensed "as is" without any warranty of any kind, whether express
	14	* or implied.
	15	*/
	16
9325fa36 VW	17	#include <linux/module.h>
	18	#include <linux/moduleparam.h>
	19	#include <linux/types.h>
	20	#include <linux/kernel.h>
	21	#include <linux/fs.h>
	22	#include <linux/miscdevice.h>
	23	#include <linux/watchdog.h>
	24	#include <linux/init.h>
	25	#include <linux/bitops.h>
	26	#include <linux/ioport.h>
	27	#include <linux/device.h>
	28	#include <linux/platform_device.h>
	29	#include <linux/clk.h>
99d2853a	30	#include <linux/spinlock.h>
84ca995c AC	31	#include <linux/uaccess.h>
84ca995c AC	32	#include <linux/io.h>
5a0e3ad6	33	#include <linux/slab.h>
a09e64fb	34	#include <mach/hardware.h>
9325fa36 VW	35
	36	#define MODULE_NAME "PNX4008-WDT: "
	37
	38	/* WatchDog Timer - Chapter 23 Page 207 */
	39
	40	#define DEFAULT_HEARTBEAT 19
	41	#define MAX_HEARTBEAT 60
	42
	43	/* Watchdog timer register set definition */
	44	#define WDTIM_INT(p) ((p) + 0x0)
	45	#define WDTIM_CTRL(p) ((p) + 0x4)
	46	#define WDTIM_COUNTER(p) ((p) + 0x8)
	47	#define WDTIM_MCTRL(p) ((p) + 0xC)
	48	#define WDTIM_MATCH0(p) ((p) + 0x10)
	49	#define WDTIM_EMR(p) ((p) + 0x14)
	50	#define WDTIM_PULSE(p) ((p) + 0x18)
	51	#define WDTIM_RES(p) ((p) + 0x1C)
	52
	53	/* WDTIM_INT bit definitions */
	54	#define MATCH_INT 1
	55
	56	/* WDTIM_CTRL bit definitions */
	57	#define COUNT_ENAB 1
143a2e54 WVS	58	#define RESET_COUNT (1 << 1)
143a2e54 WVS	59	#define DEBUG_EN (1 << 2)
9325fa36 VW	60
	61	/* WDTIM_MCTRL bit definitions */
	62	#define MR0_INT 1
	63	#undef RESET_COUNT0
143a2e54 WVS	64	#define RESET_COUNT0 (1 << 2)
	65	#define STOP_COUNT0 (1 << 2)
	66	#define M_RES1 (1 << 3)
	67	#define M_RES2 (1 << 4)
	68	#define RESFRC1 (1 << 5)
	69	#define RESFRC2 (1 << 6)
9325fa36 VW	70
	71	/* WDTIM_EMR bit definitions */
	72	#define EXT_MATCH0 1
143a2e54	73	#define MATCH_OUTPUT_HIGH (2 << 4) /a MATCH_CTRL setting /
9325fa36 VW	74
	75	/* WDTIM_RES bit definitions */
	76	#define WDOG_RESET 1 /* read only */
	77
	78	#define WDOG_COUNTER_RATE 13000000 /the counter clock is 13 MHz fixed /
	79
28981727	80	static int nowayout = WATCHDOG_NOWAYOUT;
9325fa36 VW	81	static int heartbeat = DEFAULT_HEARTBEAT;
9325fa36 VW	82
c7dfd0cc	83	static DEFINE_SPINLOCK(io_lock);
9325fa36 VW	84	static unsigned long wdt_status;
	85	#define WDT_IN_USE 0
	86	#define WDT_OK_TO_CLOSE 1
	87	#define WDT_REGION_INITED 2
	88	#define WDT_DEVICE_INITED 3
	89
	90	static unsigned long boot_status;
	91
	92	static struct resource *wdt_mem;
	93	static void __iomem *wdt_base;
	94	struct clk *wdt_clk;
	95
	96	static void wdt_enable(void)
	97	{
99d2853a WVS	98	spin_lock(&io_lock);
99d2853a WVS	99
9325fa36 VW	100	/* stop counter, initiate counter reset */
	101	__raw_writel(RESET_COUNT, WDTIM_CTRL(wdt_base));
	102	/wait for reset to complete. 100% guarantee event /
65a64ec3 VW	103	while (__raw_readl(WDTIM_COUNTER(wdt_base)))
65a64ec3 VW	104	cpu_relax();
9325fa36 VW	105	/* internal and external reset, stop after that */
	106	__raw_writel(M_RES2 \| STOP_COUNT0 \| RESET_COUNT0,
	107	WDTIM_MCTRL(wdt_base));
	108	/* configure match output */
	109	__raw_writel(MATCH_OUTPUT_HIGH, WDTIM_EMR(wdt_base));
	110	/* clear interrupt, just in case */
	111	__raw_writel(MATCH_INT, WDTIM_INT(wdt_base));
	112	/* the longest pulse period 65541/(1310^6) seconds ~ 5 ms. /
	113	__raw_writel(0xFFFF, WDTIM_PULSE(wdt_base));
	114	__raw_writel(heartbeat * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base));
	115	/enable counter, stop when debugger active /
	116	__raw_writel(COUNT_ENAB \| DEBUG_EN, WDTIM_CTRL(wdt_base));
99d2853a WVS	117
99d2853a WVS	118	spin_unlock(&io_lock);
9325fa36 VW	119	}
	120
	121	static void wdt_disable(void)
	122	{
99d2853a WVS	123	spin_lock(&io_lock);
99d2853a WVS	124
9325fa36	125	__raw_writel(0, WDTIM_CTRL(wdt_base)); /stop counter /
99d2853a WVS	126
99d2853a WVS	127	spin_unlock(&io_lock);
9325fa36 VW	128	}
	129
	130	static int pnx4008_wdt_open(struct inode inode, struct file file)
	131	{
24fd1eda RK	132	int ret;
24fd1eda RK	133
9325fa36 VW	134	if (test_and_set_bit(WDT_IN_USE, &wdt_status))
	135	return -EBUSY;
	136
	137	clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
	138
24fd1eda RK	139	ret = clk_enable(wdt_clk);
	140	if (ret) {
	141	clear_bit(WDT_IN_USE, &wdt_status);
	142	return ret;
	143	}
	144
9325fa36 VW	145	wdt_enable();
	146
	147	return nonseekable_open(inode, file);
	148	}
	149
84ca995c AC	150	static ssize_t pnx4008_wdt_write(struct file file, const char data,
84ca995c AC	151	size_t len, loff_t *ppos)
9325fa36	152	{
9325fa36 VW	153	if (len) {
	154	if (!nowayout) {
	155	size_t i;
	156
	157	clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
	158
	159	for (i = 0; i != len; i++) {
	160	char c;
	161
	162	if (get_user(c, data + i))
	163	return -EFAULT;
	164	if (c == 'V')
	165	set_bit(WDT_OK_TO_CLOSE, &wdt_status);
	166	}
	167	}
	168	wdt_enable();
	169	}
	170
	171	return len;
	172	}
	173
84ca995c	174	static const struct watchdog_info ident = {
9325fa36 VW	175	.options = WDIOF_CARDRESET \| WDIOF_MAGICCLOSE \|
	176	WDIOF_SETTIMEOUT \| WDIOF_KEEPALIVEPING,
	177	.identity = "PNX4008 Watchdog",
	178	};
	179
7275fc8c WVS	180	static long pnx4008_wdt_ioctl(struct file *file, unsigned int cmd,
7275fc8c WVS	181	unsigned long arg)
9325fa36	182	{
f311896a	183	int ret = -ENOTTY;
9325fa36 VW	184	int time;
	185
	186	switch (cmd) {
	187	case WDIOC_GETSUPPORT:
	188	ret = copy_to_user((struct watchdog_info *)arg, &ident,
	189	sizeof(ident)) ? -EFAULT : 0;
	190	break;
	191
	192	case WDIOC_GETSTATUS:
	193	ret = put_user(0, (int *)arg);
	194	break;
	195
	196	case WDIOC_GETBOOTSTATUS:
	197	ret = put_user(boot_status, (int *)arg);
	198	break;
	199
0c06090c WVS	200	case WDIOC_KEEPALIVE:
	201	wdt_enable();
	202	ret = 0;
	203	break;
	204
9325fa36 VW	205	case WDIOC_SETTIMEOUT:
	206	ret = get_user(time, (int *)arg);
	207	if (ret)
	208	break;
	209
	210	if (time <= 0 \|\| time > MAX_HEARTBEAT) {
	211	ret = -EINVAL;
	212	break;
	213	}
	214
	215	heartbeat = time;
	216	wdt_enable();
	217	/* Fall through */
	218
	219	case WDIOC_GETTIMEOUT:
	220	ret = put_user(heartbeat, (int *)arg);
	221	break;
9325fa36 VW	222	}
	223	return ret;
	224	}
	225
	226	static int pnx4008_wdt_release(struct inode inode, struct file file)
	227	{
	228	if (!test_bit(WDT_OK_TO_CLOSE, &wdt_status))
	229	printk(KERN_WARNING "WATCHDOG: Device closed unexpectdly\n");
	230
	231	wdt_disable();
24fd1eda	232	clk_disable(wdt_clk);
9325fa36 VW	233	clear_bit(WDT_IN_USE, &wdt_status);
	234	clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
	235
	236	return 0;
	237	}
	238
2b8693c0	239	static const struct file_operations pnx4008_wdt_fops = {
9325fa36 VW	240	.owner = THIS_MODULE,
	241	.llseek = no_llseek,
	242	.write = pnx4008_wdt_write,
84ca995c	243	.unlocked_ioctl = pnx4008_wdt_ioctl,
9325fa36 VW	244	.open = pnx4008_wdt_open,
	245	.release = pnx4008_wdt_release,
	246	};
	247
	248	static struct miscdevice pnx4008_wdt_miscdev = {
	249	.minor = WATCHDOG_MINOR,
	250	.name = "watchdog",
	251	.fops = &pnx4008_wdt_fops,
	252	};
	253
b6bf291f	254	static int __devinit pnx4008_wdt_probe(struct platform_device *pdev)
9325fa36 VW	255	{
	256	int ret = 0, size;
	257	struct resource *res;
	258
	259	if (heartbeat < 1 \|\| heartbeat > MAX_HEARTBEAT)
	260	heartbeat = DEFAULT_HEARTBEAT;
	261
	262	printk(KERN_INFO MODULE_NAME
	263	"PNX4008 Watchdog Timer: heartbeat %d sec\n", heartbeat);
	264
	265	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	266	if (res == NULL) {
	267	printk(KERN_INFO MODULE_NAME
	268	"failed to get memory region resouce\n");
	269	return -ENOENT;
	270	}
	271
b782a563	272	size = resource_size(res);
9325fa36 VW	273	wdt_mem = request_mem_region(res->start, size, pdev->name);
	274
	275	if (wdt_mem == NULL) {
	276	printk(KERN_INFO MODULE_NAME "failed to get memory region\n");
	277	return -ENOENT;
	278	}
	279	wdt_base = (void __iomem *)IO_ADDRESS(res->start);
	280
9bb787f4	281	wdt_clk = clk_get(&pdev->dev, NULL);
9cd44619 AM	282	if (IS_ERR(wdt_clk)) {
9cd44619 AM	283	ret = PTR_ERR(wdt_clk);
9325fa36 VW	284	release_resource(wdt_mem);
	285	kfree(wdt_mem);
	286	goto out;
24fd1eda RK	287	}
	288
	289	ret = clk_enable(wdt_clk);
	290	if (ret) {
	291	release_resource(wdt_mem);
	292	kfree(wdt_mem);
	293	goto out;
	294	}
9325fa36 VW	295
	296	ret = misc_register(&pnx4008_wdt_miscdev);
	297	if (ret < 0) {
	298	printk(KERN_ERR MODULE_NAME "cannot register misc device\n");
	299	release_resource(wdt_mem);
	300	kfree(wdt_mem);
24fd1eda RK	301	clk_disable(wdt_clk);
24fd1eda RK	302	clk_put(wdt_clk);
9325fa36 VW	303	} else {
	304	boot_status = (__raw_readl(WDTIM_RES(wdt_base)) & WDOG_RESET) ?
	305	WDIOF_CARDRESET : 0;
	306	wdt_disable(); /disable for now /
24fd1eda	307	clk_disable(wdt_clk);
9325fa36 VW	308	set_bit(WDT_DEVICE_INITED, &wdt_status);
	309	}
	310
	311	out:
	312	return ret;
	313	}
	314
b6bf291f	315	static int __devexit pnx4008_wdt_remove(struct platform_device *pdev)
9325fa36	316	{
f6764497	317	misc_deregister(&pnx4008_wdt_miscdev);
24fd1eda RK	318
	319	clk_disable(wdt_clk);
	320	clk_put(wdt_clk);
	321
f6764497 WVS	322	if (wdt_mem) {
	323	release_resource(wdt_mem);
	324	kfree(wdt_mem);
	325	wdt_mem = NULL;
	326	}
9325fa36 VW	327	return 0;
	328	}
	329
	330	static struct platform_driver platform_wdt_driver = {
	331	.driver = {
1508c995	332	.name = "pnx4008-watchdog",
f37d193c	333	.owner = THIS_MODULE,
9325fa36 VW	334	},
9325fa36 VW	335	.probe = pnx4008_wdt_probe,
b6bf291f	336	.remove = __devexit_p(pnx4008_wdt_remove),
9325fa36 VW	337	};
	338
	339	static int __init pnx4008_wdt_init(void)
	340	{
	341	return platform_driver_register(&platform_wdt_driver);
	342	}
	343
	344	static void __exit pnx4008_wdt_exit(void)
	345	{
bb0a38d8	346	platform_driver_unregister(&platform_wdt_driver);
9325fa36 VW	347	}
	348
	349	module_init(pnx4008_wdt_init);
	350	module_exit(pnx4008_wdt_exit);
	351
	352	MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
	353	MODULE_DESCRIPTION("PNX4008 Watchdog Driver");
	354
	355	module_param(heartbeat, int, 0);
	356	MODULE_PARM_DESC(heartbeat,
	357	"Watchdog heartbeat period in seconds from 1 to "
	358	__MODULE_STRING(MAX_HEARTBEAT) ", default "
	359	__MODULE_STRING(DEFAULT_HEARTBEAT));
	360
	361	module_param(nowayout, int, 0);
	362	MODULE_PARM_DESC(nowayout,
	363	"Set to 1 to keep watchdog running after device release");
	364
	365	MODULE_LICENSE("GPL");
	366	MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
1508c995	367	MODULE_ALIAS("platform:pnx4008-watchdog");