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staging: Use GFP_ATOMIC when a lock is held
[net-next-2.6.git] / drivers / staging / vme / bridges / vme_tsi148.c
CommitLineData
d22b8ed9
MW		 1/*
2 * Support for the Tundra TSI148 VME-PCI Bridge Chip
3 *
66bd8db5
MW		 4 * Author: Martyn Welch <martyn.welch@ge.com>
5 * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
d22b8ed9
MW		 6 *
7 * Based on work by Tom Armistead and Ajit Prem
8 * Copyright 2004 Motorola Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
d22b8ed9
MW		 16#include <linux/module.h>
17#include <linux/moduleparam.h>
18#include <linux/mm.h>
19#include <linux/types.h>
20#include <linux/errno.h>
21#include <linux/proc_fs.h>
22#include <linux/pci.h>
23#include <linux/poll.h>
24#include <linux/dma-mapping.h>
25#include <linux/interrupt.h>
26#include <linux/spinlock.h>
6af783c8 27#include <linux/sched.h>
5a0e3ad6 28#include <linux/slab.h>
7946328f
MW		 29#include <linux/time.h>
30#include <linux/io.h>
31#include <linux/uaccess.h>
d22b8ed9
MW		 32
33#include "../vme.h"
34#include "../vme_bridge.h"
35#include "vme_tsi148.h"
36
37static int __init tsi148_init(void);
38static int tsi148_probe(struct pci_dev *, const struct pci_device_id *);
39static void tsi148_remove(struct pci_dev *);
40static void __exit tsi148_exit(void);
41
42
29848ac9 43/* Module parameter */
42d4eff7 44static int err_chk;
638f199d 45static int geoid;
d22b8ed9 46
d22b8ed9
MW		 47static char driver_name[] = "vme_tsi148";
48
13ac58da 49static const struct pci_device_id tsi148_ids[] = {
d22b8ed9
MW		 50 { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_TSI148) },
51 { },
52};
53
54static struct pci_driver tsi148_driver = {
55 .name = driver_name,
56 .id_table = tsi148_ids,
57 .probe = tsi148_probe,
58 .remove = tsi148_remove,
59};
60
61static void reg_join(unsigned int high, unsigned int low,
62 unsigned long long *variable)
63{
64 *variable = (unsigned long long)high << 32;
65 *variable |= (unsigned long long)low;
66}
67
68static void reg_split(unsigned long long variable, unsigned int *high,
69 unsigned int *low)
70{
71 *low = (unsigned int)variable & 0xFFFFFFFF;
72 *high = (unsigned int)(variable >> 32);
73}
74
75/*
76 * Wakes up DMA queue.
77 */
29848ac9
MW		 78static u32 tsi148_DMA_irqhandler(struct tsi148_driver *bridge,
79 int channel_mask)
d22b8ed9
MW		 80{
81 u32 serviced = 0;
82
83 if (channel_mask & TSI148_LCSR_INTS_DMA0S) {
29848ac9 84 wake_up(&(bridge->dma_queue[0]));
d22b8ed9
MW		 85 serviced |= TSI148_LCSR_INTC_DMA0C;
86 }
87 if (channel_mask & TSI148_LCSR_INTS_DMA1S) {
29848ac9 88 wake_up(&(bridge->dma_queue[1]));
d22b8ed9
MW		 89 serviced |= TSI148_LCSR_INTC_DMA1C;
90 }
91
92 return serviced;
93}
94
95/*
96 * Wake up location monitor queue
97 */
29848ac9 98static u32 tsi148_LM_irqhandler(struct tsi148_driver *bridge, u32 stat)
d22b8ed9
MW		 99{
100 int i;
101 u32 serviced = 0;
102
103 for (i = 0; i < 4; i++) {
7946328f 104 if (stat & TSI148_LCSR_INTS_LMS[i]) {
d22b8ed9 105 /* We only enable interrupts if the callback is set */
29848ac9 106 bridge->lm_callback[i](i);
d22b8ed9
MW		 107 serviced |= TSI148_LCSR_INTC_LMC[i];
108 }
109 }
110
111 return serviced;
112}
113
114/*
115 * Wake up mail box queue.
116 *
117 * XXX This functionality is not exposed up though API.
118 */
48d9356e 119static u32 tsi148_MB_irqhandler(struct vme_bridge *tsi148_bridge, u32 stat)
d22b8ed9
MW		 120{
121 int i;
122 u32 val;
123 u32 serviced = 0;
48d9356e
MW		 124 struct tsi148_driver *bridge;
125
126 bridge = tsi148_bridge->driver_priv;
d22b8ed9
MW		 127
128 for (i = 0; i < 4; i++) {
7946328f 129 if (stat & TSI148_LCSR_INTS_MBS[i]) {
29848ac9 130 val = ioread32be(bridge->base + TSI148_GCSR_MBOX[i]);
48d9356e
MW		 131 dev_err(tsi148_bridge->parent, "VME Mailbox %d received"
132 ": 0x%x\n", i, val);
d22b8ed9
MW		 133 serviced |= TSI148_LCSR_INTC_MBC[i];
134 }
135 }
136
137 return serviced;
138}
139
140/*
141 * Display error & status message when PERR (PCI) exception interrupt occurs.
142 */
48d9356e 143static u32 tsi148_PERR_irqhandler(struct vme_bridge *tsi148_bridge)
d22b8ed9 144{
48d9356e
MW		 145 struct tsi148_driver *bridge;
146
147 bridge = tsi148_bridge->driver_priv;
148
149 dev_err(tsi148_bridge->parent, "PCI Exception at address: 0x%08x:%08x, "
150 "attributes: %08x\n",
29848ac9
MW		 151 ioread32be(bridge->base + TSI148_LCSR_EDPAU),
152 ioread32be(bridge->base + TSI148_LCSR_EDPAL),
48d9356e
MW		 153 ioread32be(bridge->base + TSI148_LCSR_EDPAT));
154
155 dev_err(tsi148_bridge->parent, "PCI-X attribute reg: %08x, PCI-X split "
156 "completion reg: %08x\n",
29848ac9 157 ioread32be(bridge->base + TSI148_LCSR_EDPXA),
48d9356e 158 ioread32be(bridge->base + TSI148_LCSR_EDPXS));
d22b8ed9 159
29848ac9 160 iowrite32be(TSI148_LCSR_EDPAT_EDPCL, bridge->base + TSI148_LCSR_EDPAT);
d22b8ed9
MW		 161
162 return TSI148_LCSR_INTC_PERRC;
163}
164
165/*
166 * Save address and status when VME error interrupt occurs.
167 */
29848ac9 168static u32 tsi148_VERR_irqhandler(struct vme_bridge *tsi148_bridge)
d22b8ed9
MW		 169{
170 unsigned int error_addr_high, error_addr_low;
171 unsigned long long error_addr;
172 u32 error_attrib;
173 struct vme_bus_error *error;
29848ac9
MW		 174 struct tsi148_driver *bridge;
175
176 bridge = tsi148_bridge->driver_priv;
d22b8ed9 177
29848ac9
MW		 178 error_addr_high = ioread32be(bridge->base + TSI148_LCSR_VEAU);
179 error_addr_low = ioread32be(bridge->base + TSI148_LCSR_VEAL);
180 error_attrib = ioread32be(bridge->base + TSI148_LCSR_VEAT);
d22b8ed9
MW		 181
182 reg_join(error_addr_high, error_addr_low, &error_addr);
183
184 /* Check for exception register overflow (we have lost error data) */
7946328f 185 if (error_attrib & TSI148_LCSR_VEAT_VEOF) {
48d9356e
MW		 186 dev_err(tsi148_bridge->parent, "VME Bus Exception Overflow "
187 "Occurred\n");
d22b8ed9
MW		 188 }
189
7946328f 190 error = kmalloc(sizeof(struct vme_bus_error), GFP_ATOMIC);
d22b8ed9
MW		 191 if (error) {
192 error->address = error_addr;
193 error->attributes = error_attrib;
194 list_add_tail(&(error->list), &(tsi148_bridge->vme_errors));
195 } else {
48d9356e
MW		 196 dev_err(tsi148_bridge->parent, "Unable to alloc memory for "
197 "VMEbus Error reporting\n");
198 dev_err(tsi148_bridge->parent, "VME Bus Error at address: "
199 "0x%llx, attributes: %08x\n", error_addr, error_attrib);
d22b8ed9
MW		 200 }
201
202 /* Clear Status */
29848ac9 203 iowrite32be(TSI148_LCSR_VEAT_VESCL, bridge->base + TSI148_LCSR_VEAT);
d22b8ed9
MW		 204
205 return TSI148_LCSR_INTC_VERRC;
206}
207
208/*
209 * Wake up IACK queue.
210 */
29848ac9 211static u32 tsi148_IACK_irqhandler(struct tsi148_driver *bridge)
d22b8ed9 212{
29848ac9 213 wake_up(&(bridge->iack_queue));
d22b8ed9
MW		 214
215 return TSI148_LCSR_INTC_IACKC;
216}
217
218/*
219 * Calling VME bus interrupt callback if provided.
220 */
29848ac9
MW		 221static u32 tsi148_VIRQ_irqhandler(struct vme_bridge *tsi148_bridge,
222 u32 stat)
d22b8ed9
MW		 223{
224 int vec, i, serviced = 0;
29848ac9
MW		 225 struct tsi148_driver *bridge;
226
227 bridge = tsi148_bridge->driver_priv;
d22b8ed9
MW		 228
229 for (i = 7; i > 0; i--) {
230 if (stat & (1 << i)) {
231 /*
7946328f
MW		 232 * Note: Even though the registers are defined as
233 * 32-bits in the spec, we only want to issue 8-bit
234 * IACK cycles on the bus, read from offset 3.
d22b8ed9 235 */
29848ac9 236 vec = ioread8(bridge->base + TSI148_LCSR_VIACK[i] + 3);
d22b8ed9 237
c813f592 238 vme_irq_handler(tsi148_bridge, i, vec);
d22b8ed9
MW		 239
240 serviced |= (1 << i);
241 }
242 }
243
244 return serviced;
245}
246
247/*
248 * Top level interrupt handler. Clears appropriate interrupt status bits and
249 * then calls appropriate sub handler(s).
250 */
29848ac9 251static irqreturn_t tsi148_irqhandler(int irq, void *ptr)
d22b8ed9
MW		 252{
253 u32 stat, enable, serviced = 0;
29848ac9
MW		 254 struct vme_bridge *tsi148_bridge;
255 struct tsi148_driver *bridge;
256
257 tsi148_bridge = ptr;
258
259 bridge = tsi148_bridge->driver_priv;
d22b8ed9
MW		 260
261 /* Determine which interrupts are unmasked and set */
29848ac9
MW		 262 enable = ioread32be(bridge->base + TSI148_LCSR_INTEO);
263 stat = ioread32be(bridge->base + TSI148_LCSR_INTS);
d22b8ed9
MW		 264
265 /* Only look at unmasked interrupts */
266 stat &= enable;
267
7946328f 268 if (unlikely(!stat))
d22b8ed9 269 return IRQ_NONE;
d22b8ed9
MW		 270
271 /* Call subhandlers as appropriate */
272 /* DMA irqs */
273 if (stat & (TSI148_LCSR_INTS_DMA1S | TSI148_LCSR_INTS_DMA0S))
29848ac9 274 serviced |= tsi148_DMA_irqhandler(bridge, stat);
d22b8ed9
MW		 275
276 /* Location monitor irqs */
277 if (stat & (TSI148_LCSR_INTS_LM3S | TSI148_LCSR_INTS_LM2S |
278 TSI148_LCSR_INTS_LM1S | TSI148_LCSR_INTS_LM0S))
29848ac9 279 serviced |= tsi148_LM_irqhandler(bridge, stat);
d22b8ed9
MW		 280
281 /* Mail box irqs */
282 if (stat & (TSI148_LCSR_INTS_MB3S | TSI148_LCSR_INTS_MB2S |
283 TSI148_LCSR_INTS_MB1S | TSI148_LCSR_INTS_MB0S))
48d9356e 284 serviced |= tsi148_MB_irqhandler(tsi148_bridge, stat);
d22b8ed9
MW		 285
286 /* PCI bus error */
287 if (stat & TSI148_LCSR_INTS_PERRS)
48d9356e 288 serviced |= tsi148_PERR_irqhandler(tsi148_bridge);
d22b8ed9
MW		 289
290 /* VME bus error */
291 if (stat & TSI148_LCSR_INTS_VERRS)
29848ac9 292 serviced |= tsi148_VERR_irqhandler(tsi148_bridge);
d22b8ed9
MW		 293
294 /* IACK irq */
295 if (stat & TSI148_LCSR_INTS_IACKS)
29848ac9 296 serviced |= tsi148_IACK_irqhandler(bridge);
d22b8ed9
MW		 297
298 /* VME bus irqs */
299 if (stat & (TSI148_LCSR_INTS_IRQ7S | TSI148_LCSR_INTS_IRQ6S |
300 TSI148_LCSR_INTS_IRQ5S | TSI148_LCSR_INTS_IRQ4S |
301 TSI148_LCSR_INTS_IRQ3S | TSI148_LCSR_INTS_IRQ2S |
302 TSI148_LCSR_INTS_IRQ1S))
29848ac9 303 serviced |= tsi148_VIRQ_irqhandler(tsi148_bridge, stat);
d22b8ed9
MW		 304
305 /* Clear serviced interrupts */
29848ac9 306 iowrite32be(serviced, bridge->base + TSI148_LCSR_INTC);
d22b8ed9
MW		 307
308 return IRQ_HANDLED;
309}
310
29848ac9 311static int tsi148_irq_init(struct vme_bridge *tsi148_bridge)
d22b8ed9
MW		 312{
313 int result;
314 unsigned int tmp;
315 struct pci_dev *pdev;
29848ac9
MW		 316 struct tsi148_driver *bridge;
317
318 pdev = container_of(tsi148_bridge->parent, struct pci_dev, dev);
d22b8ed9 319
29848ac9 320 bridge = tsi148_bridge->driver_priv;
d22b8ed9
MW		 321
322 /* Initialise list for VME bus errors */
29848ac9 323 INIT_LIST_HEAD(&(tsi148_bridge->vme_errors));
d22b8ed9 324
29848ac9 325 mutex_init(&(tsi148_bridge->irq_mtx));
c813f592 326
d22b8ed9
MW		 327 result = request_irq(pdev->irq,
328 tsi148_irqhandler,
329 IRQF_SHARED,
29848ac9 330 driver_name, tsi148_bridge);
d22b8ed9 331 if (result) {
48d9356e
MW		 332 dev_err(tsi148_bridge->parent, "Can't get assigned pci irq "
333 "vector %02X\n", pdev->irq);
d22b8ed9
MW		 334 return result;
335 }
336
337 /* Enable and unmask interrupts */
338 tmp = TSI148_LCSR_INTEO_DMA1EO | TSI148_LCSR_INTEO_DMA0EO |
339 TSI148_LCSR_INTEO_MB3EO | TSI148_LCSR_INTEO_MB2EO |
340 TSI148_LCSR_INTEO_MB1EO | TSI148_LCSR_INTEO_MB0EO |
341 TSI148_LCSR_INTEO_PERREO | TSI148_LCSR_INTEO_VERREO |
342 TSI148_LCSR_INTEO_IACKEO;
343
29848ac9 344 /* This leaves the following interrupts masked.
d22b8ed9
MW		 345 * TSI148_LCSR_INTEO_VIEEO
346 * TSI148_LCSR_INTEO_SYSFLEO
347 * TSI148_LCSR_INTEO_ACFLEO
348 */
349
350 /* Don't enable Location Monitor interrupts here - they will be
351 * enabled when the location monitors are properly configured and
352 * a callback has been attached.
353 * TSI148_LCSR_INTEO_LM0EO
354 * TSI148_LCSR_INTEO_LM1EO
355 * TSI148_LCSR_INTEO_LM2EO
356 * TSI148_LCSR_INTEO_LM3EO
357 */
358
359 /* Don't enable VME interrupts until we add a handler, else the board
360 * will respond to it and we don't want that unless it knows how to
361 * properly deal with it.
362 * TSI148_LCSR_INTEO_IRQ7EO
363 * TSI148_LCSR_INTEO_IRQ6EO
364 * TSI148_LCSR_INTEO_IRQ5EO
365 * TSI148_LCSR_INTEO_IRQ4EO
366 * TSI148_LCSR_INTEO_IRQ3EO
367 * TSI148_LCSR_INTEO_IRQ2EO
368 * TSI148_LCSR_INTEO_IRQ1EO
369 */
370
371 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
372 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
373
374 return 0;
375}
376
29848ac9 377static void tsi148_irq_exit(struct tsi148_driver *bridge, struct pci_dev *pdev)
d22b8ed9
MW		 378{
379 /* Turn off interrupts */
29848ac9
MW		 380 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEO);
381 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEN);
d22b8ed9
MW		 382
383 /* Clear all interrupts */
29848ac9 384 iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_INTC);
d22b8ed9
MW		 385
386 /* Detach interrupt handler */
387 free_irq(pdev->irq, pdev);
388}
389
390/*
391 * Check to see if an IACk has been received, return true (1) or false (0).
392 */
29848ac9 393int tsi148_iack_received(struct tsi148_driver *bridge)
d22b8ed9
MW		 394{
395 u32 tmp;
396
29848ac9 397 tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);
d22b8ed9
MW		 398
399 if (tmp & TSI148_LCSR_VICR_IRQS)
400 return 0;
401 else
402 return 1;
403}
404
405/*
c813f592 406 * Configure VME interrupt
d22b8ed9 407 */
29848ac9
MW		 408void tsi148_irq_set(struct vme_bridge *tsi148_bridge, int level,
409 int state, int sync)
d22b8ed9 410{
75155020 411 struct pci_dev *pdev;
c813f592 412 u32 tmp;
29848ac9
MW		 413 struct tsi148_driver *bridge;
414
415 bridge = tsi148_bridge->driver_priv;
d22b8ed9 416
c813f592
MW		 417 /* We need to do the ordering differently for enabling and disabling */
418 if (state == 0) {
29848ac9 419 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
d22b8ed9 420 tmp &= ~TSI148_LCSR_INTEN_IRQEN[level - 1];
29848ac9 421 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
df455175 422
29848ac9 423 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
df455175 424 tmp &= ~TSI148_LCSR_INTEO_IRQEO[level - 1];
29848ac9 425 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
75155020 426
c813f592
MW		 427 if (sync != 0) {
428 pdev = container_of(tsi148_bridge->parent,
429 struct pci_dev, dev);
75155020 430
c813f592
MW		 431 synchronize_irq(pdev->irq);
432 }
433 } else {
29848ac9 434 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
c813f592 435 tmp |= TSI148_LCSR_INTEO_IRQEO[level - 1];
29848ac9 436 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
df455175 437
29848ac9 438 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
c813f592 439 tmp |= TSI148_LCSR_INTEN_IRQEN[level - 1];
29848ac9 440 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
c813f592 441 }
d22b8ed9
MW		 442}
443
444/*
445 * Generate a VME bus interrupt at the requested level & vector. Wait for
446 * interrupt to be acked.
d22b8ed9 447 */
29848ac9 448int tsi148_irq_generate(struct vme_bridge *tsi148_bridge, int level, int statid)
d22b8ed9
MW		 449{
450 u32 tmp;
29848ac9
MW		 451 struct tsi148_driver *bridge;
452
453 bridge = tsi148_bridge->driver_priv;
d22b8ed9 454
29848ac9 455 mutex_lock(&(bridge->vme_int));
d22b8ed9
MW		 456
457 /* Read VICR register */
29848ac9 458 tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);
d22b8ed9
MW		 459
460 /* Set Status/ID */
461 tmp = (tmp & ~TSI148_LCSR_VICR_STID_M) |
462 (statid & TSI148_LCSR_VICR_STID_M);
29848ac9 463 iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);
d22b8ed9
MW		 464
465 /* Assert VMEbus IRQ */
466 tmp = tmp | TSI148_LCSR_VICR_IRQL[level];
29848ac9 467 iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);
d22b8ed9
MW		 468
469 /* XXX Consider implementing a timeout? */
29848ac9
MW		 470 wait_event_interruptible(bridge->iack_queue,
471 tsi148_iack_received(bridge));
d22b8ed9 472
29848ac9 473 mutex_unlock(&(bridge->vme_int));
d22b8ed9
MW		 474
475 return 0;
476}
477
478/*
479 * Find the first error in this address range
480 */
29848ac9
MW		 481static struct vme_bus_error *tsi148_find_error(struct vme_bridge *tsi148_bridge,
482 vme_address_t aspace, unsigned long long address, size_t count)
d22b8ed9
MW		 483{
484 struct list_head *err_pos;
485 struct vme_bus_error *vme_err, *valid = NULL;
486 unsigned long long bound;
487
488 bound = address + count;
489
490 /*
491 * XXX We are currently not looking at the address space when parsing
492 * for errors. This is because parsing the Address Modifier Codes
493 * is going to be quite resource intensive to do properly. We
494 * should be OK just looking at the addresses and this is certainly
495 * much better than what we had before.
496 */
497 err_pos = NULL;
498 /* Iterate through errors */
499 list_for_each(err_pos, &(tsi148_bridge->vme_errors)) {
500 vme_err = list_entry(err_pos, struct vme_bus_error, list);
7946328f
MW		 501 if ((vme_err->address >= address) &&
502 (vme_err->address < bound)) {
503
d22b8ed9
MW		 504 valid = vme_err;
505 break;
506 }
507 }
508
509 return valid;
510}
511
512/*
513 * Clear errors in the provided address range.
514 */
29848ac9
MW		 515static void tsi148_clear_errors(struct vme_bridge *tsi148_bridge,
516 vme_address_t aspace, unsigned long long address, size_t count)
d22b8ed9
MW		 517{
518 struct list_head *err_pos, *temp;
519 struct vme_bus_error *vme_err;
520 unsigned long long bound;
521
522 bound = address + count;
523
524 /*
525 * XXX We are currently not looking at the address space when parsing
526 * for errors. This is because parsing the Address Modifier Codes
527 * is going to be quite resource intensive to do properly. We
528 * should be OK just looking at the addresses and this is certainly
529 * much better than what we had before.
530 */
531 err_pos = NULL;
532 /* Iterate through errors */
533 list_for_each_safe(err_pos, temp, &(tsi148_bridge->vme_errors)) {
534 vme_err = list_entry(err_pos, struct vme_bus_error, list);
535
7946328f
MW		 536 if ((vme_err->address >= address) &&
537 (vme_err->address < bound)) {
538
d22b8ed9
MW		 539 list_del(err_pos);
540 kfree(vme_err);
541 }
542 }
543}
544
545/*
546 * Initialize a slave window with the requested attributes.
547 */
548int tsi148_slave_set(struct vme_slave_resource *image, int enabled,
549 unsigned long long vme_base, unsigned long long size,
550 dma_addr_t pci_base, vme_address_t aspace, vme_cycle_t cycle)
551{
552 unsigned int i, addr = 0, granularity = 0;
553 unsigned int temp_ctl = 0;
554 unsigned int vme_base_low, vme_base_high;
555 unsigned int vme_bound_low, vme_bound_high;
556 unsigned int pci_offset_low, pci_offset_high;
557 unsigned long long vme_bound, pci_offset;
48d9356e 558 struct vme_bridge *tsi148_bridge;
29848ac9
MW		 559 struct tsi148_driver *bridge;
560
48d9356e
MW		 561 tsi148_bridge = image->parent;
562 bridge = tsi148_bridge->driver_priv;
d22b8ed9 563
d22b8ed9
MW		 564 i = image->number;
565
566 switch (aspace) {
567 case VME_A16:
568 granularity = 0x10;
569 addr |= TSI148_LCSR_ITAT_AS_A16;
570 break;
571 case VME_A24:
572 granularity = 0x1000;
573 addr |= TSI148_LCSR_ITAT_AS_A24;
574 break;
575 case VME_A32:
576 granularity = 0x10000;
577 addr |= TSI148_LCSR_ITAT_AS_A32;
578 break;
579 case VME_A64:
580 granularity = 0x10000;
581 addr |= TSI148_LCSR_ITAT_AS_A64;
582 break;
583 case VME_CRCSR:
584 case VME_USER1:
585 case VME_USER2:
586 case VME_USER3:
587 case VME_USER4:
588 default:
48d9356e 589 dev_err(tsi148_bridge->parent, "Invalid address space\n");
d22b8ed9
MW		 590 return -EINVAL;
591 break;
592 }
593
594 /* Convert 64-bit variables to 2x 32-bit variables */
595 reg_split(vme_base, &vme_base_high, &vme_base_low);
596
597 /*
598 * Bound address is a valid address for the window, adjust
599 * accordingly
600 */
601 vme_bound = vme_base + size - granularity;
602 reg_split(vme_bound, &vme_bound_high, &vme_bound_low);
603 pci_offset = (unsigned long long)pci_base - vme_base;
604 reg_split(pci_offset, &pci_offset_high, &pci_offset_low);
605
606 if (vme_base_low & (granularity - 1)) {
48d9356e 607 dev_err(tsi148_bridge->parent, "Invalid VME base alignment\n");
d22b8ed9
MW		 608 return -EINVAL;
609 }
610 if (vme_bound_low & (granularity - 1)) {
48d9356e 611 dev_err(tsi148_bridge->parent, "Invalid VME bound alignment\n");
d22b8ed9
MW		 612 return -EINVAL;
613 }
614 if (pci_offset_low & (granularity - 1)) {
48d9356e
MW		 615 dev_err(tsi148_bridge->parent, "Invalid PCI Offset "
616 "alignment\n");
d22b8ed9
MW		 617 return -EINVAL;
618 }
619
d22b8ed9 620 /* Disable while we are mucking around */
29848ac9 621 temp_ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9
MW		 622 TSI148_LCSR_OFFSET_ITAT);
623 temp_ctl &= ~TSI148_LCSR_ITAT_EN;
29848ac9 624 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9
MW		 625 TSI148_LCSR_OFFSET_ITAT);
626
627 /* Setup mapping */
29848ac9 628 iowrite32be(vme_base_high, bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9 629 TSI148_LCSR_OFFSET_ITSAU);
29848ac9 630 iowrite32be(vme_base_low, bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9 631 TSI148_LCSR_OFFSET_ITSAL);
29848ac9 632 iowrite32be(vme_bound_high, bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9 633 TSI148_LCSR_OFFSET_ITEAU);
29848ac9 634 iowrite32be(vme_bound_low, bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9 635 TSI148_LCSR_OFFSET_ITEAL);
29848ac9 636 iowrite32be(pci_offset_high, bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9 637 TSI148_LCSR_OFFSET_ITOFU);
29848ac9 638 iowrite32be(pci_offset_low, bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9
MW		 639 TSI148_LCSR_OFFSET_ITOFL);
640
d22b8ed9
MW		 641 /* Setup 2eSST speeds */
642 temp_ctl &= ~TSI148_LCSR_ITAT_2eSSTM_M;
643 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
644 case VME_2eSST160:
645 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_160;
646 break;
647 case VME_2eSST267:
648 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_267;
649 break;
650 case VME_2eSST320:
651 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_320;
652 break;
653 }
654
655 /* Setup cycle types */
656 temp_ctl &= ~(0x1F << 7);
657 if (cycle & VME_BLT)
658 temp_ctl |= TSI148_LCSR_ITAT_BLT;
659 if (cycle & VME_MBLT)
660 temp_ctl |= TSI148_LCSR_ITAT_MBLT;
661 if (cycle & VME_2eVME)
662 temp_ctl |= TSI148_LCSR_ITAT_2eVME;
663 if (cycle & VME_2eSST)
664 temp_ctl |= TSI148_LCSR_ITAT_2eSST;
665 if (cycle & VME_2eSSTB)
666 temp_ctl |= TSI148_LCSR_ITAT_2eSSTB;
667
668 /* Setup address space */
669 temp_ctl &= ~TSI148_LCSR_ITAT_AS_M;
670 temp_ctl |= addr;
671
672 temp_ctl &= ~0xF;
673 if (cycle & VME_SUPER)
674 temp_ctl |= TSI148_LCSR_ITAT_SUPR ;
675 if (cycle & VME_USER)
676 temp_ctl |= TSI148_LCSR_ITAT_NPRIV;
677 if (cycle & VME_PROG)
678 temp_ctl |= TSI148_LCSR_ITAT_PGM;
679 if (cycle & VME_DATA)
680 temp_ctl |= TSI148_LCSR_ITAT_DATA;
681
682 /* Write ctl reg without enable */
29848ac9 683 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9
MW		 684 TSI148_LCSR_OFFSET_ITAT);
685
686 if (enabled)
687 temp_ctl |= TSI148_LCSR_ITAT_EN;
688
29848ac9 689 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9
MW		 690 TSI148_LCSR_OFFSET_ITAT);
691
692 return 0;
693}
694
695/*
696 * Get slave window configuration.
d22b8ed9
MW		 697 */
698int tsi148_slave_get(struct vme_slave_resource *image, int *enabled,
699 unsigned long long *vme_base, unsigned long long *size,
700 dma_addr_t *pci_base, vme_address_t *aspace, vme_cycle_t *cycle)
701{
702 unsigned int i, granularity = 0, ctl = 0;
703 unsigned int vme_base_low, vme_base_high;
704 unsigned int vme_bound_low, vme_bound_high;
705 unsigned int pci_offset_low, pci_offset_high;
706 unsigned long long vme_bound, pci_offset;
29848ac9 707 struct tsi148_driver *bridge;
d22b8ed9 708
29848ac9 709 bridge = image->parent->driver_priv;
d22b8ed9
MW		 710
711 i = image->number;
712
713 /* Read registers */
29848ac9 714 ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9
MW		 715 TSI148_LCSR_OFFSET_ITAT);
716
29848ac9 717 vme_base_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9 718 TSI148_LCSR_OFFSET_ITSAU);
29848ac9 719 vme_base_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9 720 TSI148_LCSR_OFFSET_ITSAL);
29848ac9 721 vme_bound_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9 722 TSI148_LCSR_OFFSET_ITEAU);
29848ac9 723 vme_bound_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9 724 TSI148_LCSR_OFFSET_ITEAL);
29848ac9 725 pci_offset_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9 726 TSI148_LCSR_OFFSET_ITOFU);
29848ac9 727 pci_offset_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9
MW		 728 TSI148_LCSR_OFFSET_ITOFL);
729
730 /* Convert 64-bit variables to 2x 32-bit variables */
731 reg_join(vme_base_high, vme_base_low, vme_base);
732 reg_join(vme_bound_high, vme_bound_low, &vme_bound);
733 reg_join(pci_offset_high, pci_offset_low, &pci_offset);
734
735 *pci_base = (dma_addr_t)vme_base + pci_offset;
736
737 *enabled = 0;
738 *aspace = 0;
739 *cycle = 0;
740
741 if (ctl & TSI148_LCSR_ITAT_EN)
742 *enabled = 1;
743
744 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A16) {
745 granularity = 0x10;
746 *aspace |= VME_A16;
747 }
748 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A24) {
749 granularity = 0x1000;
750 *aspace |= VME_A24;
751 }
752 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A32) {
753 granularity = 0x10000;
754 *aspace |= VME_A32;
755 }
756 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A64) {
757 granularity = 0x10000;
758 *aspace |= VME_A64;
759 }
760
761 /* Need granularity before we set the size */
762 *size = (unsigned long long)((vme_bound - *vme_base) + granularity);
763
764
765 if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_160)
766 *cycle |= VME_2eSST160;
767 if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_267)
768 *cycle |= VME_2eSST267;
769 if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_320)
770 *cycle |= VME_2eSST320;
771
772 if (ctl & TSI148_LCSR_ITAT_BLT)
773 *cycle |= VME_BLT;
774 if (ctl & TSI148_LCSR_ITAT_MBLT)
775 *cycle |= VME_MBLT;
776 if (ctl & TSI148_LCSR_ITAT_2eVME)
777 *cycle |= VME_2eVME;
778 if (ctl & TSI148_LCSR_ITAT_2eSST)
779 *cycle |= VME_2eSST;
780 if (ctl & TSI148_LCSR_ITAT_2eSSTB)
781 *cycle |= VME_2eSSTB;
782
783 if (ctl & TSI148_LCSR_ITAT_SUPR)
784 *cycle |= VME_SUPER;
785 if (ctl & TSI148_LCSR_ITAT_NPRIV)
786 *cycle |= VME_USER;
787 if (ctl & TSI148_LCSR_ITAT_PGM)
788 *cycle |= VME_PROG;
789 if (ctl & TSI148_LCSR_ITAT_DATA)
790 *cycle |= VME_DATA;
791
792 return 0;
793}
794
795/*
796 * Allocate and map PCI Resource
797 */
798static int tsi148_alloc_resource(struct vme_master_resource *image,
799 unsigned long long size)
800{
801 unsigned long long existing_size;
802 int retval = 0;
803 struct pci_dev *pdev;
29848ac9
MW		 804 struct vme_bridge *tsi148_bridge;
805
806 tsi148_bridge = image->parent;
d22b8ed9 807
48d9356e 808 pdev = container_of(tsi148_bridge->parent, struct pci_dev, dev);
d22b8ed9 809
8fafb476
MW		 810 existing_size = (unsigned long long)(image->bus_resource.end -
811 image->bus_resource.start);
d22b8ed9
MW		 812
813 /* If the existing size is OK, return */
59c22904 814 if ((size != 0) && (existing_size == (size - 1)))
d22b8ed9
MW		 815 return 0;
816
817 if (existing_size != 0) {
818 iounmap(image->kern_base);
819 image->kern_base = NULL;
8fafb476
MW		 820 if (image->bus_resource.name != NULL)
821 kfree(image->bus_resource.name);
822 release_resource(&(image->bus_resource));
823 memset(&(image->bus_resource), 0, sizeof(struct resource));
d22b8ed9
MW		 824 }
825
59c22904 826 /* Exit here if size is zero */
7946328f 827 if (size == 0)
59c22904 828 return 0;
59c22904 829
8fafb476 830 if (image->bus_resource.name == NULL) {
0aa3f139 831 image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_ATOMIC);
8fafb476 832 if (image->bus_resource.name == NULL) {
48d9356e
MW		 833 dev_err(tsi148_bridge->parent, "Unable to allocate "
834 "memory for resource name\n");
d22b8ed9
MW		 835 retval = -ENOMEM;
836 goto err_name;
837 }
838 }
839
8fafb476 840 sprintf((char *)image->bus_resource.name, "%s.%d", tsi148_bridge->name,
d22b8ed9
MW		 841 image->number);
842
8fafb476
MW		 843 image->bus_resource.start = 0;
844 image->bus_resource.end = (unsigned long)size;
845 image->bus_resource.flags = IORESOURCE_MEM;
d22b8ed9
MW		 846
847 retval = pci_bus_alloc_resource(pdev->bus,
8fafb476 848 &(image->bus_resource), size, size, PCIBIOS_MIN_MEM,
d22b8ed9
MW		 849 0, NULL, NULL);
850 if (retval) {
48d9356e
MW		 851 dev_err(tsi148_bridge->parent, "Failed to allocate mem "
852 "resource for window %d size 0x%lx start 0x%lx\n",
d22b8ed9 853 image->number, (unsigned long)size,
8fafb476 854 (unsigned long)image->bus_resource.start);
d22b8ed9
MW		 855 goto err_resource;
856 }
857
858 image->kern_base = ioremap_nocache(
8fafb476 859 image->bus_resource.start, size);
d22b8ed9 860 if (image->kern_base == NULL) {
48d9356e 861 dev_err(tsi148_bridge->parent, "Failed to remap resource\n");
d22b8ed9
MW		 862 retval = -ENOMEM;
863 goto err_remap;
864 }
865
866 return 0;
867
868 iounmap(image->kern_base);
869 image->kern_base = NULL;
870err_remap:
8fafb476 871 release_resource(&(image->bus_resource));
d22b8ed9 872err_resource:
8fafb476
MW		 873 kfree(image->bus_resource.name);
874 memset(&(image->bus_resource), 0, sizeof(struct resource));
d22b8ed9
MW		 875err_name:
876 return retval;
877}
878
879/*
880 * Free and unmap PCI Resource
881 */
882static void tsi148_free_resource(struct vme_master_resource *image)
883{
884 iounmap(image->kern_base);
885 image->kern_base = NULL;
8fafb476
MW		 886 release_resource(&(image->bus_resource));
887 kfree(image->bus_resource.name);
888 memset(&(image->bus_resource), 0, sizeof(struct resource));
d22b8ed9
MW		 889}
890
891/*
892 * Set the attributes of an outbound window.
893 */
7946328f 894int tsi148_master_set(struct vme_master_resource *image, int enabled,
d22b8ed9
MW		 895 unsigned long long vme_base, unsigned long long size,
896 vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth)
897{
898 int retval = 0;
899 unsigned int i;
900 unsigned int temp_ctl = 0;
901 unsigned int pci_base_low, pci_base_high;
902 unsigned int pci_bound_low, pci_bound_high;
903 unsigned int vme_offset_low, vme_offset_high;
904 unsigned long long pci_bound, vme_offset, pci_base;
48d9356e 905 struct vme_bridge *tsi148_bridge;
29848ac9
MW		 906 struct tsi148_driver *bridge;
907
48d9356e
MW		 908 tsi148_bridge = image->parent;
909
910 bridge = tsi148_bridge->driver_priv;
d22b8ed9
MW		 911
912 /* Verify input data */
913 if (vme_base & 0xFFFF) {
48d9356e
MW		 914 dev_err(tsi148_bridge->parent, "Invalid VME Window "
915 "alignment\n");
d22b8ed9
MW		 916 retval = -EINVAL;
917 goto err_window;
918 }
59c22904
MW		 919
920 if ((size == 0) && (enabled != 0)) {
48d9356e
MW		 921 dev_err(tsi148_bridge->parent, "Size must be non-zero for "
922 "enabled windows\n");
d22b8ed9
MW		 923 retval = -EINVAL;
924 goto err_window;
925 }
926
927 spin_lock(&(image->lock));
928
929 /* Let's allocate the resource here rather than further up the stack as
59c22904
MW		 930 * it avoids pushing loads of bus dependant stuff up the stack. If size
931 * is zero, any existing resource will be freed.
d22b8ed9
MW		 932 */
933 retval = tsi148_alloc_resource(image, size);
934 if (retval) {
935 spin_unlock(&(image->lock));
48d9356e 936 dev_err(tsi148_bridge->parent, "Unable to allocate memory for "
59c22904 937 "resource\n");
d22b8ed9
MW		 938 goto err_res;
939 }
940
59c22904
MW		 941 if (size == 0) {
942 pci_base = 0;
943 pci_bound = 0;
944 vme_offset = 0;
945 } else {
8fafb476 946 pci_base = (unsigned long long)image->bus_resource.start;
59c22904
MW		 947
948 /*
949 * Bound address is a valid address for the window, adjust
950 * according to window granularity.
951 */
952 pci_bound = pci_base + (size - 0x10000);
953 vme_offset = vme_base - pci_base;
954 }
d22b8ed9
MW		 955
956 /* Convert 64-bit variables to 2x 32-bit variables */
957 reg_split(pci_base, &pci_base_high, &pci_base_low);
958 reg_split(pci_bound, &pci_bound_high, &pci_bound_low);
959 reg_split(vme_offset, &vme_offset_high, &vme_offset_low);
960
961 if (pci_base_low & 0xFFFF) {
962 spin_unlock(&(image->lock));
48d9356e 963 dev_err(tsi148_bridge->parent, "Invalid PCI base alignment\n");
d22b8ed9
MW		 964 retval = -EINVAL;
965 goto err_gran;
966 }
967 if (pci_bound_low & 0xFFFF) {
968 spin_unlock(&(image->lock));
48d9356e 969 dev_err(tsi148_bridge->parent, "Invalid PCI bound alignment\n");
d22b8ed9
MW		 970 retval = -EINVAL;
971 goto err_gran;
972 }
973 if (vme_offset_low & 0xFFFF) {
974 spin_unlock(&(image->lock));
48d9356e
MW		 975 dev_err(tsi148_bridge->parent, "Invalid VME Offset "
976 "alignment\n");
d22b8ed9
MW		 977 retval = -EINVAL;
978 goto err_gran;
979 }
980
981 i = image->number;
982
983 /* Disable while we are mucking around */
29848ac9 984 temp_ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9
MW		 985 TSI148_LCSR_OFFSET_OTAT);
986 temp_ctl &= ~TSI148_LCSR_OTAT_EN;
29848ac9 987 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9
MW		 988 TSI148_LCSR_OFFSET_OTAT);
989
d22b8ed9
MW		 990 /* Setup 2eSST speeds */
991 temp_ctl &= ~TSI148_LCSR_OTAT_2eSSTM_M;
992 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
993 case VME_2eSST160:
994 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_160;
995 break;
996 case VME_2eSST267:
997 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_267;
998 break;
999 case VME_2eSST320:
1000 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_320;
1001 break;
1002 }
1003
1004 /* Setup cycle types */
1005 if (cycle & VME_BLT) {
1006 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1007 temp_ctl |= TSI148_LCSR_OTAT_TM_BLT;
1008 }
1009 if (cycle & VME_MBLT) {
1010 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1011 temp_ctl |= TSI148_LCSR_OTAT_TM_MBLT;
1012 }
1013 if (cycle & VME_2eVME) {
1014 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1015 temp_ctl |= TSI148_LCSR_OTAT_TM_2eVME;
1016 }
1017 if (cycle & VME_2eSST) {
1018 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1019 temp_ctl |= TSI148_LCSR_OTAT_TM_2eSST;
1020 }
1021 if (cycle & VME_2eSSTB) {
48d9356e
MW		 1022 dev_warn(tsi148_bridge->parent, "Currently not setting "
1023 "Broadcast Select Registers\n");
d22b8ed9
MW		 1024 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1025 temp_ctl |= TSI148_LCSR_OTAT_TM_2eSSTB;
1026 }
1027
1028 /* Setup data width */
1029 temp_ctl &= ~TSI148_LCSR_OTAT_DBW_M;
1030 switch (dwidth) {
1031 case VME_D16:
1032 temp_ctl |= TSI148_LCSR_OTAT_DBW_16;
1033 break;
1034 case VME_D32:
1035 temp_ctl |= TSI148_LCSR_OTAT_DBW_32;
1036 break;
1037 default:
1038 spin_unlock(&(image->lock));
48d9356e 1039 dev_err(tsi148_bridge->parent, "Invalid data width\n");
d22b8ed9
MW		 1040 retval = -EINVAL;
1041 goto err_dwidth;
1042 }
1043
1044 /* Setup address space */
1045 temp_ctl &= ~TSI148_LCSR_OTAT_AMODE_M;
1046 switch (aspace) {
1047 case VME_A16:
1048 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A16;
1049 break;
1050 case VME_A24:
1051 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A24;
1052 break;
1053 case VME_A32:
1054 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A32;
1055 break;
1056 case VME_A64:
1057 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A64;
1058 break;
1059 case VME_CRCSR:
1060 temp_ctl |= TSI148_LCSR_OTAT_AMODE_CRCSR;
1061 break;
1062 case VME_USER1:
1063 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER1;
1064 break;
1065 case VME_USER2:
1066 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER2;
1067 break;
1068 case VME_USER3:
1069 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER3;
1070 break;
1071 case VME_USER4:
1072 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER4;
1073 break;
1074 default:
1075 spin_unlock(&(image->lock));
48d9356e 1076 dev_err(tsi148_bridge->parent, "Invalid address space\n");
d22b8ed9
MW		 1077 retval = -EINVAL;
1078 goto err_aspace;
1079 break;
1080 }
1081
1082 temp_ctl &= ~(3<<4);
1083 if (cycle & VME_SUPER)
1084 temp_ctl |= TSI148_LCSR_OTAT_SUP;
1085 if (cycle & VME_PROG)
1086 temp_ctl |= TSI148_LCSR_OTAT_PGM;
1087
1088 /* Setup mapping */
29848ac9 1089 iowrite32be(pci_base_high, bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9 1090 TSI148_LCSR_OFFSET_OTSAU);
29848ac9 1091 iowrite32be(pci_base_low, bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9 1092 TSI148_LCSR_OFFSET_OTSAL);
29848ac9 1093 iowrite32be(pci_bound_high, bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9 1094 TSI148_LCSR_OFFSET_OTEAU);
29848ac9 1095 iowrite32be(pci_bound_low, bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9 1096 TSI148_LCSR_OFFSET_OTEAL);
29848ac9 1097 iowrite32be(vme_offset_high, bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9 1098 TSI148_LCSR_OFFSET_OTOFU);
29848ac9 1099 iowrite32be(vme_offset_low, bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9
MW		 1100 TSI148_LCSR_OFFSET_OTOFL);
1101
d22b8ed9 1102 /* Write ctl reg without enable */
29848ac9 1103 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9
MW		 1104 TSI148_LCSR_OFFSET_OTAT);
1105
1106 if (enabled)
1107 temp_ctl |= TSI148_LCSR_OTAT_EN;
1108
29848ac9 1109 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9
MW		 1110 TSI148_LCSR_OFFSET_OTAT);
1111
1112 spin_unlock(&(image->lock));
1113 return 0;
1114
1115err_aspace:
1116err_dwidth:
1117err_gran:
1118 tsi148_free_resource(image);
1119err_res:
1120err_window:
1121 return retval;
1122
1123}
1124
1125/*
1126 * Set the attributes of an outbound window.
1127 *
1128 * XXX Not parsing prefetch information.
1129 */
7946328f 1130int __tsi148_master_get(struct vme_master_resource *image, int *enabled,
d22b8ed9
MW		 1131 unsigned long long *vme_base, unsigned long long *size,
1132 vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
1133{
1134 unsigned int i, ctl;
1135 unsigned int pci_base_low, pci_base_high;
1136 unsigned int pci_bound_low, pci_bound_high;
1137 unsigned int vme_offset_low, vme_offset_high;
1138
1139 unsigned long long pci_base, pci_bound, vme_offset;
29848ac9
MW		 1140 struct tsi148_driver *bridge;
1141
1142 bridge = image->parent->driver_priv;
d22b8ed9
MW		 1143
1144 i = image->number;
1145
29848ac9 1146 ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9
MW		 1147 TSI148_LCSR_OFFSET_OTAT);
1148
29848ac9 1149 pci_base_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9 1150 TSI148_LCSR_OFFSET_OTSAU);
29848ac9 1151 pci_base_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9 1152 TSI148_LCSR_OFFSET_OTSAL);
29848ac9 1153 pci_bound_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9 1154 TSI148_LCSR_OFFSET_OTEAU);
29848ac9 1155 pci_bound_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9 1156 TSI148_LCSR_OFFSET_OTEAL);
29848ac9 1157 vme_offset_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9 1158 TSI148_LCSR_OFFSET_OTOFU);
29848ac9 1159 vme_offset_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9
MW		 1160 TSI148_LCSR_OFFSET_OTOFL);
1161
1162 /* Convert 64-bit variables to 2x 32-bit variables */
1163 reg_join(pci_base_high, pci_base_low, &pci_base);
1164 reg_join(pci_bound_high, pci_bound_low, &pci_bound);
1165 reg_join(vme_offset_high, vme_offset_low, &vme_offset);
1166
1167 *vme_base = pci_base + vme_offset;
1168 *size = (unsigned long long)(pci_bound - pci_base) + 0x10000;
1169
1170 *enabled = 0;
1171 *aspace = 0;
1172 *cycle = 0;
1173 *dwidth = 0;
1174
1175 if (ctl & TSI148_LCSR_OTAT_EN)
1176 *enabled = 1;
1177
1178 /* Setup address space */
1179 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A16)
1180 *aspace |= VME_A16;
1181 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A24)
1182 *aspace |= VME_A24;
1183 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A32)
1184 *aspace |= VME_A32;
1185 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A64)
1186 *aspace |= VME_A64;
1187 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_CRCSR)
1188 *aspace |= VME_CRCSR;
1189 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER1)
1190 *aspace |= VME_USER1;
1191 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER2)
1192 *aspace |= VME_USER2;
1193 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER3)
1194 *aspace |= VME_USER3;
1195 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER4)
1196 *aspace |= VME_USER4;
1197
1198 /* Setup 2eSST speeds */
1199 if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_160)
1200 *cycle |= VME_2eSST160;
1201 if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_267)
1202 *cycle |= VME_2eSST267;
1203 if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_320)
1204 *cycle |= VME_2eSST320;
1205
1206 /* Setup cycle types */
7946328f 1207 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_SCT)
d22b8ed9 1208 *cycle |= VME_SCT;
7946328f 1209 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_BLT)
d22b8ed9 1210 *cycle |= VME_BLT;
7946328f 1211 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_MBLT)
d22b8ed9 1212 *cycle |= VME_MBLT;
7946328f 1213 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eVME)
d22b8ed9 1214 *cycle |= VME_2eVME;
7946328f 1215 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eSST)
d22b8ed9 1216 *cycle |= VME_2eSST;
7946328f 1217 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eSSTB)
d22b8ed9
MW		 1218 *cycle |= VME_2eSSTB;
1219
1220 if (ctl & TSI148_LCSR_OTAT_SUP)
1221 *cycle |= VME_SUPER;
1222 else
1223 *cycle |= VME_USER;
1224
1225 if (ctl & TSI148_LCSR_OTAT_PGM)
1226 *cycle |= VME_PROG;
1227 else
1228 *cycle |= VME_DATA;
1229
1230 /* Setup data width */
1231 if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_16)
1232 *dwidth = VME_D16;
1233 if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_32)
1234 *dwidth = VME_D32;
1235
1236 return 0;
1237}
1238
1239
7946328f 1240int tsi148_master_get(struct vme_master_resource *image, int *enabled,
d22b8ed9
MW		 1241 unsigned long long *vme_base, unsigned long long *size,
1242 vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
1243{
1244 int retval;
1245
1246 spin_lock(&(image->lock));
1247
1248 retval = __tsi148_master_get(image, enabled, vme_base, size, aspace,
1249 cycle, dwidth);
1250
1251 spin_unlock(&(image->lock));
1252
1253 return retval;
1254}
1255
1256ssize_t tsi148_master_read(struct vme_master_resource *image, void *buf,
1257 size_t count, loff_t offset)
1258{
1259 int retval, enabled;
1260 unsigned long long vme_base, size;
1261 vme_address_t aspace;
1262 vme_cycle_t cycle;
1263 vme_width_t dwidth;
1264 struct vme_bus_error *vme_err = NULL;
29848ac9
MW		 1265 struct vme_bridge *tsi148_bridge;
1266
1267 tsi148_bridge = image->parent;
d22b8ed9
MW		 1268
1269 spin_lock(&(image->lock));
1270
1271 memcpy_fromio(buf, image->kern_base + offset, (unsigned int)count);
1272 retval = count;
1273
1274 if (!err_chk)
1275 goto skip_chk;
1276
1277 __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, &cycle,
1278 &dwidth);
1279
29848ac9
MW		 1280 vme_err = tsi148_find_error(tsi148_bridge, aspace, vme_base + offset,
1281 count);
7946328f 1282 if (vme_err != NULL) {
d22b8ed9
MW		 1283 dev_err(image->parent->parent, "First VME read error detected "
1284 "an at address 0x%llx\n", vme_err->address);
1285 retval = vme_err->address - (vme_base + offset);
1286 /* Clear down save errors in this address range */
29848ac9
MW		 1287 tsi148_clear_errors(tsi148_bridge, aspace, vme_base + offset,
1288 count);
d22b8ed9
MW		 1289 }
1290
1291skip_chk:
1292 spin_unlock(&(image->lock));
1293
1294 return retval;
1295}
1296
1297
d22b8ed9
MW		 1298ssize_t tsi148_master_write(struct vme_master_resource *image, void *buf,
1299 size_t count, loff_t offset)
1300{
1301 int retval = 0, enabled;
1302 unsigned long long vme_base, size;
1303 vme_address_t aspace;
1304 vme_cycle_t cycle;
1305 vme_width_t dwidth;
1306
1307 struct vme_bus_error *vme_err = NULL;
29848ac9
MW		 1308 struct vme_bridge *tsi148_bridge;
1309 struct tsi148_driver *bridge;
1310
1311 tsi148_bridge = image->parent;
1312
1313 bridge = tsi148_bridge->driver_priv;
d22b8ed9
MW		 1314
1315 spin_lock(&(image->lock));
1316
1317 memcpy_toio(image->kern_base + offset, buf, (unsigned int)count);
1318 retval = count;
1319
1320 /*
1321 * Writes are posted. We need to do a read on the VME bus to flush out
1322 * all of the writes before we check for errors. We can't guarentee
1323 * that reading the data we have just written is safe. It is believed
1324 * that there isn't any read, write re-ordering, so we can read any
1325 * location in VME space, so lets read the Device ID from the tsi148's
1326 * own registers as mapped into CR/CSR space.
1327 *
1328 * We check for saved errors in the written address range/space.
1329 */
1330
1331 if (!err_chk)
1332 goto skip_chk;
1333
1334 /*
1335 * Get window info first, to maximise the time that the buffers may
1336 * fluch on their own
1337 */
1338 __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, &cycle,
1339 &dwidth);
1340
29848ac9 1341 ioread16(bridge->flush_image->kern_base + 0x7F000);
d22b8ed9 1342
29848ac9
MW		 1343 vme_err = tsi148_find_error(tsi148_bridge, aspace, vme_base + offset,
1344 count);
7946328f 1345 if (vme_err != NULL) {
48d9356e
MW		 1346 dev_warn(tsi148_bridge->parent, "First VME write error detected"
1347 " an at address 0x%llx\n", vme_err->address);
d22b8ed9
MW		 1348 retval = vme_err->address - (vme_base + offset);
1349 /* Clear down save errors in this address range */
29848ac9
MW		 1350 tsi148_clear_errors(tsi148_bridge, aspace, vme_base + offset,
1351 count);
d22b8ed9
MW		 1352 }
1353
1354skip_chk:
1355 spin_unlock(&(image->lock));
1356
1357 return retval;
1358}
1359
1360/*
1361 * Perform an RMW cycle on the VME bus.
1362 *
1363 * Requires a previously configured master window, returns final value.
1364 */
1365unsigned int tsi148_master_rmw(struct vme_master_resource *image,
1366 unsigned int mask, unsigned int compare, unsigned int swap,
1367 loff_t offset)
1368{
1369 unsigned long long pci_addr;
1370 unsigned int pci_addr_high, pci_addr_low;
1371 u32 tmp, result;
1372 int i;
29848ac9 1373 struct tsi148_driver *bridge;
d22b8ed9 1374
29848ac9 1375 bridge = image->parent->driver_priv;
d22b8ed9
MW		 1376
1377 /* Find the PCI address that maps to the desired VME address */
1378 i = image->number;
1379
1380 /* Locking as we can only do one of these at a time */
29848ac9 1381 mutex_lock(&(bridge->vme_rmw));
d22b8ed9
MW		 1382
1383 /* Lock image */
1384 spin_lock(&(image->lock));
1385
29848ac9 1386 pci_addr_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9 1387 TSI148_LCSR_OFFSET_OTSAU);
29848ac9 1388 pci_addr_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9
MW		 1389 TSI148_LCSR_OFFSET_OTSAL);
1390
1391 reg_join(pci_addr_high, pci_addr_low, &pci_addr);
1392 reg_split(pci_addr + offset, &pci_addr_high, &pci_addr_low);
1393
1394 /* Configure registers */
29848ac9
MW		 1395 iowrite32be(mask, bridge->base + TSI148_LCSR_RMWEN);
1396 iowrite32be(compare, bridge->base + TSI148_LCSR_RMWC);
1397 iowrite32be(swap, bridge->base + TSI148_LCSR_RMWS);
1398 iowrite32be(pci_addr_high, bridge->base + TSI148_LCSR_RMWAU);
1399 iowrite32be(pci_addr_low, bridge->base + TSI148_LCSR_RMWAL);
d22b8ed9
MW		 1400
1401 /* Enable RMW */
29848ac9 1402 tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);
d22b8ed9 1403 tmp |= TSI148_LCSR_VMCTRL_RMWEN;
29848ac9 1404 iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);
d22b8ed9
MW		 1405
1406 /* Kick process off with a read to the required address. */
1407 result = ioread32be(image->kern_base + offset);
1408
1409 /* Disable RMW */
29848ac9 1410 tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);
d22b8ed9 1411 tmp &= ~TSI148_LCSR_VMCTRL_RMWEN;
29848ac9 1412 iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);
d22b8ed9
MW		 1413
1414 spin_unlock(&(image->lock));
1415
29848ac9 1416 mutex_unlock(&(bridge->vme_rmw));
d22b8ed9
MW		 1417
1418 return result;
1419}
1420
48d9356e
MW		 1421static int tsi148_dma_set_vme_src_attributes(struct device *dev, u32 *attr,
1422 vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth)
d22b8ed9
MW		 1423{
1424 /* Setup 2eSST speeds */
1425 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
1426 case VME_2eSST160:
1427 *attr |= TSI148_LCSR_DSAT_2eSSTM_160;
1428 break;
1429 case VME_2eSST267:
1430 *attr |= TSI148_LCSR_DSAT_2eSSTM_267;
1431 break;
1432 case VME_2eSST320:
1433 *attr |= TSI148_LCSR_DSAT_2eSSTM_320;
1434 break;
1435 }
1436
1437 /* Setup cycle types */
7946328f 1438 if (cycle & VME_SCT)
d22b8ed9 1439 *attr |= TSI148_LCSR_DSAT_TM_SCT;
7946328f
MW		 1440
1441 if (cycle & VME_BLT)
d22b8ed9 1442 *attr |= TSI148_LCSR_DSAT_TM_BLT;
7946328f
MW		 1443
1444 if (cycle & VME_MBLT)
d22b8ed9 1445 *attr |= TSI148_LCSR_DSAT_TM_MBLT;
7946328f
MW		 1446
1447 if (cycle & VME_2eVME)
d22b8ed9 1448 *attr |= TSI148_LCSR_DSAT_TM_2eVME;
7946328f
MW		 1449
1450 if (cycle & VME_2eSST)
d22b8ed9 1451 *attr |= TSI148_LCSR_DSAT_TM_2eSST;
7946328f 1452
d22b8ed9 1453 if (cycle & VME_2eSSTB) {
48d9356e
MW		 1454 dev_err(dev, "Currently not setting Broadcast Select "
1455 "Registers\n");
d22b8ed9
MW		 1456 *attr |= TSI148_LCSR_DSAT_TM_2eSSTB;
1457 }
1458
1459 /* Setup data width */
1460 switch (dwidth) {
1461 case VME_D16:
1462 *attr |= TSI148_LCSR_DSAT_DBW_16;
1463 break;
1464 case VME_D32:
1465 *attr |= TSI148_LCSR_DSAT_DBW_32;
1466 break;
1467 default:
48d9356e 1468 dev_err(dev, "Invalid data width\n");
d22b8ed9
MW		 1469 return -EINVAL;
1470 }
1471
1472 /* Setup address space */
1473 switch (aspace) {
1474 case VME_A16:
1475 *attr |= TSI148_LCSR_DSAT_AMODE_A16;
1476 break;
1477 case VME_A24:
1478 *attr |= TSI148_LCSR_DSAT_AMODE_A24;
1479 break;
1480 case VME_A32:
1481 *attr |= TSI148_LCSR_DSAT_AMODE_A32;
1482 break;
1483 case VME_A64:
1484 *attr |= TSI148_LCSR_DSAT_AMODE_A64;
1485 break;
1486 case VME_CRCSR:
1487 *attr |= TSI148_LCSR_DSAT_AMODE_CRCSR;
1488 break;
1489 case VME_USER1:
1490 *attr |= TSI148_LCSR_DSAT_AMODE_USER1;
1491 break;
1492 case VME_USER2:
1493 *attr |= TSI148_LCSR_DSAT_AMODE_USER2;
1494 break;
1495 case VME_USER3:
1496 *attr |= TSI148_LCSR_DSAT_AMODE_USER3;
1497 break;
1498 case VME_USER4:
1499 *attr |= TSI148_LCSR_DSAT_AMODE_USER4;
1500 break;
1501 default:
48d9356e 1502 dev_err(dev, "Invalid address space\n");
d22b8ed9
MW		 1503 return -EINVAL;
1504 break;
1505 }
1506
1507 if (cycle & VME_SUPER)
1508 *attr |= TSI148_LCSR_DSAT_SUP;
1509 if (cycle & VME_PROG)
1510 *attr |= TSI148_LCSR_DSAT_PGM;
1511
1512 return 0;
1513}
1514
48d9356e
MW		 1515static int tsi148_dma_set_vme_dest_attributes(struct device *dev, u32 *attr,
1516 vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth)
d22b8ed9
MW		 1517{
1518 /* Setup 2eSST speeds */
1519 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
1520 case VME_2eSST160:
1521 *attr |= TSI148_LCSR_DDAT_2eSSTM_160;
1522 break;
1523 case VME_2eSST267:
1524 *attr |= TSI148_LCSR_DDAT_2eSSTM_267;
1525 break;
1526 case VME_2eSST320:
1527 *attr |= TSI148_LCSR_DDAT_2eSSTM_320;
1528 break;
1529 }
1530
1531 /* Setup cycle types */
7946328f 1532 if (cycle & VME_SCT)
d22b8ed9 1533 *attr |= TSI148_LCSR_DDAT_TM_SCT;
7946328f
MW		 1534
1535 if (cycle & VME_BLT)
d22b8ed9 1536 *attr |= TSI148_LCSR_DDAT_TM_BLT;
7946328f
MW		 1537
1538 if (cycle & VME_MBLT)
d22b8ed9 1539 *attr |= TSI148_LCSR_DDAT_TM_MBLT;
7946328f
MW		 1540
1541 if (cycle & VME_2eVME)
d22b8ed9 1542 *attr |= TSI148_LCSR_DDAT_TM_2eVME;
7946328f
MW		 1543
1544 if (cycle & VME_2eSST)
d22b8ed9 1545 *attr |= TSI148_LCSR_DDAT_TM_2eSST;
7946328f 1546
d22b8ed9 1547 if (cycle & VME_2eSSTB) {
48d9356e
MW		 1548 dev_err(dev, "Currently not setting Broadcast Select "
1549 "Registers\n");
d22b8ed9
MW		 1550 *attr |= TSI148_LCSR_DDAT_TM_2eSSTB;
1551 }
1552
1553 /* Setup data width */
1554 switch (dwidth) {
1555 case VME_D16:
1556 *attr |= TSI148_LCSR_DDAT_DBW_16;
1557 break;
1558 case VME_D32:
1559 *attr |= TSI148_LCSR_DDAT_DBW_32;
1560 break;
1561 default:
48d9356e 1562 dev_err(dev, "Invalid data width\n");
d22b8ed9
MW		 1563 return -EINVAL;
1564 }
1565
1566 /* Setup address space */
1567 switch (aspace) {
1568 case VME_A16:
1569 *attr |= TSI148_LCSR_DDAT_AMODE_A16;
1570 break;
1571 case VME_A24:
1572 *attr |= TSI148_LCSR_DDAT_AMODE_A24;
1573 break;
1574 case VME_A32:
1575 *attr |= TSI148_LCSR_DDAT_AMODE_A32;
1576 break;
1577 case VME_A64:
1578 *attr |= TSI148_LCSR_DDAT_AMODE_A64;
1579 break;
1580 case VME_CRCSR:
1581 *attr |= TSI148_LCSR_DDAT_AMODE_CRCSR;
1582 break;
1583 case VME_USER1:
1584 *attr |= TSI148_LCSR_DDAT_AMODE_USER1;
1585 break;
1586 case VME_USER2:
1587 *attr |= TSI148_LCSR_DDAT_AMODE_USER2;
1588 break;
1589 case VME_USER3:
1590 *attr |= TSI148_LCSR_DDAT_AMODE_USER3;
1591 break;
1592 case VME_USER4:
1593 *attr |= TSI148_LCSR_DDAT_AMODE_USER4;
1594 break;
1595 default:
48d9356e 1596 dev_err(dev, "Invalid address space\n");
d22b8ed9
MW		 1597 return -EINVAL;
1598 break;
1599 }
1600
1601 if (cycle & VME_SUPER)
1602 *attr |= TSI148_LCSR_DDAT_SUP;
1603 if (cycle & VME_PROG)
1604 *attr |= TSI148_LCSR_DDAT_PGM;
1605
1606 return 0;
1607}
1608
1609/*
1610 * Add a link list descriptor to the list
d22b8ed9 1611 */
7946328f 1612int tsi148_dma_list_add(struct vme_dma_list *list, struct vme_dma_attr *src,
d22b8ed9
MW		 1613 struct vme_dma_attr *dest, size_t count)
1614{
1615 struct tsi148_dma_entry *entry, *prev;
1616 u32 address_high, address_low;
1617 struct vme_dma_pattern *pattern_attr;
1618 struct vme_dma_pci *pci_attr;
1619 struct vme_dma_vme *vme_attr;
1620 dma_addr_t desc_ptr;
1621 int retval = 0;
48d9356e
MW		 1622 struct vme_bridge *tsi148_bridge;
1623
1624 tsi148_bridge = list->parent->parent;
d22b8ed9 1625
bb9ea89e 1626 /* Descriptor must be aligned on 64-bit boundaries */
7946328f 1627 entry = kmalloc(sizeof(struct tsi148_dma_entry), GFP_KERNEL);
d22b8ed9 1628 if (entry == NULL) {
48d9356e
MW		 1629 dev_err(tsi148_bridge->parent, "Failed to allocate memory for "
1630 "dma resource structure\n");
d22b8ed9
MW		 1631 retval = -ENOMEM;
1632 goto err_mem;
1633 }
1634
1635 /* Test descriptor alignment */
1636 if ((unsigned long)&(entry->descriptor) & 0x7) {
48d9356e
MW		 1637 dev_err(tsi148_bridge->parent, "Descriptor not aligned to 8 "
1638 "byte boundary as required: %p\n",
1639 &(entry->descriptor));
d22b8ed9
MW		 1640 retval = -EINVAL;
1641 goto err_align;
1642 }
1643
1644 /* Given we are going to fill out the structure, we probably don't
1645 * need to zero it, but better safe than sorry for now.
1646 */
1647 memset(&(entry->descriptor), 0, sizeof(struct tsi148_dma_descriptor));
1648
1649 /* Fill out source part */
1650 switch (src->type) {
1651 case VME_DMA_PATTERN:
1652 pattern_attr = (struct vme_dma_pattern *)src->private;
1653
1654 entry->descriptor.dsal = pattern_attr->pattern;
1655 entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_PAT;
1656 /* Default behaviour is 32 bit pattern */
7946328f 1657 if (pattern_attr->type & VME_DMA_PATTERN_BYTE)
d22b8ed9 1658 entry->descriptor.dsat |= TSI148_LCSR_DSAT_PSZ;
7946328f 1659
d22b8ed9 1660 /* It seems that the default behaviour is to increment */
7946328f 1661 if ((pattern_attr->type & VME_DMA_PATTERN_INCREMENT) == 0)
d22b8ed9 1662 entry->descriptor.dsat |= TSI148_LCSR_DSAT_NIN;
7946328f 1663
d22b8ed9
MW		 1664 break;
1665 case VME_DMA_PCI:
1666 pci_attr = (struct vme_dma_pci *)src->private;
1667
1668 reg_split((unsigned long long)pci_attr->address, &address_high,
1669 &address_low);
1670 entry->descriptor.dsau = address_high;
1671 entry->descriptor.dsal = address_low;
1672 entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_PCI;
1673 break;
1674 case VME_DMA_VME:
1675 vme_attr = (struct vme_dma_vme *)src->private;
1676
1677 reg_split((unsigned long long)vme_attr->address, &address_high,
1678 &address_low);
1679 entry->descriptor.dsau = address_high;
1680 entry->descriptor.dsal = address_low;
1681 entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_VME;
1682
1683 retval = tsi148_dma_set_vme_src_attributes(
48d9356e
MW		 1684 tsi148_bridge->parent, &(entry->descriptor.dsat),
1685 vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth);
7946328f 1686 if (retval < 0)
d22b8ed9
MW		 1687 goto err_source;
1688 break;
1689 default:
48d9356e 1690 dev_err(tsi148_bridge->parent, "Invalid source type\n");
d22b8ed9
MW		 1691 retval = -EINVAL;
1692 goto err_source;
1693 break;
1694 }
1695
1696 /* Assume last link - this will be over-written by adding another */
1697 entry->descriptor.dnlau = 0;
1698 entry->descriptor.dnlal = TSI148_LCSR_DNLAL_LLA;
1699
1700
1701 /* Fill out destination part */
1702 switch (dest->type) {
1703 case VME_DMA_PCI:
1704 pci_attr = (struct vme_dma_pci *)dest->private;
1705
1706 reg_split((unsigned long long)pci_attr->address, &address_high,
1707 &address_low);
1708 entry->descriptor.ddau = address_high;
1709 entry->descriptor.ddal = address_low;
1710 entry->descriptor.ddat = TSI148_LCSR_DDAT_TYP_PCI;
1711 break;
1712 case VME_DMA_VME:
1713 vme_attr = (struct vme_dma_vme *)dest->private;
1714
1715 reg_split((unsigned long long)vme_attr->address, &address_high,
1716 &address_low);
1717 entry->descriptor.ddau = address_high;
1718 entry->descriptor.ddal = address_low;
1719 entry->descriptor.ddat = TSI148_LCSR_DDAT_TYP_VME;
1720
1721 retval = tsi148_dma_set_vme_dest_attributes(
48d9356e
MW		 1722 tsi148_bridge->parent, &(entry->descriptor.ddat),
1723 vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth);
7946328f 1724 if (retval < 0)
d22b8ed9
MW		 1725 goto err_dest;
1726 break;
1727 default:
48d9356e 1728 dev_err(tsi148_bridge->parent, "Invalid destination type\n");
d22b8ed9
MW		 1729 retval = -EINVAL;
1730 goto err_dest;
1731 break;
1732 }
1733
1734 /* Fill out count */
1735 entry->descriptor.dcnt = (u32)count;
1736
1737 /* Add to list */
1738 list_add_tail(&(entry->list), &(list->entries));
1739
1740 /* Fill out previous descriptors "Next Address" */
7946328f 1741 if (entry->list.prev != &(list->entries)) {
d22b8ed9
MW		 1742 prev = list_entry(entry->list.prev, struct tsi148_dma_entry,
1743 list);
1744 /* We need the bus address for the pointer */
1745 desc_ptr = virt_to_bus(&(entry->descriptor));
1746 reg_split(desc_ptr, &(prev->descriptor.dnlau),
1747 &(prev->descriptor.dnlal));
1748 }
1749
1750 return 0;
1751
1752err_dest:
1753err_source:
1754err_align:
1755 kfree(entry);
1756err_mem:
1757 return retval;
1758}
1759
1760/*
1761 * Check to see if the provided DMA channel is busy.
1762 */
29848ac9 1763static int tsi148_dma_busy(struct vme_bridge *tsi148_bridge, int channel)
d22b8ed9
MW		 1764{
1765 u32 tmp;
29848ac9
MW		 1766 struct tsi148_driver *bridge;
1767
1768 bridge = tsi148_bridge->driver_priv;
d22b8ed9 1769
29848ac9 1770 tmp = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
d22b8ed9
MW		 1771 TSI148_LCSR_OFFSET_DSTA);
1772
1773 if (tmp & TSI148_LCSR_DSTA_BSY)
1774 return 0;
1775 else
1776 return 1;
1777
1778}
1779
1780/*
1781 * Execute a previously generated link list
1782 *
1783 * XXX Need to provide control register configuration.
1784 */
1785int tsi148_dma_list_exec(struct vme_dma_list *list)
1786{
1787 struct vme_dma_resource *ctrlr;
1788 int channel, retval = 0;
1789 struct tsi148_dma_entry *entry;
1790 dma_addr_t bus_addr;
1791 u32 bus_addr_high, bus_addr_low;
1792 u32 val, dctlreg = 0;
48d9356e 1793 struct vme_bridge *tsi148_bridge;
29848ac9 1794 struct tsi148_driver *bridge;
d22b8ed9
MW		 1795
1796 ctrlr = list->parent;
1797
48d9356e
MW		 1798 tsi148_bridge = ctrlr->parent;
1799
1800 bridge = tsi148_bridge->driver_priv;
29848ac9 1801
400822fe 1802 mutex_lock(&(ctrlr->mtx));
d22b8ed9
MW		 1803
1804 channel = ctrlr->number;
1805
7946328f 1806 if (!list_empty(&(ctrlr->running))) {
d22b8ed9
MW		 1807 /*
1808 * XXX We have an active DMA transfer and currently haven't
1809 * sorted out the mechanism for "pending" DMA transfers.
1810 * Return busy.
1811 */
1812 /* Need to add to pending here */
400822fe 1813 mutex_unlock(&(ctrlr->mtx));
d22b8ed9
MW		 1814 return -EBUSY;
1815 } else {
1816 list_add(&(list->list), &(ctrlr->running));
1817 }
d22b8ed9
MW		 1818
1819 /* Get first bus address and write into registers */
1820 entry = list_first_entry(&(list->entries), struct tsi148_dma_entry,
1821 list);
1822
1823 bus_addr = virt_to_bus(&(entry->descriptor));
1824
400822fe 1825 mutex_unlock(&(ctrlr->mtx));
d22b8ed9
MW		 1826
1827 reg_split(bus_addr, &bus_addr_high, &bus_addr_low);
1828
29848ac9 1829 iowrite32be(bus_addr_high, bridge->base +
d22b8ed9 1830 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAU);
29848ac9 1831 iowrite32be(bus_addr_low, bridge->base +
d22b8ed9
MW		 1832 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAL);
1833
1834 /* Start the operation */
29848ac9 1835 iowrite32be(dctlreg | TSI148_LCSR_DCTL_DGO, bridge->base +
d22b8ed9
MW		 1836 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCTL);
1837
29848ac9
MW		 1838 wait_event_interruptible(bridge->dma_queue[channel],
1839 tsi148_dma_busy(ctrlr->parent, channel));
d22b8ed9
MW		 1840 /*
1841 * Read status register, this register is valid until we kick off a
1842 * new transfer.
1843 */
29848ac9 1844 val = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
d22b8ed9
MW		 1845 TSI148_LCSR_OFFSET_DSTA);
1846
1847 if (val & TSI148_LCSR_DSTA_VBE) {
48d9356e 1848 dev_err(tsi148_bridge->parent, "DMA Error. DSTA=%08X\n", val);
d22b8ed9
MW		 1849 retval = -EIO;
1850 }
1851
1852 /* Remove list from running list */
400822fe 1853 mutex_lock(&(ctrlr->mtx));
d22b8ed9 1854 list_del(&(list->list));
400822fe 1855 mutex_unlock(&(ctrlr->mtx));
d22b8ed9
MW		 1856
1857 return retval;
1858}
1859
1860/*
1861 * Clean up a previously generated link list
1862 *
1863 * We have a separate function, don't assume that the chain can't be reused.
1864 */
1865int tsi148_dma_list_empty(struct vme_dma_list *list)
1866{
1867 struct list_head *pos, *temp;
7946328f 1868 struct tsi148_dma_entry *entry;
d22b8ed9
MW		 1869
1870 /* detach and free each entry */
1871 list_for_each_safe(pos, temp, &(list->entries)) {
1872 list_del(pos);
1873 entry = list_entry(pos, struct tsi148_dma_entry, list);
1874 kfree(entry);
1875 }
1876
7946328f 1877 return 0;
d22b8ed9
MW		 1878}
1879
1880/*
1881 * All 4 location monitors reside at the same base - this is therefore a
1882 * system wide configuration.
1883 *
1884 * This does not enable the LM monitor - that should be done when the first
1885 * callback is attached and disabled when the last callback is removed.
1886 */
42fb5031
MW		 1887int tsi148_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base,
1888 vme_address_t aspace, vme_cycle_t cycle)
d22b8ed9
MW		 1889{
1890 u32 lm_base_high, lm_base_low, lm_ctl = 0;
1891 int i;
48d9356e 1892 struct vme_bridge *tsi148_bridge;
29848ac9
MW		 1893 struct tsi148_driver *bridge;
1894
48d9356e
MW		 1895 tsi148_bridge = lm->parent;
1896
1897 bridge = tsi148_bridge->driver_priv;
d22b8ed9 1898
42fb5031 1899 mutex_lock(&(lm->mtx));
d22b8ed9
MW		 1900
1901 /* If we already have a callback attached, we can't move it! */
42fb5031 1902 for (i = 0; i < lm->monitors; i++) {
29848ac9 1903 if (bridge->lm_callback[i] != NULL) {
42fb5031 1904 mutex_unlock(&(lm->mtx));
48d9356e
MW		 1905 dev_err(tsi148_bridge->parent, "Location monitor "
1906 "callback attached, can't reset\n");
d22b8ed9
MW		 1907 return -EBUSY;
1908 }
1909 }
1910
1911 switch (aspace) {
1912 case VME_A16:
1913 lm_ctl |= TSI148_LCSR_LMAT_AS_A16;
1914 break;
1915 case VME_A24:
1916 lm_ctl |= TSI148_LCSR_LMAT_AS_A24;
1917 break;
1918 case VME_A32:
1919 lm_ctl |= TSI148_LCSR_LMAT_AS_A32;
1920 break;
1921 case VME_A64:
1922 lm_ctl |= TSI148_LCSR_LMAT_AS_A64;
1923 break;
1924 default:
42fb5031 1925 mutex_unlock(&(lm->mtx));
48d9356e 1926 dev_err(tsi148_bridge->parent, "Invalid address space\n");
d22b8ed9
MW		 1927 return -EINVAL;
1928 break;
1929 }
1930
1931 if (cycle & VME_SUPER)
1932 lm_ctl |= TSI148_LCSR_LMAT_SUPR ;
1933 if (cycle & VME_USER)
1934 lm_ctl |= TSI148_LCSR_LMAT_NPRIV;
1935 if (cycle & VME_PROG)
1936 lm_ctl |= TSI148_LCSR_LMAT_PGM;
1937 if (cycle & VME_DATA)
1938 lm_ctl |= TSI148_LCSR_LMAT_DATA;
1939
1940 reg_split(lm_base, &lm_base_high, &lm_base_low);
1941
29848ac9
MW		 1942 iowrite32be(lm_base_high, bridge->base + TSI148_LCSR_LMBAU);
1943 iowrite32be(lm_base_low, bridge->base + TSI148_LCSR_LMBAL);
1944 iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);
d22b8ed9 1945
42fb5031 1946 mutex_unlock(&(lm->mtx));
d22b8ed9
MW		 1947
1948 return 0;
1949}
1950
1951/* Get configuration of the callback monitor and return whether it is enabled
1952 * or disabled.
1953 */
42fb5031
MW		 1954int tsi148_lm_get(struct vme_lm_resource *lm, unsigned long long *lm_base,
1955 vme_address_t *aspace, vme_cycle_t *cycle)
d22b8ed9
MW		 1956{
1957 u32 lm_base_high, lm_base_low, lm_ctl, enabled = 0;
29848ac9
MW		 1958 struct tsi148_driver *bridge;
1959
1960 bridge = lm->parent->driver_priv;
d22b8ed9 1961
42fb5031 1962 mutex_lock(&(lm->mtx));
d22b8ed9 1963
29848ac9
MW		 1964 lm_base_high = ioread32be(bridge->base + TSI148_LCSR_LMBAU);
1965 lm_base_low = ioread32be(bridge->base + TSI148_LCSR_LMBAL);
1966 lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);
d22b8ed9
MW		 1967
1968 reg_join(lm_base_high, lm_base_low, lm_base);
1969
1970 if (lm_ctl & TSI148_LCSR_LMAT_EN)
1971 enabled = 1;
1972
7946328f 1973 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A16)
d22b8ed9 1974 *aspace |= VME_A16;
7946328f
MW		 1975
1976 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A24)
d22b8ed9 1977 *aspace |= VME_A24;
7946328f
MW		 1978
1979 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A32)
d22b8ed9 1980 *aspace |= VME_A32;
7946328f
MW		 1981
1982 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A64)
d22b8ed9 1983 *aspace |= VME_A64;
7946328f 1984
d22b8ed9
MW		 1985
1986 if (lm_ctl & TSI148_LCSR_LMAT_SUPR)
1987 *cycle |= VME_SUPER;
1988 if (lm_ctl & TSI148_LCSR_LMAT_NPRIV)
1989 *cycle |= VME_USER;
1990 if (lm_ctl & TSI148_LCSR_LMAT_PGM)
1991 *cycle |= VME_PROG;
1992 if (lm_ctl & TSI148_LCSR_LMAT_DATA)
1993 *cycle |= VME_DATA;
1994
42fb5031 1995 mutex_unlock(&(lm->mtx));
d22b8ed9
MW		 1996
1997 return enabled;
1998}
1999
2000/*
2001 * Attach a callback to a specific location monitor.
2002 *
2003 * Callback will be passed the monitor triggered.
2004 */
42fb5031
MW		 2005int tsi148_lm_attach(struct vme_lm_resource *lm, int monitor,
2006 void (*callback)(int))
d22b8ed9
MW		 2007{
2008 u32 lm_ctl, tmp;
48d9356e 2009 struct vme_bridge *tsi148_bridge;
29848ac9
MW		 2010 struct tsi148_driver *bridge;
2011
48d9356e
MW		 2012 tsi148_bridge = lm->parent;
2013
2014 bridge = tsi148_bridge->driver_priv;
d22b8ed9 2015
42fb5031 2016 mutex_lock(&(lm->mtx));
d22b8ed9
MW		 2017
2018 /* Ensure that the location monitor is configured - need PGM or DATA */
29848ac9 2019 lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);
d22b8ed9 2020 if ((lm_ctl & (TSI148_LCSR_LMAT_PGM | TSI148_LCSR_LMAT_DATA)) == 0) {
42fb5031 2021 mutex_unlock(&(lm->mtx));
48d9356e
MW		 2022 dev_err(tsi148_bridge->parent, "Location monitor not properly "
2023 "configured\n");
d22b8ed9
MW		 2024 return -EINVAL;
2025 }
2026
2027 /* Check that a callback isn't already attached */
29848ac9 2028 if (bridge->lm_callback[monitor] != NULL) {
42fb5031 2029 mutex_unlock(&(lm->mtx));
48d9356e 2030 dev_err(tsi148_bridge->parent, "Existing callback attached\n");
d22b8ed9
MW		 2031 return -EBUSY;
2032 }
2033
2034 /* Attach callback */
29848ac9 2035 bridge->lm_callback[monitor] = callback;
d22b8ed9
MW		 2036
2037 /* Enable Location Monitor interrupt */
29848ac9 2038 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
d22b8ed9 2039 tmp |= TSI148_LCSR_INTEN_LMEN[monitor];
29848ac9 2040 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
d22b8ed9 2041
29848ac9 2042 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
d22b8ed9 2043 tmp |= TSI148_LCSR_INTEO_LMEO[monitor];
29848ac9 2044 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
d22b8ed9
MW		 2045
2046 /* Ensure that global Location Monitor Enable set */
2047 if ((lm_ctl & TSI148_LCSR_LMAT_EN) == 0) {
2048 lm_ctl |= TSI148_LCSR_LMAT_EN;
29848ac9 2049 iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);
d22b8ed9
MW		 2050 }
2051
42fb5031 2052 mutex_unlock(&(lm->mtx));
d22b8ed9
MW		 2053
2054 return 0;
2055}
2056
2057/*
2058 * Detach a callback function forn a specific location monitor.
2059 */
42fb5031 2060int tsi148_lm_detach(struct vme_lm_resource *lm, int monitor)
d22b8ed9
MW		 2061{
2062 u32 lm_en, tmp;
29848ac9
MW		 2063 struct tsi148_driver *bridge;
2064
2065 bridge = lm->parent->driver_priv;
d22b8ed9 2066
42fb5031 2067 mutex_lock(&(lm->mtx));
d22b8ed9
MW		 2068
2069 /* Disable Location Monitor and ensure previous interrupts are clear */
29848ac9 2070 lm_en = ioread32be(bridge->base + TSI148_LCSR_INTEN);
d22b8ed9 2071 lm_en &= ~TSI148_LCSR_INTEN_LMEN[monitor];
29848ac9 2072 iowrite32be(lm_en, bridge->base + TSI148_LCSR_INTEN);
d22b8ed9 2073
29848ac9 2074 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
d22b8ed9 2075 tmp &= ~TSI148_LCSR_INTEO_LMEO[monitor];
29848ac9 2076 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
d22b8ed9
MW		 2077
2078 iowrite32be(TSI148_LCSR_INTC_LMC[monitor],
29848ac9 2079 bridge->base + TSI148_LCSR_INTC);
d22b8ed9
MW		 2080
2081 /* Detach callback */
29848ac9 2082 bridge->lm_callback[monitor] = NULL;
d22b8ed9
MW		 2083
2084 /* If all location monitors disabled, disable global Location Monitor */
2085 if ((lm_en & (TSI148_LCSR_INTS_LM0S | TSI148_LCSR_INTS_LM1S |
2086 TSI148_LCSR_INTS_LM2S | TSI148_LCSR_INTS_LM3S)) == 0) {
29848ac9 2087 tmp = ioread32be(bridge->base + TSI148_LCSR_LMAT);
d22b8ed9 2088 tmp &= ~TSI148_LCSR_LMAT_EN;
29848ac9 2089 iowrite32be(tmp, bridge->base + TSI148_LCSR_LMAT);
d22b8ed9
MW		 2090 }
2091
42fb5031 2092 mutex_unlock(&(lm->mtx));
d22b8ed9
MW		 2093
2094 return 0;
2095}
2096
2097/*
2098 * Determine Geographical Addressing
2099 */
29848ac9 2100int tsi148_slot_get(struct vme_bridge *tsi148_bridge)
d22b8ed9 2101{
7946328f 2102 u32 slot = 0;
29848ac9
MW		 2103 struct tsi148_driver *bridge;
2104
2105 bridge = tsi148_bridge->driver_priv;
d22b8ed9 2106
638f199d 2107 if (!geoid) {
29848ac9 2108 slot = ioread32be(bridge->base + TSI148_LCSR_VSTAT);
638f199d
MW		 2109 slot = slot & TSI148_LCSR_VSTAT_GA_M;
2110 } else
2111 slot = geoid;
2112
d22b8ed9
MW		 2113 return (int)slot;
2114}
2115
2116static int __init tsi148_init(void)
2117{
2118 return pci_register_driver(&tsi148_driver);
2119}
2120
2121/*
2122 * Configure CR/CSR space
2123 *
2124 * Access to the CR/CSR can be configured at power-up. The location of the
2125 * CR/CSR registers in the CR/CSR address space is determined by the boards
2126 * Auto-ID or Geographic address. This function ensures that the window is
2127 * enabled at an offset consistent with the boards geopgraphic address.
2128 *
2129 * Each board has a 512kB window, with the highest 4kB being used for the
2130 * boards registers, this means there is a fix length 508kB window which must
2131 * be mapped onto PCI memory.
2132 */
29848ac9
MW		 2133static int tsi148_crcsr_init(struct vme_bridge *tsi148_bridge,
2134 struct pci_dev *pdev)
d22b8ed9
MW		 2135{
2136 u32 cbar, crat, vstat;
2137 u32 crcsr_bus_high, crcsr_bus_low;
2138 int retval;
29848ac9
MW		 2139 struct tsi148_driver *bridge;
2140
2141 bridge = tsi148_bridge->driver_priv;
d22b8ed9
MW		 2142
2143 /* Allocate mem for CR/CSR image */
29848ac9
MW		 2144 bridge->crcsr_kernel = pci_alloc_consistent(pdev, VME_CRCSR_BUF_SIZE,
2145 &(bridge->crcsr_bus));
2146 if (bridge->crcsr_kernel == NULL) {
48d9356e
MW		 2147 dev_err(tsi148_bridge->parent, "Failed to allocate memory for "
2148 "CR/CSR image\n");
d22b8ed9
MW		 2149 return -ENOMEM;
2150 }
2151
29848ac9 2152 memset(bridge->crcsr_kernel, 0, VME_CRCSR_BUF_SIZE);
d22b8ed9 2153
29848ac9 2154 reg_split(bridge->crcsr_bus, &crcsr_bus_high, &crcsr_bus_low);
d22b8ed9 2155
29848ac9
MW		 2156 iowrite32be(crcsr_bus_high, bridge->base + TSI148_LCSR_CROU);
2157 iowrite32be(crcsr_bus_low, bridge->base + TSI148_LCSR_CROL);
d22b8ed9
MW		 2158
2159 /* Ensure that the CR/CSR is configured at the correct offset */
29848ac9 2160 cbar = ioread32be(bridge->base + TSI148_CBAR);
d22b8ed9
MW		 2161 cbar = (cbar & TSI148_CRCSR_CBAR_M)>>3;
2162
29848ac9 2163 vstat = tsi148_slot_get(tsi148_bridge);
d22b8ed9
MW		 2164
2165 if (cbar != vstat) {
638f199d 2166 cbar = vstat;
48d9356e 2167 dev_info(tsi148_bridge->parent, "Setting CR/CSR offset\n");
29848ac9 2168 iowrite32be(cbar<<3, bridge->base + TSI148_CBAR);
d22b8ed9 2169 }
48d9356e 2170 dev_info(tsi148_bridge->parent, "CR/CSR Offset: %d\n", cbar);
d22b8ed9 2171
29848ac9 2172 crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);
d22b8ed9 2173 if (crat & TSI148_LCSR_CRAT_EN) {
48d9356e 2174 dev_info(tsi148_bridge->parent, "Enabling CR/CSR space\n");
d22b8ed9 2175 iowrite32be(crat | TSI148_LCSR_CRAT_EN,
29848ac9 2176 bridge->base + TSI148_LCSR_CRAT);
d22b8ed9 2177 } else
48d9356e 2178 dev_info(tsi148_bridge->parent, "CR/CSR already enabled\n");
d22b8ed9
MW		 2179
2180 /* If we want flushed, error-checked writes, set up a window
2181 * over the CR/CSR registers. We read from here to safely flush
2182 * through VME writes.
2183 */
7946328f 2184 if (err_chk) {
29848ac9
MW		 2185 retval = tsi148_master_set(bridge->flush_image, 1,
2186 (vstat * 0x80000), 0x80000, VME_CRCSR, VME_SCT,
2187 VME_D16);
d22b8ed9 2188 if (retval)
48d9356e
MW		 2189 dev_err(tsi148_bridge->parent, "Configuring flush image"
2190 " failed\n");
d22b8ed9
MW		 2191 }
2192
2193 return 0;
2194
2195}
2196
29848ac9
MW		 2197static void tsi148_crcsr_exit(struct vme_bridge *tsi148_bridge,
2198 struct pci_dev *pdev)
d22b8ed9
MW		 2199{
2200 u32 crat;
29848ac9
MW		 2201 struct tsi148_driver *bridge;
2202
2203 bridge = tsi148_bridge->driver_priv;
d22b8ed9
MW		 2204
2205 /* Turn off CR/CSR space */
29848ac9 2206 crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);
d22b8ed9 2207 iowrite32be(crat & ~TSI148_LCSR_CRAT_EN,
29848ac9 2208 bridge->base + TSI148_LCSR_CRAT);
d22b8ed9
MW		 2209
2210 /* Free image */
29848ac9
MW		 2211 iowrite32be(0, bridge->base + TSI148_LCSR_CROU);
2212 iowrite32be(0, bridge->base + TSI148_LCSR_CROL);
d22b8ed9 2213
29848ac9
MW		 2214 pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel,
2215 bridge->crcsr_bus);
d22b8ed9
MW		 2216}
2217
2218static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2219{
2220 int retval, i, master_num;
2221 u32 data;
2222 struct list_head *pos = NULL;
29848ac9
MW		 2223 struct vme_bridge *tsi148_bridge;
2224 struct tsi148_driver *tsi148_device;
d22b8ed9
MW		 2225 struct vme_master_resource *master_image;
2226 struct vme_slave_resource *slave_image;
2227 struct vme_dma_resource *dma_ctrlr;
42fb5031 2228 struct vme_lm_resource *lm;
d22b8ed9
MW		 2229
2230 /* If we want to support more than one of each bridge, we need to
2231 * dynamically generate this so we get one per device
2232 */
7a6cb0d5 2233 tsi148_bridge = kzalloc(sizeof(struct vme_bridge), GFP_KERNEL);
d22b8ed9
MW		 2234 if (tsi148_bridge == NULL) {
2235 dev_err(&pdev->dev, "Failed to allocate memory for device "
2236 "structure\n");
2237 retval = -ENOMEM;
2238 goto err_struct;
2239 }
2240
7a6cb0d5 2241 tsi148_device = kzalloc(sizeof(struct tsi148_driver), GFP_KERNEL);
29848ac9
MW		 2242 if (tsi148_device == NULL) {
2243 dev_err(&pdev->dev, "Failed to allocate memory for device "
2244 "structure\n");
2245 retval = -ENOMEM;
2246 goto err_driver;
2247 }
2248
29848ac9
MW		 2249 tsi148_bridge->driver_priv = tsi148_device;
2250
d22b8ed9
MW		 2251 /* Enable the device */
2252 retval = pci_enable_device(pdev);
2253 if (retval) {
2254 dev_err(&pdev->dev, "Unable to enable device\n");
2255 goto err_enable;
2256 }
2257
2258 /* Map Registers */
2259 retval = pci_request_regions(pdev, driver_name);
2260 if (retval) {
2261 dev_err(&pdev->dev, "Unable to reserve resources\n");
2262 goto err_resource;
2263 }
2264
2265 /* map registers in BAR 0 */
29848ac9
MW		 2266 tsi148_device->base = ioremap_nocache(pci_resource_start(pdev, 0),
2267 4096);
2268 if (!tsi148_device->base) {
d22b8ed9
MW		 2269 dev_err(&pdev->dev, "Unable to remap CRG region\n");
2270 retval = -EIO;
2271 goto err_remap;
2272 }
2273
2274 /* Check to see if the mapping worked out */
29848ac9 2275 data = ioread32(tsi148_device->base + TSI148_PCFS_ID) & 0x0000FFFF;
d22b8ed9
MW		 2276 if (data != PCI_VENDOR_ID_TUNDRA) {
2277 dev_err(&pdev->dev, "CRG region check failed\n");
2278 retval = -EIO;
2279 goto err_test;
2280 }
2281
2282 /* Initialize wait queues & mutual exclusion flags */
29848ac9
MW		 2283 init_waitqueue_head(&(tsi148_device->dma_queue[0]));
2284 init_waitqueue_head(&(tsi148_device->dma_queue[1]));
2285 init_waitqueue_head(&(tsi148_device->iack_queue));
2286 mutex_init(&(tsi148_device->vme_int));
2287 mutex_init(&(tsi148_device->vme_rmw));
d22b8ed9
MW		 2288
2289 tsi148_bridge->parent = &(pdev->dev);
2290 strcpy(tsi148_bridge->name, driver_name);
2291
2292 /* Setup IRQ */
2293 retval = tsi148_irq_init(tsi148_bridge);
2294 if (retval != 0) {
2295 dev_err(&pdev->dev, "Chip Initialization failed.\n");
2296 goto err_irq;
2297 }
2298
2299 /* If we are going to flush writes, we need to read from the VME bus.
2300 * We need to do this safely, thus we read the devices own CR/CSR
2301 * register. To do this we must set up a window in CR/CSR space and
2302 * hence have one less master window resource available.
2303 */
2304 master_num = TSI148_MAX_MASTER;
7946328f 2305 if (err_chk) {
d22b8ed9 2306 master_num--;
29848ac9 2307
32414878 2308 tsi148_device->flush_image =
29848ac9
MW		 2309 kmalloc(sizeof(struct vme_master_resource), GFP_KERNEL);
2310 if (tsi148_device->flush_image == NULL) {
d22b8ed9
MW		 2311 dev_err(&pdev->dev, "Failed to allocate memory for "
2312 "flush resource structure\n");
2313 retval = -ENOMEM;
2314 goto err_master;
2315 }
29848ac9
MW		 2316 tsi148_device->flush_image->parent = tsi148_bridge;
2317 spin_lock_init(&(tsi148_device->flush_image->lock));
2318 tsi148_device->flush_image->locked = 1;
2319 tsi148_device->flush_image->number = master_num;
2320 tsi148_device->flush_image->address_attr = VME_A16 | VME_A24 |
2321 VME_A32 | VME_A64;
2322 tsi148_device->flush_image->cycle_attr = VME_SCT | VME_BLT |
2323 VME_MBLT | VME_2eVME | VME_2eSST | VME_2eSSTB |
2324 VME_2eSST160 | VME_2eSST267 | VME_2eSST320 | VME_SUPER |
2325 VME_USER | VME_PROG | VME_DATA;
2326 tsi148_device->flush_image->width_attr = VME_D16 | VME_D32;
8fafb476 2327 memset(&(tsi148_device->flush_image->bus_resource), 0,
d22b8ed9 2328 sizeof(struct resource));
29848ac9 2329 tsi148_device->flush_image->kern_base = NULL;
d22b8ed9
MW		 2330 }
2331
2332 /* Add master windows to list */
2333 INIT_LIST_HEAD(&(tsi148_bridge->master_resources));
2334 for (i = 0; i < master_num; i++) {
7946328f
MW		 2335 master_image = kmalloc(sizeof(struct vme_master_resource),
2336 GFP_KERNEL);
d22b8ed9
MW		 2337 if (master_image == NULL) {
2338 dev_err(&pdev->dev, "Failed to allocate memory for "
2339 "master resource structure\n");
2340 retval = -ENOMEM;
2341 goto err_master;
2342 }
2343 master_image->parent = tsi148_bridge;
2344 spin_lock_init(&(master_image->lock));
2345 master_image->locked = 0;
2346 master_image->number = i;
2347 master_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
2348 VME_A64;
2349 master_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
2350 VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 |
2351 VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER |
2352 VME_PROG | VME_DATA;
2353 master_image->width_attr = VME_D16 | VME_D32;
8fafb476 2354 memset(&(master_image->bus_resource), 0,
d22b8ed9
MW		 2355 sizeof(struct resource));
2356 master_image->kern_base = NULL;
2357 list_add_tail(&(master_image->list),
2358 &(tsi148_bridge->master_resources));
2359 }
2360
2361 /* Add slave windows to list */
2362 INIT_LIST_HEAD(&(tsi148_bridge->slave_resources));
2363 for (i = 0; i < TSI148_MAX_SLAVE; i++) {
7946328f
MW		 2364 slave_image = kmalloc(sizeof(struct vme_slave_resource),
2365 GFP_KERNEL);
d22b8ed9
MW		 2366 if (slave_image == NULL) {
2367 dev_err(&pdev->dev, "Failed to allocate memory for "
2368 "slave resource structure\n");
2369 retval = -ENOMEM;
2370 goto err_slave;
2371 }
2372 slave_image->parent = tsi148_bridge;
400822fe 2373 mutex_init(&(slave_image->mtx));
d22b8ed9
MW		 2374 slave_image->locked = 0;
2375 slave_image->number = i;
2376 slave_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
2377 VME_A64 | VME_CRCSR | VME_USER1 | VME_USER2 |
2378 VME_USER3 | VME_USER4;
2379 slave_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
2380 VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 |
2381 VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER |
2382 VME_PROG | VME_DATA;
2383 list_add_tail(&(slave_image->list),
2384 &(tsi148_bridge->slave_resources));
2385 }
2386
2387 /* Add dma engines to list */
2388 INIT_LIST_HEAD(&(tsi148_bridge->dma_resources));
2389 for (i = 0; i < TSI148_MAX_DMA; i++) {
7946328f
MW		 2390 dma_ctrlr = kmalloc(sizeof(struct vme_dma_resource),
2391 GFP_KERNEL);
d22b8ed9
MW		 2392 if (dma_ctrlr == NULL) {
2393 dev_err(&pdev->dev, "Failed to allocate memory for "
2394 "dma resource structure\n");
2395 retval = -ENOMEM;
2396 goto err_dma;
2397 }
2398 dma_ctrlr->parent = tsi148_bridge;
400822fe 2399 mutex_init(&(dma_ctrlr->mtx));
d22b8ed9
MW		 2400 dma_ctrlr->locked = 0;
2401 dma_ctrlr->number = i;
4f723df4
MW		 2402 dma_ctrlr->route_attr = VME_DMA_VME_TO_MEM |
2403 VME_DMA_MEM_TO_VME | VME_DMA_VME_TO_VME |
2404 VME_DMA_MEM_TO_MEM | VME_DMA_PATTERN_TO_VME |
2405 VME_DMA_PATTERN_TO_MEM;
d22b8ed9
MW		 2406 INIT_LIST_HEAD(&(dma_ctrlr->pending));
2407 INIT_LIST_HEAD(&(dma_ctrlr->running));
2408 list_add_tail(&(dma_ctrlr->list),
2409 &(tsi148_bridge->dma_resources));
2410 }
2411
42fb5031
MW		 2412 /* Add location monitor to list */
2413 INIT_LIST_HEAD(&(tsi148_bridge->lm_resources));
2414 lm = kmalloc(sizeof(struct vme_lm_resource), GFP_KERNEL);
2415 if (lm == NULL) {
2416 dev_err(&pdev->dev, "Failed to allocate memory for "
2417 "location monitor resource structure\n");
2418 retval = -ENOMEM;
2419 goto err_lm;
2420 }
2421 lm->parent = tsi148_bridge;
2422 mutex_init(&(lm->mtx));
2423 lm->locked = 0;
2424 lm->number = 1;
2425 lm->monitors = 4;
2426 list_add_tail(&(lm->list), &(tsi148_bridge->lm_resources));
2427
d22b8ed9
MW		 2428 tsi148_bridge->slave_get = tsi148_slave_get;
2429 tsi148_bridge->slave_set = tsi148_slave_set;
2430 tsi148_bridge->master_get = tsi148_master_get;
2431 tsi148_bridge->master_set = tsi148_master_set;
2432 tsi148_bridge->master_read = tsi148_master_read;
2433 tsi148_bridge->master_write = tsi148_master_write;
2434 tsi148_bridge->master_rmw = tsi148_master_rmw;
2435 tsi148_bridge->dma_list_add = tsi148_dma_list_add;
2436 tsi148_bridge->dma_list_exec = tsi148_dma_list_exec;
2437 tsi148_bridge->dma_list_empty = tsi148_dma_list_empty;
c813f592
MW		 2438 tsi148_bridge->irq_set = tsi148_irq_set;
2439 tsi148_bridge->irq_generate = tsi148_irq_generate;
d22b8ed9
MW		 2440 tsi148_bridge->lm_set = tsi148_lm_set;
2441 tsi148_bridge->lm_get = tsi148_lm_get;
2442 tsi148_bridge->lm_attach = tsi148_lm_attach;
2443 tsi148_bridge->lm_detach = tsi148_lm_detach;
2444 tsi148_bridge->slot_get = tsi148_slot_get;
2445
29848ac9 2446 data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT);
d22b8ed9 2447 dev_info(&pdev->dev, "Board is%s the VME system controller\n",
7946328f 2448 (data & TSI148_LCSR_VSTAT_SCONS) ? "" : " not");
29848ac9 2449 if (!geoid)
638f199d
MW		 2450 dev_info(&pdev->dev, "VME geographical address is %d\n",
2451 data & TSI148_LCSR_VSTAT_GA_M);
29848ac9 2452 else
638f199d
MW		 2453 dev_info(&pdev->dev, "VME geographical address is set to %d\n",
2454 geoid);
29848ac9 2455
d22b8ed9
MW		 2456 dev_info(&pdev->dev, "VME Write and flush and error check is %s\n",
2457 err_chk ? "enabled" : "disabled");
2458
4839737b 2459 if (tsi148_crcsr_init(tsi148_bridge, pdev)) {
d22b8ed9
MW		 2460 dev_err(&pdev->dev, "CR/CSR configuration failed.\n");
2461 goto err_crcsr;
4839737b 2462 }
d22b8ed9 2463
d22b8ed9
MW		 2464 retval = vme_register_bridge(tsi148_bridge);
2465 if (retval != 0) {
2466 dev_err(&pdev->dev, "Chip Registration failed.\n");
2467 goto err_reg;
2468 }
2469
29848ac9
MW		 2470 pci_set_drvdata(pdev, tsi148_bridge);
2471
d22b8ed9 2472 /* Clear VME bus "board fail", and "power-up reset" lines */
29848ac9 2473 data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT);
d22b8ed9
MW		 2474 data &= ~TSI148_LCSR_VSTAT_BRDFL;
2475 data |= TSI148_LCSR_VSTAT_CPURST;
29848ac9 2476 iowrite32be(data, tsi148_device->base + TSI148_LCSR_VSTAT);
d22b8ed9
MW		 2477
2478 return 0;
2479
2480 vme_unregister_bridge(tsi148_bridge);
2481err_reg:
29848ac9 2482 tsi148_crcsr_exit(tsi148_bridge, pdev);
d22b8ed9 2483err_crcsr:
42fb5031
MW		 2484err_lm:
2485 /* resources are stored in link list */
2486 list_for_each(pos, &(tsi148_bridge->lm_resources)) {
2487 lm = list_entry(pos, struct vme_lm_resource, list);
2488 list_del(pos);
2489 kfree(lm);
2490 }
d22b8ed9
MW		 2491err_dma:
2492 /* resources are stored in link list */
2493 list_for_each(pos, &(tsi148_bridge->dma_resources)) {
2494 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
2495 list_del(pos);
2496 kfree(dma_ctrlr);
2497 }
2498err_slave:
2499 /* resources are stored in link list */
2500 list_for_each(pos, &(tsi148_bridge->slave_resources)) {
2501 slave_image = list_entry(pos, struct vme_slave_resource, list);
2502 list_del(pos);
2503 kfree(slave_image);
2504 }
2505err_master:
2506 /* resources are stored in link list */
2507 list_for_each(pos, &(tsi148_bridge->master_resources)) {
7946328f
MW		 2508 master_image = list_entry(pos, struct vme_master_resource,
2509 list);
d22b8ed9
MW		 2510 list_del(pos);
2511 kfree(master_image);
2512 }
2513
29848ac9 2514 tsi148_irq_exit(tsi148_device, pdev);
d22b8ed9
MW		 2515err_irq:
2516err_test:
29848ac9 2517 iounmap(tsi148_device->base);
d22b8ed9
MW		 2518err_remap:
2519 pci_release_regions(pdev);
2520err_resource:
2521 pci_disable_device(pdev);
2522err_enable:
29848ac9
MW		 2523 kfree(tsi148_device);
2524err_driver:
d22b8ed9
MW		 2525 kfree(tsi148_bridge);
2526err_struct:
2527 return retval;
2528
2529}
2530
2531static void tsi148_remove(struct pci_dev *pdev)
2532{
2533 struct list_head *pos = NULL;
2534 struct vme_master_resource *master_image;
2535 struct vme_slave_resource *slave_image;
2536 struct vme_dma_resource *dma_ctrlr;
2537 int i;
29848ac9
MW		 2538 struct tsi148_driver *bridge;
2539 struct vme_bridge *tsi148_bridge = pci_get_drvdata(pdev);
2540
2541 bridge = tsi148_bridge->driver_priv;
d22b8ed9 2542
d22b8ed9 2543
29848ac9 2544 dev_dbg(&pdev->dev, "Driver is being unloaded.\n");
d22b8ed9
MW		 2545
2546 /*
2547 * Shutdown all inbound and outbound windows.
2548 */
2549 for (i = 0; i < 8; i++) {
29848ac9 2550 iowrite32be(0, bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9 2551 TSI148_LCSR_OFFSET_ITAT);
29848ac9 2552 iowrite32be(0, bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9
MW		 2553 TSI148_LCSR_OFFSET_OTAT);
2554 }
2555
2556 /*
2557 * Shutdown Location monitor.
2558 */
29848ac9 2559 iowrite32be(0, bridge->base + TSI148_LCSR_LMAT);
d22b8ed9
MW		 2560
2561 /*
2562 * Shutdown CRG map.
2563 */
29848ac9 2564 iowrite32be(0, bridge->base + TSI148_LCSR_CSRAT);
d22b8ed9
MW		 2565
2566 /*
2567 * Clear error status.
2568 */
29848ac9
MW		 2569 iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_EDPAT);
2570 iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_VEAT);
2571 iowrite32be(0x07000700, bridge->base + TSI148_LCSR_PSTAT);
d22b8ed9
MW		 2572
2573 /*
2574 * Remove VIRQ interrupt (if any)
2575 */
29848ac9
MW		 2576 if (ioread32be(bridge->base + TSI148_LCSR_VICR) & 0x800)
2577 iowrite32be(0x8000, bridge->base + TSI148_LCSR_VICR);
d22b8ed9 2578
d22b8ed9
MW		 2579 /*
2580 * Map all Interrupts to PCI INTA
2581 */
29848ac9
MW		 2582 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM1);
2583 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM2);
d22b8ed9 2584
29848ac9 2585 tsi148_irq_exit(bridge, pdev);
d22b8ed9
MW		 2586
2587 vme_unregister_bridge(tsi148_bridge);
2588
29848ac9 2589 tsi148_crcsr_exit(tsi148_bridge, pdev);
d22b8ed9
MW		 2590
2591 /* resources are stored in link list */
2592 list_for_each(pos, &(tsi148_bridge->dma_resources)) {
2593 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
2594 list_del(pos);
2595 kfree(dma_ctrlr);
2596 }
2597
2598 /* resources are stored in link list */
2599 list_for_each(pos, &(tsi148_bridge->slave_resources)) {
2600 slave_image = list_entry(pos, struct vme_slave_resource, list);
2601 list_del(pos);
2602 kfree(slave_image);
2603 }
2604
2605 /* resources are stored in link list */
2606 list_for_each(pos, &(tsi148_bridge->master_resources)) {
638f199d
MW		 2607 master_image = list_entry(pos, struct vme_master_resource,
2608 list);
d22b8ed9
MW		 2609 list_del(pos);
2610 kfree(master_image);
2611 }
2612
29848ac9 2613 tsi148_irq_exit(bridge, pdev);
d22b8ed9 2614
29848ac9 2615 iounmap(bridge->base);
d22b8ed9
MW		 2616
2617 pci_release_regions(pdev);
2618
2619 pci_disable_device(pdev);
2620
29848ac9
MW		 2621 kfree(tsi148_bridge->driver_priv);
2622
d22b8ed9
MW		 2623 kfree(tsi148_bridge);
2624}
2625
2626static void __exit tsi148_exit(void)
2627{
2628 pci_unregister_driver(&tsi148_driver);
d22b8ed9
MW		 2629}
2630
2631MODULE_PARM_DESC(err_chk, "Check for VME errors on reads and writes");
2632module_param(err_chk, bool, 0);
2633
638f199d
MW		 2634MODULE_PARM_DESC(geoid, "Override geographical addressing");
2635module_param(geoid, int, 0);
2636
d22b8ed9
MW		 2637MODULE_DESCRIPTION("VME driver for the Tundra Tempe VME bridge");
2638MODULE_LICENSE("GPL");
2639
2640module_init(tsi148_init);
2641module_exit(tsi148_exit);
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