[net-next-2.6.git] / drivers / serial / msm_serial.h

/*
 * drivers/serial/msm_serial.h
 *
 * Copyright (C) 2007 Google, Inc.
 * Author: Robert Love <rlove@google.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#ifndef __DRIVERS_SERIAL_MSM_SERIAL_H
#define __DRIVERS_SERIAL_MSM_SERIAL_H

#define UART_MR1			0x0000

#define UART_MR1_AUTO_RFR_LEVEL0	0x3F
#define UART_MR1_AUTO_RFR_LEVEL1	0x3FF00
#define UART_MR1_RX_RDY_CTL    		(1 << 7)
#define UART_MR1_CTS_CTL       		(1 << 6)

#define UART_MR2			0x0004
#define UART_MR2_ERROR_MODE		(1 << 6)
#define UART_MR2_BITS_PER_CHAR		0x30
#define UART_MR2_BITS_PER_CHAR_5	(0x0 << 4)
#define UART_MR2_BITS_PER_CHAR_6	(0x1 << 4)
#define UART_MR2_BITS_PER_CHAR_7	(0x2 << 4)
#define UART_MR2_BITS_PER_CHAR_8	(0x3 << 4)
#define UART_MR2_STOP_BIT_LEN_ONE	(0x1 << 2)
#define UART_MR2_STOP_BIT_LEN_TWO	(0x3 << 2)
#define UART_MR2_PARITY_MODE_NONE	0x0
#define UART_MR2_PARITY_MODE_ODD	0x1
#define UART_MR2_PARITY_MODE_EVEN	0x2
#define UART_MR2_PARITY_MODE_SPACE	0x3
#define UART_MR2_PARITY_MODE		0x3

#define UART_CSR	0x0008
#define UART_CSR_115200	0xFF
#define UART_CSR_57600	0xEE
#define UART_CSR_38400	0xDD
#define UART_CSR_28800	0xCC
#define UART_CSR_19200	0xBB
#define UART_CSR_14400	0xAA
#define UART_CSR_9600	0x99
#define UART_CSR_4800	0x77
#define UART_CSR_2400	0x55
#define UART_CSR_1200	0x44
#define UART_CSR_600	0x33
#define UART_CSR_300	0x22

#define UART_TF		0x000C

#define UART_CR				0x0010
#define UART_CR_CMD_NULL		(0 << 4)
#define UART_CR_CMD_RESET_RX		(1 << 4)
#define UART_CR_CMD_RESET_TX		(2 << 4)
#define UART_CR_CMD_RESET_ERR		(3 << 4)
#define UART_CR_CMD_RESET_BREAK_INT	(4 << 4)
#define UART_CR_CMD_START_BREAK		(5 << 4)
#define UART_CR_CMD_STOP_BREAK		(6 << 4)
#define UART_CR_CMD_RESET_CTS		(7 << 4)
#define UART_CR_CMD_PACKET_MODE		(9 << 4)
#define UART_CR_CMD_MODE_RESET		(12 << 4)
#define UART_CR_CMD_SET_RFR		(13 << 4)
#define UART_CR_CMD_RESET_RFR		(14 << 4)
#define UART_CR_TX_DISABLE		(1 << 3)
#define UART_CR_TX_ENABLE		(1 << 3)
#define UART_CR_RX_DISABLE		(1 << 3)
#define UART_CR_RX_ENABLE		(1 << 3)

#define UART_IMR		0x0014
#define UART_IMR_TXLEV		(1 << 0)
#define UART_IMR_RXSTALE	(1 << 3)
#define UART_IMR_RXLEV		(1 << 4)
#define UART_IMR_DELTA_CTS	(1 << 5)
#define UART_IMR_CURRENT_CTS	(1 << 6)

#define UART_IPR_RXSTALE_LAST		0x20
#define UART_IPR_STALE_LSB		0x1F
#define UART_IPR_STALE_TIMEOUT_MSB	0x3FF80

#define UART_IPR	0x0018
#define UART_TFWR	0x001C
#define UART_RFWR	0x0020
#define UART_HCR	0x0024

#define UART_MREG		0x0028
#define UART_NREG		0x002C
#define UART_DREG		0x0030
#define UART_MNDREG		0x0034
#define UART_IRDA		0x0038
#define UART_MISR_MODE		0x0040
#define UART_MISR_RESET		0x0044
#define UART_MISR_EXPORT	0x0048
#define UART_MISR_VAL		0x004C
#define UART_TEST_CTRL		0x0050

#define UART_SR			0x0008
#define UART_SR_HUNT_CHAR	(1 << 7)
#define UART_SR_RX_BREAK	(1 << 6)
#define UART_SR_PAR_FRAME_ERR	(1 << 5)
#define UART_SR_OVERRUN		(1 << 4)
#define UART_SR_TX_EMPTY	(1 << 3)
#define UART_SR_TX_READY	(1 << 2)
#define UART_SR_RX_FULL		(1 << 1)
#define UART_SR_RX_READY	(1 << 0)

#define UART_RF		0x000C
#define UART_MISR	0x0010
#define UART_ISR	0x0014

#define UART_TO_MSM(uart_port)	((struct msm_port *) uart_port)

static inline
void msm_write(struct uart_port *port, unsigned int val, unsigned int off)
{
	__raw_writel(val, port->membase + off);
}

static inline
unsigned int msm_read(struct uart_port *port, unsigned int off)
{
	return __raw_readl(port->membase + off);
}

/*
 * Setup the MND registers to use the TCXO clock.
 */
static inline void msm_serial_set_mnd_regs_tcxo(struct uart_port *port)
{
	msm_write(port, 0x06, UART_MREG);
	msm_write(port, 0xF1, UART_NREG);
	msm_write(port, 0x0F, UART_DREG);
	msm_write(port, 0x1A, UART_MNDREG);
}

/*
 * Setup the MND registers to use the TCXO clock divided by 4.
 */
static inline void msm_serial_set_mnd_regs_tcxoby4(struct uart_port *port)
{
	msm_write(port, 0x18, UART_MREG);
	msm_write(port, 0xF6, UART_NREG);
	msm_write(port, 0x0F, UART_DREG);
	msm_write(port, 0x0A, UART_MNDREG);
}

static inline
void msm_serial_set_mnd_regs_from_uartclk(struct uart_port *port)
{
	if (port->uartclk == 19200000)
		msm_serial_set_mnd_regs_tcxo(port);
	else
		msm_serial_set_mnd_regs_tcxoby4(port);
}

/*
 * TROUT has a specific defect that makes it report it's uartclk
 * as 19.2Mhz (TCXO) when it's actually 4.8Mhz (TCXO/4). This special
 * cases TROUT to use the right clock.
 */
#ifdef CONFIG_MACH_TROUT
#define msm_serial_set_mnd_regs msm_serial_set_mnd_regs_tcxoby4
#else
#define msm_serial_set_mnd_regs msm_serial_set_mnd_regs_from_uartclk
#endif

#endif	/* __DRIVERS_SERIAL_MSM_SERIAL_H */
Commit	Line	Data
04896a77 RL	1	/*
	2	* drivers/serial/msm_serial.h
	3	*
	4	* Copyright (C) 2007 Google, Inc.
	5	* Author: Robert Love <rlove@google.com>
	6	*
	7	* This software is licensed under the terms of the GNU General Public
	8	* License version 2, as published by the Free Software Foundation, and
	9	* may be copied, distributed, and modified under those terms.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*/
	16
	17	#ifndef __DRIVERS_SERIAL_MSM_SERIAL_H
	18	#define __DRIVERS_SERIAL_MSM_SERIAL_H
	19
	20	#define UART_MR1 0x0000
	21
	22	#define UART_MR1_AUTO_RFR_LEVEL0 0x3F
	23	#define UART_MR1_AUTO_RFR_LEVEL1 0x3FF00
	24	#define UART_MR1_RX_RDY_CTL (1 << 7)
	25	#define UART_MR1_CTS_CTL (1 << 6)
	26
	27	#define UART_MR2 0x0004
	28	#define UART_MR2_ERROR_MODE (1 << 6)
	29	#define UART_MR2_BITS_PER_CHAR 0x30
	30	#define UART_MR2_BITS_PER_CHAR_5 (0x0 << 4)
	31	#define UART_MR2_BITS_PER_CHAR_6 (0x1 << 4)
	32	#define UART_MR2_BITS_PER_CHAR_7 (0x2 << 4)
	33	#define UART_MR2_BITS_PER_CHAR_8 (0x3 << 4)
	34	#define UART_MR2_STOP_BIT_LEN_ONE (0x1 << 2)
	35	#define UART_MR2_STOP_BIT_LEN_TWO (0x3 << 2)
	36	#define UART_MR2_PARITY_MODE_NONE 0x0
	37	#define UART_MR2_PARITY_MODE_ODD 0x1
	38	#define UART_MR2_PARITY_MODE_EVEN 0x2
	39	#define UART_MR2_PARITY_MODE_SPACE 0x3
	40	#define UART_MR2_PARITY_MODE 0x3
	41
	42	#define UART_CSR 0x0008
	43	#define UART_CSR_115200 0xFF
	44	#define UART_CSR_57600 0xEE
	45	#define UART_CSR_38400 0xDD
	46	#define UART_CSR_28800 0xCC
	47	#define UART_CSR_19200 0xBB
	48	#define UART_CSR_14400 0xAA
	49	#define UART_CSR_9600 0x99
	50	#define UART_CSR_4800 0x77
	51	#define UART_CSR_2400 0x55
	52	#define UART_CSR_1200 0x44
	53	#define UART_CSR_600 0x33
	54	#define UART_CSR_300 0x22
	55
	56	#define UART_TF 0x000C
	57
	58	#define UART_CR 0x0010
	59	#define UART_CR_CMD_NULL (0 << 4)
	60	#define UART_CR_CMD_RESET_RX (1 << 4)
	61	#define UART_CR_CMD_RESET_TX (2 << 4)
	62	#define UART_CR_CMD_RESET_ERR (3 << 4)
	63	#define UART_CR_CMD_RESET_BREAK_INT (4 << 4)
	64	#define UART_CR_CMD_START_BREAK (5 << 4)
65	#define UART_CR_CMD_STOP_BREAK (6 << 4)
66	#define UART_CR_CMD_RESET_CTS (7 << 4)
67	#define UART_CR_CMD_PACKET_MODE (9 << 4)
68	#define UART_CR_CMD_MODE_RESET (12 << 4)
69	#define UART_CR_CMD_SET_RFR (13 << 4)
70	#define UART_CR_CMD_RESET_RFR (14 << 4)
71	#define UART_CR_TX_DISABLE (1 << 3)
72	#define UART_CR_TX_ENABLE (1 << 3)
73	#define UART_CR_RX_DISABLE (1 << 3)
74	#define UART_CR_RX_ENABLE (1 << 3)
75
76	#define UART_IMR 0x0014
77	#define UART_IMR_TXLEV (1 << 0)
78	#define UART_IMR_RXSTALE (1 << 3)
79	#define UART_IMR_RXLEV (1 << 4)
80	#define UART_IMR_DELTA_CTS (1 << 5)
81	#define UART_IMR_CURRENT_CTS (1 << 6)
82
83	#define UART_IPR_RXSTALE_LAST 0x20
84	#define UART_IPR_STALE_LSB 0x1F
85	#define UART_IPR_STALE_TIMEOUT_MSB 0x3FF80
86
87	#define UART_IPR 0x0018
88	#define UART_TFWR 0x001C
89	#define UART_RFWR 0x0020
90	#define UART_HCR 0x0024
91
92	#define UART_MREG 0x0028
93	#define UART_NREG 0x002C
94	#define UART_DREG 0x0030
95	#define UART_MNDREG 0x0034
96	#define UART_IRDA 0x0038
97	#define UART_MISR_MODE 0x0040
98	#define UART_MISR_RESET 0x0044
99	#define UART_MISR_EXPORT 0x0048
100	#define UART_MISR_VAL 0x004C
101	#define UART_TEST_CTRL 0x0050
102
103	#define UART_SR 0x0008
104	#define UART_SR_HUNT_CHAR (1 << 7)
105	#define UART_SR_RX_BREAK (1 << 6)
106	#define UART_SR_PAR_FRAME_ERR (1 << 5)
107	#define UART_SR_OVERRUN (1 << 4)
108	#define UART_SR_TX_EMPTY (1 << 3)
109	#define UART_SR_TX_READY (1 << 2)
110	#define UART_SR_RX_FULL (1 << 1)
111	#define UART_SR_RX_READY (1 << 0)
112
113	#define UART_RF 0x000C
114	#define UART_MISR 0x0010
115	#define UART_ISR 0x0014
116
18c79d76 AD	117	#define UART_TO_MSM(uart_port) ((struct msm_port *) uart_port)
	118
	119	static inline
	120	void msm_write(struct uart_port *port, unsigned int val, unsigned int off)
	121	{
	122	__raw_writel(val, port->membase + off);
	123	}
	124
	125	static inline
	126	unsigned int msm_read(struct uart_port *port, unsigned int off)
	127	{
	128	return __raw_readl(port->membase + off);
	129	}
	130
	131	/*
	132	* Setup the MND registers to use the TCXO clock.
	133	*/
	134	static inline void msm_serial_set_mnd_regs_tcxo(struct uart_port *port)
	135	{
	136	msm_write(port, 0x06, UART_MREG);
	137	msm_write(port, 0xF1, UART_NREG);
	138	msm_write(port, 0x0F, UART_DREG);
	139	msm_write(port, 0x1A, UART_MNDREG);
	140	}
	141
	142	/*
	143	* Setup the MND registers to use the TCXO clock divided by 4.
	144	*/
	145	static inline void msm_serial_set_mnd_regs_tcxoby4(struct uart_port *port)
	146	{
	147	msm_write(port, 0x18, UART_MREG);
	148	msm_write(port, 0xF6, UART_NREG);
	149	msm_write(port, 0x0F, UART_DREG);
	150	msm_write(port, 0x0A, UART_MNDREG);
	151	}
	152
	153	static inline
	154	void msm_serial_set_mnd_regs_from_uartclk(struct uart_port *port)
	155	{
	156	if (port->uartclk == 19200000)
	157	msm_serial_set_mnd_regs_tcxo(port);
	158	else
	159	msm_serial_set_mnd_regs_tcxoby4(port);
	160	}
	161
	162	/*
	163	* TROUT has a specific defect that makes it report it's uartclk
	164	* as 19.2Mhz (TCXO) when it's actually 4.8Mhz (TCXO/4). This special
	165	* cases TROUT to use the right clock.
	166	*/
	167	#ifdef CONFIG_MACH_TROUT
	168	#define msm_serial_set_mnd_regs msm_serial_set_mnd_regs_tcxoby4
	169	#else
	170	#define msm_serial_set_mnd_regs msm_serial_set_mnd_regs_from_uartclk
	171	#endif
	172
04896a77	173	#endif /* __DRIVERS_SERIAL_MSM_SERIAL_H */