[net-next-2.6.git] / drivers / pci / setup-res.c

/*
 *	drivers/pci/setup-res.c
 *
 * Extruded from code written by
 *      Dave Rusling (david.rusling@reo.mts.dec.com)
 *      David Mosberger (davidm@cs.arizona.edu)
 *	David Miller (davem@redhat.com)
 *
 * Support routines for initializing a PCI subsystem.
 */

/* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */

/*
 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
 *	     Resource sorting
 */

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/cache.h>
#include <linux/slab.h>
#include "pci.h"


void pci_update_resource(struct pci_dev *dev, int resno)
{
	struct pci_bus_region region;
	u32 new, check, mask;
	int reg;
	enum pci_bar_type type;
	struct resource *res = dev->resource + resno;

	/*
	 * Ignore resources for unimplemented BARs and unused resource slots
	 * for 64 bit BARs.
	 */
	if (!res->flags)
		return;

	/*
	 * Ignore non-moveable resources.  This might be legacy resources for
	 * which no functional BAR register exists or another important
	 * system resource we shouldn't move around.
	 */
	if (res->flags & IORESOURCE_PCI_FIXED)
		return;

	pcibios_resource_to_bus(dev, &region, res);

	new = region.start | (res->flags & PCI_REGION_FLAG_MASK);
	if (res->flags & IORESOURCE_IO)
		mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
	else
		mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;

	reg = pci_resource_bar(dev, resno, &type);
	if (!reg)
		return;
	if (type != pci_bar_unknown) {
		if (!(res->flags & IORESOURCE_ROM_ENABLE))
			return;
		new |= PCI_ROM_ADDRESS_ENABLE;
	}

	pci_write_config_dword(dev, reg, new);
	pci_read_config_dword(dev, reg, &check);

	if ((new ^ check) & mask) {
		dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
			resno, new, check);
	}

	if ((new & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
	    (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64)) {
		new = region.start >> 16 >> 16;
		pci_write_config_dword(dev, reg + 4, new);
		pci_read_config_dword(dev, reg + 4, &check);
		if (check != new) {
			dev_err(&dev->dev, "BAR %d: error updating "
			       "(high %#08x != %#08x)\n", resno, new, check);
		}
	}
	res->flags &= ~IORESOURCE_UNSET;
	dev_info(&dev->dev, "BAR %d: set to %pR (PCI address [%#llx-%#llx]\n",
		 resno, res, (unsigned long long)region.start,
		 (unsigned long long)region.end);
}

int pci_claim_resource(struct pci_dev *dev, int resource)
{
	struct resource *res = &dev->resource[resource];
	struct resource *root, *conflict;

	root = pci_find_parent_resource(dev, res);
	if (!root) {
		dev_info(&dev->dev, "no compatible bridge window for %pR\n",
			 res);
		return -EINVAL;
	}

	conflict = request_resource_conflict(root, res);
	if (conflict) {
		dev_info(&dev->dev,
			 "address space collision: %pR conflicts with %s %pR\n",
			 res, conflict->name, conflict);
		return -EBUSY;
	}

	return 0;
}
EXPORT_SYMBOL(pci_claim_resource);

#ifdef CONFIG_PCI_QUIRKS
void pci_disable_bridge_window(struct pci_dev *dev)
{
	dev_info(&dev->dev, "disabling bridge mem windows\n");

	/* MMIO Base/Limit */
	pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);

	/* Prefetchable MMIO Base/Limit */
	pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
	pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
	pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
}
#endif	/* CONFIG_PCI_QUIRKS */

static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
				 int resno)
{
	struct resource *res = dev->resource + resno;
	resource_size_t size, min, align;
	int ret;

	size = resource_size(res);
	min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
	align = pci_resource_alignment(dev, res);

	/* First, try exact prefetching match.. */
	ret = pci_bus_alloc_resource(bus, res, size, align, min,
				     IORESOURCE_PREFETCH,
				     pcibios_align_resource, dev);

	if (ret < 0 && (res->flags & IORESOURCE_PREFETCH)) {
		/*
		 * That failed.
		 *
		 * But a prefetching area can handle a non-prefetching
		 * window (it will just not perform as well).
		 */
		ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
					     pcibios_align_resource, dev);
	}

	if (ret < 0 && dev->fw_addr[resno]) {
		struct resource *root, *conflict;
		resource_size_t start, end;

		/*
		 * If we failed to assign anything, let's try the address
		 * where firmware left it.  That at least has a chance of
		 * working, which is better than just leaving it disabled.
		 */

		if (res->flags & IORESOURCE_IO)
			root = &ioport_resource;
		else
			root = &iomem_resource;

		start = res->start;
		end = res->end;
		res->start = dev->fw_addr[resno];
		res->end = res->start + size - 1;
		dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n",
			 resno, res);
		conflict = request_resource_conflict(root, res);
		if (conflict) {
			dev_info(&dev->dev,
				 "BAR %d: %pR conflicts with %s %pR\n", resno,
				 res, conflict->name, conflict);
			res->start = start;
			res->end = end;
		} else
			ret = 0;
	}

	if (!ret) {
		res->flags &= ~IORESOURCE_STARTALIGN;
		dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
		if (resno < PCI_BRIDGE_RESOURCES)
			pci_update_resource(dev, resno);
	}

	return ret;
}

int pci_assign_resource(struct pci_dev *dev, int resno)
{
	struct resource *res = dev->resource + resno;
	resource_size_t align;
	struct pci_bus *bus;
	int ret;
	char *type;

	align = pci_resource_alignment(dev, res);
	if (!align) {
		dev_info(&dev->dev, "BAR %d: can't assign %pR "
			 "(bogus alignment)\n", resno, res);
		return -EINVAL;
	}

	bus = dev->bus;
	while ((ret = __pci_assign_resource(bus, dev, resno))) {
		if (bus->parent && bus->self->transparent)
			bus = bus->parent;
		else
			bus = NULL;
		if (bus)
			continue;
		break;
	}

	if (ret) {
		if (res->flags & IORESOURCE_MEM)
			if (res->flags & IORESOURCE_PREFETCH)
				type = "mem pref";
			else
				type = "mem";
		else if (res->flags & IORESOURCE_IO)
			type = "io";
		else
			type = "unknown";
		dev_info(&dev->dev,
			 "BAR %d: can't assign %s (size %#llx)\n",
			 resno, type, (unsigned long long) resource_size(res));
	}

	return ret;
}

/* Sort resources by alignment */
void pdev_sort_resources(struct pci_dev *dev, struct resource_list *head)
{
	int i;

	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
		struct resource *r;
		struct resource_list *list, *tmp;
		resource_size_t r_align;

		r = &dev->resource[i];

		if (r->flags & IORESOURCE_PCI_FIXED)
			continue;

		if (!(r->flags) || r->parent)
			continue;

		r_align = pci_resource_alignment(dev, r);
		if (!r_align) {
			dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n",
				 i, r);
			continue;
		}
		for (list = head; ; list = list->next) {
			resource_size_t align = 0;
			struct resource_list *ln = list->next;

			if (ln)
				align = pci_resource_alignment(ln->dev, ln->res);

			if (r_align > align) {
				tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
				if (!tmp)
					panic("pdev_sort_resources(): "
					      "kmalloc() failed!\n");
				tmp->next = ln;
				tmp->res = r;
				tmp->dev = dev;
				list->next = tmp;
				break;
			}
		}
	}
}

int pci_enable_resources(struct pci_dev *dev, int mask)
{
	u16 cmd, old_cmd;
	int i;
	struct resource *r;

	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	old_cmd = cmd;

	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
		if (!(mask & (1 << i)))
			continue;

		r = &dev->resource[i];

		if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
			continue;
		if ((i == PCI_ROM_RESOURCE) &&
				(!(r->flags & IORESOURCE_ROM_ENABLE)))
			continue;

		if (!r->parent) {
			dev_err(&dev->dev, "device not available "
				"(can't reserve %pR)\n", r);
			return -EINVAL;
		}

		if (r->flags & IORESOURCE_IO)
			cmd |= PCI_COMMAND_IO;
		if (r->flags & IORESOURCE_MEM)
			cmd |= PCI_COMMAND_MEMORY;
	}

	if (cmd != old_cmd) {
		dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
			 old_cmd, cmd);
		pci_write_config_word(dev, PCI_COMMAND, cmd);
	}
	return 0;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* drivers/pci/setup-res.c
	3	*
	4	* Extruded from code written by
	5	* Dave Rusling (david.rusling@reo.mts.dec.com)
	6	* David Mosberger (davidm@cs.arizona.edu)
	7	* David Miller (davem@redhat.com)
	8	*
	9	* Support routines for initializing a PCI subsystem.
	10	*/
	11
	12	/* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */
	13
	14	/*
	15	* Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
	16	* Resource sorting
	17	*/
	18
	19	#include <linux/init.h>
	20	#include <linux/kernel.h>
	21	#include <linux/pci.h>
	22	#include <linux/errno.h>
	23	#include <linux/ioport.h>
	24	#include <linux/cache.h>
	25	#include <linux/slab.h>
	26	#include "pci.h"
	27
	28
14add80b	29	void pci_update_resource(struct pci_dev *dev, int resno)
1da177e4 LT	30	{
	31	struct pci_bus_region region;
	32	u32 new, check, mask;
	33	int reg;
613e7ed6	34	enum pci_bar_type type;
14add80b	35	struct resource *res = dev->resource + resno;
1da177e4	36
fb0f2b40 RB	37	/*
	38	* Ignore resources for unimplemented BARs and unused resource slots
	39	* for 64 bit BARs.
	40	*/
cf7bee5a IK	41	if (!res->flags)
	42	return;
	43
fb0f2b40 RB	44	/*
	45	* Ignore non-moveable resources. This might be legacy resources for
	46	* which no functional BAR register exists or another important
80ccba11	47	* system resource we shouldn't move around.
fb0f2b40 RB	48	*/
	49	if (res->flags & IORESOURCE_PCI_FIXED)
	50	return;
	51
1da177e4 LT	52	pcibios_resource_to_bus(dev, &region, res);
1da177e4 LT	53
1da177e4 LT	54	new = region.start \| (res->flags & PCI_REGION_FLAG_MASK);
	55	if (res->flags & IORESOURCE_IO)
	56	mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
	57	else
	58	mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
	59
613e7ed6 YZ	60	reg = pci_resource_bar(dev, resno, &type);
	61	if (!reg)
	62	return;
	63	if (type != pci_bar_unknown) {
755528c8 LT	64	if (!(res->flags & IORESOURCE_ROM_ENABLE))
	65	return;
	66	new \|= PCI_ROM_ADDRESS_ENABLE;
1da177e4 LT	67	}
	68
	69	pci_write_config_dword(dev, reg, new);
	70	pci_read_config_dword(dev, reg, &check);
	71
	72	if ((new ^ check) & mask) {
80ccba11 BH	73	dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
80ccba11 BH	74	resno, new, check);
1da177e4 LT	75	}
	76
	77	if ((new & (PCI_BASE_ADDRESS_SPACE\|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
	78	(PCI_BASE_ADDRESS_SPACE_MEMORY\|PCI_BASE_ADDRESS_MEM_TYPE_64)) {
cf7bee5a	79	new = region.start >> 16 >> 16;
1da177e4 LT	80	pci_write_config_dword(dev, reg + 4, new);
	81	pci_read_config_dword(dev, reg + 4, &check);
	82	if (check != new) {
80ccba11 BH	83	dev_err(&dev->dev, "BAR %d: error updating "
80ccba11 BH	84	"(high %#08x != %#08x)\n", resno, new, check);
1da177e4 LT	85	}
	86	}
	87	res->flags &= ~IORESOURCE_UNSET;
865df576 BH	88	dev_info(&dev->dev, "BAR %d: set to %pR (PCI address [%#llx-%#llx]\n",
	89	resno, res, (unsigned long long)region.start,
	90	(unsigned long long)region.end);
1da177e4 LT	91	}
1da177e4 LT	92
96bde06a	93	int pci_claim_resource(struct pci_dev *dev, int resource)
1da177e4 LT	94	{
1da177e4 LT	95	struct resource *res = &dev->resource[resource];
966f3a75	96	struct resource root, conflict;
1da177e4	97
cebd78a8	98	root = pci_find_parent_resource(dev, res);
865df576	99	if (!root) {
f6d440da BH	100	dev_info(&dev->dev, "no compatible bridge window for %pR\n",
f6d440da BH	101	res);
865df576	102	return -EINVAL;
1da177e4 LT	103	}
1da177e4 LT	104
966f3a75 BH	105	conflict = request_resource_conflict(root, res);
966f3a75 BH	106	if (conflict) {
f6d440da BH	107	dev_info(&dev->dev,
	108	"address space collision: %pR conflicts with %s %pR\n",
	109	res, conflict->name, conflict);
966f3a75 BH	110	return -EBUSY;
966f3a75 BH	111	}
865df576	112
966f3a75	113	return 0;
1da177e4	114	}
eaa959df	115	EXPORT_SYMBOL(pci_claim_resource);
1da177e4	116
32a9a682 YS	117	#ifdef CONFIG_PCI_QUIRKS
	118	void pci_disable_bridge_window(struct pci_dev *dev)
	119	{
865df576	120	dev_info(&dev->dev, "disabling bridge mem windows\n");
32a9a682 YS	121
	122	/* MMIO Base/Limit */
	123	pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
	124
	125	/* Prefetchable MMIO Base/Limit */
	126	pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
	127	pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
	128	pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
	129	}
	130	#endif /* CONFIG_PCI_QUIRKS */
	131
d09ee968 YL	132	static int __pci_assign_resource(struct pci_bus bus, struct pci_dev dev,
d09ee968 YL	133	int resno)
1da177e4	134	{
1da177e4	135	struct resource *res = dev->resource + resno;
e31dd6e4	136	resource_size_t size, min, align;
1da177e4 LT	137	int ret;
1da177e4 LT	138
022edd86	139	size = resource_size(res);
1da177e4	140	min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
6faf17f6	141	align = pci_resource_alignment(dev, res);
1da177e4 LT	142
	143	/* First, try exact prefetching match.. */
	144	ret = pci_bus_alloc_resource(bus, res, size, align, min,
	145	IORESOURCE_PREFETCH,
	146	pcibios_align_resource, dev);
	147
	148	if (ret < 0 && (res->flags & IORESOURCE_PREFETCH)) {
	149	/*
	150	* That failed.
	151	*
	152	* But a prefetching area can handle a non-prefetching
	153	* window (it will just not perform as well).
	154	*/
	155	ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
	156	pcibios_align_resource, dev);
	157	}
	158
58c84eda BH	159	if (ret < 0 && dev->fw_addr[resno]) {
	160	struct resource root, conflict;
	161	resource_size_t start, end;
	162
	163	/*
	164	* If we failed to assign anything, let's try the address
	165	* where firmware left it. That at least has a chance of
	166	* working, which is better than just leaving it disabled.
	167	*/
	168
	169	if (res->flags & IORESOURCE_IO)
	170	root = &ioport_resource;
	171	else
	172	root = &iomem_resource;
	173
	174	start = res->start;
	175	end = res->end;
	176	res->start = dev->fw_addr[resno];
	177	res->end = res->start + size - 1;
	178	dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n",
	179	resno, res);
	180	conflict = request_resource_conflict(root, res);
	181	if (conflict) {
	182	dev_info(&dev->dev,
	183	"BAR %d: %pR conflicts with %s %pR\n", resno,
	184	res, conflict->name, conflict);
	185	res->start = start;
	186	res->end = end;
	187	} else
	188	ret = 0;
	189	}
	190
d09ee968	191	if (!ret) {
88452565	192	res->flags &= ~IORESOURCE_STARTALIGN;
865df576	193	dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
88452565	194	if (resno < PCI_BRIDGE_RESOURCES)
14add80b	195	pci_update_resource(dev, resno);
1da177e4 LT	196	}
	197
	198	return ret;
	199	}
	200
d09ee968 YL	201	int pci_assign_resource(struct pci_dev *dev, int resno)
	202	{
	203	struct resource *res = dev->resource + resno;
	204	resource_size_t align;
	205	struct pci_bus *bus;
	206	int ret;
865df576	207	char *type;
d09ee968	208
6faf17f6	209	align = pci_resource_alignment(dev, res);
d09ee968	210	if (!align) {
865df576	211	dev_info(&dev->dev, "BAR %d: can't assign %pR "
a369c791	212	"(bogus alignment)\n", resno, res);
d09ee968 YL	213	return -EINVAL;
	214	}
	215
	216	bus = dev->bus;
	217	while ((ret = __pci_assign_resource(bus, dev, resno))) {
	218	if (bus->parent && bus->self->transparent)
	219	bus = bus->parent;
	220	else
	221	bus = NULL;
	222	if (bus)
	223	continue;
	224	break;
	225	}
	226
865df576 BH	227	if (ret) {
	228	if (res->flags & IORESOURCE_MEM)
	229	if (res->flags & IORESOURCE_PREFETCH)
	230	type = "mem pref";
	231	else
	232	type = "mem";
	233	else if (res->flags & IORESOURCE_IO)
	234	type = "io";
	235	else
	236	type = "unknown";
	237	dev_info(&dev->dev,
	238	"BAR %d: can't assign %s (size %#llx)\n",
	239	resno, type, (unsigned long long) resource_size(res));
	240	}
d09ee968 YL	241
	242	return ret;
	243	}
	244
1da177e4	245	/* Sort resources by alignment */
96bde06a	246	void pdev_sort_resources(struct pci_dev dev, struct resource_list head)
1da177e4 LT	247	{
	248	int i;
	249
	250	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
	251	struct resource *r;
	252	struct resource_list list, tmp;
e31dd6e4	253	resource_size_t r_align;
1da177e4 LT	254
1da177e4 LT	255	r = &dev->resource[i];
fb0f2b40 RB	256
	257	if (r->flags & IORESOURCE_PCI_FIXED)
	258	continue;
	259
1da177e4 LT	260	if (!(r->flags) \|\| r->parent)
1da177e4 LT	261	continue;
88452565	262
6faf17f6	263	r_align = pci_resource_alignment(dev, r);
1da177e4	264	if (!r_align) {
c7dabef8	265	dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n",
a369c791	266	i, r);
1da177e4 LT	267	continue;
1da177e4 LT	268	}
1da177e4	269	for (list = head; ; list = list->next) {
e31dd6e4	270	resource_size_t align = 0;
1da177e4	271	struct resource_list *ln = list->next;
88452565 IK	272
88452565 IK	273	if (ln)
6faf17f6	274	align = pci_resource_alignment(ln->dev, ln->res);
88452565	275
1da177e4 LT	276	if (r_align > align) {
	277	tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
	278	if (!tmp)
	279	panic("pdev_sort_resources(): "
	280	"kmalloc() failed!\n");
	281	tmp->next = ln;
	282	tmp->res = r;
	283	tmp->dev = dev;
	284	list->next = tmp;
	285	break;
	286	}
	287	}
	288	}
	289	}
842de40d BH	290
	291	int pci_enable_resources(struct pci_dev *dev, int mask)
	292	{
	293	u16 cmd, old_cmd;
	294	int i;
	295	struct resource *r;
	296
	297	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	298	old_cmd = cmd;
	299
	300	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
	301	if (!(mask & (1 << i)))
	302	continue;
	303
	304	r = &dev->resource[i];
	305
	306	if (!(r->flags & (IORESOURCE_IO \| IORESOURCE_MEM)))
	307	continue;
	308	if ((i == PCI_ROM_RESOURCE) &&
	309	(!(r->flags & IORESOURCE_ROM_ENABLE)))
	310	continue;
	311
	312	if (!r->parent) {
865df576 BH	313	dev_err(&dev->dev, "device not available "
865df576 BH	314	"(can't reserve %pR)\n", r);
842de40d BH	315	return -EINVAL;
	316	}
	317
	318	if (r->flags & IORESOURCE_IO)
	319	cmd \|= PCI_COMMAND_IO;
	320	if (r->flags & IORESOURCE_MEM)
	321	cmd \|= PCI_COMMAND_MEMORY;
	322	}
	323
	324	if (cmd != old_cmd) {
	325	dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
	326	old_cmd, cmd);
	327	pci_write_config_word(dev, PCI_COMMAND, cmd);
	328	}
	329	return 0;
	330	}