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c27a02cd YP |
1 | /* |
2 | * Copyright (c) 2007 Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | * | |
32 | */ | |
33 | ||
34 | #include <linux/etherdevice.h> | |
35 | #include <linux/tcp.h> | |
36 | #include <linux/if_vlan.h> | |
37 | #include <linux/delay.h> | |
5a0e3ad6 | 38 | #include <linux/slab.h> |
c27a02cd YP |
39 | |
40 | #include <linux/mlx4/driver.h> | |
41 | #include <linux/mlx4/device.h> | |
42 | #include <linux/mlx4/cmd.h> | |
43 | #include <linux/mlx4/cq.h> | |
44 | ||
45 | #include "mlx4_en.h" | |
46 | #include "en_port.h" | |
47 | ||
48 | ||
49 | static void mlx4_en_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) | |
50 | { | |
51 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
52 | struct mlx4_en_dev *mdev = priv->mdev; | |
53 | int err; | |
54 | ||
453a6082 | 55 | en_dbg(HW, priv, "Registering VLAN group:%p\n", grp); |
c27a02cd YP |
56 | priv->vlgrp = grp; |
57 | ||
58 | mutex_lock(&mdev->state_lock); | |
59 | if (mdev->device_up && priv->port_up) { | |
60 | err = mlx4_SET_VLAN_FLTR(mdev->dev, priv->port, grp); | |
61 | if (err) | |
453a6082 | 62 | en_err(priv, "Failed configuring VLAN filter\n"); |
c27a02cd YP |
63 | } |
64 | mutex_unlock(&mdev->state_lock); | |
65 | } | |
66 | ||
67 | static void mlx4_en_vlan_rx_add_vid(struct net_device *dev, unsigned short vid) | |
68 | { | |
69 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
70 | struct mlx4_en_dev *mdev = priv->mdev; | |
71 | int err; | |
4c3eb3ca | 72 | int idx; |
c27a02cd YP |
73 | |
74 | if (!priv->vlgrp) | |
75 | return; | |
76 | ||
453a6082 YP |
77 | en_dbg(HW, priv, "adding VLAN:%d (vlgrp entry:%p)\n", |
78 | vid, vlan_group_get_device(priv->vlgrp, vid)); | |
c27a02cd YP |
79 | |
80 | /* Add VID to port VLAN filter */ | |
81 | mutex_lock(&mdev->state_lock); | |
82 | if (mdev->device_up && priv->port_up) { | |
83 | err = mlx4_SET_VLAN_FLTR(mdev->dev, priv->port, priv->vlgrp); | |
84 | if (err) | |
453a6082 | 85 | en_err(priv, "Failed configuring VLAN filter\n"); |
c27a02cd | 86 | } |
4c3eb3ca EC |
87 | if (mlx4_register_vlan(mdev->dev, priv->port, vid, &idx)) |
88 | en_err(priv, "failed adding vlan %d\n", vid); | |
c27a02cd | 89 | mutex_unlock(&mdev->state_lock); |
4c3eb3ca | 90 | |
c27a02cd YP |
91 | } |
92 | ||
93 | static void mlx4_en_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid) | |
94 | { | |
95 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
96 | struct mlx4_en_dev *mdev = priv->mdev; | |
97 | int err; | |
4c3eb3ca | 98 | int idx; |
c27a02cd YP |
99 | |
100 | if (!priv->vlgrp) | |
101 | return; | |
102 | ||
453a6082 YP |
103 | en_dbg(HW, priv, "Killing VID:%d (vlgrp:%p vlgrp entry:%p)\n", |
104 | vid, priv->vlgrp, vlan_group_get_device(priv->vlgrp, vid)); | |
c27a02cd YP |
105 | vlan_group_set_device(priv->vlgrp, vid, NULL); |
106 | ||
107 | /* Remove VID from port VLAN filter */ | |
108 | mutex_lock(&mdev->state_lock); | |
4c3eb3ca EC |
109 | if (!mlx4_find_cached_vlan(mdev->dev, priv->port, vid, &idx)) |
110 | mlx4_unregister_vlan(mdev->dev, priv->port, idx); | |
111 | else | |
112 | en_err(priv, "could not find vid %d in cache\n", vid); | |
113 | ||
c27a02cd YP |
114 | if (mdev->device_up && priv->port_up) { |
115 | err = mlx4_SET_VLAN_FLTR(mdev->dev, priv->port, priv->vlgrp); | |
116 | if (err) | |
453a6082 | 117 | en_err(priv, "Failed configuring VLAN filter\n"); |
c27a02cd YP |
118 | } |
119 | mutex_unlock(&mdev->state_lock); | |
120 | } | |
121 | ||
122 | static u64 mlx4_en_mac_to_u64(u8 *addr) | |
123 | { | |
124 | u64 mac = 0; | |
125 | int i; | |
126 | ||
127 | for (i = 0; i < ETH_ALEN; i++) { | |
128 | mac <<= 8; | |
129 | mac |= addr[i]; | |
130 | } | |
131 | return mac; | |
132 | } | |
133 | ||
134 | static int mlx4_en_set_mac(struct net_device *dev, void *addr) | |
135 | { | |
136 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
137 | struct mlx4_en_dev *mdev = priv->mdev; | |
138 | struct sockaddr *saddr = addr; | |
139 | ||
140 | if (!is_valid_ether_addr(saddr->sa_data)) | |
141 | return -EADDRNOTAVAIL; | |
142 | ||
143 | memcpy(dev->dev_addr, saddr->sa_data, ETH_ALEN); | |
144 | priv->mac = mlx4_en_mac_to_u64(dev->dev_addr); | |
145 | queue_work(mdev->workqueue, &priv->mac_task); | |
146 | return 0; | |
147 | } | |
148 | ||
149 | static void mlx4_en_do_set_mac(struct work_struct *work) | |
150 | { | |
151 | struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv, | |
152 | mac_task); | |
153 | struct mlx4_en_dev *mdev = priv->mdev; | |
154 | int err = 0; | |
155 | ||
156 | mutex_lock(&mdev->state_lock); | |
157 | if (priv->port_up) { | |
158 | /* Remove old MAC and insert the new one */ | |
159 | mlx4_unregister_mac(mdev->dev, priv->port, priv->mac_index); | |
160 | err = mlx4_register_mac(mdev->dev, priv->port, | |
161 | priv->mac, &priv->mac_index); | |
162 | if (err) | |
453a6082 | 163 | en_err(priv, "Failed changing HW MAC address\n"); |
c27a02cd | 164 | } else |
453a6082 YP |
165 | en_dbg(HW, priv, "Port is down while " |
166 | "registering mac, exiting...\n"); | |
c27a02cd YP |
167 | |
168 | mutex_unlock(&mdev->state_lock); | |
169 | } | |
170 | ||
171 | static void mlx4_en_clear_list(struct net_device *dev) | |
172 | { | |
173 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
c27a02cd | 174 | |
ff6e2163 JP |
175 | kfree(priv->mc_addrs); |
176 | priv->mc_addrs_cnt = 0; | |
c27a02cd YP |
177 | } |
178 | ||
179 | static void mlx4_en_cache_mclist(struct net_device *dev) | |
180 | { | |
181 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
22bedad3 | 182 | struct netdev_hw_addr *ha; |
ff6e2163 JP |
183 | char *mc_addrs; |
184 | int mc_addrs_cnt = netdev_mc_count(dev); | |
185 | int i; | |
186 | ||
187 | mc_addrs = kmalloc(mc_addrs_cnt * ETH_ALEN, GFP_ATOMIC); | |
188 | if (!mc_addrs) { | |
189 | en_err(priv, "failed to allocate multicast list\n"); | |
190 | return; | |
c27a02cd | 191 | } |
ff6e2163 | 192 | i = 0; |
22bedad3 JP |
193 | netdev_for_each_mc_addr(ha, dev) |
194 | memcpy(mc_addrs + i++ * ETH_ALEN, ha->addr, ETH_ALEN); | |
ff6e2163 JP |
195 | priv->mc_addrs = mc_addrs; |
196 | priv->mc_addrs_cnt = mc_addrs_cnt; | |
c27a02cd YP |
197 | } |
198 | ||
199 | ||
200 | static void mlx4_en_set_multicast(struct net_device *dev) | |
201 | { | |
202 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
203 | ||
204 | if (!priv->port_up) | |
205 | return; | |
206 | ||
207 | queue_work(priv->mdev->workqueue, &priv->mcast_task); | |
208 | } | |
209 | ||
210 | static void mlx4_en_do_set_multicast(struct work_struct *work) | |
211 | { | |
212 | struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv, | |
213 | mcast_task); | |
214 | struct mlx4_en_dev *mdev = priv->mdev; | |
215 | struct net_device *dev = priv->dev; | |
c27a02cd YP |
216 | u64 mcast_addr = 0; |
217 | int err; | |
218 | ||
219 | mutex_lock(&mdev->state_lock); | |
220 | if (!mdev->device_up) { | |
453a6082 YP |
221 | en_dbg(HW, priv, "Card is not up, " |
222 | "ignoring multicast change.\n"); | |
c27a02cd YP |
223 | goto out; |
224 | } | |
225 | if (!priv->port_up) { | |
453a6082 YP |
226 | en_dbg(HW, priv, "Port is down, " |
227 | "ignoring multicast change.\n"); | |
c27a02cd YP |
228 | goto out; |
229 | } | |
230 | ||
231 | /* | |
232 | * Promsicuous mode: disable all filters | |
233 | */ | |
234 | ||
235 | if (dev->flags & IFF_PROMISC) { | |
236 | if (!(priv->flags & MLX4_EN_FLAG_PROMISC)) { | |
237 | if (netif_msg_rx_status(priv)) | |
453a6082 | 238 | en_warn(priv, "Entering promiscuous mode\n"); |
c27a02cd YP |
239 | priv->flags |= MLX4_EN_FLAG_PROMISC; |
240 | ||
241 | /* Enable promiscouos mode */ | |
242 | err = mlx4_SET_PORT_qpn_calc(mdev->dev, priv->port, | |
243 | priv->base_qpn, 1); | |
244 | if (err) | |
453a6082 YP |
245 | en_err(priv, "Failed enabling " |
246 | "promiscous mode\n"); | |
c27a02cd YP |
247 | |
248 | /* Disable port multicast filter (unconditionally) */ | |
249 | err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0, | |
250 | 0, MLX4_MCAST_DISABLE); | |
251 | if (err) | |
453a6082 YP |
252 | en_err(priv, "Failed disabling " |
253 | "multicast filter\n"); | |
c27a02cd YP |
254 | |
255 | /* Disable port VLAN filter */ | |
256 | err = mlx4_SET_VLAN_FLTR(mdev->dev, priv->port, NULL); | |
257 | if (err) | |
453a6082 | 258 | en_err(priv, "Failed disabling VLAN filter\n"); |
c27a02cd YP |
259 | } |
260 | goto out; | |
261 | } | |
262 | ||
263 | /* | |
264 | * Not in promiscous mode | |
265 | */ | |
266 | ||
267 | if (priv->flags & MLX4_EN_FLAG_PROMISC) { | |
268 | if (netif_msg_rx_status(priv)) | |
453a6082 | 269 | en_warn(priv, "Leaving promiscuous mode\n"); |
c27a02cd YP |
270 | priv->flags &= ~MLX4_EN_FLAG_PROMISC; |
271 | ||
272 | /* Disable promiscouos mode */ | |
273 | err = mlx4_SET_PORT_qpn_calc(mdev->dev, priv->port, | |
274 | priv->base_qpn, 0); | |
275 | if (err) | |
453a6082 | 276 | en_err(priv, "Failed disabling promiscous mode\n"); |
c27a02cd YP |
277 | |
278 | /* Enable port VLAN filter */ | |
279 | err = mlx4_SET_VLAN_FLTR(mdev->dev, priv->port, priv->vlgrp); | |
280 | if (err) | |
453a6082 | 281 | en_err(priv, "Failed enabling VLAN filter\n"); |
c27a02cd YP |
282 | } |
283 | ||
284 | /* Enable/disable the multicast filter according to IFF_ALLMULTI */ | |
285 | if (dev->flags & IFF_ALLMULTI) { | |
286 | err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0, | |
287 | 0, MLX4_MCAST_DISABLE); | |
288 | if (err) | |
453a6082 | 289 | en_err(priv, "Failed disabling multicast filter\n"); |
c27a02cd | 290 | } else { |
ff6e2163 JP |
291 | int i; |
292 | ||
c27a02cd YP |
293 | err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0, |
294 | 0, MLX4_MCAST_DISABLE); | |
295 | if (err) | |
453a6082 | 296 | en_err(priv, "Failed disabling multicast filter\n"); |
c27a02cd YP |
297 | |
298 | /* Flush mcast filter and init it with broadcast address */ | |
299 | mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, ETH_BCAST, | |
300 | 1, MLX4_MCAST_CONFIG); | |
301 | ||
302 | /* Update multicast list - we cache all addresses so they won't | |
303 | * change while HW is updated holding the command semaphor */ | |
304 | netif_tx_lock_bh(dev); | |
305 | mlx4_en_cache_mclist(dev); | |
306 | netif_tx_unlock_bh(dev); | |
ff6e2163 JP |
307 | for (i = 0; i < priv->mc_addrs_cnt; i++) { |
308 | mcast_addr = | |
309 | mlx4_en_mac_to_u64(priv->mc_addrs + i * ETH_ALEN); | |
c27a02cd YP |
310 | mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, |
311 | mcast_addr, 0, MLX4_MCAST_CONFIG); | |
312 | } | |
313 | err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0, | |
314 | 0, MLX4_MCAST_ENABLE); | |
315 | if (err) | |
453a6082 | 316 | en_err(priv, "Failed enabling multicast filter\n"); |
c27a02cd YP |
317 | |
318 | mlx4_en_clear_list(dev); | |
319 | } | |
320 | out: | |
321 | mutex_unlock(&mdev->state_lock); | |
322 | } | |
323 | ||
324 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
325 | static void mlx4_en_netpoll(struct net_device *dev) | |
326 | { | |
327 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
328 | struct mlx4_en_cq *cq; | |
329 | unsigned long flags; | |
330 | int i; | |
331 | ||
332 | for (i = 0; i < priv->rx_ring_num; i++) { | |
333 | cq = &priv->rx_cq[i]; | |
334 | spin_lock_irqsave(&cq->lock, flags); | |
335 | napi_synchronize(&cq->napi); | |
336 | mlx4_en_process_rx_cq(dev, cq, 0); | |
337 | spin_unlock_irqrestore(&cq->lock, flags); | |
338 | } | |
339 | } | |
340 | #endif | |
341 | ||
342 | static void mlx4_en_tx_timeout(struct net_device *dev) | |
343 | { | |
344 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
345 | struct mlx4_en_dev *mdev = priv->mdev; | |
346 | ||
347 | if (netif_msg_timer(priv)) | |
453a6082 | 348 | en_warn(priv, "Tx timeout called on port:%d\n", priv->port); |
c27a02cd | 349 | |
1e338db5 | 350 | priv->port_stats.tx_timeout++; |
453a6082 | 351 | en_dbg(DRV, priv, "Scheduling watchdog\n"); |
1e338db5 | 352 | queue_work(mdev->workqueue, &priv->watchdog_task); |
c27a02cd YP |
353 | } |
354 | ||
355 | ||
356 | static struct net_device_stats *mlx4_en_get_stats(struct net_device *dev) | |
357 | { | |
358 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
359 | ||
360 | spin_lock_bh(&priv->stats_lock); | |
361 | memcpy(&priv->ret_stats, &priv->stats, sizeof(priv->stats)); | |
362 | spin_unlock_bh(&priv->stats_lock); | |
363 | ||
364 | return &priv->ret_stats; | |
365 | } | |
366 | ||
367 | static void mlx4_en_set_default_moderation(struct mlx4_en_priv *priv) | |
368 | { | |
c27a02cd YP |
369 | struct mlx4_en_cq *cq; |
370 | int i; | |
371 | ||
372 | /* If we haven't received a specific coalescing setting | |
98a1708d | 373 | * (module param), we set the moderation parameters as follows: |
c27a02cd YP |
374 | * - moder_cnt is set to the number of mtu sized packets to |
375 | * satisfy our coelsing target. | |
376 | * - moder_time is set to a fixed value. | |
377 | */ | |
3db36fb2 | 378 | priv->rx_frames = MLX4_EN_RX_COAL_TARGET; |
60b9f9e5 | 379 | priv->rx_usecs = MLX4_EN_RX_COAL_TIME; |
453a6082 YP |
380 | en_dbg(INTR, priv, "Default coalesing params for mtu:%d - " |
381 | "rx_frames:%d rx_usecs:%d\n", | |
c27a02cd YP |
382 | priv->dev->mtu, priv->rx_frames, priv->rx_usecs); |
383 | ||
384 | /* Setup cq moderation params */ | |
385 | for (i = 0; i < priv->rx_ring_num; i++) { | |
386 | cq = &priv->rx_cq[i]; | |
387 | cq->moder_cnt = priv->rx_frames; | |
388 | cq->moder_time = priv->rx_usecs; | |
389 | } | |
390 | ||
391 | for (i = 0; i < priv->tx_ring_num; i++) { | |
392 | cq = &priv->tx_cq[i]; | |
393 | cq->moder_cnt = MLX4_EN_TX_COAL_PKTS; | |
394 | cq->moder_time = MLX4_EN_TX_COAL_TIME; | |
395 | } | |
396 | ||
397 | /* Reset auto-moderation params */ | |
398 | priv->pkt_rate_low = MLX4_EN_RX_RATE_LOW; | |
399 | priv->rx_usecs_low = MLX4_EN_RX_COAL_TIME_LOW; | |
400 | priv->pkt_rate_high = MLX4_EN_RX_RATE_HIGH; | |
401 | priv->rx_usecs_high = MLX4_EN_RX_COAL_TIME_HIGH; | |
402 | priv->sample_interval = MLX4_EN_SAMPLE_INTERVAL; | |
60b9f9e5 | 403 | priv->adaptive_rx_coal = 1; |
c27a02cd YP |
404 | priv->last_moder_time = MLX4_EN_AUTO_CONF; |
405 | priv->last_moder_jiffies = 0; | |
406 | priv->last_moder_packets = 0; | |
407 | priv->last_moder_tx_packets = 0; | |
408 | priv->last_moder_bytes = 0; | |
409 | } | |
410 | ||
411 | static void mlx4_en_auto_moderation(struct mlx4_en_priv *priv) | |
412 | { | |
413 | unsigned long period = (unsigned long) (jiffies - priv->last_moder_jiffies); | |
c27a02cd YP |
414 | struct mlx4_en_cq *cq; |
415 | unsigned long packets; | |
416 | unsigned long rate; | |
417 | unsigned long avg_pkt_size; | |
418 | unsigned long rx_packets; | |
419 | unsigned long rx_bytes; | |
a35ee541 | 420 | unsigned long rx_byte_diff; |
c27a02cd YP |
421 | unsigned long tx_packets; |
422 | unsigned long tx_pkt_diff; | |
423 | unsigned long rx_pkt_diff; | |
424 | int moder_time; | |
425 | int i, err; | |
426 | ||
427 | if (!priv->adaptive_rx_coal || period < priv->sample_interval * HZ) | |
428 | return; | |
429 | ||
430 | spin_lock_bh(&priv->stats_lock); | |
431 | rx_packets = priv->stats.rx_packets; | |
432 | rx_bytes = priv->stats.rx_bytes; | |
433 | tx_packets = priv->stats.tx_packets; | |
434 | spin_unlock_bh(&priv->stats_lock); | |
435 | ||
436 | if (!priv->last_moder_jiffies || !period) | |
437 | goto out; | |
438 | ||
439 | tx_pkt_diff = ((unsigned long) (tx_packets - | |
440 | priv->last_moder_tx_packets)); | |
441 | rx_pkt_diff = ((unsigned long) (rx_packets - | |
442 | priv->last_moder_packets)); | |
443 | packets = max(tx_pkt_diff, rx_pkt_diff); | |
a35ee541 YP |
444 | rx_byte_diff = rx_bytes - priv->last_moder_bytes; |
445 | rx_byte_diff = rx_byte_diff ? rx_byte_diff : 1; | |
c27a02cd YP |
446 | rate = packets * HZ / period; |
447 | avg_pkt_size = packets ? ((unsigned long) (rx_bytes - | |
448 | priv->last_moder_bytes)) / packets : 0; | |
449 | ||
450 | /* Apply auto-moderation only when packet rate exceeds a rate that | |
451 | * it matters */ | |
452 | if (rate > MLX4_EN_RX_RATE_THRESH) { | |
453 | /* If tx and rx packet rates are not balanced, assume that | |
454 | * traffic is mainly BW bound and apply maximum moderation. | |
455 | * Otherwise, moderate according to packet rate */ | |
a35ee541 YP |
456 | if (2 * tx_pkt_diff > 3 * rx_pkt_diff && |
457 | rx_pkt_diff / rx_byte_diff < | |
458 | MLX4_EN_SMALL_PKT_SIZE) | |
459 | moder_time = priv->rx_usecs_low; | |
460 | else if (2 * rx_pkt_diff > 3 * tx_pkt_diff) | |
c27a02cd | 461 | moder_time = priv->rx_usecs_high; |
a35ee541 | 462 | else { |
c27a02cd YP |
463 | if (rate < priv->pkt_rate_low) |
464 | moder_time = priv->rx_usecs_low; | |
465 | else if (rate > priv->pkt_rate_high) | |
466 | moder_time = priv->rx_usecs_high; | |
467 | else | |
468 | moder_time = (rate - priv->pkt_rate_low) * | |
469 | (priv->rx_usecs_high - priv->rx_usecs_low) / | |
470 | (priv->pkt_rate_high - priv->pkt_rate_low) + | |
471 | priv->rx_usecs_low; | |
472 | } | |
473 | } else { | |
474 | /* When packet rate is low, use default moderation rather than | |
475 | * 0 to prevent interrupt storms if traffic suddenly increases */ | |
476 | moder_time = priv->rx_usecs; | |
477 | } | |
478 | ||
453a6082 YP |
479 | en_dbg(INTR, priv, "tx rate:%lu rx_rate:%lu\n", |
480 | tx_pkt_diff * HZ / period, rx_pkt_diff * HZ / period); | |
c27a02cd | 481 | |
453a6082 YP |
482 | en_dbg(INTR, priv, "Rx moder_time changed from:%d to %d period:%lu " |
483 | "[jiff] packets:%lu avg_pkt_size:%lu rate:%lu [p/s])\n", | |
c27a02cd YP |
484 | priv->last_moder_time, moder_time, period, packets, |
485 | avg_pkt_size, rate); | |
486 | ||
487 | if (moder_time != priv->last_moder_time) { | |
488 | priv->last_moder_time = moder_time; | |
489 | for (i = 0; i < priv->rx_ring_num; i++) { | |
490 | cq = &priv->rx_cq[i]; | |
491 | cq->moder_time = moder_time; | |
492 | err = mlx4_en_set_cq_moder(priv, cq); | |
493 | if (err) { | |
453a6082 | 494 | en_err(priv, "Failed modifying moderation for cq:%d\n", i); |
c27a02cd YP |
495 | break; |
496 | } | |
497 | } | |
498 | } | |
499 | ||
500 | out: | |
501 | priv->last_moder_packets = rx_packets; | |
502 | priv->last_moder_tx_packets = tx_packets; | |
503 | priv->last_moder_bytes = rx_bytes; | |
504 | priv->last_moder_jiffies = jiffies; | |
505 | } | |
506 | ||
507 | static void mlx4_en_do_get_stats(struct work_struct *work) | |
508 | { | |
bf6aede7 | 509 | struct delayed_work *delay = to_delayed_work(work); |
c27a02cd YP |
510 | struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv, |
511 | stats_task); | |
512 | struct mlx4_en_dev *mdev = priv->mdev; | |
513 | int err; | |
514 | ||
515 | err = mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 0); | |
516 | if (err) | |
2381a55c | 517 | en_dbg(HW, priv, "Could not update stats\n"); |
c27a02cd YP |
518 | |
519 | mutex_lock(&mdev->state_lock); | |
520 | if (mdev->device_up) { | |
521 | if (priv->port_up) | |
522 | mlx4_en_auto_moderation(priv); | |
523 | ||
524 | queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY); | |
525 | } | |
526 | mutex_unlock(&mdev->state_lock); | |
527 | } | |
528 | ||
529 | static void mlx4_en_linkstate(struct work_struct *work) | |
530 | { | |
531 | struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv, | |
532 | linkstate_task); | |
533 | struct mlx4_en_dev *mdev = priv->mdev; | |
534 | int linkstate = priv->link_state; | |
535 | ||
536 | mutex_lock(&mdev->state_lock); | |
537 | /* If observable port state changed set carrier state and | |
538 | * report to system log */ | |
539 | if (priv->last_link_state != linkstate) { | |
540 | if (linkstate == MLX4_DEV_EVENT_PORT_DOWN) { | |
453a6082 | 541 | en_dbg(LINK, priv, "Link Down\n"); |
c27a02cd YP |
542 | netif_carrier_off(priv->dev); |
543 | } else { | |
453a6082 | 544 | en_dbg(LINK, priv, "Link Up\n"); |
c27a02cd YP |
545 | netif_carrier_on(priv->dev); |
546 | } | |
547 | } | |
548 | priv->last_link_state = linkstate; | |
549 | mutex_unlock(&mdev->state_lock); | |
550 | } | |
551 | ||
552 | ||
18cc42a3 | 553 | int mlx4_en_start_port(struct net_device *dev) |
c27a02cd YP |
554 | { |
555 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
556 | struct mlx4_en_dev *mdev = priv->mdev; | |
557 | struct mlx4_en_cq *cq; | |
558 | struct mlx4_en_tx_ring *tx_ring; | |
c27a02cd YP |
559 | int rx_index = 0; |
560 | int tx_index = 0; | |
c27a02cd YP |
561 | int err = 0; |
562 | int i; | |
563 | int j; | |
564 | ||
565 | if (priv->port_up) { | |
453a6082 | 566 | en_dbg(DRV, priv, "start port called while port already up\n"); |
c27a02cd YP |
567 | return 0; |
568 | } | |
569 | ||
570 | /* Calculate Rx buf size */ | |
571 | dev->mtu = min(dev->mtu, priv->max_mtu); | |
572 | mlx4_en_calc_rx_buf(dev); | |
453a6082 | 573 | en_dbg(DRV, priv, "Rx buf size:%d\n", priv->rx_skb_size); |
38aab07c | 574 | |
c27a02cd | 575 | /* Configure rx cq's and rings */ |
38aab07c YP |
576 | err = mlx4_en_activate_rx_rings(priv); |
577 | if (err) { | |
453a6082 | 578 | en_err(priv, "Failed to activate RX rings\n"); |
38aab07c YP |
579 | return err; |
580 | } | |
c27a02cd YP |
581 | for (i = 0; i < priv->rx_ring_num; i++) { |
582 | cq = &priv->rx_cq[i]; | |
c27a02cd YP |
583 | |
584 | err = mlx4_en_activate_cq(priv, cq); | |
585 | if (err) { | |
453a6082 | 586 | en_err(priv, "Failed activating Rx CQ\n"); |
a4233304 | 587 | goto cq_err; |
c27a02cd YP |
588 | } |
589 | for (j = 0; j < cq->size; j++) | |
590 | cq->buf[j].owner_sr_opcode = MLX4_CQE_OWNER_MASK; | |
591 | err = mlx4_en_set_cq_moder(priv, cq); | |
592 | if (err) { | |
453a6082 | 593 | en_err(priv, "Failed setting cq moderation parameters"); |
c27a02cd YP |
594 | mlx4_en_deactivate_cq(priv, cq); |
595 | goto cq_err; | |
596 | } | |
597 | mlx4_en_arm_cq(priv, cq); | |
38aab07c | 598 | priv->rx_ring[i].cqn = cq->mcq.cqn; |
c27a02cd YP |
599 | ++rx_index; |
600 | } | |
601 | ||
c27a02cd YP |
602 | err = mlx4_en_config_rss_steer(priv); |
603 | if (err) { | |
453a6082 | 604 | en_err(priv, "Failed configuring rss steering\n"); |
38aab07c | 605 | goto cq_err; |
c27a02cd YP |
606 | } |
607 | ||
608 | /* Configure tx cq's and rings */ | |
609 | for (i = 0; i < priv->tx_ring_num; i++) { | |
610 | /* Configure cq */ | |
611 | cq = &priv->tx_cq[i]; | |
612 | err = mlx4_en_activate_cq(priv, cq); | |
613 | if (err) { | |
453a6082 | 614 | en_err(priv, "Failed allocating Tx CQ\n"); |
c27a02cd YP |
615 | goto tx_err; |
616 | } | |
617 | err = mlx4_en_set_cq_moder(priv, cq); | |
618 | if (err) { | |
453a6082 | 619 | en_err(priv, "Failed setting cq moderation parameters"); |
c27a02cd YP |
620 | mlx4_en_deactivate_cq(priv, cq); |
621 | goto tx_err; | |
622 | } | |
453a6082 | 623 | en_dbg(DRV, priv, "Resetting index of collapsed CQ:%d to -1\n", i); |
c27a02cd YP |
624 | cq->buf->wqe_index = cpu_to_be16(0xffff); |
625 | ||
626 | /* Configure ring */ | |
627 | tx_ring = &priv->tx_ring[i]; | |
9f519f68 | 628 | err = mlx4_en_activate_tx_ring(priv, tx_ring, cq->mcq.cqn); |
c27a02cd | 629 | if (err) { |
453a6082 | 630 | en_err(priv, "Failed allocating Tx ring\n"); |
c27a02cd YP |
631 | mlx4_en_deactivate_cq(priv, cq); |
632 | goto tx_err; | |
633 | } | |
634 | /* Set initial ownership of all Tx TXBBs to SW (1) */ | |
635 | for (j = 0; j < tx_ring->buf_size; j += STAMP_STRIDE) | |
636 | *((u32 *) (tx_ring->buf + j)) = 0xffffffff; | |
637 | ++tx_index; | |
638 | } | |
639 | ||
640 | /* Configure port */ | |
641 | err = mlx4_SET_PORT_general(mdev->dev, priv->port, | |
642 | priv->rx_skb_size + ETH_FCS_LEN, | |
d53b93f2 YP |
643 | priv->prof->tx_pause, |
644 | priv->prof->tx_ppp, | |
645 | priv->prof->rx_pause, | |
646 | priv->prof->rx_ppp); | |
c27a02cd | 647 | if (err) { |
453a6082 YP |
648 | en_err(priv, "Failed setting port general configurations " |
649 | "for port %d, with error %d\n", priv->port, err); | |
c27a02cd YP |
650 | goto tx_err; |
651 | } | |
652 | /* Set default qp number */ | |
653 | err = mlx4_SET_PORT_qpn_calc(mdev->dev, priv->port, priv->base_qpn, 0); | |
654 | if (err) { | |
453a6082 | 655 | en_err(priv, "Failed setting default qp numbers\n"); |
c27a02cd YP |
656 | goto tx_err; |
657 | } | |
658 | /* Set port mac number */ | |
453a6082 | 659 | en_dbg(DRV, priv, "Setting mac for port %d\n", priv->port); |
c27a02cd YP |
660 | err = mlx4_register_mac(mdev->dev, priv->port, |
661 | priv->mac, &priv->mac_index); | |
662 | if (err) { | |
453a6082 | 663 | en_err(priv, "Failed setting port mac\n"); |
c27a02cd YP |
664 | goto tx_err; |
665 | } | |
666 | ||
667 | /* Init port */ | |
453a6082 | 668 | en_dbg(HW, priv, "Initializing port\n"); |
c27a02cd YP |
669 | err = mlx4_INIT_PORT(mdev->dev, priv->port); |
670 | if (err) { | |
453a6082 | 671 | en_err(priv, "Failed Initializing port\n"); |
c27a02cd YP |
672 | goto mac_err; |
673 | } | |
674 | ||
675 | /* Schedule multicast task to populate multicast list */ | |
676 | queue_work(mdev->workqueue, &priv->mcast_task); | |
677 | ||
678 | priv->port_up = true; | |
a11faac7 | 679 | netif_tx_start_all_queues(dev); |
c27a02cd YP |
680 | return 0; |
681 | ||
682 | mac_err: | |
683 | mlx4_unregister_mac(mdev->dev, priv->port, priv->mac_index); | |
684 | tx_err: | |
685 | while (tx_index--) { | |
686 | mlx4_en_deactivate_tx_ring(priv, &priv->tx_ring[tx_index]); | |
687 | mlx4_en_deactivate_cq(priv, &priv->tx_cq[tx_index]); | |
688 | } | |
689 | ||
690 | mlx4_en_release_rss_steer(priv); | |
c27a02cd YP |
691 | cq_err: |
692 | while (rx_index--) | |
693 | mlx4_en_deactivate_cq(priv, &priv->rx_cq[rx_index]); | |
38aab07c YP |
694 | for (i = 0; i < priv->rx_ring_num; i++) |
695 | mlx4_en_deactivate_rx_ring(priv, &priv->rx_ring[i]); | |
c27a02cd YP |
696 | |
697 | return err; /* need to close devices */ | |
698 | } | |
699 | ||
700 | ||
18cc42a3 | 701 | void mlx4_en_stop_port(struct net_device *dev) |
c27a02cd YP |
702 | { |
703 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
704 | struct mlx4_en_dev *mdev = priv->mdev; | |
705 | int i; | |
706 | ||
707 | if (!priv->port_up) { | |
453a6082 | 708 | en_dbg(DRV, priv, "stop port called while port already down\n"); |
c27a02cd YP |
709 | return; |
710 | } | |
c27a02cd YP |
711 | |
712 | /* Synchronize with tx routine */ | |
713 | netif_tx_lock_bh(dev); | |
3c05f5ef | 714 | netif_tx_stop_all_queues(dev); |
c27a02cd YP |
715 | netif_tx_unlock_bh(dev); |
716 | ||
717 | /* close port*/ | |
3c05f5ef | 718 | priv->port_up = false; |
c27a02cd YP |
719 | mlx4_CLOSE_PORT(mdev->dev, priv->port); |
720 | ||
721 | /* Unregister Mac address for the port */ | |
722 | mlx4_unregister_mac(mdev->dev, priv->port, priv->mac_index); | |
723 | ||
724 | /* Free TX Rings */ | |
725 | for (i = 0; i < priv->tx_ring_num; i++) { | |
726 | mlx4_en_deactivate_tx_ring(priv, &priv->tx_ring[i]); | |
727 | mlx4_en_deactivate_cq(priv, &priv->tx_cq[i]); | |
728 | } | |
729 | msleep(10); | |
730 | ||
731 | for (i = 0; i < priv->tx_ring_num; i++) | |
732 | mlx4_en_free_tx_buf(dev, &priv->tx_ring[i]); | |
733 | ||
734 | /* Free RSS qps */ | |
735 | mlx4_en_release_rss_steer(priv); | |
736 | ||
737 | /* Free RX Rings */ | |
738 | for (i = 0; i < priv->rx_ring_num; i++) { | |
739 | mlx4_en_deactivate_rx_ring(priv, &priv->rx_ring[i]); | |
740 | while (test_bit(NAPI_STATE_SCHED, &priv->rx_cq[i].napi.state)) | |
741 | msleep(1); | |
742 | mlx4_en_deactivate_cq(priv, &priv->rx_cq[i]); | |
743 | } | |
744 | } | |
745 | ||
746 | static void mlx4_en_restart(struct work_struct *work) | |
747 | { | |
748 | struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv, | |
749 | watchdog_task); | |
750 | struct mlx4_en_dev *mdev = priv->mdev; | |
751 | struct net_device *dev = priv->dev; | |
752 | ||
453a6082 | 753 | en_dbg(DRV, priv, "Watchdog task called for port %d\n", priv->port); |
1e338db5 YP |
754 | |
755 | mutex_lock(&mdev->state_lock); | |
756 | if (priv->port_up) { | |
757 | mlx4_en_stop_port(dev); | |
758 | if (mlx4_en_start_port(dev)) | |
453a6082 | 759 | en_err(priv, "Failed restarting port %d\n", priv->port); |
1e338db5 YP |
760 | } |
761 | mutex_unlock(&mdev->state_lock); | |
c27a02cd YP |
762 | } |
763 | ||
764 | ||
765 | static int mlx4_en_open(struct net_device *dev) | |
766 | { | |
767 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
768 | struct mlx4_en_dev *mdev = priv->mdev; | |
769 | int i; | |
770 | int err = 0; | |
771 | ||
772 | mutex_lock(&mdev->state_lock); | |
773 | ||
774 | if (!mdev->device_up) { | |
453a6082 | 775 | en_err(priv, "Cannot open - device down/disabled\n"); |
c27a02cd YP |
776 | err = -EBUSY; |
777 | goto out; | |
778 | } | |
779 | ||
780 | /* Reset HW statistics and performance counters */ | |
781 | if (mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 1)) | |
453a6082 | 782 | en_dbg(HW, priv, "Failed dumping statistics\n"); |
c27a02cd YP |
783 | |
784 | memset(&priv->stats, 0, sizeof(priv->stats)); | |
785 | memset(&priv->pstats, 0, sizeof(priv->pstats)); | |
786 | ||
787 | for (i = 0; i < priv->tx_ring_num; i++) { | |
788 | priv->tx_ring[i].bytes = 0; | |
789 | priv->tx_ring[i].packets = 0; | |
790 | } | |
791 | for (i = 0; i < priv->rx_ring_num; i++) { | |
792 | priv->rx_ring[i].bytes = 0; | |
793 | priv->rx_ring[i].packets = 0; | |
794 | } | |
795 | ||
796 | mlx4_en_set_default_moderation(priv); | |
797 | err = mlx4_en_start_port(dev); | |
798 | if (err) | |
453a6082 | 799 | en_err(priv, "Failed starting port:%d\n", priv->port); |
c27a02cd YP |
800 | |
801 | out: | |
802 | mutex_unlock(&mdev->state_lock); | |
803 | return err; | |
804 | } | |
805 | ||
806 | ||
807 | static int mlx4_en_close(struct net_device *dev) | |
808 | { | |
809 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
810 | struct mlx4_en_dev *mdev = priv->mdev; | |
811 | ||
453a6082 | 812 | en_dbg(IFDOWN, priv, "Close port called\n"); |
c27a02cd YP |
813 | |
814 | mutex_lock(&mdev->state_lock); | |
815 | ||
816 | mlx4_en_stop_port(dev); | |
817 | netif_carrier_off(dev); | |
818 | ||
819 | mutex_unlock(&mdev->state_lock); | |
820 | return 0; | |
821 | } | |
822 | ||
18cc42a3 | 823 | void mlx4_en_free_resources(struct mlx4_en_priv *priv) |
c27a02cd YP |
824 | { |
825 | int i; | |
826 | ||
827 | for (i = 0; i < priv->tx_ring_num; i++) { | |
828 | if (priv->tx_ring[i].tx_info) | |
829 | mlx4_en_destroy_tx_ring(priv, &priv->tx_ring[i]); | |
830 | if (priv->tx_cq[i].buf) | |
831 | mlx4_en_destroy_cq(priv, &priv->tx_cq[i]); | |
832 | } | |
833 | ||
834 | for (i = 0; i < priv->rx_ring_num; i++) { | |
835 | if (priv->rx_ring[i].rx_info) | |
836 | mlx4_en_destroy_rx_ring(priv, &priv->rx_ring[i]); | |
837 | if (priv->rx_cq[i].buf) | |
838 | mlx4_en_destroy_cq(priv, &priv->rx_cq[i]); | |
839 | } | |
840 | } | |
841 | ||
18cc42a3 | 842 | int mlx4_en_alloc_resources(struct mlx4_en_priv *priv) |
c27a02cd | 843 | { |
c27a02cd YP |
844 | struct mlx4_en_port_profile *prof = priv->prof; |
845 | int i; | |
846 | ||
847 | /* Create tx Rings */ | |
848 | for (i = 0; i < priv->tx_ring_num; i++) { | |
849 | if (mlx4_en_create_cq(priv, &priv->tx_cq[i], | |
850 | prof->tx_ring_size, i, TX)) | |
851 | goto err; | |
852 | ||
853 | if (mlx4_en_create_tx_ring(priv, &priv->tx_ring[i], | |
854 | prof->tx_ring_size, TXBB_SIZE)) | |
855 | goto err; | |
856 | } | |
857 | ||
858 | /* Create rx Rings */ | |
859 | for (i = 0; i < priv->rx_ring_num; i++) { | |
860 | if (mlx4_en_create_cq(priv, &priv->rx_cq[i], | |
861 | prof->rx_ring_size, i, RX)) | |
862 | goto err; | |
863 | ||
864 | if (mlx4_en_create_rx_ring(priv, &priv->rx_ring[i], | |
865 | prof->rx_ring_size, priv->stride)) | |
866 | goto err; | |
867 | } | |
868 | ||
869 | return 0; | |
870 | ||
871 | err: | |
453a6082 | 872 | en_err(priv, "Failed to allocate NIC resources\n"); |
c27a02cd YP |
873 | return -ENOMEM; |
874 | } | |
875 | ||
876 | ||
877 | void mlx4_en_destroy_netdev(struct net_device *dev) | |
878 | { | |
879 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
880 | struct mlx4_en_dev *mdev = priv->mdev; | |
881 | ||
453a6082 | 882 | en_dbg(DRV, priv, "Destroying netdev on port:%d\n", priv->port); |
c27a02cd YP |
883 | |
884 | /* Unregister device - this will close the port if it was up */ | |
885 | if (priv->registered) | |
886 | unregister_netdev(dev); | |
887 | ||
888 | if (priv->allocated) | |
889 | mlx4_free_hwq_res(mdev->dev, &priv->res, MLX4_EN_PAGE_SIZE); | |
890 | ||
891 | cancel_delayed_work(&priv->stats_task); | |
c27a02cd YP |
892 | /* flush any pending task for this netdev */ |
893 | flush_workqueue(mdev->workqueue); | |
894 | ||
895 | /* Detach the netdev so tasks would not attempt to access it */ | |
896 | mutex_lock(&mdev->state_lock); | |
897 | mdev->pndev[priv->port] = NULL; | |
898 | mutex_unlock(&mdev->state_lock); | |
899 | ||
900 | mlx4_en_free_resources(priv); | |
901 | free_netdev(dev); | |
902 | } | |
903 | ||
904 | static int mlx4_en_change_mtu(struct net_device *dev, int new_mtu) | |
905 | { | |
906 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
907 | struct mlx4_en_dev *mdev = priv->mdev; | |
908 | int err = 0; | |
909 | ||
453a6082 | 910 | en_dbg(DRV, priv, "Change MTU called - current:%d new:%d\n", |
c27a02cd YP |
911 | dev->mtu, new_mtu); |
912 | ||
913 | if ((new_mtu < MLX4_EN_MIN_MTU) || (new_mtu > priv->max_mtu)) { | |
453a6082 | 914 | en_err(priv, "Bad MTU size:%d.\n", new_mtu); |
c27a02cd YP |
915 | return -EPERM; |
916 | } | |
917 | dev->mtu = new_mtu; | |
918 | ||
919 | if (netif_running(dev)) { | |
920 | mutex_lock(&mdev->state_lock); | |
921 | if (!mdev->device_up) { | |
922 | /* NIC is probably restarting - let watchdog task reset | |
923 | * the port */ | |
453a6082 | 924 | en_dbg(DRV, priv, "Change MTU called with card down!?\n"); |
c27a02cd YP |
925 | } else { |
926 | mlx4_en_stop_port(dev); | |
927 | mlx4_en_set_default_moderation(priv); | |
928 | err = mlx4_en_start_port(dev); | |
929 | if (err) { | |
453a6082 | 930 | en_err(priv, "Failed restarting port:%d\n", |
c27a02cd YP |
931 | priv->port); |
932 | queue_work(mdev->workqueue, &priv->watchdog_task); | |
933 | } | |
934 | } | |
935 | mutex_unlock(&mdev->state_lock); | |
936 | } | |
937 | return 0; | |
938 | } | |
939 | ||
3addc568 SH |
940 | static const struct net_device_ops mlx4_netdev_ops = { |
941 | .ndo_open = mlx4_en_open, | |
942 | .ndo_stop = mlx4_en_close, | |
943 | .ndo_start_xmit = mlx4_en_xmit, | |
f813cad8 | 944 | .ndo_select_queue = mlx4_en_select_queue, |
3addc568 SH |
945 | .ndo_get_stats = mlx4_en_get_stats, |
946 | .ndo_set_multicast_list = mlx4_en_set_multicast, | |
947 | .ndo_set_mac_address = mlx4_en_set_mac, | |
52255bbe | 948 | .ndo_validate_addr = eth_validate_addr, |
3addc568 SH |
949 | .ndo_change_mtu = mlx4_en_change_mtu, |
950 | .ndo_tx_timeout = mlx4_en_tx_timeout, | |
951 | .ndo_vlan_rx_register = mlx4_en_vlan_rx_register, | |
952 | .ndo_vlan_rx_add_vid = mlx4_en_vlan_rx_add_vid, | |
953 | .ndo_vlan_rx_kill_vid = mlx4_en_vlan_rx_kill_vid, | |
954 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
955 | .ndo_poll_controller = mlx4_en_netpoll, | |
956 | #endif | |
957 | }; | |
958 | ||
c27a02cd YP |
959 | int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port, |
960 | struct mlx4_en_port_profile *prof) | |
961 | { | |
962 | struct net_device *dev; | |
963 | struct mlx4_en_priv *priv; | |
964 | int i; | |
965 | int err; | |
966 | ||
f813cad8 | 967 | dev = alloc_etherdev_mq(sizeof(struct mlx4_en_priv), prof->tx_ring_num); |
c27a02cd YP |
968 | if (dev == NULL) { |
969 | mlx4_err(mdev, "Net device allocation failed\n"); | |
970 | return -ENOMEM; | |
971 | } | |
972 | ||
973 | SET_NETDEV_DEV(dev, &mdev->dev->pdev->dev); | |
741a00be | 974 | dev->dev_id = port - 1; |
c27a02cd YP |
975 | |
976 | /* | |
977 | * Initialize driver private data | |
978 | */ | |
979 | ||
980 | priv = netdev_priv(dev); | |
981 | memset(priv, 0, sizeof(struct mlx4_en_priv)); | |
982 | priv->dev = dev; | |
983 | priv->mdev = mdev; | |
984 | priv->prof = prof; | |
985 | priv->port = port; | |
986 | priv->port_up = false; | |
987 | priv->rx_csum = 1; | |
988 | priv->flags = prof->flags; | |
989 | priv->tx_ring_num = prof->tx_ring_num; | |
990 | priv->rx_ring_num = prof->rx_ring_num; | |
c27a02cd YP |
991 | priv->mac_index = -1; |
992 | priv->msg_enable = MLX4_EN_MSG_LEVEL; | |
993 | spin_lock_init(&priv->stats_lock); | |
994 | INIT_WORK(&priv->mcast_task, mlx4_en_do_set_multicast); | |
995 | INIT_WORK(&priv->mac_task, mlx4_en_do_set_mac); | |
c27a02cd YP |
996 | INIT_WORK(&priv->watchdog_task, mlx4_en_restart); |
997 | INIT_WORK(&priv->linkstate_task, mlx4_en_linkstate); | |
998 | INIT_DELAYED_WORK(&priv->stats_task, mlx4_en_do_get_stats); | |
999 | ||
1000 | /* Query for default mac and max mtu */ | |
1001 | priv->max_mtu = mdev->dev->caps.eth_mtu_cap[priv->port]; | |
1002 | priv->mac = mdev->dev->caps.def_mac[priv->port]; | |
1003 | if (ILLEGAL_MAC(priv->mac)) { | |
453a6082 | 1004 | en_err(priv, "Port: %d, invalid mac burned: 0x%llx, quiting\n", |
c27a02cd YP |
1005 | priv->port, priv->mac); |
1006 | err = -EINVAL; | |
1007 | goto out; | |
1008 | } | |
1009 | ||
1010 | priv->stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) + | |
1011 | DS_SIZE * MLX4_EN_MAX_RX_FRAGS); | |
1012 | err = mlx4_en_alloc_resources(priv); | |
1013 | if (err) | |
1014 | goto out; | |
1015 | ||
c27a02cd YP |
1016 | /* Allocate page for receive rings */ |
1017 | err = mlx4_alloc_hwq_res(mdev->dev, &priv->res, | |
1018 | MLX4_EN_PAGE_SIZE, MLX4_EN_PAGE_SIZE); | |
1019 | if (err) { | |
453a6082 | 1020 | en_err(priv, "Failed to allocate page for rx qps\n"); |
c27a02cd YP |
1021 | goto out; |
1022 | } | |
1023 | priv->allocated = 1; | |
1024 | ||
c27a02cd YP |
1025 | /* |
1026 | * Initialize netdev entry points | |
1027 | */ | |
3addc568 | 1028 | dev->netdev_ops = &mlx4_netdev_ops; |
c27a02cd | 1029 | dev->watchdog_timeo = MLX4_EN_WATCHDOG_TIMEOUT; |
f813cad8 | 1030 | dev->real_num_tx_queues = MLX4_EN_NUM_TX_RINGS; |
3addc568 | 1031 | |
c27a02cd YP |
1032 | SET_ETHTOOL_OPS(dev, &mlx4_en_ethtool_ops); |
1033 | ||
1034 | /* Set defualt MAC */ | |
1035 | dev->addr_len = ETH_ALEN; | |
1036 | for (i = 0; i < ETH_ALEN; i++) | |
1037 | dev->dev_addr[ETH_ALEN - 1 - i] = | |
1038 | (u8) (priv->mac >> (8 * i)); | |
1039 | ||
1040 | /* | |
1041 | * Set driver features | |
1042 | */ | |
1043 | dev->features |= NETIF_F_SG; | |
e486973e | 1044 | dev->vlan_features |= NETIF_F_SG; |
45b4d66d | 1045 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; |
e486973e | 1046 | dev->vlan_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; |
c27a02cd YP |
1047 | dev->features |= NETIF_F_HIGHDMA; |
1048 | dev->features |= NETIF_F_HW_VLAN_TX | | |
1049 | NETIF_F_HW_VLAN_RX | | |
1050 | NETIF_F_HW_VLAN_FILTER; | |
1051 | if (mdev->profile.num_lro) | |
1052 | dev->features |= NETIF_F_LRO; | |
1053 | if (mdev->LSO_support) { | |
1054 | dev->features |= NETIF_F_TSO; | |
1055 | dev->features |= NETIF_F_TSO6; | |
e486973e YP |
1056 | dev->vlan_features |= NETIF_F_TSO; |
1057 | dev->vlan_features |= NETIF_F_TSO6; | |
c27a02cd YP |
1058 | } |
1059 | ||
1060 | mdev->pndev[port] = dev; | |
1061 | ||
1062 | netif_carrier_off(dev); | |
1063 | err = register_netdev(dev); | |
1064 | if (err) { | |
453a6082 | 1065 | en_err(priv, "Netdev registration failed for port %d\n", port); |
c27a02cd YP |
1066 | goto out; |
1067 | } | |
453a6082 YP |
1068 | |
1069 | en_warn(priv, "Using %d TX rings\n", prof->tx_ring_num); | |
1070 | en_warn(priv, "Using %d RX rings\n", prof->rx_ring_num); | |
1071 | ||
c27a02cd YP |
1072 | priv->registered = 1; |
1073 | queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY); | |
1074 | return 0; | |
1075 | ||
1076 | out: | |
1077 | mlx4_en_destroy_netdev(dev); | |
1078 | return err; | |
1079 | } | |
1080 |