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[net-next-2.6.git] / drivers / net / bnx2x / bnx2x_ethtool.c
CommitLineData
de0c62db
DK		 1/* bnx2x_ethtool.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2010 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17#include <linux/ethtool.h>
18#include <linux/netdevice.h>
19#include <linux/types.h>
20#include <linux/sched.h>
21#include <linux/crc32.h>
22
23
24#include "bnx2x.h"
25#include "bnx2x_cmn.h"
26#include "bnx2x_dump.h"
27
de0c62db
DK		 28static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
29{
30 struct bnx2x *bp = netdev_priv(dev);
a22f0788
YR		 31 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
32 /* Dual Media boards present all available port types */
33 cmd->supported = bp->port.supported[cfg_idx] |
34 (bp->port.supported[cfg_idx ^ 1] &
35 (SUPPORTED_TP | SUPPORTED_FIBRE));
36 cmd->advertising = bp->port.advertising[cfg_idx];
de0c62db
DK		 37
38 if ((bp->state == BNX2X_STATE_OPEN) &&
39 !(bp->flags & MF_FUNC_DIS) &&
40 (bp->link_vars.link_up)) {
41 cmd->speed = bp->link_vars.line_speed;
42 cmd->duplex = bp->link_vars.duplex;
de0c62db 43 } else {
f2e0899f 44
a22f0788
YR		 45 cmd->speed = bp->link_params.req_line_speed[cfg_idx];
46 cmd->duplex = bp->link_params.req_duplex[cfg_idx];
de0c62db 47 }
f2e0899f
DK		 48 if (IS_MF(bp)) {
49 u16 vn_max_rate = ((bp->mf_config[BP_VN(bp)] &
50 FUNC_MF_CFG_MAX_BW_MASK) >> FUNC_MF_CFG_MAX_BW_SHIFT) *
51 100;
52
53 if (vn_max_rate < cmd->speed)
54 cmd->speed = vn_max_rate;
55 }
de0c62db 56
a22f0788
YR		 57 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
58 cmd->port = PORT_TP;
59 else if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
60 cmd->port = PORT_FIBRE;
61 else
62 BNX2X_ERR("XGXS PHY Failure detected\n");
63
de0c62db
DK		 64 cmd->phy_address = bp->mdio.prtad;
65 cmd->transceiver = XCVR_INTERNAL;
66
a22f0788 67 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
de0c62db
DK		 68 cmd->autoneg = AUTONEG_ENABLE;
69 else
70 cmd->autoneg = AUTONEG_DISABLE;
71
72 cmd->maxtxpkt = 0;
73 cmd->maxrxpkt = 0;
74
75 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
76 DP_LEVEL " supported 0x%x advertising 0x%x speed %d\n"
77 DP_LEVEL " duplex %d port %d phy_address %d transceiver %d\n"
78 DP_LEVEL " autoneg %d maxtxpkt %d maxrxpkt %d\n",
79 cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
80 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
81 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
82
83 return 0;
84}
85
86static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
87{
88 struct bnx2x *bp = netdev_priv(dev);
a22f0788 89 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
de0c62db 90
fb3bff17 91 if (IS_MF(bp))
de0c62db
DK		 92 return 0;
93
94 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
95 DP_LEVEL " supported 0x%x advertising 0x%x speed %d\n"
96 DP_LEVEL " duplex %d port %d phy_address %d transceiver %d\n"
97 DP_LEVEL " autoneg %d maxtxpkt %d maxrxpkt %d\n",
98 cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
99 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
100 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
101
a22f0788
YR		 102 cfg_idx = bnx2x_get_link_cfg_idx(bp);
103 old_multi_phy_config = bp->link_params.multi_phy_config;
104 switch (cmd->port) {
105 case PORT_TP:
106 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
107 break; /* no port change */
108
109 if (!(bp->port.supported[0] & SUPPORTED_TP ||
110 bp->port.supported[1] & SUPPORTED_TP)) {
111 DP(NETIF_MSG_LINK, "Unsupported port type\n");
112 return -EINVAL;
113 }
114 bp->link_params.multi_phy_config &=
115 ~PORT_HW_CFG_PHY_SELECTION_MASK;
116 if (bp->link_params.multi_phy_config &
117 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
118 bp->link_params.multi_phy_config |=
119 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
120 else
121 bp->link_params.multi_phy_config |=
122 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
123 break;
124 case PORT_FIBRE:
125 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
126 break; /* no port change */
127
128 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
129 bp->port.supported[1] & SUPPORTED_FIBRE)) {
130 DP(NETIF_MSG_LINK, "Unsupported port type\n");
131 return -EINVAL;
132 }
133 bp->link_params.multi_phy_config &=
134 ~PORT_HW_CFG_PHY_SELECTION_MASK;
135 if (bp->link_params.multi_phy_config &
136 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
137 bp->link_params.multi_phy_config |=
138 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
139 else
140 bp->link_params.multi_phy_config |=
141 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
142 break;
143 default:
144 DP(NETIF_MSG_LINK, "Unsupported port type\n");
145 return -EINVAL;
146 }
147 /* Save new config in case command complete successuly */
148 new_multi_phy_config = bp->link_params.multi_phy_config;
149 /* Get the new cfg_idx */
150 cfg_idx = bnx2x_get_link_cfg_idx(bp);
151 /* Restore old config in case command failed */
152 bp->link_params.multi_phy_config = old_multi_phy_config;
153 DP(NETIF_MSG_LINK, "cfg_idx = %x\n", cfg_idx);
154
de0c62db 155 if (cmd->autoneg == AUTONEG_ENABLE) {
a22f0788 156 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
de0c62db
DK		 157 DP(NETIF_MSG_LINK, "Autoneg not supported\n");
158 return -EINVAL;
159 }
160
161 /* advertise the requested speed and duplex if supported */
a22f0788 162 cmd->advertising &= bp->port.supported[cfg_idx];
de0c62db 163
a22f0788
YR		 164 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
165 bp->link_params.req_duplex[cfg_idx] = DUPLEX_FULL;
166 bp->port.advertising[cfg_idx] |= (ADVERTISED_Autoneg |
de0c62db
DK		 167 cmd->advertising);
168
169 } else { /* forced speed */
170 /* advertise the requested speed and duplex if supported */
a22f0788
YR		 171 u32 speed = cmd->speed;
172 speed |= (cmd->speed_hi << 16);
173 switch (speed) {
de0c62db
DK		 174 case SPEED_10:
175 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 176 if (!(bp->port.supported[cfg_idx] &
de0c62db
DK		 177 SUPPORTED_10baseT_Full)) {
178 DP(NETIF_MSG_LINK,
179 "10M full not supported\n");
180 return -EINVAL;
181 }
182
183 advertising = (ADVERTISED_10baseT_Full |
184 ADVERTISED_TP);
185 } else {
a22f0788 186 if (!(bp->port.supported[cfg_idx] &
de0c62db
DK		 187 SUPPORTED_10baseT_Half)) {
188 DP(NETIF_MSG_LINK,
189 "10M half not supported\n");
190 return -EINVAL;
191 }
192
193 advertising = (ADVERTISED_10baseT_Half |
194 ADVERTISED_TP);
195 }
196 break;
197
198 case SPEED_100:
199 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 200 if (!(bp->port.supported[cfg_idx] &
de0c62db
DK		 201 SUPPORTED_100baseT_Full)) {
202 DP(NETIF_MSG_LINK,
203 "100M full not supported\n");
204 return -EINVAL;
205 }
206
207 advertising = (ADVERTISED_100baseT_Full |
208 ADVERTISED_TP);
209 } else {
a22f0788 210 if (!(bp->port.supported[cfg_idx] &
de0c62db
DK		 211 SUPPORTED_100baseT_Half)) {
212 DP(NETIF_MSG_LINK,
213 "100M half not supported\n");
214 return -EINVAL;
215 }
216
217 advertising = (ADVERTISED_100baseT_Half |
218 ADVERTISED_TP);
219 }
220 break;
221
222 case SPEED_1000:
223 if (cmd->duplex != DUPLEX_FULL) {
224 DP(NETIF_MSG_LINK, "1G half not supported\n");
225 return -EINVAL;
226 }
227
a22f0788
YR		 228 if (!(bp->port.supported[cfg_idx] &
229 SUPPORTED_1000baseT_Full)) {
de0c62db
DK		 230 DP(NETIF_MSG_LINK, "1G full not supported\n");
231 return -EINVAL;
232 }
233
234 advertising = (ADVERTISED_1000baseT_Full |
235 ADVERTISED_TP);
236 break;
237
238 case SPEED_2500:
239 if (cmd->duplex != DUPLEX_FULL) {
240 DP(NETIF_MSG_LINK,
241 "2.5G half not supported\n");
242 return -EINVAL;
243 }
244
a22f0788
YR		 245 if (!(bp->port.supported[cfg_idx]
246 & SUPPORTED_2500baseX_Full)) {
de0c62db
DK		 247 DP(NETIF_MSG_LINK,
248 "2.5G full not supported\n");
249 return -EINVAL;
250 }
251
252 advertising = (ADVERTISED_2500baseX_Full |
253 ADVERTISED_TP);
254 break;
255
256 case SPEED_10000:
257 if (cmd->duplex != DUPLEX_FULL) {
258 DP(NETIF_MSG_LINK, "10G half not supported\n");
259 return -EINVAL;
260 }
261
a22f0788
YR		 262 if (!(bp->port.supported[cfg_idx]
263 & SUPPORTED_10000baseT_Full)) {
de0c62db
DK		 264 DP(NETIF_MSG_LINK, "10G full not supported\n");
265 return -EINVAL;
266 }
267
268 advertising = (ADVERTISED_10000baseT_Full |
269 ADVERTISED_FIBRE);
270 break;
271
272 default:
a22f0788 273 DP(NETIF_MSG_LINK, "Unsupported speed %d\n", speed);
de0c62db
DK		 274 return -EINVAL;
275 }
276
a22f0788
YR		 277 bp->link_params.req_line_speed[cfg_idx] = speed;
278 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
279 bp->port.advertising[cfg_idx] = advertising;
de0c62db
DK		 280 }
281
282 DP(NETIF_MSG_LINK, "req_line_speed %d\n"
283 DP_LEVEL " req_duplex %d advertising 0x%x\n",
a22f0788
YR		 284 bp->link_params.req_line_speed[cfg_idx],
285 bp->link_params.req_duplex[cfg_idx],
286 bp->port.advertising[cfg_idx]);
de0c62db 287
a22f0788
YR		 288 /* Set new config */
289 bp->link_params.multi_phy_config = new_multi_phy_config;
de0c62db
DK		 290 if (netif_running(dev)) {
291 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
292 bnx2x_link_set(bp);
293 }
294
295 return 0;
296}
297
298#define IS_E1_ONLINE(info) (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
299#define IS_E1H_ONLINE(info) (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
f2e0899f 300#define IS_E2_ONLINE(info) (((info) & RI_E2_ONLINE) == RI_E2_ONLINE)
de0c62db
DK		 301
302static int bnx2x_get_regs_len(struct net_device *dev)
303{
304 struct bnx2x *bp = netdev_priv(dev);
305 int regdump_len = 0;
306 int i;
307
308 if (CHIP_IS_E1(bp)) {
309 for (i = 0; i < REGS_COUNT; i++)
310 if (IS_E1_ONLINE(reg_addrs[i].info))
311 regdump_len += reg_addrs[i].size;
312
313 for (i = 0; i < WREGS_COUNT_E1; i++)
314 if (IS_E1_ONLINE(wreg_addrs_e1[i].info))
315 regdump_len += wreg_addrs_e1[i].size *
316 (1 + wreg_addrs_e1[i].read_regs_count);
317
f2e0899f 318 } else if (CHIP_IS_E1H(bp)) {
de0c62db
DK		 319 for (i = 0; i < REGS_COUNT; i++)
320 if (IS_E1H_ONLINE(reg_addrs[i].info))
321 regdump_len += reg_addrs[i].size;
322
323 for (i = 0; i < WREGS_COUNT_E1H; i++)
324 if (IS_E1H_ONLINE(wreg_addrs_e1h[i].info))
325 regdump_len += wreg_addrs_e1h[i].size *
326 (1 + wreg_addrs_e1h[i].read_regs_count);
f2e0899f
DK		 327 } else if (CHIP_IS_E2(bp)) {
328 for (i = 0; i < REGS_COUNT; i++)
329 if (IS_E2_ONLINE(reg_addrs[i].info))
330 regdump_len += reg_addrs[i].size;
331
332 for (i = 0; i < WREGS_COUNT_E2; i++)
333 if (IS_E2_ONLINE(wreg_addrs_e2[i].info))
334 regdump_len += wreg_addrs_e2[i].size *
335 (1 + wreg_addrs_e2[i].read_regs_count);
de0c62db
DK		 336 }
337 regdump_len *= 4;
338 regdump_len += sizeof(struct dump_hdr);
339
340 return regdump_len;
341}
342
f2e0899f
DK		 343static inline void bnx2x_read_pages_regs_e2(struct bnx2x *bp, u32 *p)
344{
345 u32 i, j, k, n;
346
347 for (i = 0; i < PAGE_MODE_VALUES_E2; i++) {
348 for (j = 0; j < PAGE_WRITE_REGS_E2; j++) {
349 REG_WR(bp, page_write_regs_e2[j], page_vals_e2[i]);
350 for (k = 0; k < PAGE_READ_REGS_E2; k++)
351 if (IS_E2_ONLINE(page_read_regs_e2[k].info))
352 for (n = 0; n <
353 page_read_regs_e2[k].size; n++)
354 *p++ = REG_RD(bp,
355 page_read_regs_e2[k].addr + n*4);
356 }
357 }
358}
359
de0c62db
DK		 360static void bnx2x_get_regs(struct net_device *dev,
361 struct ethtool_regs *regs, void *_p)
362{
363 u32 *p = _p, i, j;
364 struct bnx2x *bp = netdev_priv(dev);
365 struct dump_hdr dump_hdr = {0};
366
367 regs->version = 0;
368 memset(p, 0, regs->len);
369
370 if (!netif_running(bp->dev))
371 return;
372
373 dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
374 dump_hdr.dump_sign = dump_sign_all;
375 dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
376 dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
377 dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
378 dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
f2e0899f
DK		 379
380 if (CHIP_IS_E1(bp))
381 dump_hdr.info = RI_E1_ONLINE;
382 else if (CHIP_IS_E1H(bp))
383 dump_hdr.info = RI_E1H_ONLINE;
384 else if (CHIP_IS_E2(bp))
385 dump_hdr.info = RI_E2_ONLINE |
386 (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP);
de0c62db
DK		 387
388 memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
389 p += dump_hdr.hdr_size + 1;
390
391 if (CHIP_IS_E1(bp)) {
392 for (i = 0; i < REGS_COUNT; i++)
393 if (IS_E1_ONLINE(reg_addrs[i].info))
394 for (j = 0; j < reg_addrs[i].size; j++)
395 *p++ = REG_RD(bp,
396 reg_addrs[i].addr + j*4);
397
f2e0899f 398 } else if (CHIP_IS_E1H(bp)) {
de0c62db
DK		 399 for (i = 0; i < REGS_COUNT; i++)
400 if (IS_E1H_ONLINE(reg_addrs[i].info))
401 for (j = 0; j < reg_addrs[i].size; j++)
402 *p++ = REG_RD(bp,
403 reg_addrs[i].addr + j*4);
f2e0899f
DK		 404
405 } else if (CHIP_IS_E2(bp)) {
406 for (i = 0; i < REGS_COUNT; i++)
407 if (IS_E2_ONLINE(reg_addrs[i].info))
408 for (j = 0; j < reg_addrs[i].size; j++)
409 *p++ = REG_RD(bp,
410 reg_addrs[i].addr + j*4);
411
412 bnx2x_read_pages_regs_e2(bp, p);
de0c62db
DK		 413 }
414}
415
f2e0899f 416#define PHY_FW_VER_LEN 20
de0c62db
DK		 417
418static void bnx2x_get_drvinfo(struct net_device *dev,
419 struct ethtool_drvinfo *info)
420{
421 struct bnx2x *bp = netdev_priv(dev);
422 u8 phy_fw_ver[PHY_FW_VER_LEN];
423
424 strcpy(info->driver, DRV_MODULE_NAME);
425 strcpy(info->version, DRV_MODULE_VERSION);
426
427 phy_fw_ver[0] = '\0';
428 if (bp->port.pmf) {
429 bnx2x_acquire_phy_lock(bp);
430 bnx2x_get_ext_phy_fw_version(&bp->link_params,
431 (bp->state != BNX2X_STATE_CLOSED),
432 phy_fw_ver, PHY_FW_VER_LEN);
433 bnx2x_release_phy_lock(bp);
434 }
435
436 strncpy(info->fw_version, bp->fw_ver, 32);
437 snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
438 "bc %d.%d.%d%s%s",
439 (bp->common.bc_ver & 0xff0000) >> 16,
440 (bp->common.bc_ver & 0xff00) >> 8,
441 (bp->common.bc_ver & 0xff),
442 ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
443 strcpy(info->bus_info, pci_name(bp->pdev));
444 info->n_stats = BNX2X_NUM_STATS;
445 info->testinfo_len = BNX2X_NUM_TESTS;
446 info->eedump_len = bp->common.flash_size;
447 info->regdump_len = bnx2x_get_regs_len(dev);
448}
449
450static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
451{
452 struct bnx2x *bp = netdev_priv(dev);
453
454 if (bp->flags & NO_WOL_FLAG) {
455 wol->supported = 0;
456 wol->wolopts = 0;
457 } else {
458 wol->supported = WAKE_MAGIC;
459 if (bp->wol)
460 wol->wolopts = WAKE_MAGIC;
461 else
462 wol->wolopts = 0;
463 }
464 memset(&wol->sopass, 0, sizeof(wol->sopass));
465}
466
467static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
468{
469 struct bnx2x *bp = netdev_priv(dev);
470
471 if (wol->wolopts & ~WAKE_MAGIC)
472 return -EINVAL;
473
474 if (wol->wolopts & WAKE_MAGIC) {
475 if (bp->flags & NO_WOL_FLAG)
476 return -EINVAL;
477
478 bp->wol = 1;
479 } else
480 bp->wol = 0;
481
482 return 0;
483}
484
485static u32 bnx2x_get_msglevel(struct net_device *dev)
486{
487 struct bnx2x *bp = netdev_priv(dev);
488
489 return bp->msg_enable;
490}
491
492static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
493{
494 struct bnx2x *bp = netdev_priv(dev);
495
496 if (capable(CAP_NET_ADMIN))
497 bp->msg_enable = level;
498}
499
500static int bnx2x_nway_reset(struct net_device *dev)
501{
502 struct bnx2x *bp = netdev_priv(dev);
503
504 if (!bp->port.pmf)
505 return 0;
506
507 if (netif_running(dev)) {
508 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
509 bnx2x_link_set(bp);
510 }
511
512 return 0;
513}
514
515static u32 bnx2x_get_link(struct net_device *dev)
516{
517 struct bnx2x *bp = netdev_priv(dev);
518
f2e0899f 519 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
de0c62db
DK		 520 return 0;
521
522 return bp->link_vars.link_up;
523}
524
525static int bnx2x_get_eeprom_len(struct net_device *dev)
526{
527 struct bnx2x *bp = netdev_priv(dev);
528
529 return bp->common.flash_size;
530}
531
532static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
533{
534 int port = BP_PORT(bp);
535 int count, i;
536 u32 val = 0;
537
538 /* adjust timeout for emulation/FPGA */
539 count = NVRAM_TIMEOUT_COUNT;
540 if (CHIP_REV_IS_SLOW(bp))
541 count *= 100;
542
543 /* request access to nvram interface */
544 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
545 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
546
547 for (i = 0; i < count*10; i++) {
548 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
549 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
550 break;
551
552 udelay(5);
553 }
554
555 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
556 DP(BNX2X_MSG_NVM, "cannot get access to nvram interface\n");
557 return -EBUSY;
558 }
559
560 return 0;
561}
562
563static int bnx2x_release_nvram_lock(struct bnx2x *bp)
564{
565 int port = BP_PORT(bp);
566 int count, i;
567 u32 val = 0;
568
569 /* adjust timeout for emulation/FPGA */
570 count = NVRAM_TIMEOUT_COUNT;
571 if (CHIP_REV_IS_SLOW(bp))
572 count *= 100;
573
574 /* relinquish nvram interface */
575 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
576 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
577
578 for (i = 0; i < count*10; i++) {
579 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
580 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
581 break;
582
583 udelay(5);
584 }
585
586 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
587 DP(BNX2X_MSG_NVM, "cannot free access to nvram interface\n");
588 return -EBUSY;
589 }
590
591 return 0;
592}
593
594static void bnx2x_enable_nvram_access(struct bnx2x *bp)
595{
596 u32 val;
597
598 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
599
600 /* enable both bits, even on read */
601 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
602 (val | MCPR_NVM_ACCESS_ENABLE_EN |
603 MCPR_NVM_ACCESS_ENABLE_WR_EN));
604}
605
606static void bnx2x_disable_nvram_access(struct bnx2x *bp)
607{
608 u32 val;
609
610 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
611
612 /* disable both bits, even after read */
613 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
614 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
615 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
616}
617
618static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
619 u32 cmd_flags)
620{
621 int count, i, rc;
622 u32 val;
623
624 /* build the command word */
625 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
626
627 /* need to clear DONE bit separately */
628 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
629
630 /* address of the NVRAM to read from */
631 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
632 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
633
634 /* issue a read command */
635 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
636
637 /* adjust timeout for emulation/FPGA */
638 count = NVRAM_TIMEOUT_COUNT;
639 if (CHIP_REV_IS_SLOW(bp))
640 count *= 100;
641
642 /* wait for completion */
643 *ret_val = 0;
644 rc = -EBUSY;
645 for (i = 0; i < count; i++) {
646 udelay(5);
647 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
648
649 if (val & MCPR_NVM_COMMAND_DONE) {
650 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
651 /* we read nvram data in cpu order
652 * but ethtool sees it as an array of bytes
653 * converting to big-endian will do the work */
654 *ret_val = cpu_to_be32(val);
655 rc = 0;
656 break;
657 }
658 }
659
660 return rc;
661}
662
663static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
664 int buf_size)
665{
666 int rc;
667 u32 cmd_flags;
668 __be32 val;
669
670 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
671 DP(BNX2X_MSG_NVM,
672 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
673 offset, buf_size);
674 return -EINVAL;
675 }
676
677 if (offset + buf_size > bp->common.flash_size) {
678 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
679 " buf_size (0x%x) > flash_size (0x%x)\n",
680 offset, buf_size, bp->common.flash_size);
681 return -EINVAL;
682 }
683
684 /* request access to nvram interface */
685 rc = bnx2x_acquire_nvram_lock(bp);
686 if (rc)
687 return rc;
688
689 /* enable access to nvram interface */
690 bnx2x_enable_nvram_access(bp);
691
692 /* read the first word(s) */
693 cmd_flags = MCPR_NVM_COMMAND_FIRST;
694 while ((buf_size > sizeof(u32)) && (rc == 0)) {
695 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
696 memcpy(ret_buf, &val, 4);
697
698 /* advance to the next dword */
699 offset += sizeof(u32);
700 ret_buf += sizeof(u32);
701 buf_size -= sizeof(u32);
702 cmd_flags = 0;
703 }
704
705 if (rc == 0) {
706 cmd_flags |= MCPR_NVM_COMMAND_LAST;
707 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
708 memcpy(ret_buf, &val, 4);
709 }
710
711 /* disable access to nvram interface */
712 bnx2x_disable_nvram_access(bp);
713 bnx2x_release_nvram_lock(bp);
714
715 return rc;
716}
717
718static int bnx2x_get_eeprom(struct net_device *dev,
719 struct ethtool_eeprom *eeprom, u8 *eebuf)
720{
721 struct bnx2x *bp = netdev_priv(dev);
722 int rc;
723
724 if (!netif_running(dev))
725 return -EAGAIN;
726
727 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
728 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
729 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
730 eeprom->len, eeprom->len);
731
732 /* parameters already validated in ethtool_get_eeprom */
733
734 rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
735
736 return rc;
737}
738
739static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
740 u32 cmd_flags)
741{
742 int count, i, rc;
743
744 /* build the command word */
745 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
746
747 /* need to clear DONE bit separately */
748 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
749
750 /* write the data */
751 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
752
753 /* address of the NVRAM to write to */
754 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
755 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
756
757 /* issue the write command */
758 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
759
760 /* adjust timeout for emulation/FPGA */
761 count = NVRAM_TIMEOUT_COUNT;
762 if (CHIP_REV_IS_SLOW(bp))
763 count *= 100;
764
765 /* wait for completion */
766 rc = -EBUSY;
767 for (i = 0; i < count; i++) {
768 udelay(5);
769 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
770 if (val & MCPR_NVM_COMMAND_DONE) {
771 rc = 0;
772 break;
773 }
774 }
775
776 return rc;
777}
778
779#define BYTE_OFFSET(offset) (8 * (offset & 0x03))
780
781static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
782 int buf_size)
783{
784 int rc;
785 u32 cmd_flags;
786 u32 align_offset;
787 __be32 val;
788
789 if (offset + buf_size > bp->common.flash_size) {
790 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
791 " buf_size (0x%x) > flash_size (0x%x)\n",
792 offset, buf_size, bp->common.flash_size);
793 return -EINVAL;
794 }
795
796 /* request access to nvram interface */
797 rc = bnx2x_acquire_nvram_lock(bp);
798 if (rc)
799 return rc;
800
801 /* enable access to nvram interface */
802 bnx2x_enable_nvram_access(bp);
803
804 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
805 align_offset = (offset & ~0x03);
806 rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
807
808 if (rc == 0) {
809 val &= ~(0xff << BYTE_OFFSET(offset));
810 val |= (*data_buf << BYTE_OFFSET(offset));
811
812 /* nvram data is returned as an array of bytes
813 * convert it back to cpu order */
814 val = be32_to_cpu(val);
815
816 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
817 cmd_flags);
818 }
819
820 /* disable access to nvram interface */
821 bnx2x_disable_nvram_access(bp);
822 bnx2x_release_nvram_lock(bp);
823
824 return rc;
825}
826
827static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
828 int buf_size)
829{
830 int rc;
831 u32 cmd_flags;
832 u32 val;
833 u32 written_so_far;
834
835 if (buf_size == 1) /* ethtool */
836 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
837
838 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
839 DP(BNX2X_MSG_NVM,
840 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
841 offset, buf_size);
842 return -EINVAL;
843 }
844
845 if (offset + buf_size > bp->common.flash_size) {
846 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
847 " buf_size (0x%x) > flash_size (0x%x)\n",
848 offset, buf_size, bp->common.flash_size);
849 return -EINVAL;
850 }
851
852 /* request access to nvram interface */
853 rc = bnx2x_acquire_nvram_lock(bp);
854 if (rc)
855 return rc;
856
857 /* enable access to nvram interface */
858 bnx2x_enable_nvram_access(bp);
859
860 written_so_far = 0;
861 cmd_flags = MCPR_NVM_COMMAND_FIRST;
862 while ((written_so_far < buf_size) && (rc == 0)) {
863 if (written_so_far == (buf_size - sizeof(u32)))
864 cmd_flags |= MCPR_NVM_COMMAND_LAST;
865 else if (((offset + 4) % NVRAM_PAGE_SIZE) == 0)
866 cmd_flags |= MCPR_NVM_COMMAND_LAST;
867 else if ((offset % NVRAM_PAGE_SIZE) == 0)
868 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
869
870 memcpy(&val, data_buf, 4);
871
872 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
873
874 /* advance to the next dword */
875 offset += sizeof(u32);
876 data_buf += sizeof(u32);
877 written_so_far += sizeof(u32);
878 cmd_flags = 0;
879 }
880
881 /* disable access to nvram interface */
882 bnx2x_disable_nvram_access(bp);
883 bnx2x_release_nvram_lock(bp);
884
885 return rc;
886}
887
888static int bnx2x_set_eeprom(struct net_device *dev,
889 struct ethtool_eeprom *eeprom, u8 *eebuf)
890{
891 struct bnx2x *bp = netdev_priv(dev);
892 int port = BP_PORT(bp);
893 int rc = 0;
e10bc84d 894 u32 ext_phy_config;
de0c62db
DK		 895 if (!netif_running(dev))
896 return -EAGAIN;
897
898 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
899 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
900 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
901 eeprom->len, eeprom->len);
902
903 /* parameters already validated in ethtool_set_eeprom */
904
905 /* PHY eeprom can be accessed only by the PMF */
906 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
907 !bp->port.pmf)
908 return -EINVAL;
909
e10bc84d
YR		 910 ext_phy_config =
911 SHMEM_RD(bp,
912 dev_info.port_hw_config[port].external_phy_config);
913
de0c62db
DK		 914 if (eeprom->magic == 0x50485950) {
915 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
916 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
917
918 bnx2x_acquire_phy_lock(bp);
919 rc |= bnx2x_link_reset(&bp->link_params,
920 &bp->link_vars, 0);
e10bc84d 921 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db
DK		 922 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
923 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
924 MISC_REGISTERS_GPIO_HIGH, port);
925 bnx2x_release_phy_lock(bp);
926 bnx2x_link_report(bp);
927
928 } else if (eeprom->magic == 0x50485952) {
929 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
930 if (bp->state == BNX2X_STATE_OPEN) {
931 bnx2x_acquire_phy_lock(bp);
932 rc |= bnx2x_link_reset(&bp->link_params,
933 &bp->link_vars, 1);
934
935 rc |= bnx2x_phy_init(&bp->link_params,
936 &bp->link_vars);
937 bnx2x_release_phy_lock(bp);
938 bnx2x_calc_fc_adv(bp);
939 }
940 } else if (eeprom->magic == 0x53985943) {
941 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
e10bc84d 942 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db 943 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
de0c62db
DK		 944
945 /* DSP Remove Download Mode */
946 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
947 MISC_REGISTERS_GPIO_LOW, port);
948
949 bnx2x_acquire_phy_lock(bp);
950
e10bc84d
YR		 951 bnx2x_sfx7101_sp_sw_reset(bp,
952 &bp->link_params.phy[EXT_PHY1]);
de0c62db
DK		 953
954 /* wait 0.5 sec to allow it to run */
955 msleep(500);
956 bnx2x_ext_phy_hw_reset(bp, port);
957 msleep(500);
958 bnx2x_release_phy_lock(bp);
959 }
960 } else
961 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
962
963 return rc;
964}
f85582f8 965
de0c62db
DK		 966static int bnx2x_get_coalesce(struct net_device *dev,
967 struct ethtool_coalesce *coal)
968{
969 struct bnx2x *bp = netdev_priv(dev);
970
971 memset(coal, 0, sizeof(struct ethtool_coalesce));
972
973 coal->rx_coalesce_usecs = bp->rx_ticks;
974 coal->tx_coalesce_usecs = bp->tx_ticks;
975
976 return 0;
977}
978
979static int bnx2x_set_coalesce(struct net_device *dev,
980 struct ethtool_coalesce *coal)
981{
982 struct bnx2x *bp = netdev_priv(dev);
983
984 bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
985 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
986 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
987
988 bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
989 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
990 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
991
992 if (netif_running(dev))
993 bnx2x_update_coalesce(bp);
994
995 return 0;
996}
997
998static void bnx2x_get_ringparam(struct net_device *dev,
999 struct ethtool_ringparam *ering)
1000{
1001 struct bnx2x *bp = netdev_priv(dev);
1002
1003 ering->rx_max_pending = MAX_RX_AVAIL;
1004 ering->rx_mini_max_pending = 0;
1005 ering->rx_jumbo_max_pending = 0;
1006
25141580
DK		 1007 if (bp->rx_ring_size)
1008 ering->rx_pending = bp->rx_ring_size;
1009 else
1010 if (bp->state == BNX2X_STATE_OPEN && bp->num_queues)
1011 ering->rx_pending = MAX_RX_AVAIL/bp->num_queues;
1012 else
1013 ering->rx_pending = MAX_RX_AVAIL;
1014
de0c62db
DK		 1015 ering->rx_mini_pending = 0;
1016 ering->rx_jumbo_pending = 0;
1017
1018 ering->tx_max_pending = MAX_TX_AVAIL;
1019 ering->tx_pending = bp->tx_ring_size;
1020}
1021
1022static int bnx2x_set_ringparam(struct net_device *dev,
1023 struct ethtool_ringparam *ering)
1024{
1025 struct bnx2x *bp = netdev_priv(dev);
1026 int rc = 0;
1027
1028 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1029 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1030 return -EAGAIN;
1031 }
1032
1033 if ((ering->rx_pending > MAX_RX_AVAIL) ||
25141580 1034 (ering->rx_pending < MIN_RX_AVAIL) ||
de0c62db
DK		 1035 (ering->tx_pending > MAX_TX_AVAIL) ||
1036 (ering->tx_pending <= MAX_SKB_FRAGS + 4))
1037 return -EINVAL;
1038
1039 bp->rx_ring_size = ering->rx_pending;
1040 bp->tx_ring_size = ering->tx_pending;
1041
1042 if (netif_running(dev)) {
1043 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1044 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
1045 }
1046
1047 return rc;
1048}
1049
1050static void bnx2x_get_pauseparam(struct net_device *dev,
1051 struct ethtool_pauseparam *epause)
1052{
1053 struct bnx2x *bp = netdev_priv(dev);
a22f0788
YR		 1054 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1055 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1056 BNX2X_FLOW_CTRL_AUTO);
de0c62db
DK		 1057
1058 epause->rx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) ==
1059 BNX2X_FLOW_CTRL_RX);
1060 epause->tx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) ==
1061 BNX2X_FLOW_CTRL_TX);
1062
1063 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1064 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
1065 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1066}
1067
1068static int bnx2x_set_pauseparam(struct net_device *dev,
1069 struct ethtool_pauseparam *epause)
1070{
1071 struct bnx2x *bp = netdev_priv(dev);
a22f0788 1072 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
fb3bff17 1073 if (IS_MF(bp))
de0c62db
DK		 1074 return 0;
1075
1076 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1077 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
1078 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1079
a22f0788 1080 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
de0c62db
DK		 1081
1082 if (epause->rx_pause)
a22f0788 1083 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
de0c62db
DK		 1084
1085 if (epause->tx_pause)
a22f0788 1086 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
de0c62db 1087
a22f0788
YR		 1088 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1089 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
de0c62db
DK		 1090
1091 if (epause->autoneg) {
a22f0788 1092 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
de0c62db
DK		 1093 DP(NETIF_MSG_LINK, "autoneg not supported\n");
1094 return -EINVAL;
1095 }
1096
a22f0788
YR		 1097 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1098 bp->link_params.req_flow_ctrl[cfg_idx] =
1099 BNX2X_FLOW_CTRL_AUTO;
1100 }
de0c62db
DK		 1101 }
1102
1103 DP(NETIF_MSG_LINK,
a22f0788 1104 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
de0c62db
DK		 1105
1106 if (netif_running(dev)) {
1107 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1108 bnx2x_link_set(bp);
1109 }
1110
1111 return 0;
1112}
1113
1114static int bnx2x_set_flags(struct net_device *dev, u32 data)
1115{
1116 struct bnx2x *bp = netdev_priv(dev);
1117 int changed = 0;
1118 int rc = 0;
1119
1120 if (data & ~(ETH_FLAG_LRO | ETH_FLAG_RXHASH))
1121 return -EINVAL;
1122
1123 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1124 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1125 return -EAGAIN;
1126 }
1127
1128 /* TPA requires Rx CSUM offloading */
1129 if ((data & ETH_FLAG_LRO) && bp->rx_csum) {
1130 if (!bp->disable_tpa) {
1131 if (!(dev->features & NETIF_F_LRO)) {
1132 dev->features |= NETIF_F_LRO;
1133 bp->flags |= TPA_ENABLE_FLAG;
1134 changed = 1;
1135 }
1136 } else
1137 rc = -EINVAL;
1138 } else if (dev->features & NETIF_F_LRO) {
1139 dev->features &= ~NETIF_F_LRO;
1140 bp->flags &= ~TPA_ENABLE_FLAG;
1141 changed = 1;
1142 }
1143
1144 if (data & ETH_FLAG_RXHASH)
1145 dev->features |= NETIF_F_RXHASH;
1146 else
1147 dev->features &= ~NETIF_F_RXHASH;
1148
1149 if (changed && netif_running(dev)) {
1150 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1151 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
1152 }
1153
1154 return rc;
1155}
1156
1157static u32 bnx2x_get_rx_csum(struct net_device *dev)
1158{
1159 struct bnx2x *bp = netdev_priv(dev);
1160
1161 return bp->rx_csum;
1162}
1163
1164static int bnx2x_set_rx_csum(struct net_device *dev, u32 data)
1165{
1166 struct bnx2x *bp = netdev_priv(dev);
1167 int rc = 0;
1168
1169 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1170 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1171 return -EAGAIN;
1172 }
1173
1174 bp->rx_csum = data;
1175
1176 /* Disable TPA, when Rx CSUM is disabled. Otherwise all
1177 TPA'ed packets will be discarded due to wrong TCP CSUM */
1178 if (!data) {
1179 u32 flags = ethtool_op_get_flags(dev);
1180
1181 rc = bnx2x_set_flags(dev, (flags & ~ETH_FLAG_LRO));
1182 }
1183
1184 return rc;
1185}
1186
1187static int bnx2x_set_tso(struct net_device *dev, u32 data)
1188{
1189 if (data) {
1190 dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
1191 dev->features |= NETIF_F_TSO6;
1192 } else {
1193 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO_ECN);
1194 dev->features &= ~NETIF_F_TSO6;
1195 }
1196
1197 return 0;
1198}
1199
1200static const struct {
1201 char string[ETH_GSTRING_LEN];
1202} bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = {
1203 { "register_test (offline)" },
1204 { "memory_test (offline)" },
1205 { "loopback_test (offline)" },
1206 { "nvram_test (online)" },
1207 { "interrupt_test (online)" },
1208 { "link_test (online)" },
1209 { "idle check (online)" }
1210};
1211
1212static int bnx2x_test_registers(struct bnx2x *bp)
1213{
1214 int idx, i, rc = -ENODEV;
1215 u32 wr_val = 0;
1216 int port = BP_PORT(bp);
1217 static const struct {
1218 u32 offset0;
1219 u32 offset1;
1220 u32 mask;
1221 } reg_tbl[] = {
1222/* 0 */ { BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
1223 { DORQ_REG_DB_ADDR0, 4, 0xffffffff },
1224 { HC_REG_AGG_INT_0, 4, 0x000003ff },
1225 { PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
1226 { PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
1227 { PRS_REG_CID_PORT_0, 4, 0x00ffffff },
1228 { PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
1229 { PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1230 { PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
1231 { PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1232/* 10 */ { PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
1233 { QM_REG_CONNNUM_0, 4, 0x000fffff },
1234 { TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
1235 { SRC_REG_KEYRSS0_0, 40, 0xffffffff },
1236 { SRC_REG_KEYRSS0_7, 40, 0xffffffff },
1237 { XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
1238 { XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
1239 { XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
1240 { NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
1241 { NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
1242/* 20 */ { NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
1243 { NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
1244 { NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
1245 { NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
1246 { NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
1247 { NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
1248 { NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
1249 { NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
1250 { NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
1251 { NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
1252/* 30 */ { NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
1253 { NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
1254 { NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
1255 { NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001 },
1256 { NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
1257 { NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
1258 { NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
1259
1260 { 0xffffffff, 0, 0x00000000 }
1261 };
1262
1263 if (!netif_running(bp->dev))
1264 return rc;
1265
1266 /* Repeat the test twice:
1267 First by writing 0x00000000, second by writing 0xffffffff */
1268 for (idx = 0; idx < 2; idx++) {
1269
1270 switch (idx) {
1271 case 0:
1272 wr_val = 0;
1273 break;
1274 case 1:
1275 wr_val = 0xffffffff;
1276 break;
1277 }
1278
1279 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
1280 u32 offset, mask, save_val, val;
f2e0899f
DK		 1281 if (CHIP_IS_E2(bp) &&
1282 reg_tbl[i].offset0 == HC_REG_AGG_INT_0)
1283 continue;
de0c62db
DK		 1284
1285 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
1286 mask = reg_tbl[i].mask;
1287
1288 save_val = REG_RD(bp, offset);
1289
1290 REG_WR(bp, offset, (wr_val & mask));
f85582f8 1291
de0c62db
DK		 1292 val = REG_RD(bp, offset);
1293
1294 /* Restore the original register's value */
1295 REG_WR(bp, offset, save_val);
1296
1297 /* verify value is as expected */
1298 if ((val & mask) != (wr_val & mask)) {
1299 DP(NETIF_MSG_PROBE,
1300 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
1301 offset, val, wr_val, mask);
1302 goto test_reg_exit;
1303 }
1304 }
1305 }
1306
1307 rc = 0;
1308
1309test_reg_exit:
1310 return rc;
1311}
1312
1313static int bnx2x_test_memory(struct bnx2x *bp)
1314{
1315 int i, j, rc = -ENODEV;
1316 u32 val;
1317 static const struct {
1318 u32 offset;
1319 int size;
1320 } mem_tbl[] = {
1321 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
1322 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
1323 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
1324 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
1325 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
1326 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
1327 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
1328
1329 { 0xffffffff, 0 }
1330 };
1331 static const struct {
1332 char *name;
1333 u32 offset;
1334 u32 e1_mask;
1335 u32 e1h_mask;
f2e0899f 1336 u32 e2_mask;
de0c62db 1337 } prty_tbl[] = {
f2e0899f
DK		 1338 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 0x3ffc0, 0, 0 },
1339 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 0x2, 0x2, 0 },
1340 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 0, 0, 0 },
1341 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 0x3ffc0, 0, 0 },
1342 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 0x3ffc0, 0, 0 },
1343 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 0x3ffc1, 0, 0 },
1344
1345 { NULL, 0xffffffff, 0, 0, 0 }
de0c62db
DK		 1346 };
1347
1348 if (!netif_running(bp->dev))
1349 return rc;
1350
f2e0899f
DK		 1351 /* pre-Check the parity status */
1352 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1353 val = REG_RD(bp, prty_tbl[i].offset);
1354 if ((CHIP_IS_E1(bp) && (val & ~(prty_tbl[i].e1_mask))) ||
1355 (CHIP_IS_E1H(bp) && (val & ~(prty_tbl[i].e1h_mask))) ||
1356 (CHIP_IS_E2(bp) && (val & ~(prty_tbl[i].e2_mask)))) {
1357 DP(NETIF_MSG_HW,
1358 "%s is 0x%x\n", prty_tbl[i].name, val);
1359 goto test_mem_exit;
1360 }
1361 }
1362
de0c62db
DK		 1363 /* Go through all the memories */
1364 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
1365 for (j = 0; j < mem_tbl[i].size; j++)
1366 REG_RD(bp, mem_tbl[i].offset + j*4);
1367
1368 /* Check the parity status */
1369 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1370 val = REG_RD(bp, prty_tbl[i].offset);
1371 if ((CHIP_IS_E1(bp) && (val & ~(prty_tbl[i].e1_mask))) ||
f2e0899f
DK		 1372 (CHIP_IS_E1H(bp) && (val & ~(prty_tbl[i].e1h_mask))) ||
1373 (CHIP_IS_E2(bp) && (val & ~(prty_tbl[i].e2_mask)))) {
de0c62db
DK		 1374 DP(NETIF_MSG_HW,
1375 "%s is 0x%x\n", prty_tbl[i].name, val);
1376 goto test_mem_exit;
1377 }
1378 }
1379
1380 rc = 0;
1381
1382test_mem_exit:
1383 return rc;
1384}
1385
a22f0788 1386static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
de0c62db 1387{
f2e0899f 1388 int cnt = 1400;
de0c62db
DK		 1389
1390 if (link_up)
a22f0788 1391 while (bnx2x_link_test(bp, is_serdes) && cnt--)
de0c62db
DK		 1392 msleep(10);
1393}
1394
1395static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode, u8 link_up)
1396{
1397 unsigned int pkt_size, num_pkts, i;
1398 struct sk_buff *skb;
1399 unsigned char *packet;
1400 struct bnx2x_fastpath *fp_rx = &bp->fp[0];
1401 struct bnx2x_fastpath *fp_tx = &bp->fp[0];
1402 u16 tx_start_idx, tx_idx;
1403 u16 rx_start_idx, rx_idx;
1404 u16 pkt_prod, bd_prod;
1405 struct sw_tx_bd *tx_buf;
1406 struct eth_tx_start_bd *tx_start_bd;
f2e0899f
DK		 1407 struct eth_tx_parse_bd_e1x *pbd_e1x = NULL;
1408 struct eth_tx_parse_bd_e2 *pbd_e2 = NULL;
de0c62db
DK		 1409 dma_addr_t mapping;
1410 union eth_rx_cqe *cqe;
1411 u8 cqe_fp_flags;
1412 struct sw_rx_bd *rx_buf;
1413 u16 len;
1414 int rc = -ENODEV;
1415
1416 /* check the loopback mode */
1417 switch (loopback_mode) {
1418 case BNX2X_PHY_LOOPBACK:
de6eae1f 1419 if (bp->link_params.loopback_mode != LOOPBACK_XGXS)
de0c62db
DK		 1420 return -EINVAL;
1421 break;
1422 case BNX2X_MAC_LOOPBACK:
1423 bp->link_params.loopback_mode = LOOPBACK_BMAC;
1424 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1425 break;
1426 default:
1427 return -EINVAL;
1428 }
1429
1430 /* prepare the loopback packet */
1431 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
1432 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
1433 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
1434 if (!skb) {
1435 rc = -ENOMEM;
1436 goto test_loopback_exit;
1437 }
1438 packet = skb_put(skb, pkt_size);
1439 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
1440 memset(packet + ETH_ALEN, 0, ETH_ALEN);
1441 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
1442 for (i = ETH_HLEN; i < pkt_size; i++)
1443 packet[i] = (unsigned char) (i & 0xff);
1444
1445 /* send the loopback packet */
1446 num_pkts = 0;
1447 tx_start_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
1448 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1449
1450 pkt_prod = fp_tx->tx_pkt_prod++;
1451 tx_buf = &fp_tx->tx_buf_ring[TX_BD(pkt_prod)];
1452 tx_buf->first_bd = fp_tx->tx_bd_prod;
1453 tx_buf->skb = skb;
1454 tx_buf->flags = 0;
1455
1456 bd_prod = TX_BD(fp_tx->tx_bd_prod);
1457 tx_start_bd = &fp_tx->tx_desc_ring[bd_prod].start_bd;
1458 mapping = dma_map_single(&bp->pdev->dev, skb->data,
1459 skb_headlen(skb), DMA_TO_DEVICE);
1460 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1461 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1462 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
1463 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
523224a3 1464 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
de0c62db 1465 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
523224a3
DK		 1466 SET_FLAG(tx_start_bd->general_data,
1467 ETH_TX_START_BD_ETH_ADDR_TYPE,
1468 UNICAST_ADDRESS);
1469 SET_FLAG(tx_start_bd->general_data,
1470 ETH_TX_START_BD_HDR_NBDS,
1471 1);
de0c62db
DK		 1472
1473 /* turn on parsing and get a BD */
1474 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
f85582f8 1475
523224a3 1476 pbd_e1x = &fp_tx->tx_desc_ring[bd_prod].parse_bd_e1x;
f2e0899f 1477 pbd_e2 = &fp_tx->tx_desc_ring[bd_prod].parse_bd_e2;
de0c62db 1478
f2e0899f 1479 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
523224a3 1480 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
de0c62db
DK		 1481
1482 wmb();
1483
1484 fp_tx->tx_db.data.prod += 2;
1485 barrier();
1486 DOORBELL(bp, fp_tx->index, fp_tx->tx_db.raw);
1487
1488 mmiowb();
1489
1490 num_pkts++;
1491 fp_tx->tx_bd_prod += 2; /* start + pbd */
1492
1493 udelay(100);
1494
1495 tx_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
1496 if (tx_idx != tx_start_idx + num_pkts)
1497 goto test_loopback_exit;
1498
f2e0899f
DK		 1499 /* Unlike HC IGU won't generate an interrupt for status block
1500 * updates that have been performed while interrupts were
1501 * disabled.
1502 */
1503 if (bp->common.int_block == INT_BLOCK_IGU)
1504 bnx2x_tx_int(fp_tx);
1505
de0c62db
DK		 1506 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1507 if (rx_idx != rx_start_idx + num_pkts)
1508 goto test_loopback_exit;
1509
1510 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
1511 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
1512 if (CQE_TYPE(cqe_fp_flags) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
1513 goto test_loopback_rx_exit;
1514
1515 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
1516 if (len != pkt_size)
1517 goto test_loopback_rx_exit;
1518
1519 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
1520 skb = rx_buf->skb;
1521 skb_reserve(skb, cqe->fast_path_cqe.placement_offset);
1522 for (i = ETH_HLEN; i < pkt_size; i++)
1523 if (*(skb->data + i) != (unsigned char) (i & 0xff))
1524 goto test_loopback_rx_exit;
1525
1526 rc = 0;
1527
1528test_loopback_rx_exit:
1529
1530 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
1531 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
1532 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
1533 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
1534
1535 /* Update producers */
1536 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
1537 fp_rx->rx_sge_prod);
1538
1539test_loopback_exit:
1540 bp->link_params.loopback_mode = LOOPBACK_NONE;
1541
1542 return rc;
1543}
1544
1545static int bnx2x_test_loopback(struct bnx2x *bp, u8 link_up)
1546{
1547 int rc = 0, res;
1548
1549 if (BP_NOMCP(bp))
1550 return rc;
1551
1552 if (!netif_running(bp->dev))
1553 return BNX2X_LOOPBACK_FAILED;
1554
1555 bnx2x_netif_stop(bp, 1);
1556 bnx2x_acquire_phy_lock(bp);
1557
1558 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK, link_up);
1559 if (res) {
1560 DP(NETIF_MSG_PROBE, " PHY loopback failed (res %d)\n", res);
1561 rc |= BNX2X_PHY_LOOPBACK_FAILED;
1562 }
1563
1564 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK, link_up);
1565 if (res) {
1566 DP(NETIF_MSG_PROBE, " MAC loopback failed (res %d)\n", res);
1567 rc |= BNX2X_MAC_LOOPBACK_FAILED;
1568 }
1569
1570 bnx2x_release_phy_lock(bp);
1571 bnx2x_netif_start(bp);
1572
1573 return rc;
1574}
1575
1576#define CRC32_RESIDUAL 0xdebb20e3
1577
1578static int bnx2x_test_nvram(struct bnx2x *bp)
1579{
1580 static const struct {
1581 int offset;
1582 int size;
1583 } nvram_tbl[] = {
1584 { 0, 0x14 }, /* bootstrap */
1585 { 0x14, 0xec }, /* dir */
1586 { 0x100, 0x350 }, /* manuf_info */
1587 { 0x450, 0xf0 }, /* feature_info */
1588 { 0x640, 0x64 }, /* upgrade_key_info */
1589 { 0x6a4, 0x64 },
1590 { 0x708, 0x70 }, /* manuf_key_info */
1591 { 0x778, 0x70 },
1592 { 0, 0 }
1593 };
1594 __be32 buf[0x350 / 4];
1595 u8 *data = (u8 *)buf;
1596 int i, rc;
1597 u32 magic, crc;
1598
1599 if (BP_NOMCP(bp))
1600 return 0;
1601
1602 rc = bnx2x_nvram_read(bp, 0, data, 4);
1603 if (rc) {
1604 DP(NETIF_MSG_PROBE, "magic value read (rc %d)\n", rc);
1605 goto test_nvram_exit;
1606 }
1607
1608 magic = be32_to_cpu(buf[0]);
1609 if (magic != 0x669955aa) {
1610 DP(NETIF_MSG_PROBE, "magic value (0x%08x)\n", magic);
1611 rc = -ENODEV;
1612 goto test_nvram_exit;
1613 }
1614
1615 for (i = 0; nvram_tbl[i].size; i++) {
1616
1617 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
1618 nvram_tbl[i].size);
1619 if (rc) {
1620 DP(NETIF_MSG_PROBE,
1621 "nvram_tbl[%d] read data (rc %d)\n", i, rc);
1622 goto test_nvram_exit;
1623 }
1624
1625 crc = ether_crc_le(nvram_tbl[i].size, data);
1626 if (crc != CRC32_RESIDUAL) {
1627 DP(NETIF_MSG_PROBE,
1628 "nvram_tbl[%d] crc value (0x%08x)\n", i, crc);
1629 rc = -ENODEV;
1630 goto test_nvram_exit;
1631 }
1632 }
1633
1634test_nvram_exit:
1635 return rc;
1636}
1637
1638static int bnx2x_test_intr(struct bnx2x *bp)
1639{
1640 struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config);
1641 int i, rc;
1642
1643 if (!netif_running(bp->dev))
1644 return -ENODEV;
1645
1646 config->hdr.length = 0;
1647 if (CHIP_IS_E1(bp))
f2e0899f 1648 config->hdr.offset = (BP_PORT(bp) ? 32 : 0);
de0c62db
DK		 1649 else
1650 config->hdr.offset = BP_FUNC(bp);
1651 config->hdr.client_id = bp->fp->cl_id;
1652 config->hdr.reserved1 = 0;
1653
1654 bp->set_mac_pending++;
1655 smp_wmb();
523224a3 1656 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
de0c62db 1657 U64_HI(bnx2x_sp_mapping(bp, mac_config)),
523224a3 1658 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 1);
de0c62db
DK		 1659 if (rc == 0) {
1660 for (i = 0; i < 10; i++) {
1661 if (!bp->set_mac_pending)
1662 break;
1663 smp_rmb();
1664 msleep_interruptible(10);
1665 }
1666 if (i == 10)
1667 rc = -ENODEV;
1668 }
1669
1670 return rc;
1671}
1672
1673static void bnx2x_self_test(struct net_device *dev,
1674 struct ethtool_test *etest, u64 *buf)
1675{
1676 struct bnx2x *bp = netdev_priv(dev);
a22f0788 1677 u8 is_serdes;
de0c62db
DK		 1678 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1679 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1680 etest->flags |= ETH_TEST_FL_FAILED;
1681 return;
1682 }
1683
1684 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS);
1685
1686 if (!netif_running(dev))
1687 return;
1688
1689 /* offline tests are not supported in MF mode */
fb3bff17 1690 if (IS_MF(bp))
de0c62db 1691 etest->flags &= ~ETH_TEST_FL_OFFLINE;
a22f0788 1692 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
de0c62db
DK		 1693
1694 if (etest->flags & ETH_TEST_FL_OFFLINE) {
1695 int port = BP_PORT(bp);
1696 u32 val;
1697 u8 link_up;
1698
1699 /* save current value of input enable for TX port IF */
1700 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
1701 /* disable input for TX port IF */
1702 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
1703
a22f0788
YR		 1704 link_up = bp->link_vars.link_up;
1705
de0c62db
DK		 1706 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1707 bnx2x_nic_load(bp, LOAD_DIAG);
1708 /* wait until link state is restored */
a22f0788 1709 bnx2x_wait_for_link(bp, link_up, is_serdes);
de0c62db
DK		 1710
1711 if (bnx2x_test_registers(bp) != 0) {
1712 buf[0] = 1;
1713 etest->flags |= ETH_TEST_FL_FAILED;
1714 }
1715 if (bnx2x_test_memory(bp) != 0) {
1716 buf[1] = 1;
1717 etest->flags |= ETH_TEST_FL_FAILED;
1718 }
f85582f8 1719
de0c62db
DK		 1720 buf[2] = bnx2x_test_loopback(bp, link_up);
1721 if (buf[2] != 0)
1722 etest->flags |= ETH_TEST_FL_FAILED;
1723
1724 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1725
1726 /* restore input for TX port IF */
1727 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
1728
1729 bnx2x_nic_load(bp, LOAD_NORMAL);
1730 /* wait until link state is restored */
a22f0788 1731 bnx2x_wait_for_link(bp, link_up, is_serdes);
de0c62db
DK		 1732 }
1733 if (bnx2x_test_nvram(bp) != 0) {
1734 buf[3] = 1;
1735 etest->flags |= ETH_TEST_FL_FAILED;
1736 }
1737 if (bnx2x_test_intr(bp) != 0) {
1738 buf[4] = 1;
1739 etest->flags |= ETH_TEST_FL_FAILED;
1740 }
1741 if (bp->port.pmf)
a22f0788 1742 if (bnx2x_link_test(bp, is_serdes) != 0) {
de0c62db
DK		 1743 buf[5] = 1;
1744 etest->flags |= ETH_TEST_FL_FAILED;
1745 }
1746
1747#ifdef BNX2X_EXTRA_DEBUG
1748 bnx2x_panic_dump(bp);
1749#endif
1750}
1751
1752static const struct {
1753 long offset;
1754 int size;
1755 u8 string[ETH_GSTRING_LEN];
1756} bnx2x_q_stats_arr[BNX2X_NUM_Q_STATS] = {
1757/* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%d]: rx_bytes" },
1758 { Q_STATS_OFFSET32(error_bytes_received_hi),
1759 8, "[%d]: rx_error_bytes" },
1760 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
1761 8, "[%d]: rx_ucast_packets" },
1762 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
1763 8, "[%d]: rx_mcast_packets" },
1764 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
1765 8, "[%d]: rx_bcast_packets" },
1766 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%d]: rx_discards" },
1767 { Q_STATS_OFFSET32(rx_err_discard_pkt),
1768 4, "[%d]: rx_phy_ip_err_discards"},
1769 { Q_STATS_OFFSET32(rx_skb_alloc_failed),
1770 4, "[%d]: rx_skb_alloc_discard" },
1771 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%d]: rx_csum_offload_errors" },
1772
1773/* 10 */{ Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%d]: tx_bytes" },
1774 { Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
1775 8, "[%d]: tx_ucast_packets" },
1776 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
1777 8, "[%d]: tx_mcast_packets" },
1778 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
1779 8, "[%d]: tx_bcast_packets" }
1780};
1781
1782static const struct {
1783 long offset;
1784 int size;
1785 u32 flags;
1786#define STATS_FLAGS_PORT 1
1787#define STATS_FLAGS_FUNC 2
1788#define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
1789 u8 string[ETH_GSTRING_LEN];
1790} bnx2x_stats_arr[BNX2X_NUM_STATS] = {
1791/* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
1792 8, STATS_FLAGS_BOTH, "rx_bytes" },
1793 { STATS_OFFSET32(error_bytes_received_hi),
1794 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
1795 { STATS_OFFSET32(total_unicast_packets_received_hi),
1796 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
1797 { STATS_OFFSET32(total_multicast_packets_received_hi),
1798 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
1799 { STATS_OFFSET32(total_broadcast_packets_received_hi),
1800 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
1801 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
1802 8, STATS_FLAGS_PORT, "rx_crc_errors" },
1803 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
1804 8, STATS_FLAGS_PORT, "rx_align_errors" },
1805 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
1806 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
1807 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
1808 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
1809/* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
1810 8, STATS_FLAGS_PORT, "rx_fragments" },
1811 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
1812 8, STATS_FLAGS_PORT, "rx_jabbers" },
1813 { STATS_OFFSET32(no_buff_discard_hi),
1814 8, STATS_FLAGS_BOTH, "rx_discards" },
1815 { STATS_OFFSET32(mac_filter_discard),
1816 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
1817 { STATS_OFFSET32(xxoverflow_discard),
1818 4, STATS_FLAGS_PORT, "rx_fw_discards" },
1819 { STATS_OFFSET32(brb_drop_hi),
1820 8, STATS_FLAGS_PORT, "rx_brb_discard" },
1821 { STATS_OFFSET32(brb_truncate_hi),
1822 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
1823 { STATS_OFFSET32(pause_frames_received_hi),
1824 8, STATS_FLAGS_PORT, "rx_pause_frames" },
1825 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
1826 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
1827 { STATS_OFFSET32(nig_timer_max),
1828 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
1829/* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
1830 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
1831 { STATS_OFFSET32(rx_skb_alloc_failed),
1832 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
1833 { STATS_OFFSET32(hw_csum_err),
1834 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
1835
1836 { STATS_OFFSET32(total_bytes_transmitted_hi),
1837 8, STATS_FLAGS_BOTH, "tx_bytes" },
1838 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
1839 8, STATS_FLAGS_PORT, "tx_error_bytes" },
1840 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
1841 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
1842 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
1843 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
1844 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
1845 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
1846 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
1847 8, STATS_FLAGS_PORT, "tx_mac_errors" },
1848 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
1849 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
1850/* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
1851 8, STATS_FLAGS_PORT, "tx_single_collisions" },
1852 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
1853 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
1854 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
1855 8, STATS_FLAGS_PORT, "tx_deferred" },
1856 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
1857 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
1858 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
1859 8, STATS_FLAGS_PORT, "tx_late_collisions" },
1860 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
1861 8, STATS_FLAGS_PORT, "tx_total_collisions" },
1862 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
1863 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
1864 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
1865 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
1866 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
1867 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
1868 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
1869 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
1870/* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
1871 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
1872 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
1873 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
1874 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
1875 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
1876 { STATS_OFFSET32(pause_frames_sent_hi),
1877 8, STATS_FLAGS_PORT, "tx_pause_frames" }
1878};
1879
1880#define IS_PORT_STAT(i) \
1881 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
1882#define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
fb3bff17
DK		 1883#define IS_MF_MODE_STAT(bp) \
1884 (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
de0c62db
DK		 1885
1886static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
1887{
1888 struct bnx2x *bp = netdev_priv(dev);
1889 int i, num_stats;
1890
1891 switch (stringset) {
1892 case ETH_SS_STATS:
1893 if (is_multi(bp)) {
1894 num_stats = BNX2X_NUM_Q_STATS * bp->num_queues;
fb3bff17 1895 if (!IS_MF_MODE_STAT(bp))
de0c62db
DK		 1896 num_stats += BNX2X_NUM_STATS;
1897 } else {
fb3bff17 1898 if (IS_MF_MODE_STAT(bp)) {
de0c62db
DK		 1899 num_stats = 0;
1900 for (i = 0; i < BNX2X_NUM_STATS; i++)
1901 if (IS_FUNC_STAT(i))
1902 num_stats++;
1903 } else
1904 num_stats = BNX2X_NUM_STATS;
1905 }
1906 return num_stats;
1907
1908 case ETH_SS_TEST:
1909 return BNX2X_NUM_TESTS;
1910
1911 default:
1912 return -EINVAL;
1913 }
1914}
1915
1916static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
1917{
1918 struct bnx2x *bp = netdev_priv(dev);
1919 int i, j, k;
1920
1921 switch (stringset) {
1922 case ETH_SS_STATS:
1923 if (is_multi(bp)) {
1924 k = 0;
1925 for_each_queue(bp, i) {
1926 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
1927 sprintf(buf + (k + j)*ETH_GSTRING_LEN,
1928 bnx2x_q_stats_arr[j].string, i);
1929 k += BNX2X_NUM_Q_STATS;
1930 }
fb3bff17 1931 if (IS_MF_MODE_STAT(bp))
de0c62db
DK		 1932 break;
1933 for (j = 0; j < BNX2X_NUM_STATS; j++)
1934 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
1935 bnx2x_stats_arr[j].string);
1936 } else {
1937 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
fb3bff17 1938 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
de0c62db
DK		 1939 continue;
1940 strcpy(buf + j*ETH_GSTRING_LEN,
1941 bnx2x_stats_arr[i].string);
1942 j++;
1943 }
1944 }
1945 break;
1946
1947 case ETH_SS_TEST:
1948 memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr));
1949 break;
1950 }
1951}
1952
1953static void bnx2x_get_ethtool_stats(struct net_device *dev,
1954 struct ethtool_stats *stats, u64 *buf)
1955{
1956 struct bnx2x *bp = netdev_priv(dev);
1957 u32 *hw_stats, *offset;
1958 int i, j, k;
1959
1960 if (is_multi(bp)) {
1961 k = 0;
1962 for_each_queue(bp, i) {
1963 hw_stats = (u32 *)&bp->fp[i].eth_q_stats;
1964 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
1965 if (bnx2x_q_stats_arr[j].size == 0) {
1966 /* skip this counter */
1967 buf[k + j] = 0;
1968 continue;
1969 }
1970 offset = (hw_stats +
1971 bnx2x_q_stats_arr[j].offset);
1972 if (bnx2x_q_stats_arr[j].size == 4) {
1973 /* 4-byte counter */
1974 buf[k + j] = (u64) *offset;
1975 continue;
1976 }
1977 /* 8-byte counter */
1978 buf[k + j] = HILO_U64(*offset, *(offset + 1));
1979 }
1980 k += BNX2X_NUM_Q_STATS;
1981 }
fb3bff17 1982 if (IS_MF_MODE_STAT(bp))
de0c62db
DK		 1983 return;
1984 hw_stats = (u32 *)&bp->eth_stats;
1985 for (j = 0; j < BNX2X_NUM_STATS; j++) {
1986 if (bnx2x_stats_arr[j].size == 0) {
1987 /* skip this counter */
1988 buf[k + j] = 0;
1989 continue;
1990 }
1991 offset = (hw_stats + bnx2x_stats_arr[j].offset);
1992 if (bnx2x_stats_arr[j].size == 4) {
1993 /* 4-byte counter */
1994 buf[k + j] = (u64) *offset;
1995 continue;
1996 }
1997 /* 8-byte counter */
1998 buf[k + j] = HILO_U64(*offset, *(offset + 1));
1999 }
2000 } else {
2001 hw_stats = (u32 *)&bp->eth_stats;
2002 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
fb3bff17 2003 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
de0c62db
DK		 2004 continue;
2005 if (bnx2x_stats_arr[i].size == 0) {
2006 /* skip this counter */
2007 buf[j] = 0;
2008 j++;
2009 continue;
2010 }
2011 offset = (hw_stats + bnx2x_stats_arr[i].offset);
2012 if (bnx2x_stats_arr[i].size == 4) {
2013 /* 4-byte counter */
2014 buf[j] = (u64) *offset;
2015 j++;
2016 continue;
2017 }
2018 /* 8-byte counter */
2019 buf[j] = HILO_U64(*offset, *(offset + 1));
2020 j++;
2021 }
2022 }
2023}
2024
2025static int bnx2x_phys_id(struct net_device *dev, u32 data)
2026{
2027 struct bnx2x *bp = netdev_priv(dev);
2028 int i;
2029
2030 if (!netif_running(dev))
2031 return 0;
2032
2033 if (!bp->port.pmf)
2034 return 0;
2035
2036 if (data == 0)
2037 data = 2;
2038
2039 for (i = 0; i < (data * 2); i++) {
2040 if ((i % 2) == 0)
7f02c4ad
YR		 2041 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2042 LED_MODE_OPER, SPEED_1000);
de0c62db 2043 else
7f02c4ad
YR		 2044 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2045 LED_MODE_OFF, 0);
de0c62db
DK		 2046
2047 msleep_interruptible(500);
2048 if (signal_pending(current))
2049 break;
2050 }
2051
2052 if (bp->link_vars.link_up)
7f02c4ad 2053 bnx2x_set_led(&bp->link_params, &bp->link_vars, LED_MODE_OPER,
de0c62db
DK		 2054 bp->link_vars.line_speed);
2055
2056 return 0;
2057}
2058
2059static const struct ethtool_ops bnx2x_ethtool_ops = {
2060 .get_settings = bnx2x_get_settings,
2061 .set_settings = bnx2x_set_settings,
2062 .get_drvinfo = bnx2x_get_drvinfo,
2063 .get_regs_len = bnx2x_get_regs_len,
2064 .get_regs = bnx2x_get_regs,
2065 .get_wol = bnx2x_get_wol,
2066 .set_wol = bnx2x_set_wol,
2067 .get_msglevel = bnx2x_get_msglevel,
2068 .set_msglevel = bnx2x_set_msglevel,
2069 .nway_reset = bnx2x_nway_reset,
2070 .get_link = bnx2x_get_link,
2071 .get_eeprom_len = bnx2x_get_eeprom_len,
2072 .get_eeprom = bnx2x_get_eeprom,
2073 .set_eeprom = bnx2x_set_eeprom,
2074 .get_coalesce = bnx2x_get_coalesce,
2075 .set_coalesce = bnx2x_set_coalesce,
2076 .get_ringparam = bnx2x_get_ringparam,
2077 .set_ringparam = bnx2x_set_ringparam,
2078 .get_pauseparam = bnx2x_get_pauseparam,
2079 .set_pauseparam = bnx2x_set_pauseparam,
2080 .get_rx_csum = bnx2x_get_rx_csum,
2081 .set_rx_csum = bnx2x_set_rx_csum,
2082 .get_tx_csum = ethtool_op_get_tx_csum,
2083 .set_tx_csum = ethtool_op_set_tx_hw_csum,
2084 .set_flags = bnx2x_set_flags,
2085 .get_flags = ethtool_op_get_flags,
2086 .get_sg = ethtool_op_get_sg,
2087 .set_sg = ethtool_op_set_sg,
2088 .get_tso = ethtool_op_get_tso,
2089 .set_tso = bnx2x_set_tso,
2090 .self_test = bnx2x_self_test,
2091 .get_sset_count = bnx2x_get_sset_count,
2092 .get_strings = bnx2x_get_strings,
2093 .phys_id = bnx2x_phys_id,
2094 .get_ethtool_stats = bnx2x_get_ethtool_stats,
2095};
2096
2097void bnx2x_set_ethtool_ops(struct net_device *netdev)
2098{
2099 SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
2100}
Clone of davem's net-next-2.6 tree