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Commit | Line | Data |
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a2fbb9ea ET |
1 | /* bnx2x.h: Broadcom Everest network driver. |
2 | * | |
3359fced | 3 | * Copyright (c) 2007-2010 Broadcom Corporation |
a2fbb9ea ET |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
24e3fcef EG |
9 | * Maintained by: Eilon Greenstein <eilong@broadcom.com> |
10 | * Written by: Eliezer Tamir | |
a2fbb9ea ET |
11 | * Based on code from Michael Chan's bnx2 driver |
12 | */ | |
13 | ||
14 | #ifndef BNX2X_H | |
15 | #define BNX2X_H | |
16 | ||
34f80b04 EG |
17 | /* compilation time flags */ |
18 | ||
19 | /* define this to make the driver freeze on error to allow getting debug info | |
20 | * (you will need to reboot afterwards) */ | |
21 | /* #define BNX2X_STOP_ON_ERROR */ | |
22 | ||
25141580 DK |
23 | #define DRV_MODULE_VERSION "1.52.53-7" |
24 | #define DRV_MODULE_RELDATE "2010/09/12" | |
de0c62db DK |
25 | #define BNX2X_BC_VER 0x040200 |
26 | ||
0c6671b0 EG |
27 | #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) |
28 | #define BCM_VLAN 1 | |
29 | #endif | |
30 | ||
1ac218c8 VZ |
31 | #define BNX2X_MULTI_QUEUE |
32 | ||
33 | #define BNX2X_NEW_NAPI | |
34 | ||
35 | ||
36 | ||
993ac7b5 MC |
37 | #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE) |
38 | #define BCM_CNIC 1 | |
5d1e859c | 39 | #include "../cnic_if.h" |
993ac7b5 | 40 | #endif |
0c6671b0 | 41 | |
359d8b15 | 42 | |
1ac218c8 VZ |
43 | #ifdef BCM_CNIC |
44 | #define BNX2X_MIN_MSIX_VEC_CNT 3 | |
45 | #define BNX2X_MSIX_VEC_FP_START 2 | |
46 | #else | |
47 | #define BNX2X_MIN_MSIX_VEC_CNT 2 | |
48 | #define BNX2X_MSIX_VEC_FP_START 1 | |
49 | #endif | |
01cd4528 EG |
50 | |
51 | #include <linux/mdio.h> | |
9f6c9258 | 52 | #include <linux/pci.h> |
359d8b15 EG |
53 | #include "bnx2x_reg.h" |
54 | #include "bnx2x_fw_defs.h" | |
55 | #include "bnx2x_hsi.h" | |
56 | #include "bnx2x_link.h" | |
6c719d00 | 57 | #include "bnx2x_stats.h" |
359d8b15 | 58 | |
a2fbb9ea ET |
59 | /* error/debug prints */ |
60 | ||
34f80b04 | 61 | #define DRV_MODULE_NAME "bnx2x" |
a2fbb9ea ET |
62 | |
63 | /* for messages that are currently off */ | |
34f80b04 EG |
64 | #define BNX2X_MSG_OFF 0 |
65 | #define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */ | |
66 | #define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */ | |
67 | #define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */ | |
68 | #define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */ | |
f1410647 ET |
69 | #define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */ |
70 | #define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */ | |
a2fbb9ea | 71 | |
34f80b04 | 72 | #define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */ |
a2fbb9ea ET |
73 | |
74 | /* regular debug print */ | |
7995c64e JP |
75 | #define DP(__mask, __fmt, __args...) \ |
76 | do { \ | |
77 | if (bp->msg_enable & (__mask)) \ | |
78 | printk(DP_LEVEL "[%s:%d(%s)]" __fmt, \ | |
79 | __func__, __LINE__, \ | |
80 | bp->dev ? (bp->dev->name) : "?", \ | |
81 | ##__args); \ | |
82 | } while (0) | |
a2fbb9ea | 83 | |
34f80b04 | 84 | /* errors debug print */ |
7995c64e JP |
85 | #define BNX2X_DBG_ERR(__fmt, __args...) \ |
86 | do { \ | |
87 | if (netif_msg_probe(bp)) \ | |
88 | pr_err("[%s:%d(%s)]" __fmt, \ | |
89 | __func__, __LINE__, \ | |
90 | bp->dev ? (bp->dev->name) : "?", \ | |
91 | ##__args); \ | |
92 | } while (0) | |
a2fbb9ea | 93 | |
34f80b04 | 94 | /* for errors (never masked) */ |
7995c64e JP |
95 | #define BNX2X_ERR(__fmt, __args...) \ |
96 | do { \ | |
97 | pr_err("[%s:%d(%s)]" __fmt, \ | |
98 | __func__, __LINE__, \ | |
99 | bp->dev ? (bp->dev->name) : "?", \ | |
100 | ##__args); \ | |
cdaa7cb8 VZ |
101 | } while (0) |
102 | ||
103 | #define BNX2X_ERROR(__fmt, __args...) do { \ | |
104 | pr_err("[%s:%d]" __fmt, __func__, __LINE__, ##__args); \ | |
105 | } while (0) | |
106 | ||
f1410647 | 107 | |
a2fbb9ea | 108 | /* before we have a dev->name use dev_info() */ |
7995c64e JP |
109 | #define BNX2X_DEV_INFO(__fmt, __args...) \ |
110 | do { \ | |
111 | if (netif_msg_probe(bp)) \ | |
112 | dev_info(&bp->pdev->dev, __fmt, ##__args); \ | |
113 | } while (0) | |
a2fbb9ea | 114 | |
6c719d00 | 115 | void bnx2x_panic_dump(struct bnx2x *bp); |
a2fbb9ea ET |
116 | |
117 | #ifdef BNX2X_STOP_ON_ERROR | |
118 | #define bnx2x_panic() do { \ | |
119 | bp->panic = 1; \ | |
120 | BNX2X_ERR("driver assert\n"); \ | |
34f80b04 | 121 | bnx2x_int_disable(bp); \ |
a2fbb9ea ET |
122 | bnx2x_panic_dump(bp); \ |
123 | } while (0) | |
124 | #else | |
125 | #define bnx2x_panic() do { \ | |
e3553b29 | 126 | bp->panic = 1; \ |
a2fbb9ea ET |
127 | BNX2X_ERR("driver assert\n"); \ |
128 | bnx2x_panic_dump(bp); \ | |
129 | } while (0) | |
130 | #endif | |
131 | ||
132 | ||
34f80b04 EG |
133 | #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff) |
134 | #define U64_HI(x) (u32)(((u64)(x)) >> 32) | |
135 | #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) | |
a2fbb9ea | 136 | |
a2fbb9ea | 137 | |
34f80b04 | 138 | #define REG_ADDR(bp, offset) (bp->regview + offset) |
a2fbb9ea | 139 | |
34f80b04 EG |
140 | #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) |
141 | #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) | |
34f80b04 EG |
142 | |
143 | #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) | |
a2fbb9ea | 144 | #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) |
34f80b04 | 145 | #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) |
a2fbb9ea | 146 | |
34f80b04 EG |
147 | #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) |
148 | #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) | |
a2fbb9ea | 149 | |
c18487ee YR |
150 | #define REG_RD_DMAE(bp, offset, valp, len32) \ |
151 | do { \ | |
152 | bnx2x_read_dmae(bp, offset, len32);\ | |
573f2035 | 153 | memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \ |
c18487ee YR |
154 | } while (0) |
155 | ||
34f80b04 | 156 | #define REG_WR_DMAE(bp, offset, valp, len32) \ |
a2fbb9ea | 157 | do { \ |
573f2035 | 158 | memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \ |
a2fbb9ea ET |
159 | bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ |
160 | offset, len32); \ | |
161 | } while (0) | |
162 | ||
3359fced | 163 | #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \ |
573f2035 EG |
164 | do { \ |
165 | memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \ | |
166 | bnx2x_write_big_buf_wb(bp, addr, len32); \ | |
167 | } while (0) | |
168 | ||
34f80b04 EG |
169 | #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \ |
170 | offsetof(struct shmem_region, field)) | |
171 | #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) | |
172 | #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) | |
a2fbb9ea | 173 | |
2691d51d EG |
174 | #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \ |
175 | offsetof(struct shmem2_region, field)) | |
176 | #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field)) | |
177 | #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val) | |
178 | ||
72fd0718 VZ |
179 | #define MF_CFG_RD(bp, field) SHMEM_RD(bp, mf_cfg.field) |
180 | #define MF_CFG_WR(bp, field, val) SHMEM_WR(bp, mf_cfg.field, val) | |
181 | ||
345b5d52 | 182 | #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) |
3196a88a | 183 | #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) |
a2fbb9ea | 184 | |
72fd0718 VZ |
185 | #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ |
186 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR | |
187 | ||
a2fbb9ea | 188 | |
7a9b2557 | 189 | /* fast path */ |
a2fbb9ea | 190 | |
a2fbb9ea | 191 | struct sw_rx_bd { |
34f80b04 | 192 | struct sk_buff *skb; |
1a983142 | 193 | DEFINE_DMA_UNMAP_ADDR(mapping); |
a2fbb9ea ET |
194 | }; |
195 | ||
196 | struct sw_tx_bd { | |
34f80b04 EG |
197 | struct sk_buff *skb; |
198 | u16 first_bd; | |
ca00392c EG |
199 | u8 flags; |
200 | /* Set on the first BD descriptor when there is a split BD */ | |
201 | #define BNX2X_TSO_SPLIT_BD (1<<0) | |
a2fbb9ea ET |
202 | }; |
203 | ||
7a9b2557 VZ |
204 | struct sw_rx_page { |
205 | struct page *page; | |
1a983142 | 206 | DEFINE_DMA_UNMAP_ADDR(mapping); |
7a9b2557 VZ |
207 | }; |
208 | ||
ca00392c EG |
209 | union db_prod { |
210 | struct doorbell_set_prod data; | |
211 | u32 raw; | |
212 | }; | |
213 | ||
7a9b2557 VZ |
214 | |
215 | /* MC hsi */ | |
216 | #define BCM_PAGE_SHIFT 12 | |
217 | #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) | |
218 | #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) | |
219 | #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) | |
220 | ||
221 | #define PAGES_PER_SGE_SHIFT 0 | |
222 | #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) | |
4f40f2cb EG |
223 | #define SGE_PAGE_SIZE PAGE_SIZE |
224 | #define SGE_PAGE_SHIFT PAGE_SHIFT | |
5b6402d1 | 225 | #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr)) |
7a9b2557 VZ |
226 | |
227 | /* SGE ring related macros */ | |
228 | #define NUM_RX_SGE_PAGES 2 | |
229 | #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) | |
230 | #define MAX_RX_SGE_CNT (RX_SGE_CNT - 2) | |
33471629 | 231 | /* RX_SGE_CNT is promised to be a power of 2 */ |
7a9b2557 VZ |
232 | #define RX_SGE_MASK (RX_SGE_CNT - 1) |
233 | #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) | |
234 | #define MAX_RX_SGE (NUM_RX_SGE - 1) | |
235 | #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \ | |
236 | (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1) | |
237 | #define RX_SGE(x) ((x) & MAX_RX_SGE) | |
238 | ||
239 | /* SGE producer mask related macros */ | |
240 | /* Number of bits in one sge_mask array element */ | |
241 | #define RX_SGE_MASK_ELEM_SZ 64 | |
242 | #define RX_SGE_MASK_ELEM_SHIFT 6 | |
243 | #define RX_SGE_MASK_ELEM_MASK ((u64)RX_SGE_MASK_ELEM_SZ - 1) | |
244 | ||
245 | /* Creates a bitmask of all ones in less significant bits. | |
246 | idx - index of the most significant bit in the created mask */ | |
247 | #define RX_SGE_ONES_MASK(idx) \ | |
248 | (((u64)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1) | |
249 | #define RX_SGE_MASK_ELEM_ONE_MASK ((u64)(~0)) | |
250 | ||
251 | /* Number of u64 elements in SGE mask array */ | |
252 | #define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \ | |
253 | RX_SGE_MASK_ELEM_SZ) | |
254 | #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) | |
255 | #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) | |
256 | ||
257 | ||
a2fbb9ea ET |
258 | struct bnx2x_fastpath { |
259 | ||
34f80b04 | 260 | struct napi_struct napi; |
a2fbb9ea | 261 | struct host_status_block *status_blk; |
34f80b04 | 262 | dma_addr_t status_blk_mapping; |
a2fbb9ea | 263 | |
34f80b04 | 264 | struct sw_tx_bd *tx_buf_ring; |
a2fbb9ea | 265 | |
ca00392c | 266 | union eth_tx_bd_types *tx_desc_ring; |
34f80b04 | 267 | dma_addr_t tx_desc_mapping; |
a2fbb9ea | 268 | |
7a9b2557 VZ |
269 | struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */ |
270 | struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */ | |
a2fbb9ea ET |
271 | |
272 | struct eth_rx_bd *rx_desc_ring; | |
34f80b04 | 273 | dma_addr_t rx_desc_mapping; |
a2fbb9ea ET |
274 | |
275 | union eth_rx_cqe *rx_comp_ring; | |
34f80b04 EG |
276 | dma_addr_t rx_comp_mapping; |
277 | ||
7a9b2557 VZ |
278 | /* SGE ring */ |
279 | struct eth_rx_sge *rx_sge_ring; | |
280 | dma_addr_t rx_sge_mapping; | |
281 | ||
282 | u64 sge_mask[RX_SGE_MASK_LEN]; | |
283 | ||
34f80b04 EG |
284 | int state; |
285 | #define BNX2X_FP_STATE_CLOSED 0 | |
286 | #define BNX2X_FP_STATE_IRQ 0x80000 | |
287 | #define BNX2X_FP_STATE_OPENING 0x90000 | |
288 | #define BNX2X_FP_STATE_OPEN 0xa0000 | |
289 | #define BNX2X_FP_STATE_HALTING 0xb0000 | |
290 | #define BNX2X_FP_STATE_HALTED 0xc0000 | |
291 | ||
292 | u8 index; /* number in fp array */ | |
293 | u8 cl_id; /* eth client id */ | |
294 | u8 sb_id; /* status block number in HW */ | |
34f80b04 | 295 | |
ca00392c EG |
296 | union db_prod tx_db; |
297 | ||
34f80b04 EG |
298 | u16 tx_pkt_prod; |
299 | u16 tx_pkt_cons; | |
300 | u16 tx_bd_prod; | |
301 | u16 tx_bd_cons; | |
4781bfad | 302 | __le16 *tx_cons_sb; |
34f80b04 | 303 | |
4781bfad EG |
304 | __le16 fp_c_idx; |
305 | __le16 fp_u_idx; | |
34f80b04 EG |
306 | |
307 | u16 rx_bd_prod; | |
308 | u16 rx_bd_cons; | |
309 | u16 rx_comp_prod; | |
310 | u16 rx_comp_cons; | |
7a9b2557 VZ |
311 | u16 rx_sge_prod; |
312 | /* The last maximal completed SGE */ | |
313 | u16 last_max_sge; | |
4781bfad EG |
314 | __le16 *rx_cons_sb; |
315 | __le16 *rx_bd_cons_sb; | |
34f80b04 | 316 | |
ab6ad5a4 | 317 | |
34f80b04 | 318 | unsigned long tx_pkt, |
a2fbb9ea | 319 | rx_pkt, |
66e855f3 | 320 | rx_calls; |
ab6ad5a4 | 321 | |
7a9b2557 VZ |
322 | /* TPA related */ |
323 | struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H]; | |
324 | u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H]; | |
325 | #define BNX2X_TPA_START 1 | |
326 | #define BNX2X_TPA_STOP 2 | |
327 | u8 disable_tpa; | |
328 | #ifdef BNX2X_STOP_ON_ERROR | |
329 | u64 tpa_queue_used; | |
330 | #endif | |
a2fbb9ea | 331 | |
de832a55 EG |
332 | struct tstorm_per_client_stats old_tclient; |
333 | struct ustorm_per_client_stats old_uclient; | |
334 | struct xstorm_per_client_stats old_xclient; | |
335 | struct bnx2x_eth_q_stats eth_q_stats; | |
336 | ||
ca00392c EG |
337 | /* The size is calculated using the following: |
338 | sizeof name field from netdev structure + | |
339 | 4 ('-Xx-' string) + | |
340 | 4 (for the digits and to make it DWORD aligned) */ | |
341 | #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8) | |
342 | char name[FP_NAME_SIZE]; | |
34f80b04 | 343 | struct bnx2x *bp; /* parent */ |
a2fbb9ea ET |
344 | }; |
345 | ||
34f80b04 | 346 | #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var) |
7a9b2557 VZ |
347 | |
348 | ||
349 | /* MC hsi */ | |
350 | #define MAX_FETCH_BD 13 /* HW max BDs per packet */ | |
351 | #define RX_COPY_THRESH 92 | |
352 | ||
353 | #define NUM_TX_RINGS 16 | |
ca00392c | 354 | #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) |
7a9b2557 VZ |
355 | #define MAX_TX_DESC_CNT (TX_DESC_CNT - 1) |
356 | #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) | |
357 | #define MAX_TX_BD (NUM_TX_BD - 1) | |
358 | #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2) | |
359 | #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \ | |
360 | (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1) | |
361 | #define TX_BD(x) ((x) & MAX_TX_BD) | |
362 | #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) | |
363 | ||
364 | /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ | |
365 | #define NUM_RX_RINGS 8 | |
366 | #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) | |
367 | #define MAX_RX_DESC_CNT (RX_DESC_CNT - 2) | |
368 | #define RX_DESC_MASK (RX_DESC_CNT - 1) | |
369 | #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS) | |
370 | #define MAX_RX_BD (NUM_RX_BD - 1) | |
371 | #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2) | |
25141580 | 372 | #define MIN_RX_AVAIL 128 |
7a9b2557 VZ |
373 | #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \ |
374 | (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1) | |
375 | #define RX_BD(x) ((x) & MAX_RX_BD) | |
376 | ||
377 | /* As long as CQE is 4 times bigger than BD entry we have to allocate | |
378 | 4 times more pages for CQ ring in order to keep it balanced with | |
379 | BD ring */ | |
380 | #define NUM_RCQ_RINGS (NUM_RX_RINGS * 4) | |
381 | #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) | |
382 | #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1) | |
383 | #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS) | |
384 | #define MAX_RCQ_BD (NUM_RCQ_BD - 1) | |
385 | #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2) | |
386 | #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \ | |
387 | (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1) | |
388 | #define RCQ_BD(x) ((x) & MAX_RCQ_BD) | |
389 | ||
390 | ||
33471629 | 391 | /* This is needed for determining of last_max */ |
34f80b04 | 392 | #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) |
a2fbb9ea | 393 | |
7a9b2557 VZ |
394 | #define __SGE_MASK_SET_BIT(el, bit) \ |
395 | do { \ | |
396 | el = ((el) | ((u64)0x1 << (bit))); \ | |
397 | } while (0) | |
398 | ||
399 | #define __SGE_MASK_CLEAR_BIT(el, bit) \ | |
400 | do { \ | |
401 | el = ((el) & (~((u64)0x1 << (bit)))); \ | |
402 | } while (0) | |
403 | ||
404 | #define SGE_MASK_SET_BIT(fp, idx) \ | |
405 | __SGE_MASK_SET_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \ | |
406 | ((idx) & RX_SGE_MASK_ELEM_MASK)) | |
407 | ||
408 | #define SGE_MASK_CLEAR_BIT(fp, idx) \ | |
409 | __SGE_MASK_CLEAR_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \ | |
410 | ((idx) & RX_SGE_MASK_ELEM_MASK)) | |
411 | ||
412 | ||
413 | /* used on a CID received from the HW */ | |
414 | #define SW_CID(x) (le32_to_cpu(x) & \ | |
415 | (COMMON_RAMROD_ETH_RX_CQE_CID >> 7)) | |
416 | #define CQE_CMD(x) (le32_to_cpu(x) >> \ | |
417 | COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) | |
418 | ||
bb2a0f7a YG |
419 | #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \ |
420 | le32_to_cpu((bd)->addr_lo)) | |
421 | #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) | |
422 | ||
7a9b2557 VZ |
423 | |
424 | #define DPM_TRIGER_TYPE 0x40 | |
425 | #define DOORBELL(bp, cid, val) \ | |
426 | do { \ | |
ca00392c | 427 | writel((u32)(val), bp->doorbells + (BCM_PAGE_SIZE * (cid)) + \ |
7a9b2557 VZ |
428 | DPM_TRIGER_TYPE); \ |
429 | } while (0) | |
430 | ||
431 | ||
432 | /* TX CSUM helpers */ | |
433 | #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \ | |
434 | skb->csum_offset) | |
435 | #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \ | |
436 | skb->csum_offset)) | |
437 | ||
438 | #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff) | |
439 | ||
440 | #define XMIT_PLAIN 0 | |
441 | #define XMIT_CSUM_V4 0x1 | |
442 | #define XMIT_CSUM_V6 0x2 | |
443 | #define XMIT_CSUM_TCP 0x4 | |
444 | #define XMIT_GSO_V4 0x8 | |
445 | #define XMIT_GSO_V6 0x10 | |
446 | ||
447 | #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6) | |
448 | #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6) | |
449 | ||
450 | ||
34f80b04 | 451 | /* stuff added to make the code fit 80Col */ |
a2fbb9ea | 452 | |
34f80b04 | 453 | #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) |
a2fbb9ea | 454 | |
7a9b2557 VZ |
455 | #define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG |
456 | #define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG | |
457 | #define TPA_TYPE(cqe_fp_flags) ((cqe_fp_flags) & \ | |
458 | (TPA_TYPE_START | TPA_TYPE_END)) | |
459 | ||
1adcd8be EG |
460 | #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG |
461 | ||
462 | #define BNX2X_IP_CSUM_ERR(cqe) \ | |
463 | (!((cqe)->fast_path_cqe.status_flags & \ | |
464 | ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \ | |
465 | ((cqe)->fast_path_cqe.type_error_flags & \ | |
466 | ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG)) | |
467 | ||
468 | #define BNX2X_L4_CSUM_ERR(cqe) \ | |
469 | (!((cqe)->fast_path_cqe.status_flags & \ | |
470 | ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \ | |
471 | ((cqe)->fast_path_cqe.type_error_flags & \ | |
472 | ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)) | |
473 | ||
474 | #define BNX2X_RX_CSUM_OK(cqe) \ | |
475 | (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe))) | |
7a9b2557 | 476 | |
052a38e0 EG |
477 | #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \ |
478 | (((le16_to_cpu(flags) & \ | |
479 | PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \ | |
480 | PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \ | |
481 | == PRS_FLAG_OVERETH_IPV4) | |
7a9b2557 | 482 | #define BNX2X_RX_SUM_FIX(cqe) \ |
052a38e0 | 483 | BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags) |
7a9b2557 | 484 | |
a2fbb9ea | 485 | |
bb2a0f7a YG |
486 | #define FP_USB_FUNC_OFF (2 + 2*HC_USTORM_SB_NUM_INDICES) |
487 | #define FP_CSB_FUNC_OFF (2 + 2*HC_CSTORM_SB_NUM_INDICES) | |
488 | ||
34f80b04 EG |
489 | #define U_SB_ETH_RX_CQ_INDEX HC_INDEX_U_ETH_RX_CQ_CONS |
490 | #define U_SB_ETH_RX_BD_INDEX HC_INDEX_U_ETH_RX_BD_CONS | |
491 | #define C_SB_ETH_TX_CQ_INDEX HC_INDEX_C_ETH_TX_CQ_CONS | |
a2fbb9ea | 492 | |
34f80b04 EG |
493 | #define BNX2X_RX_SB_INDEX \ |
494 | (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX]) | |
a2fbb9ea | 495 | |
34f80b04 EG |
496 | #define BNX2X_RX_SB_BD_INDEX \ |
497 | (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_BD_INDEX]) | |
a2fbb9ea | 498 | |
34f80b04 EG |
499 | #define BNX2X_RX_SB_INDEX_NUM \ |
500 | (((U_SB_ETH_RX_CQ_INDEX << \ | |
501 | USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT) & \ | |
502 | USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER) | \ | |
503 | ((U_SB_ETH_RX_BD_INDEX << \ | |
504 | USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT) & \ | |
505 | USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER)) | |
a2fbb9ea | 506 | |
34f80b04 EG |
507 | #define BNX2X_TX_SB_INDEX \ |
508 | (&fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX]) | |
a2fbb9ea | 509 | |
7a9b2557 VZ |
510 | |
511 | /* end of fast path */ | |
512 | ||
34f80b04 | 513 | /* common */ |
a2fbb9ea | 514 | |
34f80b04 | 515 | struct bnx2x_common { |
a2fbb9ea | 516 | |
ad8d3948 | 517 | u32 chip_id; |
a2fbb9ea | 518 | /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ |
34f80b04 | 519 | #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0) |
ad8d3948 | 520 | |
34f80b04 | 521 | #define CHIP_NUM(bp) (bp->common.chip_id >> 16) |
ad8d3948 EG |
522 | #define CHIP_NUM_57710 0x164e |
523 | #define CHIP_NUM_57711 0x164f | |
524 | #define CHIP_NUM_57711E 0x1650 | |
525 | #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710) | |
526 | #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711) | |
527 | #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E) | |
528 | #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ | |
529 | CHIP_IS_57711E(bp)) | |
530 | #define IS_E1H_OFFSET CHIP_IS_E1H(bp) | |
531 | ||
34f80b04 | 532 | #define CHIP_REV(bp) (bp->common.chip_id & 0x0000f000) |
ad8d3948 EG |
533 | #define CHIP_REV_Ax 0x00000000 |
534 | /* assume maximum 5 revisions */ | |
535 | #define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000) | |
536 | /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */ | |
537 | #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \ | |
538 | !(CHIP_REV(bp) & 0x00001000)) | |
539 | /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */ | |
540 | #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \ | |
541 | (CHIP_REV(bp) & 0x00001000)) | |
542 | ||
543 | #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \ | |
544 | ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1)) | |
545 | ||
34f80b04 EG |
546 | #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) |
547 | #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) | |
a2fbb9ea | 548 | |
34f80b04 EG |
549 | int flash_size; |
550 | #define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */ | |
551 | #define NVRAM_TIMEOUT_COUNT 30000 | |
552 | #define NVRAM_PAGE_SIZE 256 | |
a2fbb9ea | 553 | |
34f80b04 | 554 | u32 shmem_base; |
2691d51d | 555 | u32 shmem2_base; |
34f80b04 EG |
556 | |
557 | u32 hw_config; | |
c18487ee | 558 | |
34f80b04 | 559 | u32 bc_ver; |
34f80b04 | 560 | }; |
c18487ee | 561 | |
34f80b04 EG |
562 | |
563 | /* end of common */ | |
564 | ||
565 | /* port */ | |
566 | ||
567 | struct bnx2x_port { | |
568 | u32 pmf; | |
c18487ee | 569 | |
a22f0788 | 570 | u32 link_config[LINK_CONFIG_SIZE]; |
a2fbb9ea | 571 | |
a22f0788 | 572 | u32 supported[LINK_CONFIG_SIZE]; |
34f80b04 EG |
573 | /* link settings - missing defines */ |
574 | #define SUPPORTED_2500baseX_Full (1 << 15) | |
575 | ||
a22f0788 | 576 | u32 advertising[LINK_CONFIG_SIZE]; |
a2fbb9ea | 577 | /* link settings - missing defines */ |
34f80b04 | 578 | #define ADVERTISED_2500baseX_Full (1 << 15) |
a2fbb9ea | 579 | |
34f80b04 | 580 | u32 phy_addr; |
c18487ee YR |
581 | |
582 | /* used to synchronize phy accesses */ | |
583 | struct mutex phy_mutex; | |
46c6a674 | 584 | int need_hw_lock; |
c18487ee | 585 | |
34f80b04 | 586 | u32 port_stx; |
a2fbb9ea | 587 | |
34f80b04 EG |
588 | struct nig_stats old_nig_stats; |
589 | }; | |
a2fbb9ea | 590 | |
34f80b04 EG |
591 | /* end of port */ |
592 | ||
bb2a0f7a | 593 | |
34f80b04 | 594 | |
37b091ba MC |
595 | #ifdef BCM_CNIC |
596 | #define MAX_CONTEXT 15 | |
597 | #else | |
34f80b04 | 598 | #define MAX_CONTEXT 16 |
37b091ba | 599 | #endif |
34f80b04 EG |
600 | |
601 | union cdu_context { | |
602 | struct eth_context eth; | |
603 | char pad[1024]; | |
604 | }; | |
605 | ||
bb2a0f7a | 606 | #define MAX_DMAE_C 8 |
34f80b04 EG |
607 | |
608 | /* DMA memory not used in fastpath */ | |
609 | struct bnx2x_slowpath { | |
610 | union cdu_context context[MAX_CONTEXT]; | |
611 | struct eth_stats_query fw_stats; | |
612 | struct mac_configuration_cmd mac_config; | |
613 | struct mac_configuration_cmd mcast_config; | |
614 | ||
615 | /* used by dmae command executer */ | |
616 | struct dmae_command dmae[MAX_DMAE_C]; | |
617 | ||
bb2a0f7a YG |
618 | u32 stats_comp; |
619 | union mac_stats mac_stats; | |
620 | struct nig_stats nig_stats; | |
621 | struct host_port_stats port_stats; | |
622 | struct host_func_stats func_stats; | |
6fe49bb9 | 623 | struct host_func_stats func_stats_base; |
34f80b04 EG |
624 | |
625 | u32 wb_comp; | |
34f80b04 EG |
626 | u32 wb_data[4]; |
627 | }; | |
628 | ||
629 | #define bnx2x_sp(bp, var) (&bp->slowpath->var) | |
630 | #define bnx2x_sp_mapping(bp, var) \ | |
631 | (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) | |
632 | ||
633 | ||
634 | /* attn group wiring */ | |
635 | #define MAX_DYNAMIC_ATTN_GRPS 8 | |
636 | ||
637 | struct attn_route { | |
638 | u32 sig[4]; | |
639 | }; | |
640 | ||
72fd0718 VZ |
641 | typedef enum { |
642 | BNX2X_RECOVERY_DONE, | |
643 | BNX2X_RECOVERY_INIT, | |
644 | BNX2X_RECOVERY_WAIT, | |
645 | } bnx2x_recovery_state_t; | |
646 | ||
34f80b04 EG |
647 | struct bnx2x { |
648 | /* Fields used in the tx and intr/napi performance paths | |
649 | * are grouped together in the beginning of the structure | |
650 | */ | |
651 | struct bnx2x_fastpath fp[MAX_CONTEXT]; | |
652 | void __iomem *regview; | |
653 | void __iomem *doorbells; | |
37b091ba MC |
654 | #ifdef BCM_CNIC |
655 | #define BNX2X_DB_SIZE (18*BCM_PAGE_SIZE) | |
656 | #else | |
a5f67a04 | 657 | #define BNX2X_DB_SIZE (16*BCM_PAGE_SIZE) |
37b091ba | 658 | #endif |
34f80b04 EG |
659 | |
660 | struct net_device *dev; | |
661 | struct pci_dev *pdev; | |
662 | ||
663 | atomic_t intr_sem; | |
72fd0718 VZ |
664 | |
665 | bnx2x_recovery_state_t recovery_state; | |
666 | int is_leader; | |
37b091ba MC |
667 | #ifdef BCM_CNIC |
668 | struct msix_entry msix_table[MAX_CONTEXT+2]; | |
669 | #else | |
7a9b2557 | 670 | struct msix_entry msix_table[MAX_CONTEXT+1]; |
37b091ba | 671 | #endif |
8badd27a EG |
672 | #define INT_MODE_INTx 1 |
673 | #define INT_MODE_MSI 2 | |
34f80b04 EG |
674 | |
675 | int tx_ring_size; | |
676 | ||
677 | #ifdef BCM_VLAN | |
678 | struct vlan_group *vlgrp; | |
679 | #endif | |
a2fbb9ea | 680 | |
34f80b04 | 681 | u32 rx_csum; |
437cf2f1 | 682 | u32 rx_buf_size; |
34f80b04 EG |
683 | #define ETH_OVREHEAD (ETH_HLEN + 8) /* 8 for CRC + VLAN */ |
684 | #define ETH_MIN_PACKET_SIZE 60 | |
685 | #define ETH_MAX_PACKET_SIZE 1500 | |
686 | #define ETH_MAX_JUMBO_PACKET_SIZE 9600 | |
a2fbb9ea | 687 | |
0f00846d EG |
688 | /* Max supported alignment is 256 (8 shift) */ |
689 | #define BNX2X_RX_ALIGN_SHIFT ((L1_CACHE_SHIFT < 8) ? \ | |
690 | L1_CACHE_SHIFT : 8) | |
691 | #define BNX2X_RX_ALIGN (1 << BNX2X_RX_ALIGN_SHIFT) | |
692 | ||
34f80b04 EG |
693 | struct host_def_status_block *def_status_blk; |
694 | #define DEF_SB_ID 16 | |
4781bfad EG |
695 | __le16 def_c_idx; |
696 | __le16 def_u_idx; | |
697 | __le16 def_x_idx; | |
698 | __le16 def_t_idx; | |
699 | __le16 def_att_idx; | |
34f80b04 EG |
700 | u32 attn_state; |
701 | struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; | |
34f80b04 EG |
702 | |
703 | /* slow path ring */ | |
704 | struct eth_spe *spq; | |
705 | dma_addr_t spq_mapping; | |
706 | u16 spq_prod_idx; | |
707 | struct eth_spe *spq_prod_bd; | |
708 | struct eth_spe *spq_last_bd; | |
4781bfad | 709 | __le16 *dsb_sp_prod; |
34f80b04 EG |
710 | u16 spq_left; /* serialize spq */ |
711 | /* used to synchronize spq accesses */ | |
712 | spinlock_t spq_lock; | |
713 | ||
bb2a0f7a YG |
714 | /* Flags for marking that there is a STAT_QUERY or |
715 | SET_MAC ramrod pending */ | |
e665bfda MC |
716 | int stats_pending; |
717 | int set_mac_pending; | |
34f80b04 | 718 | |
33471629 | 719 | /* End of fields used in the performance code paths */ |
34f80b04 EG |
720 | |
721 | int panic; | |
7995c64e | 722 | int msg_enable; |
34f80b04 EG |
723 | |
724 | u32 flags; | |
725 | #define PCIX_FLAG 1 | |
726 | #define PCI_32BIT_FLAG 2 | |
1c06328c | 727 | #define ONE_PORT_FLAG 4 |
34f80b04 EG |
728 | #define NO_WOL_FLAG 8 |
729 | #define USING_DAC_FLAG 0x10 | |
730 | #define USING_MSIX_FLAG 0x20 | |
8badd27a | 731 | #define USING_MSI_FLAG 0x40 |
7a9b2557 | 732 | #define TPA_ENABLE_FLAG 0x80 |
34f80b04 EG |
733 | #define NO_MCP_FLAG 0x100 |
734 | #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG) | |
0c6671b0 EG |
735 | #define HW_VLAN_TX_FLAG 0x400 |
736 | #define HW_VLAN_RX_FLAG 0x800 | |
f34d28ea | 737 | #define MF_FUNC_DIS 0x1000 |
34f80b04 EG |
738 | |
739 | int func; | |
740 | #define BP_PORT(bp) (bp->func % PORT_MAX) | |
741 | #define BP_FUNC(bp) (bp->func) | |
742 | #define BP_E1HVN(bp) (bp->func >> 1) | |
743 | #define BP_L_ID(bp) (BP_E1HVN(bp) << 2) | |
34f80b04 | 744 | |
37b091ba MC |
745 | #ifdef BCM_CNIC |
746 | #define BCM_CNIC_CID_START 16 | |
747 | #define BCM_ISCSI_ETH_CL_ID 17 | |
748 | #endif | |
749 | ||
34f80b04 EG |
750 | int pm_cap; |
751 | int pcie_cap; | |
8d5726c4 | 752 | int mrrs; |
34f80b04 | 753 | |
1cf167f2 | 754 | struct delayed_work sp_task; |
72fd0718 | 755 | struct delayed_work reset_task; |
34f80b04 | 756 | struct timer_list timer; |
34f80b04 EG |
757 | int current_interval; |
758 | ||
759 | u16 fw_seq; | |
760 | u16 fw_drv_pulse_wr_seq; | |
761 | u32 func_stx; | |
762 | ||
763 | struct link_params link_params; | |
764 | struct link_vars link_vars; | |
01cd4528 | 765 | struct mdio_if_info mdio; |
a2fbb9ea | 766 | |
34f80b04 EG |
767 | struct bnx2x_common common; |
768 | struct bnx2x_port port; | |
769 | ||
8a1c38d1 EG |
770 | struct cmng_struct_per_port cmng; |
771 | u32 vn_weight_sum; | |
772 | ||
34f80b04 EG |
773 | u32 mf_config; |
774 | u16 e1hov; | |
775 | u8 e1hmf; | |
3196a88a | 776 | #define IS_E1HMF(bp) (bp->e1hmf != 0) |
a2fbb9ea | 777 | |
f1410647 ET |
778 | u8 wol; |
779 | ||
34f80b04 | 780 | int rx_ring_size; |
a2fbb9ea | 781 | |
34f80b04 EG |
782 | u16 tx_quick_cons_trip_int; |
783 | u16 tx_quick_cons_trip; | |
784 | u16 tx_ticks_int; | |
785 | u16 tx_ticks; | |
a2fbb9ea | 786 | |
34f80b04 EG |
787 | u16 rx_quick_cons_trip_int; |
788 | u16 rx_quick_cons_trip; | |
789 | u16 rx_ticks_int; | |
790 | u16 rx_ticks; | |
cdaa7cb8 VZ |
791 | /* Maximal coalescing timeout in us */ |
792 | #define BNX2X_MAX_COALESCE_TOUT (0xf0*12) | |
a2fbb9ea | 793 | |
34f80b04 | 794 | u32 lin_cnt; |
a2fbb9ea | 795 | |
34f80b04 | 796 | int state; |
356e2385 | 797 | #define BNX2X_STATE_CLOSED 0 |
34f80b04 EG |
798 | #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 |
799 | #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 | |
a2fbb9ea | 800 | #define BNX2X_STATE_OPEN 0x3000 |
34f80b04 | 801 | #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 |
a2fbb9ea ET |
802 | #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 |
803 | #define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000 | |
34f80b04 EG |
804 | #define BNX2X_STATE_DIAG 0xe000 |
805 | #define BNX2X_STATE_ERROR 0xf000 | |
a2fbb9ea | 806 | |
555f6c78 | 807 | int multi_mode; |
54b9ddaa | 808 | int num_queues; |
5d7cd496 DK |
809 | int disable_tpa; |
810 | int int_mode; | |
a2fbb9ea | 811 | |
34f80b04 EG |
812 | u32 rx_mode; |
813 | #define BNX2X_RX_MODE_NONE 0 | |
814 | #define BNX2X_RX_MODE_NORMAL 1 | |
815 | #define BNX2X_RX_MODE_ALLMULTI 2 | |
816 | #define BNX2X_RX_MODE_PROMISC 3 | |
817 | #define BNX2X_MAX_MULTICAST 64 | |
818 | #define BNX2X_MAX_EMUL_MULTI 16 | |
a2fbb9ea | 819 | |
37b091ba MC |
820 | u32 rx_mode_cl_mask; |
821 | ||
34f80b04 | 822 | dma_addr_t def_status_blk_mapping; |
a2fbb9ea | 823 | |
34f80b04 EG |
824 | struct bnx2x_slowpath *slowpath; |
825 | dma_addr_t slowpath_mapping; | |
a2fbb9ea | 826 | |
a18f5128 EG |
827 | int dropless_fc; |
828 | ||
37b091ba MC |
829 | #ifdef BCM_CNIC |
830 | u32 cnic_flags; | |
831 | #define BNX2X_CNIC_FLAG_MAC_SET 1 | |
832 | ||
833 | void *t1; | |
834 | dma_addr_t t1_mapping; | |
835 | void *t2; | |
836 | dma_addr_t t2_mapping; | |
837 | void *timers; | |
838 | dma_addr_t timers_mapping; | |
839 | void *qm; | |
840 | dma_addr_t qm_mapping; | |
841 | struct cnic_ops *cnic_ops; | |
842 | void *cnic_data; | |
843 | u32 cnic_tag; | |
844 | struct cnic_eth_dev cnic_eth_dev; | |
845 | struct host_status_block *cnic_sb; | |
846 | dma_addr_t cnic_sb_mapping; | |
847 | #define CNIC_SB_ID(bp) BP_L_ID(bp) | |
848 | struct eth_spe *cnic_kwq; | |
849 | struct eth_spe *cnic_kwq_prod; | |
850 | struct eth_spe *cnic_kwq_cons; | |
851 | struct eth_spe *cnic_kwq_last; | |
852 | u16 cnic_kwq_pending; | |
853 | u16 cnic_spq_pending; | |
854 | struct mutex cnic_mutex; | |
855 | u8 iscsi_mac[6]; | |
856 | #endif | |
857 | ||
ad8d3948 EG |
858 | int dmae_ready; |
859 | /* used to synchronize dmae accesses */ | |
860 | struct mutex dmae_mutex; | |
ad8d3948 | 861 | |
c4ff7cbf EG |
862 | /* used to protect the FW mail box */ |
863 | struct mutex fw_mb_mutex; | |
864 | ||
bb2a0f7a YG |
865 | /* used to synchronize stats collecting */ |
866 | int stats_state; | |
a13773a5 VZ |
867 | |
868 | /* used for synchronization of concurrent threads statistics handling */ | |
869 | spinlock_t stats_lock; | |
870 | ||
bb2a0f7a YG |
871 | /* used by dmae command loader */ |
872 | struct dmae_command stats_dmae; | |
873 | int executer_idx; | |
ad8d3948 | 874 | |
bb2a0f7a | 875 | u16 stats_counter; |
bb2a0f7a YG |
876 | struct bnx2x_eth_stats eth_stats; |
877 | ||
878 | struct z_stream_s *strm; | |
879 | void *gunzip_buf; | |
880 | dma_addr_t gunzip_mapping; | |
881 | int gunzip_outlen; | |
ad8d3948 | 882 | #define FW_BUF_SIZE 0x8000 |
573f2035 EG |
883 | #define GUNZIP_BUF(bp) (bp->gunzip_buf) |
884 | #define GUNZIP_PHYS(bp) (bp->gunzip_mapping) | |
885 | #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen) | |
a2fbb9ea | 886 | |
ab6ad5a4 | 887 | struct raw_op *init_ops; |
94a78b79 | 888 | /* Init blocks offsets inside init_ops */ |
ab6ad5a4 | 889 | u16 *init_ops_offsets; |
94a78b79 | 890 | /* Data blob - has 32 bit granularity */ |
ab6ad5a4 | 891 | u32 *init_data; |
94a78b79 | 892 | /* Zipped PRAM blobs - raw data */ |
ab6ad5a4 EG |
893 | const u8 *tsem_int_table_data; |
894 | const u8 *tsem_pram_data; | |
895 | const u8 *usem_int_table_data; | |
896 | const u8 *usem_pram_data; | |
897 | const u8 *xsem_int_table_data; | |
898 | const u8 *xsem_pram_data; | |
899 | const u8 *csem_int_table_data; | |
900 | const u8 *csem_pram_data; | |
573f2035 EG |
901 | #define INIT_OPS(bp) (bp->init_ops) |
902 | #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets) | |
903 | #define INIT_DATA(bp) (bp->init_data) | |
904 | #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data) | |
905 | #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data) | |
906 | #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data) | |
907 | #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data) | |
908 | #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data) | |
909 | #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data) | |
910 | #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data) | |
911 | #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data) | |
912 | ||
34f24c7f | 913 | char fw_ver[32]; |
ab6ad5a4 | 914 | const struct firmware *firmware; |
a2fbb9ea ET |
915 | }; |
916 | ||
917 | ||
54b9ddaa VZ |
918 | #define BNX2X_MAX_QUEUES(bp) (IS_E1HMF(bp) ? (MAX_CONTEXT/E1HVN_MAX) \ |
919 | : MAX_CONTEXT) | |
920 | #define BNX2X_NUM_QUEUES(bp) (bp->num_queues) | |
921 | #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1) | |
3196a88a | 922 | |
555f6c78 EG |
923 | #define for_each_queue(bp, var) \ |
924 | for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++) | |
3196a88a | 925 | #define for_each_nondefault_queue(bp, var) \ |
54b9ddaa | 926 | for (var = 1; var < BNX2X_NUM_QUEUES(bp); var++) |
3196a88a EG |
927 | |
928 | ||
c18487ee YR |
929 | void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); |
930 | void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, | |
931 | u32 len32); | |
4acac6a5 | 932 | int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port); |
17de50b7 | 933 | int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); |
4acac6a5 | 934 | int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); |
a22f0788 | 935 | u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param); |
573f2035 EG |
936 | void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val); |
937 | void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, | |
938 | u32 addr, u32 len); | |
de0c62db DK |
939 | void bnx2x_calc_fc_adv(struct bnx2x *bp); |
940 | int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, | |
941 | u32 data_hi, u32 data_lo, int common); | |
942 | void bnx2x_update_coalesce(struct bnx2x *bp); | |
a22f0788 | 943 | int bnx2x_get_link_cfg_idx(struct bnx2x *bp); |
34f80b04 EG |
944 | static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, |
945 | int wait) | |
946 | { | |
947 | u32 val; | |
948 | ||
949 | do { | |
950 | val = REG_RD(bp, reg); | |
951 | if (val == expected) | |
952 | break; | |
953 | ms -= wait; | |
954 | msleep(wait); | |
955 | ||
956 | } while (ms > 0); | |
957 | ||
958 | return val; | |
959 | } | |
960 | ||
961 | ||
962 | /* load/unload mode */ | |
963 | #define LOAD_NORMAL 0 | |
964 | #define LOAD_OPEN 1 | |
965 | #define LOAD_DIAG 2 | |
966 | #define UNLOAD_NORMAL 0 | |
967 | #define UNLOAD_CLOSE 1 | |
72fd0718 | 968 | #define UNLOAD_RECOVERY 2 |
34f80b04 | 969 | |
bb2a0f7a | 970 | |
ad8d3948 EG |
971 | /* DMAE command defines */ |
972 | #define DMAE_CMD_SRC_PCI 0 | |
973 | #define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC | |
974 | ||
975 | #define DMAE_CMD_DST_PCI (1 << DMAE_COMMAND_DST_SHIFT) | |
976 | #define DMAE_CMD_DST_GRC (2 << DMAE_COMMAND_DST_SHIFT) | |
977 | ||
978 | #define DMAE_CMD_C_DST_PCI 0 | |
979 | #define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT) | |
980 | ||
981 | #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE | |
982 | ||
983 | #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
984 | #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
985 | #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
986 | #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
987 | ||
988 | #define DMAE_CMD_PORT_0 0 | |
989 | #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT | |
990 | ||
991 | #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET | |
992 | #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET | |
993 | #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT | |
994 | ||
995 | #define DMAE_LEN32_RD_MAX 0x80 | |
02e3c6cb | 996 | #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000) |
ad8d3948 EG |
997 | |
998 | #define DMAE_COMP_VAL 0xe0d0d0ae | |
999 | ||
1000 | #define MAX_DMAE_C_PER_PORT 8 | |
ab6ad5a4 | 1001 | #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ |
ad8d3948 | 1002 | BP_E1HVN(bp)) |
ab6ad5a4 | 1003 | #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ |
ad8d3948 EG |
1004 | E1HVN_MAX) |
1005 | ||
1006 | ||
25047950 ET |
1007 | /* PCIE link and speed */ |
1008 | #define PCICFG_LINK_WIDTH 0x1f00000 | |
1009 | #define PCICFG_LINK_WIDTH_SHIFT 20 | |
1010 | #define PCICFG_LINK_SPEED 0xf0000 | |
1011 | #define PCICFG_LINK_SPEED_SHIFT 16 | |
a2fbb9ea | 1012 | |
bb2a0f7a | 1013 | |
d3d4f495 | 1014 | #define BNX2X_NUM_TESTS 7 |
bb2a0f7a | 1015 | |
b5bf9068 EG |
1016 | #define BNX2X_PHY_LOOPBACK 0 |
1017 | #define BNX2X_MAC_LOOPBACK 1 | |
1018 | #define BNX2X_PHY_LOOPBACK_FAILED 1 | |
1019 | #define BNX2X_MAC_LOOPBACK_FAILED 2 | |
bb2a0f7a YG |
1020 | #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \ |
1021 | BNX2X_PHY_LOOPBACK_FAILED) | |
96fc1784 | 1022 | |
7a9b2557 VZ |
1023 | |
1024 | #define STROM_ASSERT_ARRAY_SIZE 50 | |
1025 | ||
96fc1784 | 1026 | |
34f80b04 | 1027 | /* must be used on a CID before placing it on a HW ring */ |
ab6ad5a4 EG |
1028 | #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \ |
1029 | (BP_E1HVN(bp) << 17) | (x)) | |
7a9b2557 VZ |
1030 | |
1031 | #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) | |
1032 | #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) | |
1033 | ||
1034 | ||
7d323bfd | 1035 | #define BNX2X_BTR 1 |
7a9b2557 | 1036 | #define MAX_SPQ_PENDING 8 |
a2fbb9ea | 1037 | |
a2fbb9ea | 1038 | |
34f80b04 EG |
1039 | /* CMNG constants |
1040 | derived from lab experiments, and not from system spec calculations !!! */ | |
1041 | #define DEF_MIN_RATE 100 | |
1042 | /* resolution of the rate shaping timer - 100 usec */ | |
1043 | #define RS_PERIODIC_TIMEOUT_USEC 100 | |
1044 | /* resolution of fairness algorithm in usecs - | |
33471629 | 1045 | coefficient for calculating the actual t fair */ |
34f80b04 EG |
1046 | #define T_FAIR_COEF 10000000 |
1047 | /* number of bytes in single QM arbitration cycle - | |
33471629 | 1048 | coefficient for calculating the fairness timer */ |
34f80b04 EG |
1049 | #define QM_ARB_BYTES 40000 |
1050 | #define FAIR_MEM 2 | |
1051 | ||
1052 | ||
1053 | #define ATTN_NIG_FOR_FUNC (1L << 8) | |
1054 | #define ATTN_SW_TIMER_4_FUNC (1L << 9) | |
1055 | #define GPIO_2_FUNC (1L << 10) | |
1056 | #define GPIO_3_FUNC (1L << 11) | |
1057 | #define GPIO_4_FUNC (1L << 12) | |
1058 | #define ATTN_GENERAL_ATTN_1 (1L << 13) | |
1059 | #define ATTN_GENERAL_ATTN_2 (1L << 14) | |
1060 | #define ATTN_GENERAL_ATTN_3 (1L << 15) | |
1061 | #define ATTN_GENERAL_ATTN_4 (1L << 13) | |
1062 | #define ATTN_GENERAL_ATTN_5 (1L << 14) | |
1063 | #define ATTN_GENERAL_ATTN_6 (1L << 15) | |
1064 | ||
1065 | #define ATTN_HARD_WIRED_MASK 0xff00 | |
1066 | #define ATTENTION_ID 4 | |
a2fbb9ea ET |
1067 | |
1068 | ||
34f80b04 EG |
1069 | /* stuff added to make the code fit 80Col */ |
1070 | ||
1071 | #define BNX2X_PMF_LINK_ASSERT \ | |
1072 | GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp)) | |
1073 | ||
a2fbb9ea ET |
1074 | #define BNX2X_MC_ASSERT_BITS \ |
1075 | (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ | |
1076 | GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ | |
1077 | GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ | |
1078 | GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) | |
1079 | ||
1080 | #define BNX2X_MCP_ASSERT \ | |
1081 | GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) | |
1082 | ||
34f80b04 EG |
1083 | #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) |
1084 | #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ | |
1085 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ | |
1086 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ | |
1087 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ | |
1088 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ | |
1089 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) | |
1090 | ||
a2fbb9ea ET |
1091 | #define HW_INTERRUT_ASSERT_SET_0 \ |
1092 | (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ | |
1093 | AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ | |
1094 | AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ | |
1095 | AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT) | |
34f80b04 | 1096 | #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ |
a2fbb9ea ET |
1097 | AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ |
1098 | AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ | |
1099 | AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ | |
1100 | AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR) | |
1101 | #define HW_INTERRUT_ASSERT_SET_1 \ | |
1102 | (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \ | |
1103 | AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \ | |
1104 | AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \ | |
1105 | AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \ | |
1106 | AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \ | |
1107 | AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \ | |
1108 | AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \ | |
1109 | AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \ | |
1110 | AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ | |
1111 | AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ | |
1112 | AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) | |
34f80b04 | 1113 | #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\ |
a2fbb9ea ET |
1114 | AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ |
1115 | AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ | |
1116 | AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ | |
ab6ad5a4 EG |
1117 | AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ |
1118 | AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ | |
a2fbb9ea ET |
1119 | AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ |
1120 | AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ | |
1121 | AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ | |
1122 | AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \ | |
1123 | AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR) | |
1124 | #define HW_INTERRUT_ASSERT_SET_2 \ | |
1125 | (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \ | |
1126 | AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \ | |
1127 | AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ | |
1128 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ | |
1129 | AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) | |
34f80b04 | 1130 | #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ |
a2fbb9ea ET |
1131 | AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ |
1132 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ | |
1133 | AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ | |
1134 | AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \ | |
1135 | AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ | |
1136 | AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) | |
1137 | ||
72fd0718 VZ |
1138 | #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ |
1139 | AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ | |
1140 | AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \ | |
1141 | AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) | |
a2fbb9ea | 1142 | |
c68ed255 | 1143 | #define RSS_FLAGS(bp) \ |
34f80b04 EG |
1144 | (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \ |
1145 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \ | |
1146 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \ | |
1147 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \ | |
555f6c78 EG |
1148 | (bp->multi_mode << \ |
1149 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT)) | |
34f80b04 | 1150 | #define MULTI_MASK 0x7f |
a2fbb9ea ET |
1151 | |
1152 | ||
34f80b04 EG |
1153 | #define DEF_USB_FUNC_OFF (2 + 2*HC_USTORM_DEF_SB_NUM_INDICES) |
1154 | #define DEF_CSB_FUNC_OFF (2 + 2*HC_CSTORM_DEF_SB_NUM_INDICES) | |
1155 | #define DEF_XSB_FUNC_OFF (2 + 2*HC_XSTORM_DEF_SB_NUM_INDICES) | |
1156 | #define DEF_TSB_FUNC_OFF (2 + 2*HC_TSTORM_DEF_SB_NUM_INDICES) | |
a2fbb9ea | 1157 | |
34f80b04 | 1158 | #define C_DEF_SB_SP_INDEX HC_INDEX_DEF_C_ETH_SLOW_PATH |
a2fbb9ea ET |
1159 | |
1160 | #define BNX2X_SP_DSB_INDEX \ | |
34f80b04 | 1161 | (&bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX]) |
a2fbb9ea ET |
1162 | |
1163 | ||
1164 | #define CAM_IS_INVALID(x) \ | |
1165 | (x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE) | |
1166 | ||
1167 | #define CAM_INVALIDATE(x) \ | |
34f80b04 EG |
1168 | (x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE) |
1169 | ||
1170 | ||
1171 | /* Number of u32 elements in MC hash array */ | |
1172 | #define MC_HASH_SIZE 8 | |
1173 | #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \ | |
1174 | TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4) | |
a2fbb9ea ET |
1175 | |
1176 | ||
34f80b04 EG |
1177 | #ifndef PXP2_REG_PXP2_INT_STS |
1178 | #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0 | |
1179 | #endif | |
1180 | ||
34f24c7f VZ |
1181 | #define BNX2X_VPD_LEN 128 |
1182 | #define VENDOR_ID_LEN 4 | |
1183 | ||
b0efbb99 DK |
1184 | #ifdef BNX2X_MAIN |
1185 | #define BNX2X_EXTERN | |
1186 | #else | |
1187 | #define BNX2X_EXTERN extern | |
1188 | #endif | |
1189 | ||
1190 | BNX2X_EXTERN int load_count[3]; /* 0-common, 1-port0, 2-port1 */ | |
1191 | ||
a2fbb9ea ET |
1192 | /* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */ |
1193 | ||
de0c62db DK |
1194 | extern void bnx2x_set_ethtool_ops(struct net_device *netdev); |
1195 | ||
6c719d00 DK |
1196 | void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx); |
1197 | ||
a2fbb9ea | 1198 | #endif /* bnx2x.h */ |