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Commit | Line | Data |
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56ca9040 | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/imxmmc.c - Motorola i.MX MMCI driver |
56ca9040 PP |
3 | * |
4 | * Copyright (C) 2004 Sascha Hauer, Pengutronix <sascha@saschahauer.de> | |
5 | * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com> | |
6 | * | |
7 | * derived from pxamci.c by Russell King | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
56ca9040 | 13 | */ |
56ca9040 | 14 | |
56ca9040 PP |
15 | #include <linux/module.h> |
16 | #include <linux/init.h> | |
17 | #include <linux/ioport.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/blkdev.h> | |
21 | #include <linux/dma-mapping.h> | |
22 | #include <linux/mmc/host.h> | |
23 | #include <linux/mmc/card.h> | |
56ca9040 | 24 | #include <linux/delay.h> |
38a41fdf | 25 | #include <linux/clk.h> |
4b7c0e4c | 26 | #include <linux/io.h> |
56ca9040 PP |
27 | |
28 | #include <asm/dma.h> | |
56ca9040 PP |
29 | #include <asm/irq.h> |
30 | #include <asm/sizes.h> | |
a09e64fb RK |
31 | #include <mach/mmc.h> |
32 | #include <mach/imx-dma.h> | |
56ca9040 PP |
33 | |
34 | #include "imxmmc.h" | |
35 | ||
36 | #define DRIVER_NAME "imx-mmc" | |
37 | ||
38 | #define IMXMCI_INT_MASK_DEFAULT (INT_MASK_BUF_READY | INT_MASK_DATA_TRAN | \ | |
4b7c0e4c MKB |
39 | INT_MASK_WRITE_OP_DONE | INT_MASK_END_CMD_RES | \ |
40 | INT_MASK_AUTO_CARD_DETECT | INT_MASK_DAT0_EN | INT_MASK_SDIO) | |
56ca9040 PP |
41 | |
42 | struct imxmci_host { | |
43 | struct mmc_host *mmc; | |
44 | spinlock_t lock; | |
45 | struct resource *res; | |
df25f9da | 46 | void __iomem *base; |
56ca9040 PP |
47 | int irq; |
48 | imx_dmach_t dma; | |
56ca9040 PP |
49 | volatile unsigned int imask; |
50 | unsigned int power_mode; | |
51 | unsigned int present; | |
52 | struct imxmmc_platform_data *pdata; | |
53 | ||
54 | struct mmc_request *req; | |
55 | struct mmc_command *cmd; | |
56 | struct mmc_data *data; | |
57 | ||
58 | struct timer_list timer; | |
59 | struct tasklet_struct tasklet; | |
60 | unsigned int status_reg; | |
61 | unsigned long pending_events; | |
4b7c0e4c | 62 | /* Next two fields are there for CPU driven transfers to overcome SDHC deficiencies */ |
56ca9040 PP |
63 | u16 *data_ptr; |
64 | unsigned int data_cnt; | |
65 | atomic_t stuck_timeout; | |
66 | ||
67 | unsigned int dma_nents; | |
68 | unsigned int dma_size; | |
69 | unsigned int dma_dir; | |
70 | int dma_allocated; | |
71 | ||
72 | unsigned char actual_bus_width; | |
148f93d5 PP |
73 | |
74 | int prev_cmd_code; | |
38a41fdf SH |
75 | |
76 | struct clk *clk; | |
56ca9040 PP |
77 | }; |
78 | ||
79 | #define IMXMCI_PEND_IRQ_b 0 | |
80 | #define IMXMCI_PEND_DMA_END_b 1 | |
81 | #define IMXMCI_PEND_DMA_ERR_b 2 | |
82 | #define IMXMCI_PEND_WAIT_RESP_b 3 | |
83 | #define IMXMCI_PEND_DMA_DATA_b 4 | |
84 | #define IMXMCI_PEND_CPU_DATA_b 5 | |
85 | #define IMXMCI_PEND_CARD_XCHG_b 6 | |
86 | #define IMXMCI_PEND_SET_INIT_b 7 | |
81d38428 | 87 | #define IMXMCI_PEND_STARTED_b 8 |
56ca9040 PP |
88 | |
89 | #define IMXMCI_PEND_IRQ_m (1 << IMXMCI_PEND_IRQ_b) | |
90 | #define IMXMCI_PEND_DMA_END_m (1 << IMXMCI_PEND_DMA_END_b) | |
91 | #define IMXMCI_PEND_DMA_ERR_m (1 << IMXMCI_PEND_DMA_ERR_b) | |
92 | #define IMXMCI_PEND_WAIT_RESP_m (1 << IMXMCI_PEND_WAIT_RESP_b) | |
93 | #define IMXMCI_PEND_DMA_DATA_m (1 << IMXMCI_PEND_DMA_DATA_b) | |
94 | #define IMXMCI_PEND_CPU_DATA_m (1 << IMXMCI_PEND_CPU_DATA_b) | |
95 | #define IMXMCI_PEND_CARD_XCHG_m (1 << IMXMCI_PEND_CARD_XCHG_b) | |
96 | #define IMXMCI_PEND_SET_INIT_m (1 << IMXMCI_PEND_SET_INIT_b) | |
81d38428 | 97 | #define IMXMCI_PEND_STARTED_m (1 << IMXMCI_PEND_STARTED_b) |
56ca9040 PP |
98 | |
99 | static void imxmci_stop_clock(struct imxmci_host *host) | |
100 | { | |
101 | int i = 0; | |
df25f9da MKB |
102 | u16 reg; |
103 | ||
104 | reg = readw(host->base + MMC_REG_STR_STP_CLK); | |
105 | writew(reg & ~STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK); | |
4b7c0e4c | 106 | while (i < 0x1000) { |
df25f9da MKB |
107 | if (!(i & 0x7f)) { |
108 | reg = readw(host->base + MMC_REG_STR_STP_CLK); | |
109 | writew(reg | STR_STP_CLK_STOP_CLK, | |
110 | host->base + MMC_REG_STR_STP_CLK); | |
111 | } | |
56ca9040 | 112 | |
df25f9da MKB |
113 | reg = readw(host->base + MMC_REG_STATUS); |
114 | if (!(reg & STATUS_CARD_BUS_CLK_RUN)) { | |
56ca9040 | 115 | /* Check twice before cut */ |
df25f9da MKB |
116 | reg = readw(host->base + MMC_REG_STATUS); |
117 | if (!(reg & STATUS_CARD_BUS_CLK_RUN)) | |
56ca9040 PP |
118 | return; |
119 | } | |
120 | ||
121 | i++; | |
122 | } | |
123 | dev_dbg(mmc_dev(host->mmc), "imxmci_stop_clock blocked, no luck\n"); | |
124 | } | |
125 | ||
81d38428 | 126 | static int imxmci_start_clock(struct imxmci_host *host) |
56ca9040 | 127 | { |
81d38428 PP |
128 | unsigned int trials = 0; |
129 | unsigned int delay_limit = 128; | |
130 | unsigned long flags; | |
df25f9da | 131 | u16 reg; |
81d38428 | 132 | |
df25f9da MKB |
133 | reg = readw(host->base + MMC_REG_STR_STP_CLK); |
134 | writew(reg & ~STR_STP_CLK_STOP_CLK, host->base + MMC_REG_STR_STP_CLK); | |
56ca9040 | 135 | |
81d38428 PP |
136 | clear_bit(IMXMCI_PEND_STARTED_b, &host->pending_events); |
137 | ||
138 | /* | |
139 | * Command start of the clock, this usually succeeds in less | |
140 | * then 6 delay loops, but during card detection (low clockrate) | |
141 | * it takes up to 5000 delay loops and sometimes fails for the first time | |
142 | */ | |
df25f9da MKB |
143 | reg = readw(host->base + MMC_REG_STR_STP_CLK); |
144 | writew(reg | STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK); | |
81d38428 PP |
145 | |
146 | do { | |
147 | unsigned int delay = delay_limit; | |
148 | ||
4b7c0e4c | 149 | while (delay--) { |
df25f9da | 150 | reg = readw(host->base + MMC_REG_STATUS); |
7c5367f2 | 151 | if (reg & STATUS_CARD_BUS_CLK_RUN) { |
81d38428 | 152 | /* Check twice before cut */ |
df25f9da MKB |
153 | reg = readw(host->base + MMC_REG_STATUS); |
154 | if (reg & STATUS_CARD_BUS_CLK_RUN) | |
81d38428 | 155 | return 0; |
7c5367f2 | 156 | } |
81d38428 | 157 | |
4b7c0e4c | 158 | if (test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events)) |
81d38428 | 159 | return 0; |
56ca9040 PP |
160 | } |
161 | ||
81d38428 PP |
162 | local_irq_save(flags); |
163 | /* | |
164 | * Ensure, that request is not doubled under all possible circumstances. | |
165 | * It is possible, that cock running state is missed, because some other | |
166 | * IRQ or schedule delays this function execution and the clocks has | |
167 | * been already stopped by other means (response processing, SDHC HW) | |
168 | */ | |
df25f9da MKB |
169 | if (!test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events)) { |
170 | reg = readw(host->base + MMC_REG_STR_STP_CLK); | |
171 | writew(reg | STR_STP_CLK_START_CLK, | |
172 | host->base + MMC_REG_STR_STP_CLK); | |
173 | } | |
81d38428 PP |
174 | local_irq_restore(flags); |
175 | ||
4b7c0e4c | 176 | } while (++trials < 256); |
81d38428 PP |
177 | |
178 | dev_err(mmc_dev(host->mmc), "imxmci_start_clock blocked, no luck\n"); | |
179 | ||
180 | return -1; | |
56ca9040 PP |
181 | } |
182 | ||
df25f9da | 183 | static void imxmci_softreset(struct imxmci_host *host) |
56ca9040 | 184 | { |
df25f9da MKB |
185 | int i; |
186 | ||
56ca9040 | 187 | /* reset sequence */ |
df25f9da MKB |
188 | writew(0x08, host->base + MMC_REG_STR_STP_CLK); |
189 | writew(0x0D, host->base + MMC_REG_STR_STP_CLK); | |
190 | ||
191 | for (i = 0; i < 8; i++) | |
192 | writew(0x05, host->base + MMC_REG_STR_STP_CLK); | |
193 | ||
194 | writew(0xff, host->base + MMC_REG_RES_TO); | |
195 | writew(512, host->base + MMC_REG_BLK_LEN); | |
196 | writew(1, host->base + MMC_REG_NOB); | |
56ca9040 PP |
197 | } |
198 | ||
199 | static int imxmci_busy_wait_for_status(struct imxmci_host *host, | |
4b7c0e4c MKB |
200 | unsigned int *pstat, unsigned int stat_mask, |
201 | int timeout, const char *where) | |
56ca9040 | 202 | { |
4b7c0e4c MKB |
203 | int loops = 0; |
204 | ||
205 | while (!(*pstat & stat_mask)) { | |
206 | loops += 2; | |
207 | if (loops >= timeout) { | |
56ca9040 PP |
208 | dev_dbg(mmc_dev(host->mmc), "busy wait timeout in %s, STATUS = 0x%x (0x%x)\n", |
209 | where, *pstat, stat_mask); | |
210 | return -1; | |
211 | } | |
212 | udelay(2); | |
df25f9da | 213 | *pstat |= readw(host->base + MMC_REG_STATUS); |
56ca9040 | 214 | } |
4b7c0e4c | 215 | if (!loops) |
56ca9040 PP |
216 | return 0; |
217 | ||
2c171bf1 | 218 | /* The busy-wait is expected there for clock <8MHz due to SDHC hardware flaws */ |
4b7c0e4c | 219 | if (!(stat_mask & STATUS_END_CMD_RESP) || (host->mmc->ios.clock >= 8000000)) |
2c171bf1 | 220 | dev_info(mmc_dev(host->mmc), "busy wait for %d usec in %s, STATUS = 0x%x (0x%x)\n", |
4b7c0e4c | 221 | loops, where, *pstat, stat_mask); |
56ca9040 PP |
222 | return loops; |
223 | } | |
224 | ||
225 | static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data) | |
226 | { | |
227 | unsigned int nob = data->blocks; | |
a3fd4a1b | 228 | unsigned int blksz = data->blksz; |
56ca9040 PP |
229 | unsigned int datasz = nob * blksz; |
230 | int i; | |
231 | ||
232 | if (data->flags & MMC_DATA_STREAM) | |
233 | nob = 0xffff; | |
234 | ||
235 | host->data = data; | |
236 | data->bytes_xfered = 0; | |
237 | ||
df25f9da MKB |
238 | writew(nob, host->base + MMC_REG_NOB); |
239 | writew(blksz, host->base + MMC_REG_BLK_LEN); | |
56ca9040 PP |
240 | |
241 | /* | |
242 | * DMA cannot be used for small block sizes, we have to use CPU driven transfers otherwise. | |
243 | * We are in big troubles for non-512 byte transfers according to note in the paragraph | |
244 | * 20.6.7 of User Manual anyway, but we need to be able to transfer SCR at least. | |
245 | * The situation is even more complex in reality. The SDHC in not able to handle wll | |
246 | * partial FIFO fills and reads. The length has to be rounded up to burst size multiple. | |
247 | * This is required for SCR read at least. | |
248 | */ | |
148f93d5 | 249 | if (datasz < 512) { |
56ca9040 PP |
250 | host->dma_size = datasz; |
251 | if (data->flags & MMC_DATA_READ) { | |
252 | host->dma_dir = DMA_FROM_DEVICE; | |
253 | ||
254 | /* Hack to enable read SCR */ | |
df25f9da MKB |
255 | writew(1, host->base + MMC_REG_NOB); |
256 | writew(512, host->base + MMC_REG_BLK_LEN); | |
56ca9040 PP |
257 | } else { |
258 | host->dma_dir = DMA_TO_DEVICE; | |
259 | } | |
260 | ||
261 | /* Convert back to virtual address */ | |
4b7c0e4c | 262 | host->data_ptr = (u16 *)sg_virt(data->sg); |
56ca9040 PP |
263 | host->data_cnt = 0; |
264 | ||
265 | clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events); | |
266 | set_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events); | |
267 | ||
268 | return; | |
269 | } | |
270 | ||
271 | if (data->flags & MMC_DATA_READ) { | |
272 | host->dma_dir = DMA_FROM_DEVICE; | |
273 | host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg, | |
4b7c0e4c | 274 | data->sg_len, host->dma_dir); |
56ca9040 PP |
275 | |
276 | imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz, | |
df25f9da MKB |
277 | host->res->start + MMC_REG_BUFFER_ACCESS, |
278 | DMA_MODE_READ); | |
56ca9040 PP |
279 | |
280 | /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_READ, IMX_DMA_WIDTH_16, CCR_REN);*/ | |
281 | CCR(host->dma) = CCR_DMOD_LINEAR | CCR_DSIZ_32 | CCR_SMOD_FIFO | CCR_SSIZ_16 | CCR_REN; | |
282 | } else { | |
283 | host->dma_dir = DMA_TO_DEVICE; | |
284 | ||
285 | host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg, | |
4b7c0e4c | 286 | data->sg_len, host->dma_dir); |
56ca9040 PP |
287 | |
288 | imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz, | |
df25f9da MKB |
289 | host->res->start + MMC_REG_BUFFER_ACCESS, |
290 | DMA_MODE_WRITE); | |
56ca9040 PP |
291 | |
292 | /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_WRITE, IMX_DMA_WIDTH_16, CCR_REN);*/ | |
293 | CCR(host->dma) = CCR_SMOD_LINEAR | CCR_SSIZ_32 | CCR_DMOD_FIFO | CCR_DSIZ_16 | CCR_REN; | |
294 | } | |
295 | ||
296 | #if 1 /* This code is there only for consistency checking and can be disabled in future */ | |
297 | host->dma_size = 0; | |
4b7c0e4c MKB |
298 | for (i = 0; i < host->dma_nents; i++) |
299 | host->dma_size += data->sg[i].length; | |
56ca9040 PP |
300 | |
301 | if (datasz > host->dma_size) { | |
302 | dev_err(mmc_dev(host->mmc), "imxmci_setup_data datasz 0x%x > 0x%x dm_size\n", | |
4b7c0e4c | 303 | datasz, host->dma_size); |
56ca9040 PP |
304 | } |
305 | #endif | |
306 | ||
307 | host->dma_size = datasz; | |
308 | ||
309 | wmb(); | |
310 | ||
56ca9040 PP |
311 | set_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events); |
312 | clear_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events); | |
313 | ||
314 | /* start DMA engine for read, write is delayed after initial response */ | |
4b7c0e4c | 315 | if (host->dma_dir == DMA_FROM_DEVICE) |
56ca9040 | 316 | imx_dma_enable(host->dma); |
56ca9040 PP |
317 | } |
318 | ||
319 | static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd, unsigned int cmdat) | |
320 | { | |
321 | unsigned long flags; | |
322 | u32 imask; | |
323 | ||
324 | WARN_ON(host->cmd != NULL); | |
325 | host->cmd = cmd; | |
326 | ||
2c171bf1 PP |
327 | /* Ensure, that clock are stopped else command programming and start fails */ |
328 | imxmci_stop_clock(host); | |
329 | ||
56ca9040 PP |
330 | if (cmd->flags & MMC_RSP_BUSY) |
331 | cmdat |= CMD_DAT_CONT_BUSY; | |
332 | ||
333 | switch (mmc_resp_type(cmd)) { | |
334 | case MMC_RSP_R1: /* short CRC, OPCODE */ | |
335 | case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */ | |
336 | cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R1; | |
337 | break; | |
338 | case MMC_RSP_R2: /* long 136 bit + CRC */ | |
339 | cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R2; | |
340 | break; | |
341 | case MMC_RSP_R3: /* short */ | |
342 | cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R3; | |
343 | break; | |
56ca9040 PP |
344 | default: |
345 | break; | |
346 | } | |
347 | ||
4b7c0e4c | 348 | if (test_and_clear_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events)) |
56ca9040 PP |
349 | cmdat |= CMD_DAT_CONT_INIT; /* This command needs init */ |
350 | ||
4b7c0e4c | 351 | if (host->actual_bus_width == MMC_BUS_WIDTH_4) |
56ca9040 PP |
352 | cmdat |= CMD_DAT_CONT_BUS_WIDTH_4; |
353 | ||
df25f9da MKB |
354 | writew(cmd->opcode, host->base + MMC_REG_CMD); |
355 | writew(cmd->arg >> 16, host->base + MMC_REG_ARGH); | |
356 | writew(cmd->arg & 0xffff, host->base + MMC_REG_ARGL); | |
357 | writew(cmdat, host->base + MMC_REG_CMD_DAT_CONT); | |
56ca9040 PP |
358 | |
359 | atomic_set(&host->stuck_timeout, 0); | |
360 | set_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events); | |
361 | ||
362 | ||
363 | imask = IMXMCI_INT_MASK_DEFAULT; | |
364 | imask &= ~INT_MASK_END_CMD_RES; | |
4b7c0e4c MKB |
365 | if (cmdat & CMD_DAT_CONT_DATA_ENABLE) { |
366 | /* imask &= ~INT_MASK_BUF_READY; */ | |
56ca9040 | 367 | imask &= ~INT_MASK_DATA_TRAN; |
4b7c0e4c | 368 | if (cmdat & CMD_DAT_CONT_WRITE) |
56ca9040 | 369 | imask &= ~INT_MASK_WRITE_OP_DONE; |
4b7c0e4c | 370 | if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) |
56ca9040 PP |
371 | imask &= ~INT_MASK_BUF_READY; |
372 | } | |
373 | ||
374 | spin_lock_irqsave(&host->lock, flags); | |
375 | host->imask = imask; | |
df25f9da | 376 | writew(host->imask, host->base + MMC_REG_INT_MASK); |
56ca9040 PP |
377 | spin_unlock_irqrestore(&host->lock, flags); |
378 | ||
379 | dev_dbg(mmc_dev(host->mmc), "CMD%02d (0x%02x) mask set to 0x%04x\n", | |
380 | cmd->opcode, cmd->opcode, imask); | |
381 | ||
382 | imxmci_start_clock(host); | |
383 | } | |
384 | ||
385 | static void imxmci_finish_request(struct imxmci_host *host, struct mmc_request *req) | |
386 | { | |
387 | unsigned long flags; | |
388 | ||
389 | spin_lock_irqsave(&host->lock, flags); | |
390 | ||
391 | host->pending_events &= ~(IMXMCI_PEND_WAIT_RESP_m | IMXMCI_PEND_DMA_END_m | | |
4b7c0e4c | 392 | IMXMCI_PEND_DMA_DATA_m | IMXMCI_PEND_CPU_DATA_m); |
56ca9040 PP |
393 | |
394 | host->imask = IMXMCI_INT_MASK_DEFAULT; | |
df25f9da | 395 | writew(host->imask, host->base + MMC_REG_INT_MASK); |
56ca9040 PP |
396 | |
397 | spin_unlock_irqrestore(&host->lock, flags); | |
398 | ||
4b7c0e4c | 399 | if (req && req->cmd) |
148f93d5 PP |
400 | host->prev_cmd_code = req->cmd->opcode; |
401 | ||
56ca9040 PP |
402 | host->req = NULL; |
403 | host->cmd = NULL; | |
404 | host->data = NULL; | |
405 | mmc_request_done(host->mmc, req); | |
406 | } | |
407 | ||
408 | static int imxmci_finish_data(struct imxmci_host *host, unsigned int stat) | |
409 | { | |
410 | struct mmc_data *data = host->data; | |
411 | int data_error; | |
412 | ||
4b7c0e4c | 413 | if (test_and_clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) { |
56ca9040 PP |
414 | imx_dma_disable(host->dma); |
415 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_nents, | |
416 | host->dma_dir); | |
417 | } | |
418 | ||
4b7c0e4c MKB |
419 | if (stat & STATUS_ERR_MASK) { |
420 | dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n", stat); | |
421 | if (stat & (STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR)) | |
17b0429d | 422 | data->error = -EILSEQ; |
4b7c0e4c | 423 | else if (stat & STATUS_TIME_OUT_READ) |
17b0429d | 424 | data->error = -ETIMEDOUT; |
56ca9040 | 425 | else |
17b0429d | 426 | data->error = -EIO; |
56ca9040 PP |
427 | } else { |
428 | data->bytes_xfered = host->dma_size; | |
429 | } | |
430 | ||
431 | data_error = data->error; | |
432 | ||
433 | host->data = NULL; | |
434 | ||
435 | return data_error; | |
436 | } | |
437 | ||
438 | static int imxmci_cmd_done(struct imxmci_host *host, unsigned int stat) | |
439 | { | |
440 | struct mmc_command *cmd = host->cmd; | |
441 | int i; | |
4b7c0e4c | 442 | u32 a, b, c; |
56ca9040 PP |
443 | struct mmc_data *data = host->data; |
444 | ||
445 | if (!cmd) | |
446 | return 0; | |
447 | ||
448 | host->cmd = NULL; | |
449 | ||
450 | if (stat & STATUS_TIME_OUT_RESP) { | |
451 | dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n"); | |
17b0429d | 452 | cmd->error = -ETIMEDOUT; |
56ca9040 PP |
453 | } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) { |
454 | dev_dbg(mmc_dev(host->mmc), "cmd crc error\n"); | |
17b0429d | 455 | cmd->error = -EILSEQ; |
56ca9040 PP |
456 | } |
457 | ||
4b7c0e4c MKB |
458 | if (cmd->flags & MMC_RSP_PRESENT) { |
459 | if (cmd->flags & MMC_RSP_136) { | |
56ca9040 | 460 | for (i = 0; i < 4; i++) { |
df25f9da MKB |
461 | a = readw(host->base + MMC_REG_RES_FIFO); |
462 | b = readw(host->base + MMC_REG_RES_FIFO); | |
463 | cmd->resp[i] = a << 16 | b; | |
56ca9040 PP |
464 | } |
465 | } else { | |
df25f9da MKB |
466 | a = readw(host->base + MMC_REG_RES_FIFO); |
467 | b = readw(host->base + MMC_REG_RES_FIFO); | |
468 | c = readw(host->base + MMC_REG_RES_FIFO); | |
4b7c0e4c | 469 | cmd->resp[0] = a << 24 | b << 8 | c >> 8; |
56ca9040 PP |
470 | } |
471 | } | |
472 | ||
473 | dev_dbg(mmc_dev(host->mmc), "RESP 0x%08x, 0x%08x, 0x%08x, 0x%08x, error %d\n", | |
474 | cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3], cmd->error); | |
475 | ||
17b0429d | 476 | if (data && !cmd->error && !(stat & STATUS_ERR_MASK)) { |
56ca9040 PP |
477 | if (host->req->data->flags & MMC_DATA_WRITE) { |
478 | ||
479 | /* Wait for FIFO to be empty before starting DMA write */ | |
480 | ||
df25f9da | 481 | stat = readw(host->base + MMC_REG_STATUS); |
4b7c0e4c MKB |
482 | if (imxmci_busy_wait_for_status(host, &stat, |
483 | STATUS_APPL_BUFF_FE, | |
484 | 40, "imxmci_cmd_done DMA WR") < 0) { | |
17b0429d | 485 | cmd->error = -EIO; |
56ca9040 | 486 | imxmci_finish_data(host, stat); |
4b7c0e4c | 487 | if (host->req) |
56ca9040 PP |
488 | imxmci_finish_request(host, host->req); |
489 | dev_warn(mmc_dev(host->mmc), "STATUS = 0x%04x\n", | |
4b7c0e4c | 490 | stat); |
56ca9040 PP |
491 | return 0; |
492 | } | |
493 | ||
4b7c0e4c | 494 | if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) |
56ca9040 | 495 | imx_dma_enable(host->dma); |
56ca9040 PP |
496 | } |
497 | } else { | |
498 | struct mmc_request *req; | |
499 | imxmci_stop_clock(host); | |
500 | req = host->req; | |
501 | ||
4b7c0e4c | 502 | if (data) |
56ca9040 PP |
503 | imxmci_finish_data(host, stat); |
504 | ||
4b7c0e4c | 505 | if (req) |
56ca9040 | 506 | imxmci_finish_request(host, req); |
4b7c0e4c | 507 | else |
56ca9040 | 508 | dev_warn(mmc_dev(host->mmc), "imxmci_cmd_done: no request to finish\n"); |
56ca9040 PP |
509 | } |
510 | ||
511 | return 1; | |
512 | } | |
513 | ||
514 | static int imxmci_data_done(struct imxmci_host *host, unsigned int stat) | |
515 | { | |
516 | struct mmc_data *data = host->data; | |
517 | int data_error; | |
518 | ||
519 | if (!data) | |
520 | return 0; | |
521 | ||
522 | data_error = imxmci_finish_data(host, stat); | |
523 | ||
58741e8b | 524 | if (host->req->stop) { |
56ca9040 PP |
525 | imxmci_stop_clock(host); |
526 | imxmci_start_cmd(host, host->req->stop, 0); | |
527 | } else { | |
528 | struct mmc_request *req; | |
529 | req = host->req; | |
4b7c0e4c | 530 | if (req) |
56ca9040 | 531 | imxmci_finish_request(host, req); |
4b7c0e4c | 532 | else |
56ca9040 | 533 | dev_warn(mmc_dev(host->mmc), "imxmci_data_done: no request to finish\n"); |
56ca9040 PP |
534 | } |
535 | ||
536 | return 1; | |
537 | } | |
538 | ||
539 | static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat) | |
540 | { | |
541 | int i; | |
542 | int burst_len; | |
56ca9040 PP |
543 | int trans_done = 0; |
544 | unsigned int stat = *pstat; | |
545 | ||
4b7c0e4c | 546 | if (host->actual_bus_width != MMC_BUS_WIDTH_4) |
56ca9040 PP |
547 | burst_len = 16; |
548 | else | |
549 | burst_len = 64; | |
550 | ||
551 | /* This is unfortunately required */ | |
552 | dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data running STATUS = 0x%x\n", | |
553 | stat); | |
554 | ||
148f93d5 PP |
555 | udelay(20); /* required for clocks < 8MHz*/ |
556 | ||
4b7c0e4c | 557 | if (host->dma_dir == DMA_FROM_DEVICE) { |
56ca9040 | 558 | imxmci_busy_wait_for_status(host, &stat, |
4b7c0e4c MKB |
559 | STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE | |
560 | STATUS_TIME_OUT_READ, | |
561 | 50, "imxmci_cpu_driven_data read"); | |
56ca9040 | 562 | |
4b7c0e4c MKB |
563 | while ((stat & (STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE)) && |
564 | !(stat & STATUS_TIME_OUT_READ) && | |
565 | (host->data_cnt < 512)) { | |
148f93d5 PP |
566 | |
567 | udelay(20); /* required for clocks < 8MHz*/ | |
56ca9040 | 568 | |
4b7c0e4c | 569 | for (i = burst_len; i >= 2 ; i -= 2) { |
148f93d5 | 570 | u16 data; |
df25f9da | 571 | data = readw(host->base + MMC_REG_BUFFER_ACCESS); |
148f93d5 | 572 | udelay(10); /* required for clocks < 8MHz*/ |
4b7c0e4c | 573 | if (host->data_cnt+2 <= host->dma_size) { |
148f93d5 PP |
574 | *(host->data_ptr++) = data; |
575 | } else { | |
4b7c0e4c MKB |
576 | if (host->data_cnt < host->dma_size) |
577 | *(u8 *)(host->data_ptr) = data; | |
148f93d5 PP |
578 | } |
579 | host->data_cnt += 2; | |
56ca9040 PP |
580 | } |
581 | ||
df25f9da | 582 | stat = readw(host->base + MMC_REG_STATUS); |
56ca9040 | 583 | |
148f93d5 PP |
584 | dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read %d burst %d STATUS = 0x%x\n", |
585 | host->data_cnt, burst_len, stat); | |
56ca9040 | 586 | } |
148f93d5 | 587 | |
4b7c0e4c | 588 | if ((stat & STATUS_DATA_TRANS_DONE) && (host->data_cnt >= 512)) |
148f93d5 PP |
589 | trans_done = 1; |
590 | ||
4b7c0e4c | 591 | if (host->dma_size & 0x1ff) |
148f93d5 PP |
592 | stat &= ~STATUS_CRC_READ_ERR; |
593 | ||
4b7c0e4c | 594 | if (stat & STATUS_TIME_OUT_READ) { |
2cb3320b PP |
595 | dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read timeout STATUS = 0x%x\n", |
596 | stat); | |
597 | trans_done = -1; | |
598 | } | |
599 | ||
56ca9040 PP |
600 | } else { |
601 | imxmci_busy_wait_for_status(host, &stat, | |
4b7c0e4c MKB |
602 | STATUS_APPL_BUFF_FE, |
603 | 20, "imxmci_cpu_driven_data write"); | |
56ca9040 | 604 | |
4b7c0e4c MKB |
605 | while ((stat & STATUS_APPL_BUFF_FE) && |
606 | (host->data_cnt < host->dma_size)) { | |
607 | if (burst_len >= host->dma_size - host->data_cnt) { | |
56ca9040 PP |
608 | burst_len = host->dma_size - host->data_cnt; |
609 | host->data_cnt = host->dma_size; | |
610 | trans_done = 1; | |
611 | } else { | |
612 | host->data_cnt += burst_len; | |
613 | } | |
614 | ||
4b7c0e4c | 615 | for (i = burst_len; i > 0 ; i -= 2) |
df25f9da | 616 | writew(*(host->data_ptr++), host->base + MMC_REG_BUFFER_ACCESS); |
56ca9040 | 617 | |
df25f9da | 618 | stat = readw(host->base + MMC_REG_STATUS); |
56ca9040 PP |
619 | |
620 | dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data write burst %d STATUS = 0x%x\n", | |
621 | burst_len, stat); | |
622 | } | |
623 | } | |
624 | ||
625 | *pstat = stat; | |
626 | ||
627 | return trans_done; | |
628 | } | |
629 | ||
7d12e780 | 630 | static void imxmci_dma_irq(int dma, void *devid) |
56ca9040 PP |
631 | { |
632 | struct imxmci_host *host = devid; | |
df25f9da | 633 | u32 stat = readw(host->base + MMC_REG_STATUS); |
56ca9040 PP |
634 | |
635 | atomic_set(&host->stuck_timeout, 0); | |
636 | host->status_reg = stat; | |
637 | set_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events); | |
638 | tasklet_schedule(&host->tasklet); | |
639 | } | |
640 | ||
7d12e780 | 641 | static irqreturn_t imxmci_irq(int irq, void *devid) |
56ca9040 PP |
642 | { |
643 | struct imxmci_host *host = devid; | |
df25f9da | 644 | u32 stat = readw(host->base + MMC_REG_STATUS); |
56ca9040 PP |
645 | int handled = 1; |
646 | ||
df25f9da MKB |
647 | writew(host->imask | INT_MASK_SDIO | INT_MASK_AUTO_CARD_DETECT, |
648 | host->base + MMC_REG_INT_MASK); | |
56ca9040 PP |
649 | |
650 | atomic_set(&host->stuck_timeout, 0); | |
651 | host->status_reg = stat; | |
652 | set_bit(IMXMCI_PEND_IRQ_b, &host->pending_events); | |
81d38428 | 653 | set_bit(IMXMCI_PEND_STARTED_b, &host->pending_events); |
56ca9040 PP |
654 | tasklet_schedule(&host->tasklet); |
655 | ||
a9239d75 | 656 | return IRQ_RETVAL(handled); |
56ca9040 PP |
657 | } |
658 | ||
659 | static void imxmci_tasklet_fnc(unsigned long data) | |
660 | { | |
661 | struct imxmci_host *host = (struct imxmci_host *)data; | |
662 | u32 stat; | |
663 | unsigned int data_dir_mask = 0; /* STATUS_WR_CRC_ERROR_CODE_MASK */ | |
664 | int timeout = 0; | |
665 | ||
4b7c0e4c | 666 | if (atomic_read(&host->stuck_timeout) > 4) { |
56ca9040 PP |
667 | char *what; |
668 | timeout = 1; | |
df25f9da | 669 | stat = readw(host->base + MMC_REG_STATUS); |
56ca9040 PP |
670 | host->status_reg = stat; |
671 | if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) | |
672 | if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) | |
673 | what = "RESP+DMA"; | |
674 | else | |
675 | what = "RESP"; | |
676 | else | |
677 | if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) | |
4b7c0e4c | 678 | if (test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events)) |
56ca9040 PP |
679 | what = "DATA"; |
680 | else | |
681 | what = "DMA"; | |
682 | else | |
683 | what = "???"; | |
684 | ||
df25f9da MKB |
685 | dev_err(mmc_dev(host->mmc), |
686 | "%s TIMEOUT, hardware stucked STATUS = 0x%04x IMASK = 0x%04x\n", | |
687 | what, stat, | |
688 | readw(host->base + MMC_REG_INT_MASK)); | |
689 | dev_err(mmc_dev(host->mmc), | |
690 | "CMD_DAT_CONT = 0x%04x, MMC_BLK_LEN = 0x%04x, MMC_NOB = 0x%04x, DMA_CCR = 0x%08x\n", | |
691 | readw(host->base + MMC_REG_CMD_DAT_CONT), | |
692 | readw(host->base + MMC_REG_BLK_LEN), | |
693 | readw(host->base + MMC_REG_NOB), | |
694 | CCR(host->dma)); | |
148f93d5 | 695 | dev_err(mmc_dev(host->mmc), "CMD%d, prevCMD%d, bus %d-bit, dma_size = 0x%x\n", |
df25f9da MKB |
696 | host->cmd ? host->cmd->opcode : 0, |
697 | host->prev_cmd_code, | |
698 | 1 << host->actual_bus_width, host->dma_size); | |
56ca9040 PP |
699 | } |
700 | ||
4b7c0e4c | 701 | if (!host->present || timeout) |
56ca9040 | 702 | host->status_reg = STATUS_TIME_OUT_RESP | STATUS_TIME_OUT_READ | |
4b7c0e4c | 703 | STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR; |
56ca9040 | 704 | |
4b7c0e4c | 705 | if (test_bit(IMXMCI_PEND_IRQ_b, &host->pending_events) || timeout) { |
56ca9040 PP |
706 | clear_bit(IMXMCI_PEND_IRQ_b, &host->pending_events); |
707 | ||
df25f9da | 708 | stat = readw(host->base + MMC_REG_STATUS); |
56ca9040 PP |
709 | /* |
710 | * This is not required in theory, but there is chance to miss some flag | |
711 | * which clears automatically by mask write, FreeScale original code keeps | |
712 | * stat from IRQ time so do I | |
713 | */ | |
714 | stat |= host->status_reg; | |
715 | ||
4b7c0e4c | 716 | if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) |
2cb3320b PP |
717 | stat &= ~STATUS_CRC_READ_ERR; |
718 | ||
4b7c0e4c | 719 | if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) { |
56ca9040 | 720 | imxmci_busy_wait_for_status(host, &stat, |
4b7c0e4c MKB |
721 | STATUS_END_CMD_RESP | STATUS_ERR_MASK, |
722 | 20, "imxmci_tasklet_fnc resp (ERRATUM #4)"); | |
56ca9040 PP |
723 | } |
724 | ||
4b7c0e4c MKB |
725 | if (stat & (STATUS_END_CMD_RESP | STATUS_ERR_MASK)) { |
726 | if (test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) | |
56ca9040 | 727 | imxmci_cmd_done(host, stat); |
4b7c0e4c | 728 | if (host->data && (stat & STATUS_ERR_MASK)) |
56ca9040 PP |
729 | imxmci_data_done(host, stat); |
730 | } | |
731 | ||
4b7c0e4c | 732 | if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) { |
df25f9da | 733 | stat |= readw(host->base + MMC_REG_STATUS); |
4b7c0e4c MKB |
734 | if (imxmci_cpu_driven_data(host, &stat)) { |
735 | if (test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) | |
56ca9040 PP |
736 | imxmci_cmd_done(host, stat); |
737 | atomic_clear_mask(IMXMCI_PEND_IRQ_m|IMXMCI_PEND_CPU_DATA_m, | |
4b7c0e4c | 738 | &host->pending_events); |
56ca9040 PP |
739 | imxmci_data_done(host, stat); |
740 | } | |
741 | } | |
742 | } | |
743 | ||
4b7c0e4c MKB |
744 | if (test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events) && |
745 | !test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) { | |
56ca9040 | 746 | |
df25f9da | 747 | stat = readw(host->base + MMC_REG_STATUS); |
56ca9040 PP |
748 | /* Same as above */ |
749 | stat |= host->status_reg; | |
750 | ||
4b7c0e4c | 751 | if (host->dma_dir == DMA_TO_DEVICE) |
56ca9040 | 752 | data_dir_mask = STATUS_WRITE_OP_DONE; |
4b7c0e4c | 753 | else |
56ca9040 | 754 | data_dir_mask = STATUS_DATA_TRANS_DONE; |
56ca9040 | 755 | |
4b7c0e4c | 756 | if (stat & data_dir_mask) { |
56ca9040 PP |
757 | clear_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events); |
758 | imxmci_data_done(host, stat); | |
759 | } | |
760 | } | |
761 | ||
4b7c0e4c | 762 | if (test_and_clear_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events)) { |
56ca9040 | 763 | |
4b7c0e4c | 764 | if (host->cmd) |
56ca9040 PP |
765 | imxmci_cmd_done(host, STATUS_TIME_OUT_RESP); |
766 | ||
4b7c0e4c | 767 | if (host->data) |
56ca9040 PP |
768 | imxmci_data_done(host, STATUS_TIME_OUT_READ | |
769 | STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR); | |
770 | ||
4b7c0e4c | 771 | if (host->req) |
56ca9040 PP |
772 | imxmci_finish_request(host, host->req); |
773 | ||
774 | mmc_detect_change(host->mmc, msecs_to_jiffies(100)); | |
775 | ||
776 | } | |
777 | } | |
778 | ||
779 | static void imxmci_request(struct mmc_host *mmc, struct mmc_request *req) | |
780 | { | |
781 | struct imxmci_host *host = mmc_priv(mmc); | |
782 | unsigned int cmdat; | |
783 | ||
784 | WARN_ON(host->req != NULL); | |
785 | ||
786 | host->req = req; | |
787 | ||
788 | cmdat = 0; | |
789 | ||
790 | if (req->data) { | |
791 | imxmci_setup_data(host, req->data); | |
792 | ||
793 | cmdat |= CMD_DAT_CONT_DATA_ENABLE; | |
794 | ||
795 | if (req->data->flags & MMC_DATA_WRITE) | |
796 | cmdat |= CMD_DAT_CONT_WRITE; | |
797 | ||
4b7c0e4c | 798 | if (req->data->flags & MMC_DATA_STREAM) |
56ca9040 | 799 | cmdat |= CMD_DAT_CONT_STREAM_BLOCK; |
56ca9040 PP |
800 | } |
801 | ||
802 | imxmci_start_cmd(host, req->cmd, cmdat); | |
803 | } | |
804 | ||
805 | #define CLK_RATE 19200000 | |
806 | ||
807 | static void imxmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
808 | { | |
809 | struct imxmci_host *host = mmc_priv(mmc); | |
810 | int prescaler; | |
811 | ||
4b7c0e4c | 812 | if (ios->bus_width == MMC_BUS_WIDTH_4) { |
56ca9040 PP |
813 | host->actual_bus_width = MMC_BUS_WIDTH_4; |
814 | imx_gpio_mode(PB11_PF_SD_DAT3); | |
34b28950 | 815 | BLR(host->dma) = 0; /* burst 64 byte read/write */ |
4b7c0e4c | 816 | } else { |
56ca9040 PP |
817 | host->actual_bus_width = MMC_BUS_WIDTH_1; |
818 | imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11); | |
34b28950 | 819 | BLR(host->dma) = 16; /* burst 16 byte read/write */ |
56ca9040 PP |
820 | } |
821 | ||
4b7c0e4c | 822 | if (host->power_mode != ios->power_mode) { |
56ca9040 PP |
823 | switch (ios->power_mode) { |
824 | case MMC_POWER_OFF: | |
4b7c0e4c | 825 | break; |
56ca9040 PP |
826 | case MMC_POWER_UP: |
827 | set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events); | |
4b7c0e4c | 828 | break; |
56ca9040 | 829 | case MMC_POWER_ON: |
4b7c0e4c | 830 | break; |
56ca9040 PP |
831 | } |
832 | host->power_mode = ios->power_mode; | |
833 | } | |
834 | ||
4b7c0e4c | 835 | if (ios->clock) { |
56ca9040 | 836 | unsigned int clk; |
df25f9da | 837 | u16 reg; |
56ca9040 PP |
838 | |
839 | /* The prescaler is 5 for PERCLK2 equal to 96MHz | |
840 | * then 96MHz / 5 = 19.2 MHz | |
841 | */ | |
38a41fdf | 842 | clk = clk_get_rate(host->clk); |
4b7c0e4c MKB |
843 | prescaler = (clk + (CLK_RATE * 7) / 8) / CLK_RATE; |
844 | switch (prescaler) { | |
56ca9040 PP |
845 | case 0: |
846 | case 1: prescaler = 0; | |
847 | break; | |
848 | case 2: prescaler = 1; | |
849 | break; | |
850 | case 3: prescaler = 2; | |
851 | break; | |
852 | case 4: prescaler = 4; | |
853 | break; | |
854 | default: | |
855 | case 5: prescaler = 5; | |
856 | break; | |
857 | } | |
858 | ||
859 | dev_dbg(mmc_dev(host->mmc), "PERCLK2 %d MHz -> prescaler %d\n", | |
860 | clk, prescaler); | |
861 | ||
4b7c0e4c | 862 | for (clk = 0; clk < 8; clk++) { |
56ca9040 | 863 | int x; |
4b7c0e4c MKB |
864 | x = CLK_RATE / (1 << clk); |
865 | if (x <= ios->clock) | |
56ca9040 PP |
866 | break; |
867 | } | |
868 | ||
df25f9da MKB |
869 | /* enable controller */ |
870 | reg = readw(host->base + MMC_REG_STR_STP_CLK); | |
871 | writew(reg | STR_STP_CLK_ENABLE, | |
872 | host->base + MMC_REG_STR_STP_CLK); | |
56ca9040 PP |
873 | |
874 | imxmci_stop_clock(host); | |
df25f9da | 875 | writew((prescaler << 3) | clk, host->base + MMC_REG_CLK_RATE); |
2c171bf1 PP |
876 | /* |
877 | * Under my understanding, clock should not be started there, because it would | |
878 | * initiate SDHC sequencer and send last or random command into card | |
879 | */ | |
4b7c0e4c | 880 | /* imxmci_start_clock(host); */ |
56ca9040 | 881 | |
df25f9da MKB |
882 | dev_dbg(mmc_dev(host->mmc), |
883 | "MMC_CLK_RATE: 0x%08x\n", | |
884 | readw(host->base + MMC_REG_CLK_RATE)); | |
56ca9040 PP |
885 | } else { |
886 | imxmci_stop_clock(host); | |
887 | } | |
888 | } | |
889 | ||
faf39ede PP |
890 | static int imxmci_get_ro(struct mmc_host *mmc) |
891 | { | |
892 | struct imxmci_host *host = mmc_priv(mmc); | |
893 | ||
894 | if (host->pdata && host->pdata->get_ro) | |
08f80bb5 AV |
895 | return !!host->pdata->get_ro(mmc_dev(mmc)); |
896 | /* | |
897 | * Board doesn't support read only detection; let the mmc core | |
898 | * decide what to do. | |
899 | */ | |
900 | return -ENOSYS; | |
faf39ede PP |
901 | } |
902 | ||
903 | ||
ab7aefd0 | 904 | static const struct mmc_host_ops imxmci_ops = { |
56ca9040 PP |
905 | .request = imxmci_request, |
906 | .set_ios = imxmci_set_ios, | |
faf39ede | 907 | .get_ro = imxmci_get_ro, |
56ca9040 PP |
908 | }; |
909 | ||
56ca9040 PP |
910 | static void imxmci_check_status(unsigned long data) |
911 | { | |
912 | struct imxmci_host *host = (struct imxmci_host *)data; | |
913 | ||
c5d5e9c4 PZ |
914 | if (host->pdata && host->pdata->card_present && |
915 | host->pdata->card_present(mmc_dev(host->mmc)) != host->present) { | |
56ca9040 PP |
916 | host->present ^= 1; |
917 | dev_info(mmc_dev(host->mmc), "card %s\n", | |
918 | host->present ? "inserted" : "removed"); | |
919 | ||
920 | set_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events); | |
921 | tasklet_schedule(&host->tasklet); | |
922 | } | |
923 | ||
4b7c0e4c MKB |
924 | if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events) || |
925 | test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) { | |
56ca9040 | 926 | atomic_inc(&host->stuck_timeout); |
4b7c0e4c | 927 | if (atomic_read(&host->stuck_timeout) > 4) |
56ca9040 PP |
928 | tasklet_schedule(&host->tasklet); |
929 | } else { | |
930 | atomic_set(&host->stuck_timeout, 0); | |
931 | ||
932 | } | |
933 | ||
934 | mod_timer(&host->timer, jiffies + (HZ>>1)); | |
935 | } | |
936 | ||
b513b6cc | 937 | static int __init imxmci_probe(struct platform_device *pdev) |
56ca9040 PP |
938 | { |
939 | struct mmc_host *mmc; | |
940 | struct imxmci_host *host = NULL; | |
941 | struct resource *r; | |
942 | int ret = 0, irq; | |
df25f9da | 943 | u16 rev_no; |
56ca9040 PP |
944 | |
945 | printk(KERN_INFO "i.MX mmc driver\n"); | |
946 | ||
5fc63dfb PZ |
947 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
948 | irq = platform_get_irq(pdev, 0); | |
949 | if (!r || irq < 0) | |
56ca9040 PP |
950 | return -ENXIO; |
951 | ||
df25f9da MKB |
952 | r = request_mem_region(r->start, resource_size(r), pdev->name); |
953 | if (!r) | |
56ca9040 PP |
954 | return -EBUSY; |
955 | ||
956 | mmc = mmc_alloc_host(sizeof(struct imxmci_host), &pdev->dev); | |
957 | if (!mmc) { | |
958 | ret = -ENOMEM; | |
959 | goto out; | |
960 | } | |
961 | ||
962 | mmc->ops = &imxmci_ops; | |
963 | mmc->f_min = 150000; | |
964 | mmc->f_max = CLK_RATE/2; | |
965 | mmc->ocr_avail = MMC_VDD_32_33; | |
255d01af | 966 | mmc->caps = MMC_CAP_4_BIT_DATA; |
56ca9040 PP |
967 | |
968 | /* MMC core transfer sizes tunable parameters */ | |
969 | mmc->max_hw_segs = 64; | |
970 | mmc->max_phys_segs = 64; | |
56ca9040 | 971 | mmc->max_seg_size = 64*512; /* default PAGE_CACHE_SIZE */ |
55db890a | 972 | mmc->max_req_size = 64*512; /* default PAGE_CACHE_SIZE */ |
fe4a3c7a | 973 | mmc->max_blk_size = 2048; |
55db890a | 974 | mmc->max_blk_count = 65535; |
56ca9040 PP |
975 | |
976 | host = mmc_priv(mmc); | |
df25f9da MKB |
977 | host->base = ioremap(r->start, resource_size(r)); |
978 | if (!host->base) { | |
979 | ret = -ENOMEM; | |
980 | goto out; | |
981 | } | |
982 | ||
56ca9040 PP |
983 | host->mmc = mmc; |
984 | host->dma_allocated = 0; | |
985 | host->pdata = pdev->dev.platform_data; | |
c5d5e9c4 PZ |
986 | if (!host->pdata) |
987 | dev_warn(&pdev->dev, "No platform data provided!\n"); | |
56ca9040 PP |
988 | |
989 | spin_lock_init(&host->lock); | |
990 | host->res = r; | |
991 | host->irq = irq; | |
992 | ||
38a41fdf SH |
993 | host->clk = clk_get(&pdev->dev, "perclk2"); |
994 | if (IS_ERR(host->clk)) { | |
995 | ret = PTR_ERR(host->clk); | |
996 | goto out; | |
997 | } | |
998 | clk_enable(host->clk); | |
999 | ||
56ca9040 PP |
1000 | imx_gpio_mode(PB8_PF_SD_DAT0); |
1001 | imx_gpio_mode(PB9_PF_SD_DAT1); | |
1002 | imx_gpio_mode(PB10_PF_SD_DAT2); | |
1003 | /* Configured as GPIO with pull-up to ensure right MCC card mode */ | |
1004 | /* Switched to PB11_PF_SD_DAT3 if 4 bit bus is configured */ | |
1005 | imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11); | |
1006 | /* imx_gpio_mode(PB11_PF_SD_DAT3); */ | |
1007 | imx_gpio_mode(PB12_PF_SD_CLK); | |
1008 | imx_gpio_mode(PB13_PF_SD_CMD); | |
1009 | ||
df25f9da | 1010 | imxmci_softreset(host); |
56ca9040 | 1011 | |
df25f9da MKB |
1012 | rev_no = readw(host->base + MMC_REG_REV_NO); |
1013 | if (rev_no != 0x390) { | |
56ca9040 | 1014 | dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n", |
df25f9da | 1015 | readw(host->base + MMC_REG_REV_NO)); |
56ca9040 PP |
1016 | goto out; |
1017 | } | |
1018 | ||
df25f9da MKB |
1019 | /* recommended in data sheet */ |
1020 | writew(0x2db4, host->base + MMC_REG_READ_TO); | |
56ca9040 PP |
1021 | |
1022 | host->imask = IMXMCI_INT_MASK_DEFAULT; | |
df25f9da | 1023 | writew(host->imask, host->base + MMC_REG_INT_MASK); |
56ca9040 | 1024 | |
f7def13e PZ |
1025 | host->dma = imx_dma_request_by_prio(DRIVER_NAME, DMA_PRIO_LOW); |
1026 | if(host->dma < 0) { | |
56ca9040 PP |
1027 | dev_err(mmc_dev(host->mmc), "imx_dma_request_by_prio failed\n"); |
1028 | ret = -EBUSY; | |
1029 | goto out; | |
1030 | } | |
4b7c0e4c | 1031 | host->dma_allocated = 1; |
56ca9040 | 1032 | imx_dma_setup_handlers(host->dma, imxmci_dma_irq, NULL, host); |
34b28950 | 1033 | RSSR(host->dma) = DMA_REQ_SDHC; |
56ca9040 PP |
1034 | |
1035 | tasklet_init(&host->tasklet, imxmci_tasklet_fnc, (unsigned long)host); | |
1036 | host->status_reg=0; | |
1037 | host->pending_events=0; | |
1038 | ||
1039 | ret = request_irq(host->irq, imxmci_irq, 0, DRIVER_NAME, host); | |
1040 | if (ret) | |
1041 | goto out; | |
1042 | ||
c5d5e9c4 PZ |
1043 | if (host->pdata && host->pdata->card_present) |
1044 | host->present = host->pdata->card_present(mmc_dev(mmc)); | |
1045 | else /* if there is no way to detect assume that card is present */ | |
1046 | host->present = 1; | |
1047 | ||
56ca9040 PP |
1048 | init_timer(&host->timer); |
1049 | host->timer.data = (unsigned long)host; | |
1050 | host->timer.function = imxmci_check_status; | |
1051 | add_timer(&host->timer); | |
4b7c0e4c | 1052 | mod_timer(&host->timer, jiffies + (HZ >> 1)); |
56ca9040 PP |
1053 | |
1054 | platform_set_drvdata(pdev, mmc); | |
1055 | ||
1056 | mmc_add_host(mmc); | |
1057 | ||
1058 | return 0; | |
1059 | ||
1060 | out: | |
1061 | if (host) { | |
4b7c0e4c | 1062 | if (host->dma_allocated) { |
56ca9040 | 1063 | imx_dma_free(host->dma); |
4b7c0e4c | 1064 | host->dma_allocated = 0; |
56ca9040 | 1065 | } |
38a41fdf SH |
1066 | if (host->clk) { |
1067 | clk_disable(host->clk); | |
1068 | clk_put(host->clk); | |
1069 | } | |
df25f9da MKB |
1070 | if (host->base) |
1071 | iounmap(host->base); | |
56ca9040 PP |
1072 | } |
1073 | if (mmc) | |
1074 | mmc_free_host(mmc); | |
df25f9da | 1075 | release_mem_region(r->start, resource_size(r)); |
56ca9040 PP |
1076 | return ret; |
1077 | } | |
1078 | ||
b513b6cc | 1079 | static int __exit imxmci_remove(struct platform_device *pdev) |
56ca9040 PP |
1080 | { |
1081 | struct mmc_host *mmc = platform_get_drvdata(pdev); | |
1082 | ||
1083 | platform_set_drvdata(pdev, NULL); | |
1084 | ||
1085 | if (mmc) { | |
1086 | struct imxmci_host *host = mmc_priv(mmc); | |
1087 | ||
1088 | tasklet_disable(&host->tasklet); | |
1089 | ||
1090 | del_timer_sync(&host->timer); | |
1091 | mmc_remove_host(mmc); | |
1092 | ||
1093 | free_irq(host->irq, host); | |
df25f9da | 1094 | iounmap(host->base); |
4b7c0e4c | 1095 | if (host->dma_allocated) { |
56ca9040 | 1096 | imx_dma_free(host->dma); |
4b7c0e4c | 1097 | host->dma_allocated = 0; |
56ca9040 PP |
1098 | } |
1099 | ||
1100 | tasklet_kill(&host->tasklet); | |
1101 | ||
38a41fdf SH |
1102 | clk_disable(host->clk); |
1103 | clk_put(host->clk); | |
1104 | ||
df25f9da | 1105 | release_mem_region(host->res->start, resource_size(host->res)); |
56ca9040 PP |
1106 | |
1107 | mmc_free_host(mmc); | |
1108 | } | |
1109 | return 0; | |
1110 | } | |
1111 | ||
1112 | #ifdef CONFIG_PM | |
1113 | static int imxmci_suspend(struct platform_device *dev, pm_message_t state) | |
1114 | { | |
1115 | struct mmc_host *mmc = platform_get_drvdata(dev); | |
1116 | int ret = 0; | |
1117 | ||
1118 | if (mmc) | |
1a13f8fa | 1119 | ret = mmc_suspend_host(mmc); |
56ca9040 PP |
1120 | |
1121 | return ret; | |
1122 | } | |
1123 | ||
1124 | static int imxmci_resume(struct platform_device *dev) | |
1125 | { | |
1126 | struct mmc_host *mmc = platform_get_drvdata(dev); | |
1127 | struct imxmci_host *host; | |
1128 | int ret = 0; | |
1129 | ||
1130 | if (mmc) { | |
1131 | host = mmc_priv(mmc); | |
4b7c0e4c | 1132 | if (host) |
56ca9040 PP |
1133 | set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events); |
1134 | ret = mmc_resume_host(mmc); | |
1135 | } | |
1136 | ||
1137 | return ret; | |
1138 | } | |
1139 | #else | |
1140 | #define imxmci_suspend NULL | |
1141 | #define imxmci_resume NULL | |
1142 | #endif /* CONFIG_PM */ | |
1143 | ||
1144 | static struct platform_driver imxmci_driver = { | |
b513b6cc | 1145 | .remove = __exit_p(imxmci_remove), |
56ca9040 PP |
1146 | .suspend = imxmci_suspend, |
1147 | .resume = imxmci_resume, | |
1148 | .driver = { | |
1149 | .name = DRIVER_NAME, | |
bc65c724 | 1150 | .owner = THIS_MODULE, |
56ca9040 PP |
1151 | } |
1152 | }; | |
1153 | ||
1154 | static int __init imxmci_init(void) | |
1155 | { | |
b513b6cc | 1156 | return platform_driver_probe(&imxmci_driver, imxmci_probe); |
56ca9040 PP |
1157 | } |
1158 | ||
1159 | static void __exit imxmci_exit(void) | |
1160 | { | |
1161 | platform_driver_unregister(&imxmci_driver); | |
1162 | } | |
1163 | ||
1164 | module_init(imxmci_init); | |
1165 | module_exit(imxmci_exit); | |
1166 | ||
1167 | MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver"); | |
1168 | MODULE_AUTHOR("Sascha Hauer, Pengutronix"); | |
1169 | MODULE_LICENSE("GPL"); | |
bc65c724 | 1170 | MODULE_ALIAS("platform:imx-mmc"); |