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hwmon: (w83627ehf) Driver cleanup
[net-next-2.6.git] / drivers / hwmon / w83627ehf.c
CommitLineData
08e7e278
JD		 1/*
2 w83627ehf - Driver for the hardware monitoring functionality of
3 the Winbond W83627EHF Super-I/O chip
4 Copyright (C) 2005 Jean Delvare <khali@linux-fr.org>
3379ceee 5 Copyright (C) 2006 Yuan Mu (Winbond),
7188cc66 6 Rudolf Marek <r.marek@assembler.cz>
c18beb5b 7 David Hubbard <david.c.hubbard@gmail.com>
41e9a062 8 Daniel J Blueman <daniel.blueman@gmail.com>
08e7e278
JD		 9
10 Shamelessly ripped from the w83627hf driver
11 Copyright (C) 2003 Mark Studebaker
12
13 Thanks to Leon Moonen, Steve Cliffe and Grant Coady for their help
14 in testing and debugging this driver.
15
8dd2d2ca
JD		 16 This driver also supports the W83627EHG, which is the lead-free
17 version of the W83627EHF.
18
08e7e278
JD		 19 This program is free software; you can redistribute it and/or modify
20 it under the terms of the GNU General Public License as published by
21 the Free Software Foundation; either version 2 of the License, or
22 (at your option) any later version.
23
24 This program is distributed in the hope that it will be useful,
25 but WITHOUT ANY WARRANTY; without even the implied warranty of
26 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 GNU General Public License for more details.
28
29 You should have received a copy of the GNU General Public License
30 along with this program; if not, write to the Free Software
31 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
32
33
34 Supports the following chips:
35
657c93b1
DH		 36 Chip #vin #fan #pwm #temp chip IDs man ID
37 w83627ehf 10 5 4 3 0x8850 0x88 0x5ca3
38 0x8860 0xa1
39 w83627dhg 9 5 4 3 0xa020 0xc1 0x5ca3
c1e48dce 40 w83627dhg-p 9 5 4 3 0xb070 0xc1 0x5ca3
237c8d2f 41 w83667hg 9 5 3 3 0xa510 0xc1 0x5ca3
08e7e278
JD		 42*/
43
44#include <linux/module.h>
45#include <linux/init.h>
46#include <linux/slab.h>
1ea6dd38
DH		 47#include <linux/jiffies.h>
48#include <linux/platform_device.h>
943b0830 49#include <linux/hwmon.h>
412fec82 50#include <linux/hwmon-sysfs.h>
fc18d6c0 51#include <linux/hwmon-vid.h>
943b0830 52#include <linux/err.h>
9a61bf63 53#include <linux/mutex.h>
b9acb64a 54#include <linux/acpi.h>
6055fae8 55#include <linux/io.h>
08e7e278
JD		 56#include "lm75.h"
57
c1e48dce 58enum kinds { w83627ehf, w83627dhg, w83627dhg_p, w83667hg };
08e7e278 59
1ea6dd38
DH		 60/* used to set data->name = w83627ehf_device_names[data->sio_kind] */
61static const char * w83627ehf_device_names[] = {
62 "w83627ehf",
63 "w83627dhg",
c1e48dce 64 "w83627dhg",
237c8d2f 65 "w83667hg",
1ea6dd38
DH		 66};
67
67b671bc
JD		 68static unsigned short force_id;
69module_param(force_id, ushort, 0);
70MODULE_PARM_DESC(force_id, "Override the detected device ID");
71
1ea6dd38 72#define DRVNAME "w83627ehf"
08e7e278 73
657c93b1 74/*
1ea6dd38 75 * Super-I/O constants and functions
657c93b1 76 */
08e7e278
JD		 77
78#define W83627EHF_LD_HWM 0x0b
237c8d2f 79#define W83667HG_LD_VID 0x0d
08e7e278
JD		 80
81#define SIO_REG_LDSEL 0x07 /* Logical device select */
82#define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
fc18d6c0 83#define SIO_REG_EN_VRM10 0x2C /* GPIO3, GPIO4 selection */
08e7e278
JD		 84#define SIO_REG_ENABLE 0x30 /* Logical device enable */
85#define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
fc18d6c0
JD		 86#define SIO_REG_VID_CTRL 0xF0 /* VID control */
87#define SIO_REG_VID_DATA 0xF1 /* VID data */
08e7e278 88
657c93b1
DH		 89#define SIO_W83627EHF_ID 0x8850
90#define SIO_W83627EHG_ID 0x8860
91#define SIO_W83627DHG_ID 0xa020
c1e48dce 92#define SIO_W83627DHG_P_ID 0xb070
237c8d2f 93#define SIO_W83667HG_ID 0xa510
657c93b1 94#define SIO_ID_MASK 0xFFF0
08e7e278
JD		 95
96static inline void
1ea6dd38 97superio_outb(int ioreg, int reg, int val)
08e7e278 98{
1ea6dd38
DH		 99 outb(reg, ioreg);
100 outb(val, ioreg + 1);
08e7e278
JD		 101}
102
103static inline int
1ea6dd38 104superio_inb(int ioreg, int reg)
08e7e278 105{
1ea6dd38
DH		 106 outb(reg, ioreg);
107 return inb(ioreg + 1);
08e7e278
JD		 108}
109
110static inline void
1ea6dd38 111superio_select(int ioreg, int ld)
08e7e278 112{
1ea6dd38
DH		 113 outb(SIO_REG_LDSEL, ioreg);
114 outb(ld, ioreg + 1);
08e7e278
JD		 115}
116
117static inline void
1ea6dd38 118superio_enter(int ioreg)
08e7e278 119{
1ea6dd38
DH		 120 outb(0x87, ioreg);
121 outb(0x87, ioreg);
08e7e278
JD		 122}
123
124static inline void
1ea6dd38 125superio_exit(int ioreg)
08e7e278 126{
1ea6dd38
DH		 127 outb(0x02, ioreg);
128 outb(0x02, ioreg + 1);
08e7e278
JD		 129}
130
131/*
132 * ISA constants
133 */
134
1a641fce
JD		 135#define IOREGION_ALIGNMENT ~7
136#define IOREGION_OFFSET 5
137#define IOREGION_LENGTH 2
1ea6dd38
DH		 138#define ADDR_REG_OFFSET 0
139#define DATA_REG_OFFSET 1
08e7e278
JD		 140
141#define W83627EHF_REG_BANK 0x4E
142#define W83627EHF_REG_CONFIG 0x40
657c93b1
DH		 143
144/* Not currently used:
145 * REG_MAN_ID has the value 0x5ca3 for all supported chips.
146 * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model.
147 * REG_MAN_ID is at port 0x4f
148 * REG_CHIP_ID is at port 0x58 */
08e7e278
JD		 149
150static const u16 W83627EHF_REG_FAN[] = { 0x28, 0x29, 0x2a, 0x3f, 0x553 };
151static const u16 W83627EHF_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d, 0x3e, 0x55c };
152
cf0676fe
RM		 153/* The W83627EHF registers for nr=7,8,9 are in bank 5 */
154#define W83627EHF_REG_IN_MAX(nr) ((nr < 7) ? (0x2b + (nr) * 2) : \
155 (0x554 + (((nr) - 7) * 2)))
156#define W83627EHF_REG_IN_MIN(nr) ((nr < 7) ? (0x2c + (nr) * 2) : \
157 (0x555 + (((nr) - 7) * 2)))
158#define W83627EHF_REG_IN(nr) ((nr < 7) ? (0x20 + (nr)) : \
159 (0x550 + (nr) - 7))
160
08e7e278
JD		 161#define W83627EHF_REG_TEMP1 0x27
162#define W83627EHF_REG_TEMP1_HYST 0x3a
163#define W83627EHF_REG_TEMP1_OVER 0x39
164static const u16 W83627EHF_REG_TEMP[] = { 0x150, 0x250 };
165static const u16 W83627EHF_REG_TEMP_HYST[] = { 0x153, 0x253 };
166static const u16 W83627EHF_REG_TEMP_OVER[] = { 0x155, 0x255 };
167static const u16 W83627EHF_REG_TEMP_CONFIG[] = { 0x152, 0x252 };
168
169/* Fan clock dividers are spread over the following five registers */
170#define W83627EHF_REG_FANDIV1 0x47
171#define W83627EHF_REG_FANDIV2 0x4B
172#define W83627EHF_REG_VBAT 0x5D
173#define W83627EHF_REG_DIODE 0x59
174#define W83627EHF_REG_SMI_OVT 0x4C
175
a4589dbb
JD		 176#define W83627EHF_REG_ALARM1 0x459
177#define W83627EHF_REG_ALARM2 0x45A
178#define W83627EHF_REG_ALARM3 0x45B
179
08c79950 180/* SmartFan registers */
41e9a062
DB		 181#define W83627EHF_REG_FAN_STEPUP_TIME 0x0f
182#define W83627EHF_REG_FAN_STEPDOWN_TIME 0x0e
183
08c79950
RM		 184/* DC or PWM output fan configuration */
185static const u8 W83627EHF_REG_PWM_ENABLE[] = {
186 0x04, /* SYS FAN0 output mode and PWM mode */
187 0x04, /* CPU FAN0 output mode and PWM mode */
188 0x12, /* AUX FAN mode */
41e9a062 189 0x62, /* CPU FAN1 mode */
08c79950
RM		 190};
191
192static const u8 W83627EHF_PWM_MODE_SHIFT[] = { 0, 1, 0, 6 };
193static const u8 W83627EHF_PWM_ENABLE_SHIFT[] = { 2, 4, 1, 4 };
194
195/* FAN Duty Cycle, be used to control */
196static const u8 W83627EHF_REG_PWM[] = { 0x01, 0x03, 0x11, 0x61 };
197static const u8 W83627EHF_REG_TARGET[] = { 0x05, 0x06, 0x13, 0x63 };
198static const u8 W83627EHF_REG_TOLERANCE[] = { 0x07, 0x07, 0x14, 0x62 };
199
08c79950 200/* Advanced Fan control, some values are common for all fans */
41e9a062
DB		 201static const u8 W83627EHF_REG_FAN_START_OUTPUT[] = { 0x0a, 0x0b, 0x16, 0x65 };
202static const u8 W83627EHF_REG_FAN_STOP_OUTPUT[] = { 0x08, 0x09, 0x15, 0x64 };
203static const u8 W83627EHF_REG_FAN_STOP_TIME[] = { 0x0c, 0x0d, 0x17, 0x66 };
204static const u8 W83627EHF_REG_FAN_MAX_OUTPUT[] = { 0xff, 0x67, 0xff, 0x69 };
205static const u8 W83627EHF_REG_FAN_STEP_OUTPUT[] = { 0xff, 0x68, 0xff, 0x6a };
08c79950 206
08e7e278
JD		 207/*
208 * Conversions
209 */
210
08c79950
RM		 211/* 1 is PWM mode, output in ms */
212static inline unsigned int step_time_from_reg(u8 reg, u8 mode)
213{
214 return mode ? 100 * reg : 400 * reg;
215}
216
217static inline u8 step_time_to_reg(unsigned int msec, u8 mode)
218{
219 return SENSORS_LIMIT((mode ? (msec + 50) / 100 :
220 (msec + 200) / 400), 1, 255);
221}
222
08e7e278
JD		 223static inline unsigned int
224fan_from_reg(u8 reg, unsigned int div)
225{
226 if (reg == 0 || reg == 255)
227 return 0;
228 return 1350000U / (reg * div);
229}
230
231static inline unsigned int
232div_from_reg(u8 reg)
233{
234 return 1 << reg;
235}
236
237static inline int
238temp1_from_reg(s8 reg)
239{
240 return reg * 1000;
241}
242
243static inline s8
5bfedac0 244temp1_to_reg(long temp, int min, int max)
08e7e278 245{
08c79950
RM		 246 if (temp <= min)
247 return min / 1000;
248 if (temp >= max)
249 return max / 1000;
08e7e278
JD		 250 if (temp < 0)
251 return (temp - 500) / 1000;
252 return (temp + 500) / 1000;
253}
254
cf0676fe
RM		 255/* Some of analog inputs have internal scaling (2x), 8mV is ADC LSB */
256
257static u8 scale_in[10] = { 8, 8, 16, 16, 8, 8, 8, 16, 16, 8 };
258
259static inline long in_from_reg(u8 reg, u8 nr)
260{
261 return reg * scale_in[nr];
262}
263
264static inline u8 in_to_reg(u32 val, u8 nr)
265{
266 return SENSORS_LIMIT(((val + (scale_in[nr] / 2)) / scale_in[nr]), 0, 255);
267}
268
08e7e278
JD		 269/*
270 * Data structures and manipulation thereof
271 */
272
273struct w83627ehf_data {
1ea6dd38
DH		 274 int addr; /* IO base of hw monitor block */
275 const char *name;
276
1beeffe4 277 struct device *hwmon_dev;
9a61bf63 278 struct mutex lock;
08e7e278 279
da2e0255
GR		 280 const u8 *REG_FAN_START_OUTPUT;
281 const u8 *REG_FAN_STOP_OUTPUT;
282 const u8 *REG_FAN_MAX_OUTPUT;
283 const u8 *REG_FAN_STEP_OUTPUT;
284
9a61bf63 285 struct mutex update_lock;
08e7e278
JD		 286 char valid; /* !=0 if following fields are valid */
287 unsigned long last_updated; /* In jiffies */
288
289 /* Register values */
1ea6dd38 290 u8 in_num; /* number of in inputs we have */
cf0676fe
RM		 291 u8 in[10]; /* Register value */
292 u8 in_max[10]; /* Register value */
293 u8 in_min[10]; /* Register value */
08e7e278
JD		 294 u8 fan[5];
295 u8 fan_min[5];
296 u8 fan_div[5];
297 u8 has_fan; /* some fan inputs can be disabled */
da667365 298 u8 temp_type[3];
08e7e278
JD		 299 s8 temp1;
300 s8 temp1_max;
301 s8 temp1_max_hyst;
302 s16 temp[2];
303 s16 temp_max[2];
304 s16 temp_max_hyst[2];
a4589dbb 305 u32 alarms;
08c79950
RM		 306
307 u8 pwm_mode[4]; /* 0->DC variable voltage, 1->PWM variable duty cycle */
308 u8 pwm_enable[4]; /* 1->manual
41e9a062
DB		 309 2->thermal cruise mode (also called SmartFan I)
310 3->fan speed cruise mode
311 4->variable thermal cruise (also called SmartFan III) */
237c8d2f 312 u8 pwm_num; /* number of pwm */
08c79950
RM		 313 u8 pwm[4];
314 u8 target_temp[4];
315 u8 tolerance[4];
316
41e9a062
DB		 317 u8 fan_start_output[4]; /* minimum fan speed when spinning up */
318 u8 fan_stop_output[4]; /* minimum fan speed when spinning down */
319 u8 fan_stop_time[4]; /* time at minimum before disabling fan */
320 u8 fan_max_output[4]; /* maximum fan speed */
321 u8 fan_step_output[4]; /* rate of change output value */
fc18d6c0
JD		 322
323 u8 vid;
324 u8 vrm;
a157d06d
GJ		 325
326 u8 temp3_disable;
327 u8 in6_skip;
08e7e278
JD		 328};
329
1ea6dd38
DH		 330struct w83627ehf_sio_data {
331 int sioreg;
332 enum kinds kind;
333};
334
08e7e278
JD		 335static inline int is_word_sized(u16 reg)
336{
337 return (((reg & 0xff00) == 0x100
338 || (reg & 0xff00) == 0x200)
339 && ((reg & 0x00ff) == 0x50
340 || (reg & 0x00ff) == 0x53
341 || (reg & 0x00ff) == 0x55));
342}
343
0956895a 344/* Registers 0x50-0x5f are banked */
1ea6dd38 345static inline void w83627ehf_set_bank(struct w83627ehf_data *data, u16 reg)
08e7e278 346{
0956895a 347 if ((reg & 0x00f0) == 0x50) {
1ea6dd38
DH		 348 outb_p(W83627EHF_REG_BANK, data->addr + ADDR_REG_OFFSET);
349 outb_p(reg >> 8, data->addr + DATA_REG_OFFSET);
08e7e278
JD		 350 }
351}
352
0956895a 353/* Not strictly necessary, but play it safe for now */
1ea6dd38 354static inline void w83627ehf_reset_bank(struct w83627ehf_data *data, u16 reg)
08e7e278
JD		 355{
356 if (reg & 0xff00) {
1ea6dd38
DH		 357 outb_p(W83627EHF_REG_BANK, data->addr + ADDR_REG_OFFSET);
358 outb_p(0, data->addr + DATA_REG_OFFSET);
08e7e278
JD		 359 }
360}
361
1ea6dd38 362static u16 w83627ehf_read_value(struct w83627ehf_data *data, u16 reg)
08e7e278 363{
08e7e278
JD		 364 int res, word_sized = is_word_sized(reg);
365
9a61bf63 366 mutex_lock(&data->lock);
08e7e278 367
1ea6dd38
DH		 368 w83627ehf_set_bank(data, reg);
369 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
370 res = inb_p(data->addr + DATA_REG_OFFSET);
08e7e278
JD		 371 if (word_sized) {
372 outb_p((reg & 0xff) + 1,
1ea6dd38
DH		 373 data->addr + ADDR_REG_OFFSET);
374 res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET);
08e7e278 375 }
1ea6dd38 376 w83627ehf_reset_bank(data, reg);
08e7e278 377
9a61bf63 378 mutex_unlock(&data->lock);
08e7e278
JD		 379
380 return res;
381}
382
1ea6dd38 383static int w83627ehf_write_value(struct w83627ehf_data *data, u16 reg, u16 value)
08e7e278 384{
08e7e278
JD		 385 int word_sized = is_word_sized(reg);
386
9a61bf63 387 mutex_lock(&data->lock);
08e7e278 388
1ea6dd38
DH		 389 w83627ehf_set_bank(data, reg);
390 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
08e7e278 391 if (word_sized) {
1ea6dd38 392 outb_p(value >> 8, data->addr + DATA_REG_OFFSET);
08e7e278 393 outb_p((reg & 0xff) + 1,
1ea6dd38 394 data->addr + ADDR_REG_OFFSET);
08e7e278 395 }
1ea6dd38
DH		 396 outb_p(value & 0xff, data->addr + DATA_REG_OFFSET);
397 w83627ehf_reset_bank(data, reg);
08e7e278 398
9a61bf63 399 mutex_unlock(&data->lock);
08e7e278
JD		 400 return 0;
401}
402
403/* This function assumes that the caller holds data->update_lock */
1ea6dd38 404static void w83627ehf_write_fan_div(struct w83627ehf_data *data, int nr)
08e7e278 405{
08e7e278
JD		 406 u8 reg;
407
408 switch (nr) {
409 case 0:
1ea6dd38 410 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0xcf)
08e7e278 411 | ((data->fan_div[0] & 0x03) << 4);
14992c7e
RM		 412 /* fan5 input control bit is write only, compute the value */
413 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
1ea6dd38
DH		 414 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
415 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xdf)
08e7e278 416 | ((data->fan_div[0] & 0x04) << 3);
1ea6dd38 417 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 418 break;
419 case 1:
1ea6dd38 420 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0x3f)
08e7e278 421 | ((data->fan_div[1] & 0x03) << 6);
14992c7e
RM		 422 /* fan5 input control bit is write only, compute the value */
423 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
1ea6dd38
DH		 424 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
425 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xbf)
08e7e278 426 | ((data->fan_div[1] & 0x04) << 4);
1ea6dd38 427 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 428 break;
429 case 2:
1ea6dd38 430 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV2) & 0x3f)
08e7e278 431 | ((data->fan_div[2] & 0x03) << 6);
1ea6dd38
DH		 432 w83627ehf_write_value(data, W83627EHF_REG_FANDIV2, reg);
433 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0x7f)
08e7e278 434 | ((data->fan_div[2] & 0x04) << 5);
1ea6dd38 435 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 436 break;
437 case 3:
1ea6dd38 438 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0xfc)
08e7e278 439 | (data->fan_div[3] & 0x03);
1ea6dd38
DH		 440 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
441 reg = (w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT) & 0x7f)
08e7e278 442 | ((data->fan_div[3] & 0x04) << 5);
1ea6dd38 443 w83627ehf_write_value(data, W83627EHF_REG_SMI_OVT, reg);
08e7e278
JD		 444 break;
445 case 4:
1ea6dd38 446 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0x73)
33725ad3 447 | ((data->fan_div[4] & 0x03) << 2)
08e7e278 448 | ((data->fan_div[4] & 0x04) << 5);
1ea6dd38 449 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
08e7e278
JD		 450 break;
451 }
452}
453
ea7be66c
MH		 454static void w83627ehf_update_fan_div(struct w83627ehf_data *data)
455{
456 int i;
457
458 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
459 data->fan_div[0] = (i >> 4) & 0x03;
460 data->fan_div[1] = (i >> 6) & 0x03;
461 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV2);
462 data->fan_div[2] = (i >> 6) & 0x03;
463 i = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
464 data->fan_div[0] |= (i >> 3) & 0x04;
465 data->fan_div[1] |= (i >> 4) & 0x04;
466 data->fan_div[2] |= (i >> 5) & 0x04;
467 if (data->has_fan & ((1 << 3) | (1 << 4))) {
468 i = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
469 data->fan_div[3] = i & 0x03;
470 data->fan_div[4] = ((i >> 2) & 0x03)
471 | ((i >> 5) & 0x04);
472 }
473 if (data->has_fan & (1 << 3)) {
474 i = w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT);
475 data->fan_div[3] |= (i >> 5) & 0x04;
476 }
477}
478
08e7e278
JD		 479static struct w83627ehf_data *w83627ehf_update_device(struct device *dev)
480{
1ea6dd38 481 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950 482 int pwmcfg = 0, tolerance = 0; /* shut up the compiler */
08e7e278
JD		 483 int i;
484
9a61bf63 485 mutex_lock(&data->update_lock);
08e7e278 486
6b3e4645 487 if (time_after(jiffies, data->last_updated + HZ + HZ/2)
08e7e278
JD		 488 || !data->valid) {
489 /* Fan clock dividers */
ea7be66c 490 w83627ehf_update_fan_div(data);
08e7e278 491
cf0676fe 492 /* Measured voltages and limits */
1ea6dd38
DH		 493 for (i = 0; i < data->in_num; i++) {
494 data->in[i] = w83627ehf_read_value(data,
cf0676fe 495 W83627EHF_REG_IN(i));
1ea6dd38 496 data->in_min[i] = w83627ehf_read_value(data,
cf0676fe 497 W83627EHF_REG_IN_MIN(i));
1ea6dd38 498 data->in_max[i] = w83627ehf_read_value(data,
cf0676fe
RM		 499 W83627EHF_REG_IN_MAX(i));
500 }
501
08e7e278
JD		 502 /* Measured fan speeds and limits */
503 for (i = 0; i < 5; i++) {
504 if (!(data->has_fan & (1 << i)))
505 continue;
506
1ea6dd38 507 data->fan[i] = w83627ehf_read_value(data,
08e7e278 508 W83627EHF_REG_FAN[i]);
1ea6dd38 509 data->fan_min[i] = w83627ehf_read_value(data,
08e7e278
JD		 510 W83627EHF_REG_FAN_MIN[i]);
511
512 /* If we failed to measure the fan speed and clock
513 divider can be increased, let's try that for next
514 time */
515 if (data->fan[i] == 0xff
516 && data->fan_div[i] < 0x07) {
1ea6dd38 517 dev_dbg(dev, "Increasing fan%d "
08e7e278 518 "clock divider from %u to %u\n",
33725ad3 519 i + 1, div_from_reg(data->fan_div[i]),
08e7e278
JD		 520 div_from_reg(data->fan_div[i] + 1));
521 data->fan_div[i]++;
1ea6dd38 522 w83627ehf_write_fan_div(data, i);
08e7e278
JD		 523 /* Preserve min limit if possible */
524 if (data->fan_min[i] >= 2
525 && data->fan_min[i] != 255)
1ea6dd38 526 w83627ehf_write_value(data,
08e7e278
JD		 527 W83627EHF_REG_FAN_MIN[i],
528 (data->fan_min[i] /= 2));
529 }
530 }
531
da2e0255
GR		 532 for (i = 0; i < data->pwm_num; i++) {
533 if (!(data->has_fan & (1 << i)))
534 continue;
535
77fa49d9 536 /* pwmcfg, tolerance mapped for i=0, i=1 to same reg */
08c79950 537 if (i != 1) {
1ea6dd38 538 pwmcfg = w83627ehf_read_value(data,
08c79950 539 W83627EHF_REG_PWM_ENABLE[i]);
1ea6dd38 540 tolerance = w83627ehf_read_value(data,
08c79950
RM		 541 W83627EHF_REG_TOLERANCE[i]);
542 }
543 data->pwm_mode[i] =
544 ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1)
545 ? 0 : 1;
546 data->pwm_enable[i] =
547 ((pwmcfg >> W83627EHF_PWM_ENABLE_SHIFT[i])
548 & 3) + 1;
1ea6dd38 549 data->pwm[i] = w83627ehf_read_value(data,
08c79950 550 W83627EHF_REG_PWM[i]);
41e9a062
DB		 551 data->fan_start_output[i] = w83627ehf_read_value(data,
552 W83627EHF_REG_FAN_START_OUTPUT[i]);
553 data->fan_stop_output[i] = w83627ehf_read_value(data,
554 W83627EHF_REG_FAN_STOP_OUTPUT[i]);
1ea6dd38 555 data->fan_stop_time[i] = w83627ehf_read_value(data,
08c79950 556 W83627EHF_REG_FAN_STOP_TIME[i]);
da2e0255
GR		 557
558 if (data->REG_FAN_MAX_OUTPUT[i] != 0xff)
559 data->fan_max_output[i] =
560 w83627ehf_read_value(data,
561 data->REG_FAN_MAX_OUTPUT[i]);
562
563 if (data->REG_FAN_STEP_OUTPUT[i] != 0xff)
564 data->fan_step_output[i] =
565 w83627ehf_read_value(data,
566 data->REG_FAN_STEP_OUTPUT[i]);
567
08c79950 568 data->target_temp[i] =
1ea6dd38 569 w83627ehf_read_value(data,
08c79950
RM		 570 W83627EHF_REG_TARGET[i]) &
571 (data->pwm_mode[i] == 1 ? 0x7f : 0xff);
572 data->tolerance[i] = (tolerance >> (i == 1 ? 4 : 0))
573 & 0x0f;
574 }
575
08e7e278 576 /* Measured temperatures and limits */
1ea6dd38 577 data->temp1 = w83627ehf_read_value(data,
08e7e278 578 W83627EHF_REG_TEMP1);
1ea6dd38 579 data->temp1_max = w83627ehf_read_value(data,
08e7e278 580 W83627EHF_REG_TEMP1_OVER);
1ea6dd38 581 data->temp1_max_hyst = w83627ehf_read_value(data,
08e7e278
JD		 582 W83627EHF_REG_TEMP1_HYST);
583 for (i = 0; i < 2; i++) {
1ea6dd38 584 data->temp[i] = w83627ehf_read_value(data,
08e7e278 585 W83627EHF_REG_TEMP[i]);
1ea6dd38 586 data->temp_max[i] = w83627ehf_read_value(data,
08e7e278 587 W83627EHF_REG_TEMP_OVER[i]);
1ea6dd38 588 data->temp_max_hyst[i] = w83627ehf_read_value(data,
08e7e278
JD		 589 W83627EHF_REG_TEMP_HYST[i]);
590 }
591
1ea6dd38 592 data->alarms = w83627ehf_read_value(data,
a4589dbb 593 W83627EHF_REG_ALARM1) |
1ea6dd38 594 (w83627ehf_read_value(data,
a4589dbb 595 W83627EHF_REG_ALARM2) << 8) |
1ea6dd38 596 (w83627ehf_read_value(data,
a4589dbb
JD		 597 W83627EHF_REG_ALARM3) << 16);
598
08e7e278
JD		 599 data->last_updated = jiffies;
600 data->valid = 1;
601 }
602
9a61bf63 603 mutex_unlock(&data->update_lock);
08e7e278
JD		 604 return data;
605}
606
607/*
608 * Sysfs callback functions
609 */
cf0676fe
RM		 610#define show_in_reg(reg) \
611static ssize_t \
612show_##reg(struct device *dev, struct device_attribute *attr, \
613 char *buf) \
614{ \
615 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
616 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
617 int nr = sensor_attr->index; \
618 return sprintf(buf, "%ld\n", in_from_reg(data->reg[nr], nr)); \
619}
620show_in_reg(in)
621show_in_reg(in_min)
622show_in_reg(in_max)
623
624#define store_in_reg(REG, reg) \
625static ssize_t \
626store_in_##reg (struct device *dev, struct device_attribute *attr, \
627 const char *buf, size_t count) \
628{ \
1ea6dd38 629 struct w83627ehf_data *data = dev_get_drvdata(dev); \
cf0676fe
RM		 630 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
631 int nr = sensor_attr->index; \
632 u32 val = simple_strtoul(buf, NULL, 10); \
633 \
634 mutex_lock(&data->update_lock); \
635 data->in_##reg[nr] = in_to_reg(val, nr); \
1ea6dd38 636 w83627ehf_write_value(data, W83627EHF_REG_IN_##REG(nr), \
cf0676fe
RM		 637 data->in_##reg[nr]); \
638 mutex_unlock(&data->update_lock); \
639 return count; \
640}
641
642store_in_reg(MIN, min)
643store_in_reg(MAX, max)
644
a4589dbb
JD		 645static ssize_t show_alarm(struct device *dev, struct device_attribute *attr, char *buf)
646{
647 struct w83627ehf_data *data = w83627ehf_update_device(dev);
648 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
649 int nr = sensor_attr->index;
650 return sprintf(buf, "%u\n", (data->alarms >> nr) & 0x01);
651}
652
cf0676fe
RM		 653static struct sensor_device_attribute sda_in_input[] = {
654 SENSOR_ATTR(in0_input, S_IRUGO, show_in, NULL, 0),
655 SENSOR_ATTR(in1_input, S_IRUGO, show_in, NULL, 1),
656 SENSOR_ATTR(in2_input, S_IRUGO, show_in, NULL, 2),
657 SENSOR_ATTR(in3_input, S_IRUGO, show_in, NULL, 3),
658 SENSOR_ATTR(in4_input, S_IRUGO, show_in, NULL, 4),
659 SENSOR_ATTR(in5_input, S_IRUGO, show_in, NULL, 5),
660 SENSOR_ATTR(in6_input, S_IRUGO, show_in, NULL, 6),
661 SENSOR_ATTR(in7_input, S_IRUGO, show_in, NULL, 7),
662 SENSOR_ATTR(in8_input, S_IRUGO, show_in, NULL, 8),
663 SENSOR_ATTR(in9_input, S_IRUGO, show_in, NULL, 9),
664};
665
a4589dbb
JD		 666static struct sensor_device_attribute sda_in_alarm[] = {
667 SENSOR_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 0),
668 SENSOR_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 1),
669 SENSOR_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 2),
670 SENSOR_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 3),
671 SENSOR_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 8),
672 SENSOR_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 21),
673 SENSOR_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 20),
674 SENSOR_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 16),
675 SENSOR_ATTR(in8_alarm, S_IRUGO, show_alarm, NULL, 17),
676 SENSOR_ATTR(in9_alarm, S_IRUGO, show_alarm, NULL, 19),
677};
678
cf0676fe
RM		 679static struct sensor_device_attribute sda_in_min[] = {
680 SENSOR_ATTR(in0_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 0),
681 SENSOR_ATTR(in1_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 1),
682 SENSOR_ATTR(in2_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 2),
683 SENSOR_ATTR(in3_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 3),
684 SENSOR_ATTR(in4_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 4),
685 SENSOR_ATTR(in5_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 5),
686 SENSOR_ATTR(in6_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 6),
687 SENSOR_ATTR(in7_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 7),
688 SENSOR_ATTR(in8_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 8),
689 SENSOR_ATTR(in9_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 9),
690};
691
692static struct sensor_device_attribute sda_in_max[] = {
693 SENSOR_ATTR(in0_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 0),
694 SENSOR_ATTR(in1_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 1),
695 SENSOR_ATTR(in2_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 2),
696 SENSOR_ATTR(in3_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 3),
697 SENSOR_ATTR(in4_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 4),
698 SENSOR_ATTR(in5_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 5),
699 SENSOR_ATTR(in6_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 6),
700 SENSOR_ATTR(in7_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 7),
701 SENSOR_ATTR(in8_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 8),
702 SENSOR_ATTR(in9_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 9),
703};
704
08e7e278
JD		 705#define show_fan_reg(reg) \
706static ssize_t \
412fec82
YM		 707show_##reg(struct device *dev, struct device_attribute *attr, \
708 char *buf) \
08e7e278
JD		 709{ \
710 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
412fec82
YM		 711 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
712 int nr = sensor_attr->index; \
08e7e278
JD		 713 return sprintf(buf, "%d\n", \
714 fan_from_reg(data->reg[nr], \
715 div_from_reg(data->fan_div[nr]))); \
716}
717show_fan_reg(fan);
718show_fan_reg(fan_min);
719
720static ssize_t
412fec82
YM		 721show_fan_div(struct device *dev, struct device_attribute *attr,
722 char *buf)
08e7e278
JD		 723{
724 struct w83627ehf_data *data = w83627ehf_update_device(dev);
412fec82
YM		 725 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
726 int nr = sensor_attr->index;
727 return sprintf(buf, "%u\n", div_from_reg(data->fan_div[nr]));
08e7e278
JD		 728}
729
730static ssize_t
412fec82
YM		 731store_fan_min(struct device *dev, struct device_attribute *attr,
732 const char *buf, size_t count)
08e7e278 733{
1ea6dd38 734 struct w83627ehf_data *data = dev_get_drvdata(dev);
412fec82
YM		 735 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
736 int nr = sensor_attr->index;
08e7e278
JD		 737 unsigned int val = simple_strtoul(buf, NULL, 10);
738 unsigned int reg;
739 u8 new_div;
740
9a61bf63 741 mutex_lock(&data->update_lock);
08e7e278
JD		 742 if (!val) {
743 /* No min limit, alarm disabled */
744 data->fan_min[nr] = 255;
745 new_div = data->fan_div[nr]; /* No change */
746 dev_info(dev, "fan%u low limit and alarm disabled\n", nr + 1);
747 } else if ((reg = 1350000U / val) >= 128 * 255) {
748 /* Speed below this value cannot possibly be represented,
749 even with the highest divider (128) */
750 data->fan_min[nr] = 254;
751 new_div = 7; /* 128 == (1 << 7) */
752 dev_warn(dev, "fan%u low limit %u below minimum %u, set to "
753 "minimum\n", nr + 1, val, fan_from_reg(254, 128));
754 } else if (!reg) {
755 /* Speed above this value cannot possibly be represented,
756 even with the lowest divider (1) */
757 data->fan_min[nr] = 1;
758 new_div = 0; /* 1 == (1 << 0) */
759 dev_warn(dev, "fan%u low limit %u above maximum %u, set to "
b9110b1c 760 "maximum\n", nr + 1, val, fan_from_reg(1, 1));
08e7e278
JD		 761 } else {
762 /* Automatically pick the best divider, i.e. the one such
763 that the min limit will correspond to a register value
764 in the 96..192 range */
765 new_div = 0;
766 while (reg > 192 && new_div < 7) {
767 reg >>= 1;
768 new_div++;
769 }
770 data->fan_min[nr] = reg;
771 }
772
773 /* Write both the fan clock divider (if it changed) and the new
774 fan min (unconditionally) */
775 if (new_div != data->fan_div[nr]) {
158ce075
JD		 776 /* Preserve the fan speed reading */
777 if (data->fan[nr] != 0xff) {
778 if (new_div > data->fan_div[nr])
779 data->fan[nr] >>= new_div - data->fan_div[nr];
780 else if (data->fan[nr] & 0x80)
781 data->fan[nr] = 0xff;
782 else
783 data->fan[nr] <<= data->fan_div[nr] - new_div;
784 }
08e7e278
JD		 785
786 dev_dbg(dev, "fan%u clock divider changed from %u to %u\n",
787 nr + 1, div_from_reg(data->fan_div[nr]),
788 div_from_reg(new_div));
789 data->fan_div[nr] = new_div;
1ea6dd38 790 w83627ehf_write_fan_div(data, nr);
6b3e4645
JD		 791 /* Give the chip time to sample a new speed value */
792 data->last_updated = jiffies;
08e7e278 793 }
1ea6dd38 794 w83627ehf_write_value(data, W83627EHF_REG_FAN_MIN[nr],
08e7e278 795 data->fan_min[nr]);
9a61bf63 796 mutex_unlock(&data->update_lock);
08e7e278
JD		 797
798 return count;
799}
800
412fec82
YM		 801static struct sensor_device_attribute sda_fan_input[] = {
802 SENSOR_ATTR(fan1_input, S_IRUGO, show_fan, NULL, 0),
803 SENSOR_ATTR(fan2_input, S_IRUGO, show_fan, NULL, 1),
804 SENSOR_ATTR(fan3_input, S_IRUGO, show_fan, NULL, 2),
805 SENSOR_ATTR(fan4_input, S_IRUGO, show_fan, NULL, 3),
806 SENSOR_ATTR(fan5_input, S_IRUGO, show_fan, NULL, 4),
807};
08e7e278 808
a4589dbb
JD		 809static struct sensor_device_attribute sda_fan_alarm[] = {
810 SENSOR_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 6),
811 SENSOR_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 7),
812 SENSOR_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 11),
813 SENSOR_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 10),
814 SENSOR_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 23),
815};
816
412fec82
YM		 817static struct sensor_device_attribute sda_fan_min[] = {
818 SENSOR_ATTR(fan1_min, S_IWUSR | S_IRUGO, show_fan_min,
819 store_fan_min, 0),
820 SENSOR_ATTR(fan2_min, S_IWUSR | S_IRUGO, show_fan_min,
821 store_fan_min, 1),
822 SENSOR_ATTR(fan3_min, S_IWUSR | S_IRUGO, show_fan_min,
823 store_fan_min, 2),
824 SENSOR_ATTR(fan4_min, S_IWUSR | S_IRUGO, show_fan_min,
825 store_fan_min, 3),
826 SENSOR_ATTR(fan5_min, S_IWUSR | S_IRUGO, show_fan_min,
827 store_fan_min, 4),
828};
08e7e278 829
412fec82
YM		 830static struct sensor_device_attribute sda_fan_div[] = {
831 SENSOR_ATTR(fan1_div, S_IRUGO, show_fan_div, NULL, 0),
832 SENSOR_ATTR(fan2_div, S_IRUGO, show_fan_div, NULL, 1),
833 SENSOR_ATTR(fan3_div, S_IRUGO, show_fan_div, NULL, 2),
834 SENSOR_ATTR(fan4_div, S_IRUGO, show_fan_div, NULL, 3),
835 SENSOR_ATTR(fan5_div, S_IRUGO, show_fan_div, NULL, 4),
836};
837
08e7e278
JD		 838#define show_temp1_reg(reg) \
839static ssize_t \
6f637a64
GKH		 840show_##reg(struct device *dev, struct device_attribute *attr, \
841 char *buf) \
08e7e278
JD		 842{ \
843 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
844 return sprintf(buf, "%d\n", temp1_from_reg(data->reg)); \
845}
846show_temp1_reg(temp1);
847show_temp1_reg(temp1_max);
848show_temp1_reg(temp1_max_hyst);
849
850#define store_temp1_reg(REG, reg) \
851static ssize_t \
6f637a64
GKH		 852store_temp1_##reg(struct device *dev, struct device_attribute *attr, \
853 const char *buf, size_t count) \
08e7e278 854{ \
1ea6dd38 855 struct w83627ehf_data *data = dev_get_drvdata(dev); \
5bfedac0 856 long val = simple_strtol(buf, NULL, 10); \
08e7e278 857 \
9a61bf63 858 mutex_lock(&data->update_lock); \
08c79950 859 data->temp1_##reg = temp1_to_reg(val, -128000, 127000); \
1ea6dd38 860 w83627ehf_write_value(data, W83627EHF_REG_TEMP1_##REG, \
08e7e278 861 data->temp1_##reg); \
9a61bf63 862 mutex_unlock(&data->update_lock); \
08e7e278
JD		 863 return count; \
864}
865store_temp1_reg(OVER, max);
866store_temp1_reg(HYST, max_hyst);
867
08e7e278
JD		 868#define show_temp_reg(reg) \
869static ssize_t \
412fec82
YM		 870show_##reg(struct device *dev, struct device_attribute *attr, \
871 char *buf) \
08e7e278
JD		 872{ \
873 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
412fec82
YM		 874 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
875 int nr = sensor_attr->index; \
08e7e278
JD		 876 return sprintf(buf, "%d\n", \
877 LM75_TEMP_FROM_REG(data->reg[nr])); \
878}
879show_temp_reg(temp);
880show_temp_reg(temp_max);
881show_temp_reg(temp_max_hyst);
882
883#define store_temp_reg(REG, reg) \
884static ssize_t \
412fec82
YM		 885store_##reg(struct device *dev, struct device_attribute *attr, \
886 const char *buf, size_t count) \
08e7e278 887{ \
1ea6dd38 888 struct w83627ehf_data *data = dev_get_drvdata(dev); \
412fec82
YM		 889 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
890 int nr = sensor_attr->index; \
5bfedac0 891 long val = simple_strtol(buf, NULL, 10); \
08e7e278 892 \
9a61bf63 893 mutex_lock(&data->update_lock); \
08e7e278 894 data->reg[nr] = LM75_TEMP_TO_REG(val); \
1ea6dd38 895 w83627ehf_write_value(data, W83627EHF_REG_TEMP_##REG[nr], \
08e7e278 896 data->reg[nr]); \
9a61bf63 897 mutex_unlock(&data->update_lock); \
08e7e278
JD		 898 return count; \
899}
900store_temp_reg(OVER, temp_max);
901store_temp_reg(HYST, temp_max_hyst);
902
da667365
JD		 903static ssize_t
904show_temp_type(struct device *dev, struct device_attribute *attr, char *buf)
905{
906 struct w83627ehf_data *data = w83627ehf_update_device(dev);
907 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
908 int nr = sensor_attr->index;
909 return sprintf(buf, "%d\n", (int)data->temp_type[nr]);
910}
911
a157d06d 912static struct sensor_device_attribute sda_temp_input[] = {
412fec82
YM		 913 SENSOR_ATTR(temp1_input, S_IRUGO, show_temp1, NULL, 0),
914 SENSOR_ATTR(temp2_input, S_IRUGO, show_temp, NULL, 0),
915 SENSOR_ATTR(temp3_input, S_IRUGO, show_temp, NULL, 1),
a157d06d
GJ		 916};
917
918static struct sensor_device_attribute sda_temp_max[] = {
412fec82
YM		 919 SENSOR_ATTR(temp1_max, S_IRUGO | S_IWUSR, show_temp1_max,
920 store_temp1_max, 0),
921 SENSOR_ATTR(temp2_max, S_IRUGO | S_IWUSR, show_temp_max,
922 store_temp_max, 0),
923 SENSOR_ATTR(temp3_max, S_IRUGO | S_IWUSR, show_temp_max,
924 store_temp_max, 1),
a157d06d
GJ		 925};
926
927static struct sensor_device_attribute sda_temp_max_hyst[] = {
412fec82
YM		 928 SENSOR_ATTR(temp1_max_hyst, S_IRUGO | S_IWUSR, show_temp1_max_hyst,
929 store_temp1_max_hyst, 0),
930 SENSOR_ATTR(temp2_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
931 store_temp_max_hyst, 0),
932 SENSOR_ATTR(temp3_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
933 store_temp_max_hyst, 1),
a157d06d
GJ		 934};
935
936static struct sensor_device_attribute sda_temp_alarm[] = {
a4589dbb
JD		 937 SENSOR_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 4),
938 SENSOR_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 5),
939 SENSOR_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 13),
a157d06d
GJ		 940};
941
942static struct sensor_device_attribute sda_temp_type[] = {
da667365
JD		 943 SENSOR_ATTR(temp1_type, S_IRUGO, show_temp_type, NULL, 0),
944 SENSOR_ATTR(temp2_type, S_IRUGO, show_temp_type, NULL, 1),
945 SENSOR_ATTR(temp3_type, S_IRUGO, show_temp_type, NULL, 2),
412fec82 946};
08e7e278 947
08c79950
RM		 948#define show_pwm_reg(reg) \
949static ssize_t show_##reg (struct device *dev, struct device_attribute *attr, \
950 char *buf) \
951{ \
952 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
953 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
954 int nr = sensor_attr->index; \
955 return sprintf(buf, "%d\n", data->reg[nr]); \
956}
957
958show_pwm_reg(pwm_mode)
959show_pwm_reg(pwm_enable)
960show_pwm_reg(pwm)
961
962static ssize_t
963store_pwm_mode(struct device *dev, struct device_attribute *attr,
964 const char *buf, size_t count)
965{
1ea6dd38 966 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 967 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
968 int nr = sensor_attr->index;
969 u32 val = simple_strtoul(buf, NULL, 10);
970 u16 reg;
971
972 if (val > 1)
973 return -EINVAL;
974 mutex_lock(&data->update_lock);
1ea6dd38 975 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]);
08c79950
RM		 976 data->pwm_mode[nr] = val;
977 reg &= ~(1 << W83627EHF_PWM_MODE_SHIFT[nr]);
978 if (!val)
979 reg |= 1 << W83627EHF_PWM_MODE_SHIFT[nr];
1ea6dd38 980 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg);
08c79950
RM		 981 mutex_unlock(&data->update_lock);
982 return count;
983}
984
985static ssize_t
986store_pwm(struct device *dev, struct device_attribute *attr,
987 const char *buf, size_t count)
988{
1ea6dd38 989 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 990 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
991 int nr = sensor_attr->index;
992 u32 val = SENSORS_LIMIT(simple_strtoul(buf, NULL, 10), 0, 255);
993
994 mutex_lock(&data->update_lock);
995 data->pwm[nr] = val;
1ea6dd38 996 w83627ehf_write_value(data, W83627EHF_REG_PWM[nr], val);
08c79950
RM		 997 mutex_unlock(&data->update_lock);
998 return count;
999}
1000
1001static ssize_t
1002store_pwm_enable(struct device *dev, struct device_attribute *attr,
1003 const char *buf, size_t count)
1004{
1ea6dd38 1005 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 1006 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1007 int nr = sensor_attr->index;
1008 u32 val = simple_strtoul(buf, NULL, 10);
1009 u16 reg;
1010
41e9a062 1011 if (!val || (val > 4))
08c79950
RM		 1012 return -EINVAL;
1013 mutex_lock(&data->update_lock);
1ea6dd38 1014 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]);
08c79950
RM		 1015 data->pwm_enable[nr] = val;
1016 reg &= ~(0x03 << W83627EHF_PWM_ENABLE_SHIFT[nr]);
1017 reg |= (val - 1) << W83627EHF_PWM_ENABLE_SHIFT[nr];
1ea6dd38 1018 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg);
08c79950
RM		 1019 mutex_unlock(&data->update_lock);
1020 return count;
1021}
1022
1023
1024#define show_tol_temp(reg) \
1025static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1026 char *buf) \
1027{ \
1028 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
1029 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
1030 int nr = sensor_attr->index; \
1031 return sprintf(buf, "%d\n", temp1_from_reg(data->reg[nr])); \
1032}
1033
1034show_tol_temp(tolerance)
1035show_tol_temp(target_temp)
1036
1037static ssize_t
1038store_target_temp(struct device *dev, struct device_attribute *attr,
1039 const char *buf, size_t count)
1040{
1ea6dd38 1041 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 1042 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1043 int nr = sensor_attr->index;
1044 u8 val = temp1_to_reg(simple_strtoul(buf, NULL, 10), 0, 127000);
1045
1046 mutex_lock(&data->update_lock);
1047 data->target_temp[nr] = val;
1ea6dd38 1048 w83627ehf_write_value(data, W83627EHF_REG_TARGET[nr], val);
08c79950
RM		 1049 mutex_unlock(&data->update_lock);
1050 return count;
1051}
1052
1053static ssize_t
1054store_tolerance(struct device *dev, struct device_attribute *attr,
1055 const char *buf, size_t count)
1056{
1ea6dd38 1057 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 1058 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1059 int nr = sensor_attr->index;
1060 u16 reg;
1061 /* Limit the temp to 0C - 15C */
1062 u8 val = temp1_to_reg(simple_strtoul(buf, NULL, 10), 0, 15000);
1063
1064 mutex_lock(&data->update_lock);
1ea6dd38 1065 reg = w83627ehf_read_value(data, W83627EHF_REG_TOLERANCE[nr]);
08c79950
RM		 1066 data->tolerance[nr] = val;
1067 if (nr == 1)
1068 reg = (reg & 0x0f) | (val << 4);
1069 else
1070 reg = (reg & 0xf0) | val;
1ea6dd38 1071 w83627ehf_write_value(data, W83627EHF_REG_TOLERANCE[nr], reg);
08c79950
RM		 1072 mutex_unlock(&data->update_lock);
1073 return count;
1074}
1075
1076static struct sensor_device_attribute sda_pwm[] = {
1077 SENSOR_ATTR(pwm1, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0),
1078 SENSOR_ATTR(pwm2, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 1),
1079 SENSOR_ATTR(pwm3, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 2),
1080 SENSOR_ATTR(pwm4, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 3),
1081};
1082
1083static struct sensor_device_attribute sda_pwm_mode[] = {
1084 SENSOR_ATTR(pwm1_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1085 store_pwm_mode, 0),
1086 SENSOR_ATTR(pwm2_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1087 store_pwm_mode, 1),
1088 SENSOR_ATTR(pwm3_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1089 store_pwm_mode, 2),
1090 SENSOR_ATTR(pwm4_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1091 store_pwm_mode, 3),
1092};
1093
1094static struct sensor_device_attribute sda_pwm_enable[] = {
1095 SENSOR_ATTR(pwm1_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1096 store_pwm_enable, 0),
1097 SENSOR_ATTR(pwm2_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1098 store_pwm_enable, 1),
1099 SENSOR_ATTR(pwm3_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1100 store_pwm_enable, 2),
1101 SENSOR_ATTR(pwm4_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1102 store_pwm_enable, 3),
1103};
1104
1105static struct sensor_device_attribute sda_target_temp[] = {
1106 SENSOR_ATTR(pwm1_target, S_IWUSR | S_IRUGO, show_target_temp,
1107 store_target_temp, 0),
1108 SENSOR_ATTR(pwm2_target, S_IWUSR | S_IRUGO, show_target_temp,
1109 store_target_temp, 1),
1110 SENSOR_ATTR(pwm3_target, S_IWUSR | S_IRUGO, show_target_temp,
1111 store_target_temp, 2),
1112 SENSOR_ATTR(pwm4_target, S_IWUSR | S_IRUGO, show_target_temp,
1113 store_target_temp, 3),
1114};
1115
1116static struct sensor_device_attribute sda_tolerance[] = {
1117 SENSOR_ATTR(pwm1_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1118 store_tolerance, 0),
1119 SENSOR_ATTR(pwm2_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1120 store_tolerance, 1),
1121 SENSOR_ATTR(pwm3_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1122 store_tolerance, 2),
1123 SENSOR_ATTR(pwm4_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1124 store_tolerance, 3),
1125};
1126
08c79950
RM		 1127/* Smart Fan registers */
1128
1129#define fan_functions(reg, REG) \
1130static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1131 char *buf) \
1132{ \
1133 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
1134 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
1135 int nr = sensor_attr->index; \
1136 return sprintf(buf, "%d\n", data->reg[nr]); \
1137}\
1138static ssize_t \
1139store_##reg(struct device *dev, struct device_attribute *attr, \
1140 const char *buf, size_t count) \
1141{\
1ea6dd38 1142 struct w83627ehf_data *data = dev_get_drvdata(dev); \
08c79950
RM		 1143 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
1144 int nr = sensor_attr->index; \
1145 u32 val = SENSORS_LIMIT(simple_strtoul(buf, NULL, 10), 1, 255); \
1146 mutex_lock(&data->update_lock); \
1147 data->reg[nr] = val; \
da2e0255 1148 w83627ehf_write_value(data, data->REG_##REG[nr], val); \
08c79950
RM		 1149 mutex_unlock(&data->update_lock); \
1150 return count; \
1151}
1152
41e9a062
DB		 1153fan_functions(fan_start_output, FAN_START_OUTPUT)
1154fan_functions(fan_stop_output, FAN_STOP_OUTPUT)
1155fan_functions(fan_max_output, FAN_MAX_OUTPUT)
1156fan_functions(fan_step_output, FAN_STEP_OUTPUT)
08c79950
RM		 1157
1158#define fan_time_functions(reg, REG) \
1159static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1160 char *buf) \
1161{ \
1162 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
1163 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
1164 int nr = sensor_attr->index; \
1165 return sprintf(buf, "%d\n", \
1166 step_time_from_reg(data->reg[nr], data->pwm_mode[nr])); \
1167} \
1168\
1169static ssize_t \
1170store_##reg(struct device *dev, struct device_attribute *attr, \
1171 const char *buf, size_t count) \
1172{ \
1ea6dd38 1173 struct w83627ehf_data *data = dev_get_drvdata(dev); \
08c79950
RM		 1174 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
1175 int nr = sensor_attr->index; \
1176 u8 val = step_time_to_reg(simple_strtoul(buf, NULL, 10), \
1177 data->pwm_mode[nr]); \
1178 mutex_lock(&data->update_lock); \
1179 data->reg[nr] = val; \
1ea6dd38 1180 w83627ehf_write_value(data, W83627EHF_REG_##REG[nr], val); \
08c79950
RM		 1181 mutex_unlock(&data->update_lock); \
1182 return count; \
1183} \
1184
1185fan_time_functions(fan_stop_time, FAN_STOP_TIME)
1186
1ea6dd38
DH		 1187static ssize_t show_name(struct device *dev, struct device_attribute *attr,
1188 char *buf)
1189{
1190 struct w83627ehf_data *data = dev_get_drvdata(dev);
1191
1192 return sprintf(buf, "%s\n", data->name);
1193}
1194static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
08c79950
RM		 1195
1196static struct sensor_device_attribute sda_sf3_arrays_fan4[] = {
1197 SENSOR_ATTR(pwm4_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1198 store_fan_stop_time, 3),
41e9a062
DB		 1199 SENSOR_ATTR(pwm4_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1200 store_fan_start_output, 3),
1201 SENSOR_ATTR(pwm4_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1202 store_fan_stop_output, 3),
1203 SENSOR_ATTR(pwm4_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1204 store_fan_max_output, 3),
1205 SENSOR_ATTR(pwm4_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1206 store_fan_step_output, 3),
08c79950
RM		 1207};
1208
1209static struct sensor_device_attribute sda_sf3_arrays[] = {
1210 SENSOR_ATTR(pwm1_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1211 store_fan_stop_time, 0),
1212 SENSOR_ATTR(pwm2_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1213 store_fan_stop_time, 1),
1214 SENSOR_ATTR(pwm3_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1215 store_fan_stop_time, 2),
41e9a062
DB		 1216 SENSOR_ATTR(pwm1_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1217 store_fan_start_output, 0),
1218 SENSOR_ATTR(pwm2_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1219 store_fan_start_output, 1),
1220 SENSOR_ATTR(pwm3_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1221 store_fan_start_output, 2),
1222 SENSOR_ATTR(pwm1_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1223 store_fan_stop_output, 0),
1224 SENSOR_ATTR(pwm2_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1225 store_fan_stop_output, 1),
1226 SENSOR_ATTR(pwm3_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1227 store_fan_stop_output, 2),
da2e0255 1228};
41e9a062 1229
da2e0255
GR		 1230
1231/*
1232 * pwm1 and pwm3 don't support max and step settings on all chips.
1233 * Need to check support while generating/removing attribute files.
1234 */
1235static struct sensor_device_attribute sda_sf3_max_step_arrays[] = {
1236 SENSOR_ATTR(pwm1_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1237 store_fan_max_output, 0),
1238 SENSOR_ATTR(pwm1_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1239 store_fan_step_output, 0),
41e9a062
DB		 1240 SENSOR_ATTR(pwm2_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1241 store_fan_max_output, 1),
1242 SENSOR_ATTR(pwm2_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1243 store_fan_step_output, 1),
da2e0255
GR		 1244 SENSOR_ATTR(pwm3_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1245 store_fan_max_output, 2),
1246 SENSOR_ATTR(pwm3_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1247 store_fan_step_output, 2),
08c79950
RM		 1248};
1249
fc18d6c0
JD		 1250static ssize_t
1251show_vid(struct device *dev, struct device_attribute *attr, char *buf)
1252{
1253 struct w83627ehf_data *data = dev_get_drvdata(dev);
1254 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
1255}
1256static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid, NULL);
1257
08e7e278 1258/*
1ea6dd38 1259 * Driver and device management
08e7e278
JD		 1260 */
1261
c18beb5b
DH		 1262static void w83627ehf_device_remove_files(struct device *dev)
1263{
1264 /* some entries in the following arrays may not have been used in
1265 * device_create_file(), but device_remove_file() will ignore them */
1266 int i;
1ea6dd38 1267 struct w83627ehf_data *data = dev_get_drvdata(dev);
c18beb5b
DH		 1268
1269 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++)
1270 device_remove_file(dev, &sda_sf3_arrays[i].dev_attr);
da2e0255
GR		 1271 for (i = 0; i < ARRAY_SIZE(sda_sf3_max_step_arrays); i++) {
1272 struct sensor_device_attribute *attr =
1273 &sda_sf3_max_step_arrays[i];
1274 if (data->REG_FAN_STEP_OUTPUT[attr->index] != 0xff)
1275 device_remove_file(dev, &attr->dev_attr);
1276 }
c18beb5b
DH		 1277 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++)
1278 device_remove_file(dev, &sda_sf3_arrays_fan4[i].dev_attr);
1ea6dd38 1279 for (i = 0; i < data->in_num; i++) {
a157d06d
GJ		 1280 if ((i == 6) && data->in6_skip)
1281 continue;
c18beb5b
DH		 1282 device_remove_file(dev, &sda_in_input[i].dev_attr);
1283 device_remove_file(dev, &sda_in_alarm[i].dev_attr);
1284 device_remove_file(dev, &sda_in_min[i].dev_attr);
1285 device_remove_file(dev, &sda_in_max[i].dev_attr);
1286 }
1287 for (i = 0; i < 5; i++) {
1288 device_remove_file(dev, &sda_fan_input[i].dev_attr);
1289 device_remove_file(dev, &sda_fan_alarm[i].dev_attr);
1290 device_remove_file(dev, &sda_fan_div[i].dev_attr);
1291 device_remove_file(dev, &sda_fan_min[i].dev_attr);
1292 }
237c8d2f 1293 for (i = 0; i < data->pwm_num; i++) {
c18beb5b
DH		 1294 device_remove_file(dev, &sda_pwm[i].dev_attr);
1295 device_remove_file(dev, &sda_pwm_mode[i].dev_attr);
1296 device_remove_file(dev, &sda_pwm_enable[i].dev_attr);
1297 device_remove_file(dev, &sda_target_temp[i].dev_attr);
1298 device_remove_file(dev, &sda_tolerance[i].dev_attr);
1299 }
a157d06d
GJ		 1300 for (i = 0; i < 3; i++) {
1301 if ((i == 2) && data->temp3_disable)
1302 continue;
1303 device_remove_file(dev, &sda_temp_input[i].dev_attr);
1304 device_remove_file(dev, &sda_temp_max[i].dev_attr);
1305 device_remove_file(dev, &sda_temp_max_hyst[i].dev_attr);
1306 device_remove_file(dev, &sda_temp_alarm[i].dev_attr);
1307 device_remove_file(dev, &sda_temp_type[i].dev_attr);
1308 }
c18beb5b 1309
1ea6dd38 1310 device_remove_file(dev, &dev_attr_name);
cbe311f2 1311 device_remove_file(dev, &dev_attr_cpu0_vid);
1ea6dd38 1312}
08e7e278 1313
1ea6dd38
DH		 1314/* Get the monitoring functions started */
1315static inline void __devinit w83627ehf_init_device(struct w83627ehf_data *data)
08e7e278
JD		 1316{
1317 int i;
da667365 1318 u8 tmp, diode;
08e7e278
JD		 1319
1320 /* Start monitoring is needed */
1ea6dd38 1321 tmp = w83627ehf_read_value(data, W83627EHF_REG_CONFIG);
08e7e278 1322 if (!(tmp & 0x01))
1ea6dd38 1323 w83627ehf_write_value(data, W83627EHF_REG_CONFIG,
08e7e278
JD		 1324 tmp | 0x01);
1325
1326 /* Enable temp2 and temp3 if needed */
1327 for (i = 0; i < 2; i++) {
1ea6dd38 1328 tmp = w83627ehf_read_value(data,
08e7e278 1329 W83627EHF_REG_TEMP_CONFIG[i]);
a157d06d
GJ		 1330 if ((i == 1) && data->temp3_disable)
1331 continue;
08e7e278 1332 if (tmp & 0x01)
1ea6dd38 1333 w83627ehf_write_value(data,
08e7e278
JD		 1334 W83627EHF_REG_TEMP_CONFIG[i],
1335 tmp & 0xfe);
1336 }
d3130f0e
JD		 1337
1338 /* Enable VBAT monitoring if needed */
1339 tmp = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
1340 if (!(tmp & 0x01))
1341 w83627ehf_write_value(data, W83627EHF_REG_VBAT, tmp | 0x01);
da667365
JD		 1342
1343 /* Get thermal sensor types */
1344 diode = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
1345 for (i = 0; i < 3; i++) {
1346 if ((tmp & (0x02 << i)))
1347 data->temp_type[i] = (diode & (0x10 << i)) ? 1 : 2;
1348 else
1349 data->temp_type[i] = 4; /* thermistor */
1350 }
08e7e278
JD		 1351}
1352
1ea6dd38 1353static int __devinit w83627ehf_probe(struct platform_device *pdev)
08e7e278 1354{
1ea6dd38
DH		 1355 struct device *dev = &pdev->dev;
1356 struct w83627ehf_sio_data *sio_data = dev->platform_data;
08e7e278 1357 struct w83627ehf_data *data;
1ea6dd38 1358 struct resource *res;
fc18d6c0 1359 u8 fan4pin, fan5pin, en_vrm10;
08e7e278
JD		 1360 int i, err = 0;
1361
1ea6dd38
DH		 1362 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
1363 if (!request_region(res->start, IOREGION_LENGTH, DRVNAME)) {
08e7e278 1364 err = -EBUSY;
1ea6dd38
DH		 1365 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
1366 (unsigned long)res->start,
1367 (unsigned long)res->start + IOREGION_LENGTH - 1);
08e7e278
JD		 1368 goto exit;
1369 }
1370
ba9c2e8d 1371 if (!(data = kzalloc(sizeof(struct w83627ehf_data), GFP_KERNEL))) {
08e7e278
JD		 1372 err = -ENOMEM;
1373 goto exit_release;
1374 }
08e7e278 1375
1ea6dd38 1376 data->addr = res->start;
9a61bf63 1377 mutex_init(&data->lock);
9a61bf63 1378 mutex_init(&data->update_lock);
1ea6dd38
DH		 1379 data->name = w83627ehf_device_names[sio_data->kind];
1380 platform_set_drvdata(pdev, data);
08e7e278 1381
237c8d2f
GJ		 1382 /* 627EHG and 627EHF have 10 voltage inputs; 627DHG and 667HG have 9 */
1383 data->in_num = (sio_data->kind == w83627ehf) ? 10 : 9;
1384 /* 667HG has 3 pwms */
1385 data->pwm_num = (sio_data->kind == w83667hg) ? 3 : 4;
08e7e278 1386
a157d06d
GJ		 1387 /* Check temp3 configuration bit for 667HG */
1388 if (sio_data->kind == w83667hg) {
1389 data->temp3_disable = w83627ehf_read_value(data,
1390 W83627EHF_REG_TEMP_CONFIG[1]) & 0x01;
1391 data->in6_skip = !data->temp3_disable;
1392 }
1393
da2e0255
GR		 1394 data->REG_FAN_START_OUTPUT = W83627EHF_REG_FAN_START_OUTPUT;
1395 data->REG_FAN_STOP_OUTPUT = W83627EHF_REG_FAN_STOP_OUTPUT;
1396 data->REG_FAN_MAX_OUTPUT = W83627EHF_REG_FAN_MAX_OUTPUT;
1397 data->REG_FAN_STEP_OUTPUT = W83627EHF_REG_FAN_STEP_OUTPUT;
1398
08e7e278 1399 /* Initialize the chip */
1ea6dd38 1400 w83627ehf_init_device(data);
08e7e278 1401
fc18d6c0
JD		 1402 data->vrm = vid_which_vrm();
1403 superio_enter(sio_data->sioreg);
fc18d6c0 1404 /* Read VID value */
237c8d2f
GJ		 1405 if (sio_data->kind == w83667hg) {
1406 /* W83667HG has different pins for VID input and output, so
1407 we can get the VID input values directly at logical device D
1408 0xe3. */
1409 superio_select(sio_data->sioreg, W83667HG_LD_VID);
1410 data->vid = superio_inb(sio_data->sioreg, 0xe3);
cbe311f2
JD		 1411 err = device_create_file(dev, &dev_attr_cpu0_vid);
1412 if (err)
1413 goto exit_release;
58e6e781 1414 } else {
237c8d2f
GJ		 1415 superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
1416 if (superio_inb(sio_data->sioreg, SIO_REG_VID_CTRL) & 0x80) {
1417 /* Set VID input sensibility if needed. In theory the
1418 BIOS should have set it, but in practice it's not
1419 always the case. We only do it for the W83627EHF/EHG
1420 because the W83627DHG is more complex in this
1421 respect. */
1422 if (sio_data->kind == w83627ehf) {
1423 en_vrm10 = superio_inb(sio_data->sioreg,
1424 SIO_REG_EN_VRM10);
1425 if ((en_vrm10 & 0x08) && data->vrm == 90) {
1426 dev_warn(dev, "Setting VID input "
1427 "voltage to TTL\n");
1428 superio_outb(sio_data->sioreg,
1429 SIO_REG_EN_VRM10,
1430 en_vrm10 & ~0x08);
1431 } else if (!(en_vrm10 & 0x08)
1432 && data->vrm == 100) {
1433 dev_warn(dev, "Setting VID input "
1434 "voltage to VRM10\n");
1435 superio_outb(sio_data->sioreg,
1436 SIO_REG_EN_VRM10,
1437 en_vrm10 | 0x08);
1438 }
1439 }
1440
1441 data->vid = superio_inb(sio_data->sioreg,
1442 SIO_REG_VID_DATA);
1443 if (sio_data->kind == w83627ehf) /* 6 VID pins only */
1444 data->vid &= 0x3f;
1445
1446 err = device_create_file(dev, &dev_attr_cpu0_vid);
1447 if (err)
1448 goto exit_release;
1449 } else {
1450 dev_info(dev, "VID pins in output mode, CPU VID not "
1451 "available\n");
1452 }
fc18d6c0
JD		 1453 }
1454
08c79950 1455 /* fan4 and fan5 share some pins with the GPIO and serial flash */
237c8d2f
GJ		 1456 if (sio_data->kind == w83667hg) {
1457 fan5pin = superio_inb(sio_data->sioreg, 0x27) & 0x20;
1458 fan4pin = superio_inb(sio_data->sioreg, 0x27) & 0x40;
1459 } else {
1460 fan5pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x02);
1461 fan4pin = !(superio_inb(sio_data->sioreg, 0x29) & 0x06);
1462 }
1ea6dd38 1463 superio_exit(sio_data->sioreg);
08c79950 1464
08e7e278 1465 /* It looks like fan4 and fan5 pins can be alternatively used
14992c7e
RM		 1466 as fan on/off switches, but fan5 control is write only :/
1467 We assume that if the serial interface is disabled, designers
1468 connected fan5 as input unless they are emitting log 1, which
1469 is not the default. */
08c79950 1470
08e7e278 1471 data->has_fan = 0x07; /* fan1, fan2 and fan3 */
1ea6dd38 1472 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
1704b26e 1473 if ((i & (1 << 2)) && fan4pin)
08e7e278 1474 data->has_fan |= (1 << 3);
1704b26e 1475 if (!(i & (1 << 1)) && fan5pin)
08e7e278
JD		 1476 data->has_fan |= (1 << 4);
1477
ea7be66c
MH		 1478 /* Read fan clock dividers immediately */
1479 w83627ehf_update_fan_div(data);
1480
08e7e278 1481 /* Register sysfs hooks */
08c79950 1482 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++)
c18beb5b
DH		 1483 if ((err = device_create_file(dev,
1484 &sda_sf3_arrays[i].dev_attr)))
1485 goto exit_remove;
08c79950 1486
da2e0255
GR		 1487 for (i = 0; i < ARRAY_SIZE(sda_sf3_max_step_arrays); i++) {
1488 struct sensor_device_attribute *attr =
1489 &sda_sf3_max_step_arrays[i];
1490 if (data->REG_FAN_STEP_OUTPUT[attr->index] != 0xff) {
1491 err = device_create_file(dev, &attr->dev_attr);
1492 if (err)
1493 goto exit_remove;
1494 }
1495 }
08c79950 1496 /* if fan4 is enabled create the sf3 files for it */
237c8d2f 1497 if ((data->has_fan & (1 << 3)) && data->pwm_num >= 4)
c18beb5b
DH		 1498 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++) {
1499 if ((err = device_create_file(dev,
1500 &sda_sf3_arrays_fan4[i].dev_attr)))
1501 goto exit_remove;
1502 }
08c79950 1503
a157d06d
GJ		 1504 for (i = 0; i < data->in_num; i++) {
1505 if ((i == 6) && data->in6_skip)
1506 continue;
c18beb5b
DH		 1507 if ((err = device_create_file(dev, &sda_in_input[i].dev_attr))
1508 || (err = device_create_file(dev,
1509 &sda_in_alarm[i].dev_attr))
1510 || (err = device_create_file(dev,
1511 &sda_in_min[i].dev_attr))
1512 || (err = device_create_file(dev,
1513 &sda_in_max[i].dev_attr)))
1514 goto exit_remove;
a157d06d 1515 }
cf0676fe 1516
412fec82 1517 for (i = 0; i < 5; i++) {
08c79950 1518 if (data->has_fan & (1 << i)) {
c18beb5b
DH		 1519 if ((err = device_create_file(dev,
1520 &sda_fan_input[i].dev_attr))
1521 || (err = device_create_file(dev,
1522 &sda_fan_alarm[i].dev_attr))
1523 || (err = device_create_file(dev,
1524 &sda_fan_div[i].dev_attr))
1525 || (err = device_create_file(dev,
1526 &sda_fan_min[i].dev_attr)))
1527 goto exit_remove;
237c8d2f 1528 if (i < data->pwm_num &&
c18beb5b
DH		 1529 ((err = device_create_file(dev,
1530 &sda_pwm[i].dev_attr))
1531 || (err = device_create_file(dev,
1532 &sda_pwm_mode[i].dev_attr))
1533 || (err = device_create_file(dev,
1534 &sda_pwm_enable[i].dev_attr))
1535 || (err = device_create_file(dev,
1536 &sda_target_temp[i].dev_attr))
1537 || (err = device_create_file(dev,
1538 &sda_tolerance[i].dev_attr))))
1539 goto exit_remove;
08c79950 1540 }
08e7e278 1541 }
08c79950 1542
a157d06d
GJ		 1543 for (i = 0; i < 3; i++) {
1544 if ((i == 2) && data->temp3_disable)
1545 continue;
1546 if ((err = device_create_file(dev,
1547 &sda_temp_input[i].dev_attr))
1548 || (err = device_create_file(dev,
1549 &sda_temp_max[i].dev_attr))
1550 || (err = device_create_file(dev,
1551 &sda_temp_max_hyst[i].dev_attr))
1552 || (err = device_create_file(dev,
1553 &sda_temp_alarm[i].dev_attr))
1554 || (err = device_create_file(dev,
1555 &sda_temp_type[i].dev_attr)))
c18beb5b 1556 goto exit_remove;
a157d06d 1557 }
c18beb5b 1558
1ea6dd38
DH		 1559 err = device_create_file(dev, &dev_attr_name);
1560 if (err)
1561 goto exit_remove;
1562
1beeffe4
TJ		 1563 data->hwmon_dev = hwmon_device_register(dev);
1564 if (IS_ERR(data->hwmon_dev)) {
1565 err = PTR_ERR(data->hwmon_dev);
c18beb5b
DH		 1566 goto exit_remove;
1567 }
08e7e278
JD		 1568
1569 return 0;
1570
c18beb5b
DH		 1571exit_remove:
1572 w83627ehf_device_remove_files(dev);
08e7e278 1573 kfree(data);
1ea6dd38 1574 platform_set_drvdata(pdev, NULL);
08e7e278 1575exit_release:
1ea6dd38 1576 release_region(res->start, IOREGION_LENGTH);
08e7e278
JD		 1577exit:
1578 return err;
1579}
1580
1ea6dd38 1581static int __devexit w83627ehf_remove(struct platform_device *pdev)
08e7e278 1582{
1ea6dd38 1583 struct w83627ehf_data *data = platform_get_drvdata(pdev);
08e7e278 1584
1beeffe4 1585 hwmon_device_unregister(data->hwmon_dev);
1ea6dd38
DH		 1586 w83627ehf_device_remove_files(&pdev->dev);
1587 release_region(data->addr, IOREGION_LENGTH);
1588 platform_set_drvdata(pdev, NULL);
943b0830 1589 kfree(data);
08e7e278
JD		 1590
1591 return 0;
1592}
1593
1ea6dd38 1594static struct platform_driver w83627ehf_driver = {
cdaf7934 1595 .driver = {
87218842 1596 .owner = THIS_MODULE,
1ea6dd38 1597 .name = DRVNAME,
cdaf7934 1598 },
1ea6dd38
DH		 1599 .probe = w83627ehf_probe,
1600 .remove = __devexit_p(w83627ehf_remove),
08e7e278
JD		 1601};
1602
1ea6dd38
DH		 1603/* w83627ehf_find() looks for a '627 in the Super-I/O config space */
1604static int __init w83627ehf_find(int sioaddr, unsigned short *addr,
1605 struct w83627ehf_sio_data *sio_data)
08e7e278 1606{
1ea6dd38
DH		 1607 static const char __initdata sio_name_W83627EHF[] = "W83627EHF";
1608 static const char __initdata sio_name_W83627EHG[] = "W83627EHG";
1609 static const char __initdata sio_name_W83627DHG[] = "W83627DHG";
c1e48dce 1610 static const char __initdata sio_name_W83627DHG_P[] = "W83627DHG-P";
237c8d2f 1611 static const char __initdata sio_name_W83667HG[] = "W83667HG";
1ea6dd38 1612
08e7e278 1613 u16 val;
1ea6dd38 1614 const char *sio_name;
08e7e278 1615
1ea6dd38 1616 superio_enter(sioaddr);
08e7e278 1617
67b671bc
JD		 1618 if (force_id)
1619 val = force_id;
1620 else
1621 val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8)
1622 | superio_inb(sioaddr, SIO_REG_DEVID + 1);
657c93b1 1623 switch (val & SIO_ID_MASK) {
657c93b1 1624 case SIO_W83627EHF_ID:
1ea6dd38
DH		 1625 sio_data->kind = w83627ehf;
1626 sio_name = sio_name_W83627EHF;
1627 break;
657c93b1 1628 case SIO_W83627EHG_ID:
1ea6dd38
DH		 1629 sio_data->kind = w83627ehf;
1630 sio_name = sio_name_W83627EHG;
1631 break;
1632 case SIO_W83627DHG_ID:
1633 sio_data->kind = w83627dhg;
1634 sio_name = sio_name_W83627DHG;
657c93b1 1635 break;
c1e48dce
JD		 1636 case SIO_W83627DHG_P_ID:
1637 sio_data->kind = w83627dhg_p;
1638 sio_name = sio_name_W83627DHG_P;
1639 break;
237c8d2f
GJ		 1640 case SIO_W83667HG_ID:
1641 sio_data->kind = w83667hg;
1642 sio_name = sio_name_W83667HG;
1643 break;
657c93b1 1644 default:
9f66036b
JD		 1645 if (val != 0xffff)
1646 pr_debug(DRVNAME ": unsupported chip ID: 0x%04x\n",
1647 val);
1ea6dd38 1648 superio_exit(sioaddr);
08e7e278
JD		 1649 return -ENODEV;
1650 }
1651
1ea6dd38
DH		 1652 /* We have a known chip, find the HWM I/O address */
1653 superio_select(sioaddr, W83627EHF_LD_HWM);
1654 val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8)
1655 | superio_inb(sioaddr, SIO_REG_ADDR + 1);
1a641fce 1656 *addr = val & IOREGION_ALIGNMENT;
2d8672c5 1657 if (*addr == 0) {
475ef855
DH		 1658 printk(KERN_ERR DRVNAME ": Refusing to enable a Super-I/O "
1659 "device with a base I/O port 0.\n");
1ea6dd38 1660 superio_exit(sioaddr);
08e7e278
JD		 1661 return -ENODEV;
1662 }
1663
1664 /* Activate logical device if needed */
1ea6dd38 1665 val = superio_inb(sioaddr, SIO_REG_ENABLE);
475ef855
DH		 1666 if (!(val & 0x01)) {
1667 printk(KERN_WARNING DRVNAME ": Forcibly enabling Super-I/O. "
1668 "Sensor is probably unusable.\n");
1ea6dd38 1669 superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01);
475ef855 1670 }
1ea6dd38
DH		 1671
1672 superio_exit(sioaddr);
1673 pr_info(DRVNAME ": Found %s chip at %#x\n", sio_name, *addr);
1674 sio_data->sioreg = sioaddr;
08e7e278 1675
08e7e278
JD		 1676 return 0;
1677}
1678
1ea6dd38
DH		 1679/* when Super-I/O functions move to a separate file, the Super-I/O
1680 * bus will manage the lifetime of the device and this module will only keep
1681 * track of the w83627ehf driver. But since we platform_device_alloc(), we
1682 * must keep track of the device */
1683static struct platform_device *pdev;
1684
08e7e278
JD		 1685static int __init sensors_w83627ehf_init(void)
1686{
1ea6dd38
DH		 1687 int err;
1688 unsigned short address;
1689 struct resource res;
1690 struct w83627ehf_sio_data sio_data;
1691
1692 /* initialize sio_data->kind and sio_data->sioreg.
1693 *
1694 * when Super-I/O functions move to a separate file, the Super-I/O
1695 * driver will probe 0x2e and 0x4e and auto-detect the presence of a
1696 * w83627ehf hardware monitor, and call probe() */
1697 if (w83627ehf_find(0x2e, &address, &sio_data) &&
1698 w83627ehf_find(0x4e, &address, &sio_data))
08e7e278
JD		 1699 return -ENODEV;
1700
1ea6dd38
DH		 1701 err = platform_driver_register(&w83627ehf_driver);
1702 if (err)
1703 goto exit;
1704
1705 if (!(pdev = platform_device_alloc(DRVNAME, address))) {
1706 err = -ENOMEM;
1707 printk(KERN_ERR DRVNAME ": Device allocation failed\n");
1708 goto exit_unregister;
1709 }
1710
1711 err = platform_device_add_data(pdev, &sio_data,
1712 sizeof(struct w83627ehf_sio_data));
1713 if (err) {
1714 printk(KERN_ERR DRVNAME ": Platform data allocation failed\n");
1715 goto exit_device_put;
1716 }
1717
1718 memset(&res, 0, sizeof(res));
1719 res.name = DRVNAME;
1720 res.start = address + IOREGION_OFFSET;
1721 res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1;
1722 res.flags = IORESOURCE_IO;
b9acb64a
JD		 1723
1724 err = acpi_check_resource_conflict(&res);
1725 if (err)
18632f84 1726 goto exit_device_put;
b9acb64a 1727
1ea6dd38
DH		 1728 err = platform_device_add_resources(pdev, &res, 1);
1729 if (err) {
1730 printk(KERN_ERR DRVNAME ": Device resource addition failed "
1731 "(%d)\n", err);
1732 goto exit_device_put;
1733 }
1734
1735 /* platform_device_add calls probe() */
1736 err = platform_device_add(pdev);
1737 if (err) {
1738 printk(KERN_ERR DRVNAME ": Device addition failed (%d)\n",
1739 err);
1740 goto exit_device_put;
1741 }
1742
1743 return 0;
1744
1745exit_device_put:
1746 platform_device_put(pdev);
1747exit_unregister:
1748 platform_driver_unregister(&w83627ehf_driver);
1749exit:
1750 return err;
08e7e278
JD		 1751}
1752
1753static void __exit sensors_w83627ehf_exit(void)
1754{
1ea6dd38
DH		 1755 platform_device_unregister(pdev);
1756 platform_driver_unregister(&w83627ehf_driver);
08e7e278
JD		 1757}
1758
1759MODULE_AUTHOR("Jean Delvare <khali@linux-fr.org>");
1760MODULE_DESCRIPTION("W83627EHF driver");
1761MODULE_LICENSE("GPL");
1762
1763module_init(sensors_w83627ehf_init);
1764module_exit(sensors_w83627ehf_exit);
Clone of davem's net-next-2.6 tree