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drm/radeon/kms: remove stray radeon_i2c_destroy
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_pm.c
CommitLineData
7433874e
RM		 1/*
2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
8 *
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
56278a8e 21 * Alex Deucher <alexdeucher@gmail.com>
7433874e
RM		 22 */
23#include "drmP.h"
24#include "radeon.h"
f735261b 25#include "avivod.h"
ce8f5370
AD		 26#ifdef CONFIG_ACPI
27#include <linux/acpi.h>
28#endif
29#include <linux/power_supply.h>
21a8122a
AD		 30#include <linux/hwmon.h>
31#include <linux/hwmon-sysfs.h>
7433874e 32
c913e23a
RM		 33#define RADEON_IDLE_LOOP_MS 100
34#define RADEON_RECLOCK_DELAY_MS 200
73a6d3fc 35#define RADEON_WAIT_VBLANK_TIMEOUT 200
2031f77c 36#define RADEON_WAIT_IDLE_TIMEOUT 200
c913e23a 37
f712d0c7
RM		 38static const char *radeon_pm_state_type_name[5] = {
39 "Default",
40 "Powersave",
41 "Battery",
42 "Balanced",
43 "Performance",
44};
45
ce8f5370 46static void radeon_dynpm_idle_work_handler(struct work_struct *work);
c913e23a 47static int radeon_debugfs_pm_init(struct radeon_device *rdev);
ce8f5370
AD		 48static bool radeon_pm_in_vbl(struct radeon_device *rdev);
49static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
50static void radeon_pm_update_profile(struct radeon_device *rdev);
51static void radeon_pm_set_clocks(struct radeon_device *rdev);
52
53#define ACPI_AC_CLASS "ac_adapter"
54
55#ifdef CONFIG_ACPI
56static int radeon_acpi_event(struct notifier_block *nb,
57 unsigned long val,
58 void *data)
59{
60 struct radeon_device *rdev = container_of(nb, struct radeon_device, acpi_nb);
61 struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
62
63 if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
64 if (power_supply_is_system_supplied() > 0)
d9fdaafb 65 DRM_DEBUG_DRIVER("pm: AC\n");
ce8f5370 66 else
d9fdaafb 67 DRM_DEBUG_DRIVER("pm: DC\n");
ce8f5370
AD		 68
69 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
70 if (rdev->pm.profile == PM_PROFILE_AUTO) {
71 mutex_lock(&rdev->pm.mutex);
72 radeon_pm_update_profile(rdev);
73 radeon_pm_set_clocks(rdev);
74 mutex_unlock(&rdev->pm.mutex);
75 }
76 }
77 }
78
79 return NOTIFY_OK;
80}
81#endif
82
83static void radeon_pm_update_profile(struct radeon_device *rdev)
84{
85 switch (rdev->pm.profile) {
86 case PM_PROFILE_DEFAULT:
87 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
88 break;
89 case PM_PROFILE_AUTO:
90 if (power_supply_is_system_supplied() > 0) {
91 if (rdev->pm.active_crtc_count > 1)
92 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
93 else
94 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
95 } else {
96 if (rdev->pm.active_crtc_count > 1)
c9e75b21 97 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
ce8f5370 98 else
c9e75b21 99 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
ce8f5370
AD		 100 }
101 break;
102 case PM_PROFILE_LOW:
103 if (rdev->pm.active_crtc_count > 1)
104 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
105 else
106 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
107 break;
c9e75b21
AD		 108 case PM_PROFILE_MID:
109 if (rdev->pm.active_crtc_count > 1)
110 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
111 else
112 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
113 break;
ce8f5370
AD		 114 case PM_PROFILE_HIGH:
115 if (rdev->pm.active_crtc_count > 1)
116 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
117 else
118 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
119 break;
120 }
121
122 if (rdev->pm.active_crtc_count == 0) {
123 rdev->pm.requested_power_state_index =
124 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
125 rdev->pm.requested_clock_mode_index =
126 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
127 } else {
128 rdev->pm.requested_power_state_index =
129 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
130 rdev->pm.requested_clock_mode_index =
131 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
132 }
133}
c913e23a 134
5876dd24
MG		 135static void radeon_unmap_vram_bos(struct radeon_device *rdev)
136{
137 struct radeon_bo *bo, *n;
138
139 if (list_empty(&rdev->gem.objects))
140 return;
141
142 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
143 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
144 ttm_bo_unmap_virtual(&bo->tbo);
145 }
5876dd24
MG		 146}
147
ce8f5370 148static void radeon_sync_with_vblank(struct radeon_device *rdev)
a424816f 149{
ce8f5370
AD		 150 if (rdev->pm.active_crtcs) {
151 rdev->pm.vblank_sync = false;
152 wait_event_timeout(
153 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
154 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
155 }
156}
157
158static void radeon_set_power_state(struct radeon_device *rdev)
159{
160 u32 sclk, mclk;
92645879 161 bool misc_after = false;
ce8f5370
AD		 162
163 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
164 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
165 return;
166
167 if (radeon_gui_idle(rdev)) {
168 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
169 clock_info[rdev->pm.requested_clock_mode_index].sclk;
170 if (sclk > rdev->clock.default_sclk)
171 sclk = rdev->clock.default_sclk;
172
173 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
174 clock_info[rdev->pm.requested_clock_mode_index].mclk;
175 if (mclk > rdev->clock.default_mclk)
176 mclk = rdev->clock.default_mclk;
177
92645879
AD		 178 /* upvolt before raising clocks, downvolt after lowering clocks */
179 if (sclk < rdev->pm.current_sclk)
180 misc_after = true;
ce8f5370 181
92645879 182 radeon_sync_with_vblank(rdev);
ce8f5370 183
92645879 184 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 185 if (!radeon_pm_in_vbl(rdev))
186 return;
92645879 187 }
ce8f5370 188
92645879 189 radeon_pm_prepare(rdev);
ce8f5370 190
92645879
AD		 191 if (!misc_after)
192 /* voltage, pcie lanes, etc.*/
193 radeon_pm_misc(rdev);
194
195 /* set engine clock */
196 if (sclk != rdev->pm.current_sclk) {
197 radeon_pm_debug_check_in_vbl(rdev, false);
198 radeon_set_engine_clock(rdev, sclk);
199 radeon_pm_debug_check_in_vbl(rdev, true);
200 rdev->pm.current_sclk = sclk;
d9fdaafb 201 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
92645879
AD		 202 }
203
204 /* set memory clock */
205 if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
206 radeon_pm_debug_check_in_vbl(rdev, false);
207 radeon_set_memory_clock(rdev, mclk);
208 radeon_pm_debug_check_in_vbl(rdev, true);
209 rdev->pm.current_mclk = mclk;
d9fdaafb 210 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
ce8f5370 211 }
2aba631c 212
92645879
AD		 213 if (misc_after)
214 /* voltage, pcie lanes, etc.*/
215 radeon_pm_misc(rdev);
216
217 radeon_pm_finish(rdev);
218
ce8f5370
AD		 219 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
220 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
221 } else
d9fdaafb 222 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
ce8f5370
AD		 223}
224
225static void radeon_pm_set_clocks(struct radeon_device *rdev)
226{
227 int i;
c37d230a 228
4e186b2d
AD		 229 /* no need to take locks, etc. if nothing's going to change */
230 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
231 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
232 return;
233
612e06ce
MG		 234 mutex_lock(&rdev->ddev->struct_mutex);
235 mutex_lock(&rdev->vram_mutex);
a424816f 236 mutex_lock(&rdev->cp.mutex);
4f3218cb
AD		 237
238 /* gui idle int has issues on older chips it seems */
239 if (rdev->family >= CHIP_R600) {
ce8f5370
AD		 240 if (rdev->irq.installed) {
241 /* wait for GPU idle */
242 rdev->pm.gui_idle = false;
243 rdev->irq.gui_idle = true;
244 radeon_irq_set(rdev);
245 wait_event_interruptible_timeout(
246 rdev->irq.idle_queue, rdev->pm.gui_idle,
247 msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
248 rdev->irq.gui_idle = false;
249 radeon_irq_set(rdev);
250 }
01434b4b 251 } else {
ce8f5370
AD		 252 if (rdev->cp.ready) {
253 struct radeon_fence *fence;
254 radeon_ring_alloc(rdev, 64);
255 radeon_fence_create(rdev, &fence);
256 radeon_fence_emit(rdev, fence);
257 radeon_ring_commit(rdev);
258 radeon_fence_wait(fence, false);
259 radeon_fence_unref(&fence);
260 }
4f3218cb 261 }
5876dd24
MG		 262 radeon_unmap_vram_bos(rdev);
263
ce8f5370 264 if (rdev->irq.installed) {
2aba631c
MG		 265 for (i = 0; i < rdev->num_crtc; i++) {
266 if (rdev->pm.active_crtcs & (1 << i)) {
267 rdev->pm.req_vblank |= (1 << i);
268 drm_vblank_get(rdev->ddev, i);
269 }
270 }
271 }
539d2418 272
ce8f5370 273 radeon_set_power_state(rdev);
2aba631c 274
ce8f5370 275 if (rdev->irq.installed) {
2aba631c
MG		 276 for (i = 0; i < rdev->num_crtc; i++) {
277 if (rdev->pm.req_vblank & (1 << i)) {
278 rdev->pm.req_vblank &= ~(1 << i);
279 drm_vblank_put(rdev->ddev, i);
280 }
281 }
282 }
5876dd24 283
a424816f
AD		 284 /* update display watermarks based on new power state */
285 radeon_update_bandwidth_info(rdev);
286 if (rdev->pm.active_crtc_count)
287 radeon_bandwidth_update(rdev);
288
ce8f5370 289 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
2aba631c 290
a424816f 291 mutex_unlock(&rdev->cp.mutex);
612e06ce
MG		 292 mutex_unlock(&rdev->vram_mutex);
293 mutex_unlock(&rdev->ddev->struct_mutex);
a424816f
AD		 294}
295
f712d0c7
RM		 296static void radeon_pm_print_states(struct radeon_device *rdev)
297{
298 int i, j;
299 struct radeon_power_state *power_state;
300 struct radeon_pm_clock_info *clock_info;
301
d9fdaafb 302 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
f712d0c7
RM		 303 for (i = 0; i < rdev->pm.num_power_states; i++) {
304 power_state = &rdev->pm.power_state[i];
d9fdaafb 305 DRM_DEBUG_DRIVER("State %d: %s\n", i,
f712d0c7
RM		 306 radeon_pm_state_type_name[power_state->type]);
307 if (i == rdev->pm.default_power_state_index)
d9fdaafb 308 DRM_DEBUG_DRIVER("\tDefault");
f712d0c7 309 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
d9fdaafb 310 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
f712d0c7 311 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
d9fdaafb
DA		 312 DRM_DEBUG_DRIVER("\tSingle display only\n");
313 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
f712d0c7
RM		 314 for (j = 0; j < power_state->num_clock_modes; j++) {
315 clock_info = &(power_state->clock_info[j]);
316 if (rdev->flags & RADEON_IS_IGP)
d9fdaafb 317 DRM_DEBUG_DRIVER("\t\t%d e: %d%s\n",
f712d0c7
RM		 318 j,
319 clock_info->sclk * 10,
320 clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
321 else
d9fdaafb 322 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d%s\n",
f712d0c7
RM		 323 j,
324 clock_info->sclk * 10,
325 clock_info->mclk * 10,
326 clock_info->voltage.voltage,
327 clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
328 }
329 }
330}
331
ce8f5370
AD		 332static ssize_t radeon_get_pm_profile(struct device *dev,
333 struct device_attribute *attr,
334 char *buf)
a424816f
AD		 335{
336 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
337 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 338 int cp = rdev->pm.profile;
a424816f 339
ce8f5370
AD		 340 return snprintf(buf, PAGE_SIZE, "%s\n",
341 (cp == PM_PROFILE_AUTO) ? "auto" :
342 (cp == PM_PROFILE_LOW) ? "low" :
12e27be8 343 (cp == PM_PROFILE_MID) ? "mid" :
ce8f5370 344 (cp == PM_PROFILE_HIGH) ? "high" : "default");
a424816f
AD		 345}
346
ce8f5370
AD		 347static ssize_t radeon_set_pm_profile(struct device *dev,
348 struct device_attribute *attr,
349 const char *buf,
350 size_t count)
a424816f
AD		 351{
352 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
353 struct radeon_device *rdev = ddev->dev_private;
a424816f
AD		 354
355 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 356 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
357 if (strncmp("default", buf, strlen("default")) == 0)
358 rdev->pm.profile = PM_PROFILE_DEFAULT;
359 else if (strncmp("auto", buf, strlen("auto")) == 0)
360 rdev->pm.profile = PM_PROFILE_AUTO;
361 else if (strncmp("low", buf, strlen("low")) == 0)
362 rdev->pm.profile = PM_PROFILE_LOW;
c9e75b21
AD		 363 else if (strncmp("mid", buf, strlen("mid")) == 0)
364 rdev->pm.profile = PM_PROFILE_MID;
ce8f5370
AD		 365 else if (strncmp("high", buf, strlen("high")) == 0)
366 rdev->pm.profile = PM_PROFILE_HIGH;
367 else {
368 DRM_ERROR("invalid power profile!\n");
369 goto fail;
a424816f 370 }
ce8f5370
AD		 371 radeon_pm_update_profile(rdev);
372 radeon_pm_set_clocks(rdev);
373 }
374fail:
a424816f
AD		 375 mutex_unlock(&rdev->pm.mutex);
376
377 return count;
378}
379
ce8f5370
AD		 380static ssize_t radeon_get_pm_method(struct device *dev,
381 struct device_attribute *attr,
382 char *buf)
a424816f
AD		 383{
384 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
385 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 386 int pm = rdev->pm.pm_method;
a424816f
AD		 387
388 return snprintf(buf, PAGE_SIZE, "%s\n",
ce8f5370 389 (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile");
a424816f
AD		 390}
391
ce8f5370
AD		 392static ssize_t radeon_set_pm_method(struct device *dev,
393 struct device_attribute *attr,
394 const char *buf,
395 size_t count)
a424816f
AD		 396{
397 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
398 struct radeon_device *rdev = ddev->dev_private;
a424816f 399
ce8f5370
AD		 400
401 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
a424816f 402 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 403 rdev->pm.pm_method = PM_METHOD_DYNPM;
404 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
405 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
a424816f 406 mutex_unlock(&rdev->pm.mutex);
ce8f5370 407 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
3f53eb6f
RW		 408 bool flush_wq = false;
409
ce8f5370 410 mutex_lock(&rdev->pm.mutex);
3f53eb6f
RW		 411 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
412 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
413 flush_wq = true;
414 }
ce8f5370
AD		 415 /* disable dynpm */
416 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
417 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
3f53eb6f 418 rdev->pm.pm_method = PM_METHOD_PROFILE;
ce8f5370 419 mutex_unlock(&rdev->pm.mutex);
3f53eb6f
RW		 420 if (flush_wq)
421 flush_workqueue(rdev->wq);
ce8f5370
AD		 422 } else {
423 DRM_ERROR("invalid power method!\n");
424 goto fail;
425 }
426 radeon_pm_compute_clocks(rdev);
427fail:
a424816f
AD		 428 return count;
429}
430
ce8f5370
AD		 431static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
432static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
a424816f 433
21a8122a
AD		 434static ssize_t radeon_hwmon_show_temp(struct device *dev,
435 struct device_attribute *attr,
436 char *buf)
437{
438 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
439 struct radeon_device *rdev = ddev->dev_private;
440 u32 temp;
441
442 switch (rdev->pm.int_thermal_type) {
443 case THERMAL_TYPE_RV6XX:
444 temp = rv6xx_get_temp(rdev);
445 break;
446 case THERMAL_TYPE_RV770:
447 temp = rv770_get_temp(rdev);
448 break;
449 case THERMAL_TYPE_EVERGREEN:
450 temp = evergreen_get_temp(rdev);
451 break;
452 default:
453 temp = 0;
454 break;
455 }
456
457 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
458}
459
460static ssize_t radeon_hwmon_show_name(struct device *dev,
461 struct device_attribute *attr,
462 char *buf)
463{
464 return sprintf(buf, "radeon\n");
465}
466
467static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
468static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
469
470static struct attribute *hwmon_attributes[] = {
471 &sensor_dev_attr_temp1_input.dev_attr.attr,
472 &sensor_dev_attr_name.dev_attr.attr,
473 NULL
474};
475
476static const struct attribute_group hwmon_attrgroup = {
477 .attrs = hwmon_attributes,
478};
479
0d18abed 480static int radeon_hwmon_init(struct radeon_device *rdev)
21a8122a 481{
0d18abed 482 int err = 0;
21a8122a
AD		 483
484 rdev->pm.int_hwmon_dev = NULL;
485
486 switch (rdev->pm.int_thermal_type) {
487 case THERMAL_TYPE_RV6XX:
488 case THERMAL_TYPE_RV770:
489 case THERMAL_TYPE_EVERGREEN:
490 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
0d18abed
DC		 491 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
492 err = PTR_ERR(rdev->pm.int_hwmon_dev);
493 dev_err(rdev->dev,
494 "Unable to register hwmon device: %d\n", err);
495 break;
496 }
21a8122a
AD		 497 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
498 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
499 &hwmon_attrgroup);
0d18abed
DC		 500 if (err) {
501 dev_err(rdev->dev,
502 "Unable to create hwmon sysfs file: %d\n", err);
503 hwmon_device_unregister(rdev->dev);
504 }
21a8122a
AD		 505 break;
506 default:
507 break;
508 }
0d18abed
DC		 509
510 return err;
21a8122a
AD		 511}
512
513static void radeon_hwmon_fini(struct radeon_device *rdev)
514{
515 if (rdev->pm.int_hwmon_dev) {
516 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup);
517 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
518 }
519}
520
ce8f5370 521void radeon_pm_suspend(struct radeon_device *rdev)
56278a8e 522{
3f53eb6f
RW		 523 bool flush_wq = false;
524
ce8f5370 525 mutex_lock(&rdev->pm.mutex);
3f53eb6f
RW		 526 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
527 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
528 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
529 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
530 flush_wq = true;
531 }
ce8f5370 532 mutex_unlock(&rdev->pm.mutex);
3f53eb6f
RW		 533 if (flush_wq)
534 flush_workqueue(rdev->wq);
56278a8e
AD		 535}
536
ce8f5370 537void radeon_pm_resume(struct radeon_device *rdev)
d0d6cb81 538{
f8ed8b4c
AD		 539 /* asic init will reset the default power state */
540 mutex_lock(&rdev->pm.mutex);
541 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
542 rdev->pm.current_clock_mode_index = 0;
543 rdev->pm.current_sclk = rdev->clock.default_sclk;
544 rdev->pm.current_mclk = rdev->clock.default_mclk;
4d60173f 545 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
3f53eb6f
RW		 546 if (rdev->pm.pm_method == PM_METHOD_DYNPM
547 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
548 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
549 queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
550 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
551 }
f8ed8b4c 552 mutex_unlock(&rdev->pm.mutex);
ce8f5370 553 radeon_pm_compute_clocks(rdev);
d0d6cb81
RM		 554}
555
7433874e
RM		 556int radeon_pm_init(struct radeon_device *rdev)
557{
26481fb1 558 int ret;
0d18abed 559
ce8f5370
AD		 560 /* default to profile method */
561 rdev->pm.pm_method = PM_METHOD_PROFILE;
f8ed8b4c 562 rdev->pm.profile = PM_PROFILE_DEFAULT;
ce8f5370
AD		 563 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
564 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
565 rdev->pm.dynpm_can_upclock = true;
566 rdev->pm.dynpm_can_downclock = true;
f8ed8b4c
AD		 567 rdev->pm.current_sclk = rdev->clock.default_sclk;
568 rdev->pm.current_mclk = rdev->clock.default_mclk;
21a8122a 569 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
c913e23a 570
56278a8e
AD		 571 if (rdev->bios) {
572 if (rdev->is_atom_bios)
573 radeon_atombios_get_power_modes(rdev);
574 else
575 radeon_combios_get_power_modes(rdev);
f712d0c7 576 radeon_pm_print_states(rdev);
ce8f5370 577 radeon_pm_init_profile(rdev);
56278a8e
AD		 578 }
579
21a8122a 580 /* set up the internal thermal sensor if applicable */
0d18abed
DC		 581 ret = radeon_hwmon_init(rdev);
582 if (ret)
583 return ret;
ce8f5370 584 if (rdev->pm.num_power_states > 1) {
ce8f5370 585 /* where's the best place to put these? */
26481fb1
DA		 586 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
587 if (ret)
588 DRM_ERROR("failed to create device file for power profile\n");
589 ret = device_create_file(rdev->dev, &dev_attr_power_method);
590 if (ret)
591 DRM_ERROR("failed to create device file for power method\n");
a424816f 592
ce8f5370
AD		 593#ifdef CONFIG_ACPI
594 rdev->acpi_nb.notifier_call = radeon_acpi_event;
595 register_acpi_notifier(&rdev->acpi_nb);
596#endif
597 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
c913e23a 598
ce8f5370
AD		 599 if (radeon_debugfs_pm_init(rdev)) {
600 DRM_ERROR("Failed to register debugfs file for PM!\n");
601 }
c913e23a 602
ce8f5370
AD		 603 DRM_INFO("radeon: power management initialized\n");
604 }
c913e23a 605
7433874e
RM		 606 return 0;
607}
608
29fb52ca
AD		 609void radeon_pm_fini(struct radeon_device *rdev)
610{
ce8f5370 611 if (rdev->pm.num_power_states > 1) {
3f53eb6f
RW		 612 bool flush_wq = false;
613
a424816f 614 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 615 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
616 rdev->pm.profile = PM_PROFILE_DEFAULT;
617 radeon_pm_update_profile(rdev);
618 radeon_pm_set_clocks(rdev);
619 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
620 /* cancel work */
3f53eb6f
RW		 621 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
622 flush_wq = true;
ce8f5370
AD		 623 /* reset default clocks */
624 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
625 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
626 radeon_pm_set_clocks(rdev);
627 }
a424816f 628 mutex_unlock(&rdev->pm.mutex);
3f53eb6f
RW		 629 if (flush_wq)
630 flush_workqueue(rdev->wq);
58e21dff 631
ce8f5370
AD		 632 device_remove_file(rdev->dev, &dev_attr_power_profile);
633 device_remove_file(rdev->dev, &dev_attr_power_method);
634#ifdef CONFIG_ACPI
635 unregister_acpi_notifier(&rdev->acpi_nb);
636#endif
637 }
a424816f 638
21a8122a 639 radeon_hwmon_fini(rdev);
29fb52ca
AD		 640}
641
c913e23a
RM		 642void radeon_pm_compute_clocks(struct radeon_device *rdev)
643{
644 struct drm_device *ddev = rdev->ddev;
a48b9b4e 645 struct drm_crtc *crtc;
c913e23a 646 struct radeon_crtc *radeon_crtc;
c913e23a 647
ce8f5370
AD		 648 if (rdev->pm.num_power_states < 2)
649 return;
650
c913e23a
RM		 651 mutex_lock(&rdev->pm.mutex);
652
653 rdev->pm.active_crtcs = 0;
a48b9b4e
AD		 654 rdev->pm.active_crtc_count = 0;
655 list_for_each_entry(crtc,
656 &ddev->mode_config.crtc_list, head) {
657 radeon_crtc = to_radeon_crtc(crtc);
658 if (radeon_crtc->enabled) {
c913e23a 659 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
a48b9b4e 660 rdev->pm.active_crtc_count++;
c913e23a
RM		 661 }
662 }
663
ce8f5370
AD		 664 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
665 radeon_pm_update_profile(rdev);
666 radeon_pm_set_clocks(rdev);
667 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
668 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
669 if (rdev->pm.active_crtc_count > 1) {
670 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
671 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
672
673 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
674 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
675 radeon_pm_get_dynpm_state(rdev);
676 radeon_pm_set_clocks(rdev);
677
d9fdaafb 678 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
ce8f5370
AD		 679 }
680 } else if (rdev->pm.active_crtc_count == 1) {
681 /* TODO: Increase clocks if needed for current mode */
682
683 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
684 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
685 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
686 radeon_pm_get_dynpm_state(rdev);
687 radeon_pm_set_clocks(rdev);
688
689 queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
690 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
691 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
692 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
693 queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
694 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
d9fdaafb 695 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
ce8f5370
AD		 696 }
697 } else { /* count == 0 */
698 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
699 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
700
701 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
702 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
703 radeon_pm_get_dynpm_state(rdev);
704 radeon_pm_set_clocks(rdev);
705 }
706 }
c913e23a 707 }
c913e23a 708 }
73a6d3fc
RM		 709
710 mutex_unlock(&rdev->pm.mutex);
c913e23a
RM		 711}
712
ce8f5370 713static bool radeon_pm_in_vbl(struct radeon_device *rdev)
f735261b 714{
539d2418 715 u32 stat_crtc = 0, vbl = 0, position = 0;
f735261b
DA		 716 bool in_vbl = true;
717
bae6b562
AD		 718 if (ASIC_IS_DCE4(rdev)) {
719 if (rdev->pm.active_crtcs & (1 << 0)) {
539d2418
AD		 720 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
721 EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
722 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
723 EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
bae6b562
AD		 724 }
725 if (rdev->pm.active_crtcs & (1 << 1)) {
539d2418
AD		 726 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
727 EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
728 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
729 EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
bae6b562
AD		 730 }
731 if (rdev->pm.active_crtcs & (1 << 2)) {
539d2418
AD		 732 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
733 EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
734 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
735 EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
bae6b562
AD		 736 }
737 if (rdev->pm.active_crtcs & (1 << 3)) {
539d2418
AD		 738 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
739 EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
740 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
741 EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
bae6b562
AD		 742 }
743 if (rdev->pm.active_crtcs & (1 << 4)) {
539d2418
AD		 744 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
745 EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
746 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
747 EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
bae6b562
AD		 748 }
749 if (rdev->pm.active_crtcs & (1 << 5)) {
539d2418
AD		 750 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
751 EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
752 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
753 EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
bae6b562
AD		 754 }
755 } else if (ASIC_IS_AVIVO(rdev)) {
756 if (rdev->pm.active_crtcs & (1 << 0)) {
539d2418
AD		 757 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END) & 0xfff;
758 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION) & 0xfff;
bae6b562
AD		 759 }
760 if (rdev->pm.active_crtcs & (1 << 1)) {
539d2418
AD		 761 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END) & 0xfff;
762 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION) & 0xfff;
bae6b562 763 }
539d2418
AD		 764 if (position < vbl && position > 1)
765 in_vbl = false;
bae6b562 766 } else {
f735261b 767 if (rdev->pm.active_crtcs & (1 << 0)) {
bae6b562
AD		 768 stat_crtc = RREG32(RADEON_CRTC_STATUS);
769 if (!(stat_crtc & 1))
f735261b
DA		 770 in_vbl = false;
771 }
772 if (rdev->pm.active_crtcs & (1 << 1)) {
bae6b562
AD		 773 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
774 if (!(stat_crtc & 1))
f735261b
DA		 775 in_vbl = false;
776 }
777 }
f81f2024 778
539d2418
AD		 779 if (position < vbl && position > 1)
780 in_vbl = false;
781
f81f2024
MG		 782 return in_vbl;
783}
784
ce8f5370 785static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
f81f2024
MG		 786{
787 u32 stat_crtc = 0;
788 bool in_vbl = radeon_pm_in_vbl(rdev);
789
f735261b 790 if (in_vbl == false)
d9fdaafb 791 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
bae6b562 792 finish ? "exit" : "entry");
f735261b
DA		 793 return in_vbl;
794}
c913e23a 795
ce8f5370 796static void radeon_dynpm_idle_work_handler(struct work_struct *work)
c913e23a
RM		 797{
798 struct radeon_device *rdev;
d9932a32 799 int resched;
c913e23a 800 rdev = container_of(work, struct radeon_device,
ce8f5370 801 pm.dynpm_idle_work.work);
c913e23a 802
d9932a32 803 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
c913e23a 804 mutex_lock(&rdev->pm.mutex);
ce8f5370 805 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
c913e23a
RM		 806 unsigned long irq_flags;
807 int not_processed = 0;
808
809 read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
810 if (!list_empty(&rdev->fence_drv.emited)) {
811 struct list_head *ptr;
812 list_for_each(ptr, &rdev->fence_drv.emited) {
813 /* count up to 3, that's enought info */
814 if (++not_processed >= 3)
815 break;
816 }
817 }
818 read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
819
820 if (not_processed >= 3) { /* should upclock */
ce8f5370
AD		 821 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
822 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
823 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
824 rdev->pm.dynpm_can_upclock) {
825 rdev->pm.dynpm_planned_action =
826 DYNPM_ACTION_UPCLOCK;
827 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 828 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
829 }
830 } else if (not_processed == 0) { /* should downclock */
ce8f5370
AD		 831 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
832 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
833 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
834 rdev->pm.dynpm_can_downclock) {
835 rdev->pm.dynpm_planned_action =
836 DYNPM_ACTION_DOWNCLOCK;
837 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 838 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
839 }
840 }
841
d7311171
AD		 842 /* Note, radeon_pm_set_clocks is called with static_switch set
843 * to false since we want to wait for vbl to avoid flicker.
844 */
ce8f5370
AD		 845 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
846 jiffies > rdev->pm.dynpm_action_timeout) {
847 radeon_pm_get_dynpm_state(rdev);
848 radeon_pm_set_clocks(rdev);
c913e23a 849 }
3f53eb6f
RW		 850
851 queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
852 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
c913e23a
RM		 853 }
854 mutex_unlock(&rdev->pm.mutex);
d9932a32 855 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
c913e23a
RM		 856}
857
7433874e
RM		 858/*
859 * Debugfs info
860 */
861#if defined(CONFIG_DEBUG_FS)
862
863static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
864{
865 struct drm_info_node *node = (struct drm_info_node *) m->private;
866 struct drm_device *dev = node->minor->dev;
867 struct radeon_device *rdev = dev->dev_private;
868
6234077d
RM		 869 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
870 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
871 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
872 if (rdev->asic->get_memory_clock)
873 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
0fcbe947
RM		 874 if (rdev->pm.current_vddc)
875 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
aa5120d2
RM		 876 if (rdev->asic->get_pcie_lanes)
877 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
7433874e
RM		 878
879 return 0;
880}
881
882static struct drm_info_list radeon_pm_info_list[] = {
883 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
884};
885#endif
886
c913e23a 887static int radeon_debugfs_pm_init(struct radeon_device *rdev)
7433874e
RM		 888{
889#if defined(CONFIG_DEBUG_FS)
890 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
891#else
892 return 0;
893#endif
894}
Clone of davem's net-next-2.6 tree