[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_object.c

/*
 * Copyright 2009 Jerome Glisse.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 */
/*
 * Authors:
 *    Jerome Glisse <glisse@freedesktop.org>
 *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
 *    Dave Airlie
 */
#include <linux/list.h>
#include <linux/slab.h>
#include <drm/drmP.h>
#include "radeon_drm.h"
#include "radeon.h"


int radeon_ttm_init(struct radeon_device *rdev);
void radeon_ttm_fini(struct radeon_device *rdev);
static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);

/*
 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
 * function are calling it.
 */

static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
{
	struct radeon_bo *bo;

	bo = container_of(tbo, struct radeon_bo, tbo);
	mutex_lock(&bo->rdev->gem.mutex);
	list_del_init(&bo->list);
	mutex_unlock(&bo->rdev->gem.mutex);
	radeon_bo_clear_surface_reg(bo);
	kfree(bo);
}

bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
{
	if (bo->destroy == &radeon_ttm_bo_destroy)
		return true;
	return false;
}

void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
{
	u32 c = 0;

	rbo->placement.fpfn = 0;
	rbo->placement.lpfn = rbo->rdev->mc.active_vram_size >> PAGE_SHIFT;
	rbo->placement.placement = rbo->placements;
	rbo->placement.busy_placement = rbo->placements;
	if (domain & RADEON_GEM_DOMAIN_VRAM)
		rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
					TTM_PL_FLAG_VRAM;
	if (domain & RADEON_GEM_DOMAIN_GTT)
		rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
	if (domain & RADEON_GEM_DOMAIN_CPU)
		rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
	if (!c)
		rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
	rbo->placement.num_placement = c;
	rbo->placement.num_busy_placement = c;
}

int radeon_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj,
			unsigned long size, bool kernel, u32 domain,
			struct radeon_bo **bo_ptr)
{
	struct radeon_bo *bo;
	enum ttm_bo_type type;
	int r;

	if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
		rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
	}
	if (kernel) {
		type = ttm_bo_type_kernel;
	} else {
		type = ttm_bo_type_device;
	}
	*bo_ptr = NULL;
	bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
	if (bo == NULL)
		return -ENOMEM;
	bo->rdev = rdev;
	bo->gobj = gobj;
	bo->surface_reg = -1;
	INIT_LIST_HEAD(&bo->list);

retry:
	radeon_ttm_placement_from_domain(bo, domain);
	/* Kernel allocation are uninterruptible */
	mutex_lock(&rdev->vram_mutex);
	r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
			&bo->placement, 0, 0, !kernel, NULL, size,
			&radeon_ttm_bo_destroy);
	mutex_unlock(&rdev->vram_mutex);
	if (unlikely(r != 0)) {
		if (r != -ERESTARTSYS) {
			if (domain == RADEON_GEM_DOMAIN_VRAM) {
				domain |= RADEON_GEM_DOMAIN_GTT;
				goto retry;
			}
			dev_err(rdev->dev,
				"object_init failed for (%lu, 0x%08X)\n",
				size, domain);
		}
		return r;
	}
	*bo_ptr = bo;
	if (gobj) {
		mutex_lock(&bo->rdev->gem.mutex);
		list_add_tail(&bo->list, &rdev->gem.objects);
		mutex_unlock(&bo->rdev->gem.mutex);
	}
	return 0;
}

int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
{
	bool is_iomem;
	int r;

	if (bo->kptr) {
		if (ptr) {
			*ptr = bo->kptr;
		}
		return 0;
	}
	r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
	if (r) {
		return r;
	}
	bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
	if (ptr) {
		*ptr = bo->kptr;
	}
	radeon_bo_check_tiling(bo, 0, 0);
	return 0;
}

void radeon_bo_kunmap(struct radeon_bo *bo)
{
	if (bo->kptr == NULL)
		return;
	bo->kptr = NULL;
	radeon_bo_check_tiling(bo, 0, 0);
	ttm_bo_kunmap(&bo->kmap);
}

void radeon_bo_unref(struct radeon_bo **bo)
{
	struct ttm_buffer_object *tbo;
	struct radeon_device *rdev;

	if ((*bo) == NULL)
		return;
	rdev = (*bo)->rdev;
	tbo = &((*bo)->tbo);
	mutex_lock(&rdev->vram_mutex);
	ttm_bo_unref(&tbo);
	mutex_unlock(&rdev->vram_mutex);
	if (tbo == NULL)
		*bo = NULL;
}

int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
{
	int r, i;

	if (bo->pin_count) {
		bo->pin_count++;
		if (gpu_addr)
			*gpu_addr = radeon_bo_gpu_offset(bo);
		return 0;
	}
	radeon_ttm_placement_from_domain(bo, domain);
	if (domain == RADEON_GEM_DOMAIN_VRAM) {
		/* force to pin into visible video ram */
		bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
	}
	for (i = 0; i < bo->placement.num_placement; i++)
		bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
	if (likely(r == 0)) {
		bo->pin_count = 1;
		if (gpu_addr != NULL)
			*gpu_addr = radeon_bo_gpu_offset(bo);
	}
	if (unlikely(r != 0))
		dev_err(bo->rdev->dev, "%p pin failed\n", bo);
	return r;
}

int radeon_bo_unpin(struct radeon_bo *bo)
{
	int r, i;

	if (!bo->pin_count) {
		dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
		return 0;
	}
	bo->pin_count--;
	if (bo->pin_count)
		return 0;
	for (i = 0; i < bo->placement.num_placement; i++)
		bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
	if (unlikely(r != 0))
		dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
	return r;
}

int radeon_bo_evict_vram(struct radeon_device *rdev)
{
	/* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
	if (0 && (rdev->flags & RADEON_IS_IGP)) {
		if (rdev->mc.igp_sideport_enabled == false)
			/* Useless to evict on IGP chips */
			return 0;
	}
	return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
}

void radeon_bo_force_delete(struct radeon_device *rdev)
{
	struct radeon_bo *bo, *n;
	struct drm_gem_object *gobj;

	if (list_empty(&rdev->gem.objects)) {
		return;
	}
	dev_err(rdev->dev, "Userspace still has active objects !\n");
	list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
		mutex_lock(&rdev->ddev->struct_mutex);
		gobj = bo->gobj;
		dev_err(rdev->dev, "%p %p %lu %lu force free\n",
			gobj, bo, (unsigned long)gobj->size,
			*((unsigned long *)&gobj->refcount));
		mutex_lock(&bo->rdev->gem.mutex);
		list_del_init(&bo->list);
		mutex_unlock(&bo->rdev->gem.mutex);
		radeon_bo_unref(&bo);
		gobj->driver_private = NULL;
		drm_gem_object_unreference(gobj);
		mutex_unlock(&rdev->ddev->struct_mutex);
	}
}

int radeon_bo_init(struct radeon_device *rdev)
{
	/* Add an MTRR for the VRAM */
	rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
			MTRR_TYPE_WRCOMB, 1);
	DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
		rdev->mc.mc_vram_size >> 20,
		(unsigned long long)rdev->mc.aper_size >> 20);
	DRM_INFO("RAM width %dbits %cDR\n",
			rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
	return radeon_ttm_init(rdev);
}

void radeon_bo_fini(struct radeon_device *rdev)
{
	radeon_ttm_fini(rdev);
}

void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
				struct list_head *head)
{
	if (lobj->wdomain) {
		list_add(&lobj->list, head);
	} else {
		list_add_tail(&lobj->list, head);
	}
}

int radeon_bo_list_reserve(struct list_head *head)
{
	struct radeon_bo_list *lobj;
	int r;

	list_for_each_entry(lobj, head, list){
		r = radeon_bo_reserve(lobj->bo, false);
		if (unlikely(r != 0))
			return r;
		lobj->reserved = true;
	}
	return 0;
}

void radeon_bo_list_unreserve(struct list_head *head)
{
	struct radeon_bo_list *lobj;

	list_for_each_entry(lobj, head, list) {
		/* only unreserve object we successfully reserved */
		if (lobj->reserved && radeon_bo_is_reserved(lobj->bo))
			radeon_bo_unreserve(lobj->bo);
	}
}

int radeon_bo_list_validate(struct list_head *head)
{
	struct radeon_bo_list *lobj;
	struct radeon_bo *bo;
	u32 domain;
	int r;

	list_for_each_entry(lobj, head, list) {
		lobj->reserved = false;
	}
	r = radeon_bo_list_reserve(head);
	if (unlikely(r != 0)) {
		return r;
	}
	list_for_each_entry(lobj, head, list) {
		bo = lobj->bo;
		if (!bo->pin_count) {
			domain = lobj->wdomain ? lobj->wdomain : lobj->rdomain;
			
		retry:
			radeon_ttm_placement_from_domain(bo, domain);
			r = ttm_bo_validate(&bo->tbo, &bo->placement,
						true, false, false);
			if (unlikely(r)) {
				if (r != -ERESTARTSYS && domain == RADEON_GEM_DOMAIN_VRAM) {
					domain |= RADEON_GEM_DOMAIN_GTT;
					goto retry;
				}
				return r;
			}
		}
		lobj->gpu_offset = radeon_bo_gpu_offset(bo);
		lobj->tiling_flags = bo->tiling_flags;
	}
	return 0;
}

void radeon_bo_list_fence(struct list_head *head, void *fence)
{
	struct radeon_bo_list *lobj;
	struct radeon_bo *bo;
	struct radeon_fence *old_fence = NULL;

	list_for_each_entry(lobj, head, list) {
		bo = lobj->bo;
		spin_lock(&bo->tbo.lock);
		old_fence = (struct radeon_fence *)bo->tbo.sync_obj;
		bo->tbo.sync_obj = radeon_fence_ref(fence);
		bo->tbo.sync_obj_arg = NULL;
		spin_unlock(&bo->tbo.lock);
		if (old_fence) {
			radeon_fence_unref(&old_fence);
		}
	}
}

int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
			     struct vm_area_struct *vma)
{
	return ttm_fbdev_mmap(vma, &bo->tbo);
}

int radeon_bo_get_surface_reg(struct radeon_bo *bo)
{
	struct radeon_device *rdev = bo->rdev;
	struct radeon_surface_reg *reg;
	struct radeon_bo *old_object;
	int steal;
	int i;

	BUG_ON(!atomic_read(&bo->tbo.reserved));

	if (!bo->tiling_flags)
		return 0;

	if (bo->surface_reg >= 0) {
		reg = &rdev->surface_regs[bo->surface_reg];
		i = bo->surface_reg;
		goto out;
	}

	steal = -1;
	for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {

		reg = &rdev->surface_regs[i];
		if (!reg->bo)
			break;

		old_object = reg->bo;
		if (old_object->pin_count == 0)
			steal = i;
	}

	/* if we are all out */
	if (i == RADEON_GEM_MAX_SURFACES) {
		if (steal == -1)
			return -ENOMEM;
		/* find someone with a surface reg and nuke their BO */
		reg = &rdev->surface_regs[steal];
		old_object = reg->bo;
		/* blow away the mapping */
		DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
		ttm_bo_unmap_virtual(&old_object->tbo);
		old_object->surface_reg = -1;
		i = steal;
	}

	bo->surface_reg = i;
	reg->bo = bo;

out:
	radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
			       bo->tbo.mem.mm_node->start << PAGE_SHIFT,
			       bo->tbo.num_pages << PAGE_SHIFT);
	return 0;
}

static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
{
	struct radeon_device *rdev = bo->rdev;
	struct radeon_surface_reg *reg;

	if (bo->surface_reg == -1)
		return;

	reg = &rdev->surface_regs[bo->surface_reg];
	radeon_clear_surface_reg(rdev, bo->surface_reg);

	reg->bo = NULL;
	bo->surface_reg = -1;
}

int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
				uint32_t tiling_flags, uint32_t pitch)
{
	int r;

	r = radeon_bo_reserve(bo, false);
	if (unlikely(r != 0))
		return r;
	bo->tiling_flags = tiling_flags;
	bo->pitch = pitch;
	radeon_bo_unreserve(bo);
	return 0;
}

void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
				uint32_t *tiling_flags,
				uint32_t *pitch)
{
	BUG_ON(!atomic_read(&bo->tbo.reserved));
	if (tiling_flags)
		*tiling_flags = bo->tiling_flags;
	if (pitch)
		*pitch = bo->pitch;
}

int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
				bool force_drop)
{
	BUG_ON(!atomic_read(&bo->tbo.reserved));

	if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
		return 0;

	if (force_drop) {
		radeon_bo_clear_surface_reg(bo);
		return 0;
	}

	if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
		if (!has_moved)
			return 0;

		if (bo->surface_reg >= 0)
			radeon_bo_clear_surface_reg(bo);
		return 0;
	}

	if ((bo->surface_reg >= 0) && !has_moved)
		return 0;

	return radeon_bo_get_surface_reg(bo);
}

void radeon_bo_move_notify(struct ttm_buffer_object *bo,
			   struct ttm_mem_reg *mem)
{
	struct radeon_bo *rbo;
	if (!radeon_ttm_bo_is_radeon_bo(bo))
		return;
	rbo = container_of(bo, struct radeon_bo, tbo);
	radeon_bo_check_tiling(rbo, 0, 1);
}

int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
{
	struct radeon_device *rdev;
	struct radeon_bo *rbo;
	unsigned long offset, size;
	int r;

	if (!radeon_ttm_bo_is_radeon_bo(bo))
		return 0;
	rbo = container_of(bo, struct radeon_bo, tbo);
	radeon_bo_check_tiling(rbo, 0, 0);
	rdev = rbo->rdev;
	if (bo->mem.mem_type == TTM_PL_VRAM) {
		size = bo->mem.num_pages << PAGE_SHIFT;
		offset = bo->mem.mm_node->start << PAGE_SHIFT;
		if ((offset + size) > rdev->mc.visible_vram_size) {
			/* hurrah the memory is not visible ! */
			radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
			rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
			r = ttm_bo_validate(bo, &rbo->placement, false, true, false);
			if (unlikely(r != 0))
				return r;
			offset = bo->mem.mm_node->start << PAGE_SHIFT;
			/* this should not happen */
			if ((offset + size) > rdev->mc.visible_vram_size)
				return -EINVAL;
		}
	}
	return 0;
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2009 Jerome Glisse.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the
	7	* "Software"), to deal in the Software without restriction, including
	8	* without limitation the rights to use, copy, modify, merge, publish,
	9	* distribute, sub license, and/or sell copies of the Software, and to
	10	* permit persons to whom the Software is furnished to do so, subject to
	11	* the following conditions:
	12	*
	13	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	14	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	15	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
	16	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
	17	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
	18	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
	19	* USE OR OTHER DEALINGS IN THE SOFTWARE.
	20	*
	21	* The above copyright notice and this permission notice (including the
	22	* next paragraph) shall be included in all copies or substantial portions
	23	* of the Software.
	24	*
	25	*/
	26	/*
	27	* Authors:
	28	* Jerome Glisse <glisse@freedesktop.org>
	29	* Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
	30	* Dave Airlie
	31	*/
	32	#include <linux/list.h>
5a0e3ad6	33	#include <linux/slab.h>
771fe6b9 JG	34	#include <drm/drmP.h>
	35	#include "radeon_drm.h"
	36	#include "radeon.h"
	37
771fe6b9 JG	38
	39	int radeon_ttm_init(struct radeon_device *rdev);
	40	void radeon_ttm_fini(struct radeon_device *rdev);
4c788679	41	static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
771fe6b9 JG	42
	43	/*
	44	* To exclude mutual BO access we rely on bo_reserve exclusion, as all
	45	* function are calling it.
	46	*/
	47
4c788679	48	static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
771fe6b9	49	{
4c788679	50	struct radeon_bo *bo;
771fe6b9	51
4c788679 JG	52	bo = container_of(tbo, struct radeon_bo, tbo);
	53	mutex_lock(&bo->rdev->gem.mutex);
	54	list_del_init(&bo->list);
	55	mutex_unlock(&bo->rdev->gem.mutex);
	56	radeon_bo_clear_surface_reg(bo);
	57	kfree(bo);
771fe6b9 JG	58	}
771fe6b9 JG	59
d03d8589 JG	60	bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
	61	{
	62	if (bo->destroy == &radeon_ttm_bo_destroy)
	63	return true;
	64	return false;
	65	}
	66
312ea8da JG	67	void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
	68	{
	69	u32 c = 0;
	70
	71	rbo->placement.fpfn = 0;
c919b371	72	rbo->placement.lpfn = rbo->rdev->mc.active_vram_size >> PAGE_SHIFT;
312ea8da JG	73	rbo->placement.placement = rbo->placements;
	74	rbo->placement.busy_placement = rbo->placements;
	75	if (domain & RADEON_GEM_DOMAIN_VRAM)
	76	rbo->placements[c++] = TTM_PL_FLAG_WC \| TTM_PL_FLAG_UNCACHED \|
	77	TTM_PL_FLAG_VRAM;
	78	if (domain & RADEON_GEM_DOMAIN_GTT)
	79	rbo->placements[c++] = TTM_PL_MASK_CACHING \| TTM_PL_FLAG_TT;
	80	if (domain & RADEON_GEM_DOMAIN_CPU)
	81	rbo->placements[c++] = TTM_PL_MASK_CACHING \| TTM_PL_FLAG_SYSTEM;
9fb03e63 JG	82	if (!c)
9fb03e63 JG	83	rbo->placements[c++] = TTM_PL_MASK_CACHING \| TTM_PL_FLAG_SYSTEM;
312ea8da JG	84	rbo->placement.num_placement = c;
	85	rbo->placement.num_busy_placement = c;
	86	}
	87
4c788679 JG	88	int radeon_bo_create(struct radeon_device rdev, struct drm_gem_object gobj,
	89	unsigned long size, bool kernel, u32 domain,
	90	struct radeon_bo **bo_ptr)
771fe6b9	91	{
4c788679	92	struct radeon_bo *bo;
771fe6b9	93	enum ttm_bo_type type;
771fe6b9 JG	94	int r;
	95
	96	if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
	97	rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
	98	}
	99	if (kernel) {
	100	type = ttm_bo_type_kernel;
	101	} else {
	102	type = ttm_bo_type_device;
	103	}
4c788679 JG	104	*bo_ptr = NULL;
	105	bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
	106	if (bo == NULL)
771fe6b9	107	return -ENOMEM;
4c788679 JG	108	bo->rdev = rdev;
	109	bo->gobj = gobj;
	110	bo->surface_reg = -1;
	111	INIT_LIST_HEAD(&bo->list);
	112
e376573f	113	retry:
1fb107fc	114	radeon_ttm_placement_from_domain(bo, domain);
5cc6fbab	115	/* Kernel allocation are uninterruptible */
5876dd24	116	mutex_lock(&rdev->vram_mutex);
1fb107fc JG	117	r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
	118	&bo->placement, 0, 0, !kernel, NULL, size,
	119	&radeon_ttm_bo_destroy);
5876dd24	120	mutex_unlock(&rdev->vram_mutex);
771fe6b9	121	if (unlikely(r != 0)) {
e376573f MD	122	if (r != -ERESTARTSYS) {
	123	if (domain == RADEON_GEM_DOMAIN_VRAM) {
	124	domain \|= RADEON_GEM_DOMAIN_GTT;
	125	goto retry;
	126	}
5cc6fbab	127	dev_err(rdev->dev,
1fb107fc JG	128	"object_init failed for (%lu, 0x%08X)\n",
1fb107fc JG	129	size, domain);
e376573f	130	}
771fe6b9 JG	131	return r;
771fe6b9 JG	132	}
4c788679	133	*bo_ptr = bo;
771fe6b9	134	if (gobj) {
4c788679 JG	135	mutex_lock(&bo->rdev->gem.mutex);
	136	list_add_tail(&bo->list, &rdev->gem.objects);
	137	mutex_unlock(&bo->rdev->gem.mutex);
771fe6b9 JG	138	}
	139	return 0;
	140	}
	141
4c788679	142	int radeon_bo_kmap(struct radeon_bo bo, void *ptr)
771fe6b9	143	{
4c788679	144	bool is_iomem;
771fe6b9 JG	145	int r;
771fe6b9 JG	146
4c788679	147	if (bo->kptr) {
771fe6b9	148	if (ptr) {
4c788679	149	*ptr = bo->kptr;
771fe6b9	150	}
771fe6b9 JG	151	return 0;
771fe6b9 JG	152	}
4c788679	153	r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
771fe6b9 JG	154	if (r) {
	155	return r;
	156	}
4c788679	157	bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
771fe6b9	158	if (ptr) {
4c788679	159	*ptr = bo->kptr;
771fe6b9	160	}
4c788679	161	radeon_bo_check_tiling(bo, 0, 0);
771fe6b9 JG	162	return 0;
	163	}
	164
4c788679	165	void radeon_bo_kunmap(struct radeon_bo *bo)
771fe6b9	166	{
4c788679	167	if (bo->kptr == NULL)
771fe6b9	168	return;
4c788679 JG	169	bo->kptr = NULL;
	170	radeon_bo_check_tiling(bo, 0, 0);
	171	ttm_bo_kunmap(&bo->kmap);
771fe6b9 JG	172	}
771fe6b9 JG	173
4c788679	174	void radeon_bo_unref(struct radeon_bo **bo)
771fe6b9	175	{
4c788679	176	struct ttm_buffer_object *tbo;
f4b7fb94	177	struct radeon_device *rdev;
771fe6b9	178
4c788679	179	if ((*bo) == NULL)
771fe6b9	180	return;
f4b7fb94	181	rdev = (*bo)->rdev;
4c788679	182	tbo = &((*bo)->tbo);
f4b7fb94	183	mutex_lock(&rdev->vram_mutex);
4c788679	184	ttm_bo_unref(&tbo);
f4b7fb94	185	mutex_unlock(&rdev->vram_mutex);
4c788679 JG	186	if (tbo == NULL)
4c788679 JG	187	*bo = NULL;
771fe6b9 JG	188	}
771fe6b9 JG	189
4c788679	190	int radeon_bo_pin(struct radeon_bo bo, u32 domain, u64 gpu_addr)
771fe6b9	191	{
312ea8da	192	int r, i;
771fe6b9	193
4c788679 JG	194	if (bo->pin_count) {
	195	bo->pin_count++;
	196	if (gpu_addr)
	197	*gpu_addr = radeon_bo_gpu_offset(bo);
771fe6b9 JG	198	return 0;
771fe6b9 JG	199	}
312ea8da	200	radeon_ttm_placement_from_domain(bo, domain);
3ca82da3 MD	201	if (domain == RADEON_GEM_DOMAIN_VRAM) {
	202	/* force to pin into visible video ram */
	203	bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
	204	}
312ea8da JG	205	for (i = 0; i < bo->placement.num_placement; i++)
312ea8da JG	206	bo->placements[i] \|= TTM_PL_FLAG_NO_EVICT;
9d87fa21	207	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
4c788679 JG	208	if (likely(r == 0)) {
	209	bo->pin_count = 1;
	210	if (gpu_addr != NULL)
	211	*gpu_addr = radeon_bo_gpu_offset(bo);
771fe6b9	212	}
5cc6fbab	213	if (unlikely(r != 0))
4c788679	214	dev_err(bo->rdev->dev, "%p pin failed\n", bo);
771fe6b9 JG	215	return r;
	216	}
	217
4c788679	218	int radeon_bo_unpin(struct radeon_bo *bo)
771fe6b9	219	{
312ea8da	220	int r, i;
771fe6b9	221
4c788679 JG	222	if (!bo->pin_count) {
	223	dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
	224	return 0;
771fe6b9	225	}
4c788679 JG	226	bo->pin_count--;
	227	if (bo->pin_count)
	228	return 0;
312ea8da JG	229	for (i = 0; i < bo->placement.num_placement; i++)
312ea8da JG	230	bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
9d87fa21	231	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
5cc6fbab	232	if (unlikely(r != 0))
4c788679	233	dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
5cc6fbab	234	return r;
cefb87ef DA	235	}
cefb87ef DA	236
4c788679	237	int radeon_bo_evict_vram(struct radeon_device *rdev)
771fe6b9	238	{
d796d844 DA	239	/* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
d796d844 DA	240	if (0 && (rdev->flags & RADEON_IS_IGP)) {
06b6476d AD	241	if (rdev->mc.igp_sideport_enabled == false)
	242	/* Useless to evict on IGP chips */
	243	return 0;
771fe6b9 JG	244	}
	245	return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
	246	}
	247
4c788679	248	void radeon_bo_force_delete(struct radeon_device *rdev)
771fe6b9	249	{
4c788679	250	struct radeon_bo bo, n;
771fe6b9 JG	251	struct drm_gem_object *gobj;
	252
	253	if (list_empty(&rdev->gem.objects)) {
	254	return;
	255	}
4c788679 JG	256	dev_err(rdev->dev, "Userspace still has active objects !\n");
4c788679 JG	257	list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
771fe6b9	258	mutex_lock(&rdev->ddev->struct_mutex);
4c788679 JG	259	gobj = bo->gobj;
	260	dev_err(rdev->dev, "%p %p %lu %lu force free\n",
	261	gobj, bo, (unsigned long)gobj->size,
	262	((unsigned long )&gobj->refcount));
	263	mutex_lock(&bo->rdev->gem.mutex);
	264	list_del_init(&bo->list);
	265	mutex_unlock(&bo->rdev->gem.mutex);
	266	radeon_bo_unref(&bo);
771fe6b9 JG	267	gobj->driver_private = NULL;
	268	drm_gem_object_unreference(gobj);
	269	mutex_unlock(&rdev->ddev->struct_mutex);
	270	}
	271	}
	272
4c788679	273	int radeon_bo_init(struct radeon_device *rdev)
771fe6b9	274	{
a4d68279 JG	275	/* Add an MTRR for the VRAM */
	276	rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
	277	MTRR_TYPE_WRCOMB, 1);
	278	DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
	279	rdev->mc.mc_vram_size >> 20,
	280	(unsigned long long)rdev->mc.aper_size >> 20);
	281	DRM_INFO("RAM width %dbits %cDR\n",
	282	rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
771fe6b9 JG	283	return radeon_ttm_init(rdev);
	284	}
	285
4c788679	286	void radeon_bo_fini(struct radeon_device *rdev)
771fe6b9 JG	287	{
	288	radeon_ttm_fini(rdev);
	289	}
	290
4c788679 JG	291	void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
4c788679 JG	292	struct list_head *head)
771fe6b9 JG	293	{
	294	if (lobj->wdomain) {
	295	list_add(&lobj->list, head);
	296	} else {
	297	list_add_tail(&lobj->list, head);
	298	}
	299	}
	300
4c788679	301	int radeon_bo_list_reserve(struct list_head *head)
771fe6b9	302	{
4c788679	303	struct radeon_bo_list *lobj;
771fe6b9 JG	304	int r;
771fe6b9 JG	305
9d8401fc	306	list_for_each_entry(lobj, head, list){
4c788679 JG	307	r = radeon_bo_reserve(lobj->bo, false);
	308	if (unlikely(r != 0))
	309	return r;
e8652753	310	lobj->reserved = true;
771fe6b9 JG	311	}
	312	return 0;
	313	}
	314
4c788679	315	void radeon_bo_list_unreserve(struct list_head *head)
771fe6b9	316	{
4c788679	317	struct radeon_bo_list *lobj;
771fe6b9	318
9d8401fc	319	list_for_each_entry(lobj, head, list) {
4c788679	320	/* only unreserve object we successfully reserved */
e8652753	321	if (lobj->reserved && radeon_bo_is_reserved(lobj->bo))
4c788679	322	radeon_bo_unreserve(lobj->bo);
771fe6b9 JG	323	}
	324	}
	325
6cb8e1f7	326	int radeon_bo_list_validate(struct list_head *head)
771fe6b9	327	{
4c788679 JG	328	struct radeon_bo_list *lobj;
4c788679 JG	329	struct radeon_bo *bo;
e376573f	330	u32 domain;
771fe6b9 JG	331	int r;
771fe6b9 JG	332
e8652753 JG	333	list_for_each_entry(lobj, head, list) {
	334	lobj->reserved = false;
	335	}
4c788679	336	r = radeon_bo_list_reserve(head);
771fe6b9	337	if (unlikely(r != 0)) {
771fe6b9 JG	338	return r;
771fe6b9 JG	339	}
9d8401fc	340	list_for_each_entry(lobj, head, list) {
4c788679 JG	341	bo = lobj->bo;
4c788679 JG	342	if (!bo->pin_count) {
e376573f MD	343	domain = lobj->wdomain ? lobj->wdomain : lobj->rdomain;
	344
	345	retry:
	346	radeon_ttm_placement_from_domain(bo, domain);
1fb107fc	347	r = ttm_bo_validate(&bo->tbo, &bo->placement,
9d87fa21	348	true, false, false);
e376573f MD	349	if (unlikely(r)) {
	350	if (r != -ERESTARTSYS && domain == RADEON_GEM_DOMAIN_VRAM) {
	351	domain \|= RADEON_GEM_DOMAIN_GTT;
	352	goto retry;
	353	}
771fe6b9	354	return r;
e376573f	355	}
771fe6b9	356	}
4c788679 JG	357	lobj->gpu_offset = radeon_bo_gpu_offset(bo);
4c788679 JG	358	lobj->tiling_flags = bo->tiling_flags;
771fe6b9 JG	359	}
	360	return 0;
	361	}
	362
6cb8e1f7	363	void radeon_bo_list_fence(struct list_head head, void fence)
771fe6b9	364	{
4c788679	365	struct radeon_bo_list *lobj;
6cb8e1f7 JG	366	struct radeon_bo *bo;
	367	struct radeon_fence *old_fence = NULL;
	368
	369	list_for_each_entry(lobj, head, list) {
	370	bo = lobj->bo;
	371	spin_lock(&bo->tbo.lock);
	372	old_fence = (struct radeon_fence *)bo->tbo.sync_obj;
	373	bo->tbo.sync_obj = radeon_fence_ref(fence);
	374	bo->tbo.sync_obj_arg = NULL;
	375	spin_unlock(&bo->tbo.lock);
	376	if (old_fence) {
	377	radeon_fence_unref(&old_fence);
771fe6b9	378	}
6cb8e1f7	379	}
771fe6b9 JG	380	}
771fe6b9 JG	381
4c788679	382	int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
771fe6b9 JG	383	struct vm_area_struct *vma)
771fe6b9 JG	384	{
4c788679	385	return ttm_fbdev_mmap(vma, &bo->tbo);
771fe6b9 JG	386	}
771fe6b9 JG	387
550e2d92	388	int radeon_bo_get_surface_reg(struct radeon_bo *bo)
771fe6b9	389	{
4c788679	390	struct radeon_device *rdev = bo->rdev;
e024e110	391	struct radeon_surface_reg *reg;
4c788679	392	struct radeon_bo *old_object;
e024e110 DA	393	int steal;
	394	int i;
	395
4c788679 JG	396	BUG_ON(!atomic_read(&bo->tbo.reserved));
	397
	398	if (!bo->tiling_flags)
e024e110 DA	399	return 0;
e024e110 DA	400
4c788679 JG	401	if (bo->surface_reg >= 0) {
	402	reg = &rdev->surface_regs[bo->surface_reg];
	403	i = bo->surface_reg;
e024e110 DA	404	goto out;
	405	}
	406
	407	steal = -1;
	408	for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
	409
	410	reg = &rdev->surface_regs[i];
4c788679	411	if (!reg->bo)
e024e110 DA	412	break;
e024e110 DA	413
4c788679	414	old_object = reg->bo;
e024e110 DA	415	if (old_object->pin_count == 0)
	416	steal = i;
	417	}
	418
	419	/* if we are all out */
	420	if (i == RADEON_GEM_MAX_SURFACES) {
	421	if (steal == -1)
	422	return -ENOMEM;
	423	/* find someone with a surface reg and nuke their BO */
	424	reg = &rdev->surface_regs[steal];
4c788679	425	old_object = reg->bo;
e024e110 DA	426	/* blow away the mapping */
e024e110 DA	427	DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
4c788679	428	ttm_bo_unmap_virtual(&old_object->tbo);
e024e110 DA	429	old_object->surface_reg = -1;
	430	i = steal;
	431	}
	432
4c788679 JG	433	bo->surface_reg = i;
4c788679 JG	434	reg->bo = bo;
e024e110 DA	435
e024e110 DA	436	out:
4c788679 JG	437	radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
	438	bo->tbo.mem.mm_node->start << PAGE_SHIFT,
	439	bo->tbo.num_pages << PAGE_SHIFT);
e024e110 DA	440	return 0;
	441	}
	442
4c788679	443	static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
e024e110	444	{
4c788679	445	struct radeon_device *rdev = bo->rdev;
e024e110 DA	446	struct radeon_surface_reg *reg;
e024e110 DA	447
4c788679	448	if (bo->surface_reg == -1)
e024e110 DA	449	return;
e024e110 DA	450
4c788679 JG	451	reg = &rdev->surface_regs[bo->surface_reg];
4c788679 JG	452	radeon_clear_surface_reg(rdev, bo->surface_reg);
e024e110	453
4c788679 JG	454	reg->bo = NULL;
4c788679 JG	455	bo->surface_reg = -1;
e024e110 DA	456	}
e024e110 DA	457
4c788679 JG	458	int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
4c788679 JG	459	uint32_t tiling_flags, uint32_t pitch)
e024e110	460	{
4c788679 JG	461	int r;
	462
	463	r = radeon_bo_reserve(bo, false);
	464	if (unlikely(r != 0))
	465	return r;
	466	bo->tiling_flags = tiling_flags;
	467	bo->pitch = pitch;
	468	radeon_bo_unreserve(bo);
	469	return 0;
e024e110 DA	470	}
e024e110 DA	471
4c788679 JG	472	void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
	473	uint32_t *tiling_flags,
	474	uint32_t *pitch)
e024e110	475	{
4c788679	476	BUG_ON(!atomic_read(&bo->tbo.reserved));
e024e110	477	if (tiling_flags)
4c788679	478	*tiling_flags = bo->tiling_flags;
e024e110	479	if (pitch)
4c788679	480	*pitch = bo->pitch;
e024e110 DA	481	}
e024e110 DA	482
4c788679 JG	483	int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
4c788679 JG	484	bool force_drop)
e024e110	485	{
4c788679 JG	486	BUG_ON(!atomic_read(&bo->tbo.reserved));
	487
	488	if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
e024e110 DA	489	return 0;
	490
	491	if (force_drop) {
4c788679	492	radeon_bo_clear_surface_reg(bo);
e024e110 DA	493	return 0;
	494	}
	495
4c788679	496	if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
e024e110 DA	497	if (!has_moved)
	498	return 0;
	499
4c788679 JG	500	if (bo->surface_reg >= 0)
4c788679 JG	501	radeon_bo_clear_surface_reg(bo);
e024e110 DA	502	return 0;
	503	}
	504
4c788679	505	if ((bo->surface_reg >= 0) && !has_moved)
e024e110 DA	506	return 0;
e024e110 DA	507
4c788679	508	return radeon_bo_get_surface_reg(bo);
e024e110 DA	509	}
	510
	511	void radeon_bo_move_notify(struct ttm_buffer_object *bo,
d03d8589	512	struct ttm_mem_reg *mem)
e024e110	513	{
d03d8589 JG	514	struct radeon_bo *rbo;
	515	if (!radeon_ttm_bo_is_radeon_bo(bo))
	516	return;
	517	rbo = container_of(bo, struct radeon_bo, tbo);
4c788679	518	radeon_bo_check_tiling(rbo, 0, 1);
e024e110 DA	519	}
e024e110 DA	520
0a2d50e3	521	int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
e024e110	522	{
0a2d50e3	523	struct radeon_device *rdev;
d03d8589	524	struct radeon_bo *rbo;
0a2d50e3 JG	525	unsigned long offset, size;
	526	int r;
	527
d03d8589	528	if (!radeon_ttm_bo_is_radeon_bo(bo))
0a2d50e3	529	return 0;
d03d8589	530	rbo = container_of(bo, struct radeon_bo, tbo);
4c788679	531	radeon_bo_check_tiling(rbo, 0, 0);
0a2d50e3 JG	532	rdev = rbo->rdev;
	533	if (bo->mem.mem_type == TTM_PL_VRAM) {
	534	size = bo->mem.num_pages << PAGE_SHIFT;
	535	offset = bo->mem.mm_node->start << PAGE_SHIFT;
	536	if ((offset + size) > rdev->mc.visible_vram_size) {
	537	/* hurrah the memory is not visible ! */
	538	radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
	539	rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
	540	r = ttm_bo_validate(bo, &rbo->placement, false, true, false);
	541	if (unlikely(r != 0))
	542	return r;
	543	offset = bo->mem.mm_node->start << PAGE_SHIFT;
	544	/* this should not happen */
	545	if ((offset + size) > rdev->mc.visible_vram_size)
	546	return -EINVAL;
	547	}
	548	}
	549	return 0;
e024e110	550	}