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6ee73861 BS |
1 | /* |
2 | * Copyright 2003 NVIDIA, Corporation | |
3 | * Copyright 2006 Dave Airlie | |
4 | * Copyright 2007 Maarten Maathuis | |
5 | * Copyright 2007-2009 Stuart Bennett | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the "Software"), | |
9 | * to deal in the Software without restriction, including without limitation | |
10 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
11 | * and/or sell copies of the Software, and to permit persons to whom the | |
12 | * Software is furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice (including the next | |
15 | * paragraph) shall be included in all copies or substantial portions of the | |
16 | * Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
23 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
24 | * DEALINGS IN THE SOFTWARE. | |
25 | */ | |
26 | ||
27 | #include "drmP.h" | |
28 | #include "drm_crtc_helper.h" | |
29 | ||
30 | #include "nouveau_drv.h" | |
31 | #include "nouveau_encoder.h" | |
32 | #include "nouveau_connector.h" | |
33 | #include "nouveau_crtc.h" | |
34 | #include "nouveau_hw.h" | |
35 | #include "nvreg.h" | |
36 | ||
4a9f822f FJ |
37 | #include "i2c/sil164.h" |
38 | ||
6ee73861 BS |
39 | #define FP_TG_CONTROL_ON (NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS | \ |
40 | NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS | \ | |
41 | NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS) | |
42 | #define FP_TG_CONTROL_OFF (NV_PRAMDAC_FP_TG_CONTROL_DISPEN_DISABLE | \ | |
43 | NV_PRAMDAC_FP_TG_CONTROL_HSYNC_DISABLE | \ | |
44 | NV_PRAMDAC_FP_TG_CONTROL_VSYNC_DISABLE) | |
45 | ||
46 | static inline bool is_fpc_off(uint32_t fpc) | |
47 | { | |
48 | return ((fpc & (FP_TG_CONTROL_ON | FP_TG_CONTROL_OFF)) == | |
49 | FP_TG_CONTROL_OFF); | |
50 | } | |
51 | ||
52 | int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent) | |
53 | { | |
54 | /* special case of nv_read_tmds to find crtc associated with an output. | |
55 | * this does not give a correct answer for off-chip dvi, but there's no | |
56 | * use for such an answer anyway | |
57 | */ | |
58 | int ramdac = (dcbent->or & OUTPUT_C) >> 2; | |
59 | ||
60 | NVWriteRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_CONTROL, | |
61 | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE | 0x4); | |
62 | return ((NVReadRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_DATA) & 0x8) >> 3) ^ ramdac; | |
63 | } | |
64 | ||
65 | void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, | |
66 | int head, bool dl) | |
67 | { | |
68 | /* The BIOS scripts don't do this for us, sadly | |
69 | * Luckily we do know the values ;-) | |
70 | * | |
71 | * head < 0 indicates we wish to force a setting with the overrideval | |
72 | * (for VT restore etc.) | |
73 | */ | |
74 | ||
75 | int ramdac = (dcbent->or & OUTPUT_C) >> 2; | |
76 | uint8_t tmds04 = 0x80; | |
77 | ||
78 | if (head != ramdac) | |
79 | tmds04 = 0x88; | |
80 | ||
81 | if (dcbent->type == OUTPUT_LVDS) | |
82 | tmds04 |= 0x01; | |
83 | ||
84 | nv_write_tmds(dev, dcbent->or, 0, 0x04, tmds04); | |
85 | ||
86 | if (dl) /* dual link */ | |
87 | nv_write_tmds(dev, dcbent->or, 1, 0x04, tmds04 ^ 0x08); | |
88 | } | |
89 | ||
90 | void nv04_dfp_disable(struct drm_device *dev, int head) | |
91 | { | |
92 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
93 | struct nv04_crtc_reg *crtcstate = dev_priv->mode_reg.crtc_reg; | |
94 | ||
95 | if (NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL) & | |
96 | FP_TG_CONTROL_ON) { | |
97 | /* digital remnants must be cleaned before new crtc | |
98 | * values programmed. delay is time for the vga stuff | |
99 | * to realise it's in control again | |
100 | */ | |
101 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, | |
102 | FP_TG_CONTROL_OFF); | |
103 | msleep(50); | |
104 | } | |
105 | /* don't inadvertently turn it on when state written later */ | |
106 | crtcstate[head].fp_control = FP_TG_CONTROL_OFF; | |
107 | } | |
108 | ||
109 | void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode) | |
110 | { | |
111 | struct drm_device *dev = encoder->dev; | |
112 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
113 | struct drm_crtc *crtc; | |
114 | struct nouveau_crtc *nv_crtc; | |
115 | uint32_t *fpc; | |
116 | ||
117 | if (mode == DRM_MODE_DPMS_ON) { | |
118 | nv_crtc = nouveau_crtc(encoder->crtc); | |
119 | fpc = &dev_priv->mode_reg.crtc_reg[nv_crtc->index].fp_control; | |
120 | ||
121 | if (is_fpc_off(*fpc)) { | |
122 | /* using saved value is ok, as (is_digital && dpms_on && | |
123 | * fp_control==OFF) is (at present) *only* true when | |
124 | * fpc's most recent change was by below "off" code | |
125 | */ | |
126 | *fpc = nv_crtc->dpms_saved_fp_control; | |
127 | } | |
128 | ||
129 | nv_crtc->fp_users |= 1 << nouveau_encoder(encoder)->dcb->index; | |
130 | NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_FP_TG_CONTROL, *fpc); | |
131 | } else { | |
132 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
133 | nv_crtc = nouveau_crtc(crtc); | |
134 | fpc = &dev_priv->mode_reg.crtc_reg[nv_crtc->index].fp_control; | |
135 | ||
136 | nv_crtc->fp_users &= ~(1 << nouveau_encoder(encoder)->dcb->index); | |
137 | if (!is_fpc_off(*fpc) && !nv_crtc->fp_users) { | |
138 | nv_crtc->dpms_saved_fp_control = *fpc; | |
139 | /* cut the FP output */ | |
140 | *fpc &= ~FP_TG_CONTROL_ON; | |
141 | *fpc |= FP_TG_CONTROL_OFF; | |
142 | NVWriteRAMDAC(dev, nv_crtc->index, | |
143 | NV_PRAMDAC_FP_TG_CONTROL, *fpc); | |
144 | } | |
145 | } | |
146 | } | |
147 | } | |
148 | ||
2d14e35c FJ |
149 | static struct drm_encoder *get_tmds_slave(struct drm_encoder *encoder) |
150 | { | |
151 | struct drm_device *dev = encoder->dev; | |
152 | struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb; | |
153 | struct drm_encoder *slave; | |
154 | ||
155 | if (dcb->type != OUTPUT_TMDS || dcb->location == DCB_LOC_ON_CHIP) | |
156 | return NULL; | |
157 | ||
158 | /* Some BIOSes (e.g. the one in a Quadro FX1000) report several | |
159 | * TMDS transmitters at the same I2C address, in the same I2C | |
160 | * bus. This can still work because in that case one of them is | |
161 | * always hard-wired to a reasonable configuration using straps, | |
162 | * and the other one needs to be programmed. | |
163 | * | |
164 | * I don't think there's a way to know which is which, even the | |
165 | * blob programs the one exposed via I2C for *both* heads, so | |
166 | * let's do the same. | |
167 | */ | |
168 | list_for_each_entry(slave, &dev->mode_config.encoder_list, head) { | |
169 | struct dcb_entry *slave_dcb = nouveau_encoder(slave)->dcb; | |
170 | ||
171 | if (slave_dcb->type == OUTPUT_TMDS && get_slave_funcs(slave) && | |
172 | slave_dcb->tmdsconf.slave_addr == dcb->tmdsconf.slave_addr) | |
173 | return slave; | |
174 | } | |
175 | ||
176 | return NULL; | |
177 | } | |
178 | ||
6ee73861 BS |
179 | static bool nv04_dfp_mode_fixup(struct drm_encoder *encoder, |
180 | struct drm_display_mode *mode, | |
181 | struct drm_display_mode *adjusted_mode) | |
182 | { | |
183 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
184 | struct nouveau_connector *nv_connector = nouveau_encoder_connector_get(nv_encoder); | |
185 | ||
186 | /* For internal panels and gpu scaling on DVI we need the native mode */ | |
187 | if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) { | |
188 | if (!nv_connector->native_mode) | |
189 | return false; | |
190 | nv_encoder->mode = *nv_connector->native_mode; | |
191 | adjusted_mode->clock = nv_connector->native_mode->clock; | |
192 | } else { | |
193 | nv_encoder->mode = *adjusted_mode; | |
194 | } | |
195 | ||
196 | return true; | |
197 | } | |
198 | ||
199 | static void nv04_dfp_prepare_sel_clk(struct drm_device *dev, | |
200 | struct nouveau_encoder *nv_encoder, int head) | |
201 | { | |
202 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
203 | struct nv04_mode_state *state = &dev_priv->mode_reg; | |
204 | uint32_t bits1618 = nv_encoder->dcb->or & OUTPUT_A ? 0x10000 : 0x40000; | |
205 | ||
206 | if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP) | |
207 | return; | |
208 | ||
209 | /* SEL_CLK is only used on the primary ramdac | |
210 | * It toggles spread spectrum PLL output and sets the bindings of PLLs | |
211 | * to heads on digital outputs | |
212 | */ | |
213 | if (head) | |
214 | state->sel_clk |= bits1618; | |
215 | else | |
216 | state->sel_clk &= ~bits1618; | |
217 | ||
218 | /* nv30: | |
219 | * bit 0 NVClk spread spectrum on/off | |
220 | * bit 2 MemClk spread spectrum on/off | |
221 | * bit 4 PixClk1 spread spectrum on/off toggle | |
222 | * bit 6 PixClk2 spread spectrum on/off toggle | |
223 | * | |
224 | * nv40 (observations from bios behaviour and mmio traces): | |
225 | * bits 4&6 as for nv30 | |
226 | * bits 5&7 head dependent as for bits 4&6, but do not appear with 4&6; | |
227 | * maybe a different spread mode | |
228 | * bits 8&10 seen on dual-link dvi outputs, purpose unknown (set by POST scripts) | |
229 | * The logic behind turning spread spectrum on/off in the first place, | |
230 | * and which bit-pair to use, is unclear on nv40 (for earlier cards, the fp table | |
231 | * entry has the necessary info) | |
232 | */ | |
233 | if (nv_encoder->dcb->type == OUTPUT_LVDS && dev_priv->saved_reg.sel_clk & 0xf0) { | |
234 | int shift = (dev_priv->saved_reg.sel_clk & 0x50) ? 0 : 1; | |
235 | ||
236 | state->sel_clk &= ~0xf0; | |
237 | state->sel_clk |= (head ? 0x40 : 0x10) << shift; | |
238 | } | |
239 | } | |
240 | ||
241 | static void nv04_dfp_prepare(struct drm_encoder *encoder) | |
242 | { | |
243 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
244 | struct drm_encoder_helper_funcs *helper = encoder->helper_private; | |
245 | struct drm_device *dev = encoder->dev; | |
246 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
247 | int head = nouveau_crtc(encoder->crtc)->index; | |
248 | struct nv04_crtc_reg *crtcstate = dev_priv->mode_reg.crtc_reg; | |
249 | uint8_t *cr_lcd = &crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX]; | |
250 | uint8_t *cr_lcd_oth = &crtcstate[head ^ 1].CRTC[NV_CIO_CRE_LCD__INDEX]; | |
251 | ||
252 | helper->dpms(encoder, DRM_MODE_DPMS_OFF); | |
253 | ||
254 | nv04_dfp_prepare_sel_clk(dev, nv_encoder, head); | |
255 | ||
256 | /* Some NV4x have unknown values (0x3f, 0x50, 0x54, 0x6b, 0x79, 0x7f) | |
257 | * at LCD__INDEX which we don't alter | |
258 | */ | |
259 | if (!(*cr_lcd & 0x44)) { | |
260 | *cr_lcd = 0x3; | |
261 | ||
262 | if (nv_two_heads(dev)) { | |
263 | if (nv_encoder->dcb->location == DCB_LOC_ON_CHIP) | |
264 | *cr_lcd |= head ? 0x0 : 0x8; | |
265 | else { | |
266 | *cr_lcd |= (nv_encoder->dcb->or << 4) & 0x30; | |
267 | if (nv_encoder->dcb->type == OUTPUT_LVDS) | |
268 | *cr_lcd |= 0x30; | |
269 | if ((*cr_lcd & 0x30) == (*cr_lcd_oth & 0x30)) { | |
270 | /* avoid being connected to both crtcs */ | |
271 | *cr_lcd_oth &= ~0x30; | |
272 | NVWriteVgaCrtc(dev, head ^ 1, | |
273 | NV_CIO_CRE_LCD__INDEX, | |
274 | *cr_lcd_oth); | |
275 | } | |
276 | } | |
277 | } | |
278 | } | |
279 | } | |
280 | ||
281 | ||
282 | static void nv04_dfp_mode_set(struct drm_encoder *encoder, | |
283 | struct drm_display_mode *mode, | |
284 | struct drm_display_mode *adjusted_mode) | |
285 | { | |
286 | struct drm_device *dev = encoder->dev; | |
287 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
288 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); | |
289 | struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index]; | |
290 | struct nv04_crtc_reg *savep = &dev_priv->saved_reg.crtc_reg[nv_crtc->index]; | |
291 | struct nouveau_connector *nv_connector = nouveau_crtc_connector_get(nv_crtc); | |
292 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
293 | struct drm_display_mode *output_mode = &nv_encoder->mode; | |
294 | uint32_t mode_ratio, panel_ratio; | |
295 | ||
ef2bb506 | 296 | NV_DEBUG_KMS(dev, "Output mode on CRTC %d:\n", nv_crtc->index); |
6ee73861 BS |
297 | drm_mode_debug_printmodeline(output_mode); |
298 | ||
299 | /* Initialize the FP registers in this CRTC. */ | |
300 | regp->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1; | |
301 | regp->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1; | |
302 | if (!nv_gf4_disp_arch(dev) || | |
303 | (output_mode->hsync_start - output_mode->hdisplay) >= | |
04a39c57 | 304 | dev_priv->vbios.digital_min_front_porch) |
6ee73861 BS |
305 | regp->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay; |
306 | else | |
04a39c57 | 307 | regp->fp_horiz_regs[FP_CRTC] = output_mode->hsync_start - dev_priv->vbios.digital_min_front_porch - 1; |
6ee73861 BS |
308 | regp->fp_horiz_regs[FP_SYNC_START] = output_mode->hsync_start - 1; |
309 | regp->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1; | |
310 | regp->fp_horiz_regs[FP_VALID_START] = output_mode->hskew; | |
311 | regp->fp_horiz_regs[FP_VALID_END] = output_mode->hdisplay - 1; | |
312 | ||
313 | regp->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1; | |
314 | regp->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1; | |
315 | regp->fp_vert_regs[FP_CRTC] = output_mode->vtotal - 5 - 1; | |
316 | regp->fp_vert_regs[FP_SYNC_START] = output_mode->vsync_start - 1; | |
317 | regp->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1; | |
318 | regp->fp_vert_regs[FP_VALID_START] = 0; | |
319 | regp->fp_vert_regs[FP_VALID_END] = output_mode->vdisplay - 1; | |
320 | ||
321 | /* bit26: a bit seen on some g7x, no as yet discernable purpose */ | |
322 | regp->fp_control = NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS | | |
323 | (savep->fp_control & (1 << 26 | NV_PRAMDAC_FP_TG_CONTROL_READ_PROG)); | |
324 | /* Deal with vsync/hsync polarity */ | |
325 | /* LVDS screens do set this, but modes with +ve syncs are very rare */ | |
326 | if (output_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
327 | regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS; | |
328 | if (output_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
329 | regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS; | |
330 | /* panel scaling first, as native would get set otherwise */ | |
331 | if (nv_connector->scaling_mode == DRM_MODE_SCALE_NONE || | |
332 | nv_connector->scaling_mode == DRM_MODE_SCALE_CENTER) /* panel handles it */ | |
333 | regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_CENTER; | |
334 | else if (adjusted_mode->hdisplay == output_mode->hdisplay && | |
335 | adjusted_mode->vdisplay == output_mode->vdisplay) /* native mode */ | |
336 | regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_NATIVE; | |
337 | else /* gpu needs to scale */ | |
338 | regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_SCALE; | |
339 | if (nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT) | |
340 | regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12; | |
341 | if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP && | |
342 | output_mode->clock > 165000) | |
343 | regp->fp_control |= (2 << 24); | |
344 | if (nv_encoder->dcb->type == OUTPUT_LVDS) { | |
345 | bool duallink, dummy; | |
346 | ||
347 | nouveau_bios_parse_lvds_table(dev, nv_connector->native_mode-> | |
348 | clock, &duallink, &dummy); | |
349 | if (duallink) | |
350 | regp->fp_control |= (8 << 28); | |
351 | } else | |
352 | if (output_mode->clock > 165000) | |
353 | regp->fp_control |= (8 << 28); | |
354 | ||
355 | regp->fp_debug_0 = NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND | | |
356 | NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_ROUND | | |
357 | NV_PRAMDAC_FP_DEBUG_0_YINTERP_BILINEAR | | |
358 | NV_PRAMDAC_FP_DEBUG_0_XINTERP_BILINEAR | | |
359 | NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED | | |
360 | NV_PRAMDAC_FP_DEBUG_0_YSCALE_ENABLE | | |
361 | NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE; | |
362 | ||
363 | /* We want automatic scaling */ | |
364 | regp->fp_debug_1 = 0; | |
365 | /* This can override HTOTAL and VTOTAL */ | |
366 | regp->fp_debug_2 = 0; | |
367 | ||
368 | /* Use 20.12 fixed point format to avoid floats */ | |
369 | mode_ratio = (1 << 12) * adjusted_mode->hdisplay / adjusted_mode->vdisplay; | |
370 | panel_ratio = (1 << 12) * output_mode->hdisplay / output_mode->vdisplay; | |
371 | /* if ratios are equal, SCALE_ASPECT will automatically (and correctly) | |
372 | * get treated the same as SCALE_FULLSCREEN */ | |
373 | if (nv_connector->scaling_mode == DRM_MODE_SCALE_ASPECT && | |
374 | mode_ratio != panel_ratio) { | |
375 | uint32_t diff, scale; | |
376 | bool divide_by_2 = nv_gf4_disp_arch(dev); | |
377 | ||
378 | if (mode_ratio < panel_ratio) { | |
379 | /* vertical needs to expand to glass size (automatic) | |
380 | * horizontal needs to be scaled at vertical scale factor | |
381 | * to maintain aspect */ | |
382 | ||
383 | scale = (1 << 12) * adjusted_mode->vdisplay / output_mode->vdisplay; | |
384 | regp->fp_debug_1 = NV_PRAMDAC_FP_DEBUG_1_XSCALE_TESTMODE_ENABLE | | |
385 | XLATE(scale, divide_by_2, NV_PRAMDAC_FP_DEBUG_1_XSCALE_VALUE); | |
386 | ||
387 | /* restrict area of screen used, horizontally */ | |
388 | diff = output_mode->hdisplay - | |
389 | output_mode->vdisplay * mode_ratio / (1 << 12); | |
390 | regp->fp_horiz_regs[FP_VALID_START] += diff / 2; | |
391 | regp->fp_horiz_regs[FP_VALID_END] -= diff / 2; | |
392 | } | |
393 | ||
394 | if (mode_ratio > panel_ratio) { | |
395 | /* horizontal needs to expand to glass size (automatic) | |
396 | * vertical needs to be scaled at horizontal scale factor | |
397 | * to maintain aspect */ | |
398 | ||
399 | scale = (1 << 12) * adjusted_mode->hdisplay / output_mode->hdisplay; | |
400 | regp->fp_debug_1 = NV_PRAMDAC_FP_DEBUG_1_YSCALE_TESTMODE_ENABLE | | |
401 | XLATE(scale, divide_by_2, NV_PRAMDAC_FP_DEBUG_1_YSCALE_VALUE); | |
402 | ||
403 | /* restrict area of screen used, vertically */ | |
404 | diff = output_mode->vdisplay - | |
405 | (1 << 12) * output_mode->hdisplay / mode_ratio; | |
406 | regp->fp_vert_regs[FP_VALID_START] += diff / 2; | |
407 | regp->fp_vert_regs[FP_VALID_END] -= diff / 2; | |
408 | } | |
409 | } | |
410 | ||
411 | /* Output property. */ | |
412 | if (nv_connector->use_dithering) { | |
413 | if (dev_priv->chipset == 0x11) | |
414 | regp->dither = savep->dither | 0x00010000; | |
415 | else { | |
416 | int i; | |
417 | regp->dither = savep->dither | 0x00000001; | |
418 | for (i = 0; i < 3; i++) { | |
419 | regp->dither_regs[i] = 0xe4e4e4e4; | |
420 | regp->dither_regs[i + 3] = 0x44444444; | |
421 | } | |
422 | } | |
423 | } else { | |
424 | if (dev_priv->chipset != 0x11) { | |
425 | /* reset them */ | |
426 | int i; | |
427 | for (i = 0; i < 3; i++) { | |
428 | regp->dither_regs[i] = savep->dither_regs[i]; | |
429 | regp->dither_regs[i + 3] = savep->dither_regs[i + 3]; | |
430 | } | |
431 | } | |
432 | regp->dither = savep->dither; | |
433 | } | |
434 | ||
435 | regp->fp_margin_color = 0; | |
436 | } | |
437 | ||
438 | static void nv04_dfp_commit(struct drm_encoder *encoder) | |
439 | { | |
440 | struct drm_device *dev = encoder->dev; | |
441 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
442 | struct drm_encoder_helper_funcs *helper = encoder->helper_private; | |
443 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); | |
444 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
445 | struct dcb_entry *dcbe = nv_encoder->dcb; | |
446 | int head = nouveau_crtc(encoder->crtc)->index; | |
f5cb8ab1 | 447 | struct drm_encoder *slave_encoder; |
6ee73861 | 448 | |
6ee73861 BS |
449 | if (dcbe->type == OUTPUT_TMDS) |
450 | run_tmds_table(dev, dcbe, head, nv_encoder->mode.clock); | |
451 | else if (dcbe->type == OUTPUT_LVDS) | |
452 | call_lvds_script(dev, dcbe, head, LVDS_RESET, nv_encoder->mode.clock); | |
453 | ||
454 | /* update fp_control state for any changes made by scripts, | |
455 | * so correct value is written at DPMS on */ | |
456 | dev_priv->mode_reg.crtc_reg[head].fp_control = | |
457 | NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL); | |
458 | ||
459 | /* This could use refinement for flatpanels, but it should work this way */ | |
460 | if (dev_priv->chipset < 0x44) | |
461 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0xf0000000); | |
462 | else | |
463 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0x00100000); | |
464 | ||
4a9f822f | 465 | /* Init external transmitters */ |
f5cb8ab1 PM |
466 | slave_encoder = get_tmds_slave(encoder); |
467 | if (slave_encoder) | |
468 | get_slave_funcs(slave_encoder)->mode_set( | |
469 | slave_encoder, &nv_encoder->mode, &nv_encoder->mode); | |
4a9f822f | 470 | |
6ee73861 BS |
471 | helper->dpms(encoder, DRM_MODE_DPMS_ON); |
472 | ||
473 | NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n", | |
474 | drm_get_connector_name(&nouveau_encoder_connector_get(nv_encoder)->base), | |
475 | nv_crtc->index, '@' + ffs(nv_encoder->dcb->or)); | |
476 | } | |
477 | ||
478 | static inline bool is_powersaving_dpms(int mode) | |
479 | { | |
480 | return (mode != DRM_MODE_DPMS_ON); | |
481 | } | |
482 | ||
483 | static void nv04_lvds_dpms(struct drm_encoder *encoder, int mode) | |
484 | { | |
485 | struct drm_device *dev = encoder->dev; | |
486 | struct drm_crtc *crtc = encoder->crtc; | |
487 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
488 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
489 | bool was_powersaving = is_powersaving_dpms(nv_encoder->last_dpms); | |
490 | ||
491 | if (nv_encoder->last_dpms == mode) | |
492 | return; | |
493 | nv_encoder->last_dpms = mode; | |
494 | ||
495 | NV_INFO(dev, "Setting dpms mode %d on lvds encoder (output %d)\n", | |
496 | mode, nv_encoder->dcb->index); | |
497 | ||
498 | if (was_powersaving && is_powersaving_dpms(mode)) | |
499 | return; | |
500 | ||
501 | if (nv_encoder->dcb->lvdsconf.use_power_scripts) { | |
502 | struct nouveau_connector *nv_connector = nouveau_encoder_connector_get(nv_encoder); | |
503 | ||
504 | /* when removing an output, crtc may not be set, but PANEL_OFF | |
505 | * must still be run | |
506 | */ | |
507 | int head = crtc ? nouveau_crtc(crtc)->index : | |
508 | nv04_dfp_get_bound_head(dev, nv_encoder->dcb); | |
509 | ||
510 | if (mode == DRM_MODE_DPMS_ON) { | |
511 | if (!nv_connector->native_mode) { | |
512 | NV_ERROR(dev, "Not turning on LVDS without native mode\n"); | |
513 | return; | |
514 | } | |
515 | call_lvds_script(dev, nv_encoder->dcb, head, | |
516 | LVDS_PANEL_ON, nv_connector->native_mode->clock); | |
517 | } else | |
518 | /* pxclk of 0 is fine for PANEL_OFF, and for a | |
519 | * disconnected LVDS encoder there is no native_mode | |
520 | */ | |
521 | call_lvds_script(dev, nv_encoder->dcb, head, | |
522 | LVDS_PANEL_OFF, 0); | |
523 | } | |
524 | ||
525 | nv04_dfp_update_fp_control(encoder, mode); | |
526 | ||
527 | if (mode == DRM_MODE_DPMS_ON) | |
528 | nv04_dfp_prepare_sel_clk(dev, nv_encoder, nouveau_crtc(crtc)->index); | |
529 | else { | |
530 | dev_priv->mode_reg.sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK); | |
531 | dev_priv->mode_reg.sel_clk &= ~0xf0; | |
532 | } | |
533 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, dev_priv->mode_reg.sel_clk); | |
534 | } | |
535 | ||
536 | static void nv04_tmds_dpms(struct drm_encoder *encoder, int mode) | |
537 | { | |
538 | struct drm_device *dev = encoder->dev; | |
539 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
540 | ||
541 | if (nv_encoder->last_dpms == mode) | |
542 | return; | |
543 | nv_encoder->last_dpms = mode; | |
544 | ||
545 | NV_INFO(dev, "Setting dpms mode %d on tmds encoder (output %d)\n", | |
546 | mode, nv_encoder->dcb->index); | |
547 | ||
548 | nv04_dfp_update_fp_control(encoder, mode); | |
549 | } | |
550 | ||
551 | static void nv04_dfp_save(struct drm_encoder *encoder) | |
552 | { | |
553 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
554 | struct drm_device *dev = encoder->dev; | |
555 | ||
556 | if (nv_two_heads(dev)) | |
557 | nv_encoder->restore.head = | |
558 | nv04_dfp_get_bound_head(dev, nv_encoder->dcb); | |
559 | } | |
560 | ||
561 | static void nv04_dfp_restore(struct drm_encoder *encoder) | |
562 | { | |
563 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
564 | struct drm_device *dev = encoder->dev; | |
565 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
566 | int head = nv_encoder->restore.head; | |
567 | ||
568 | if (nv_encoder->dcb->type == OUTPUT_LVDS) { | |
569 | struct drm_display_mode *native_mode = nouveau_encoder_connector_get(nv_encoder)->native_mode; | |
570 | if (native_mode) | |
571 | call_lvds_script(dev, nv_encoder->dcb, head, LVDS_PANEL_ON, | |
572 | native_mode->clock); | |
573 | else | |
574 | NV_ERROR(dev, "Not restoring LVDS without native mode\n"); | |
575 | ||
576 | } else if (nv_encoder->dcb->type == OUTPUT_TMDS) { | |
577 | int clock = nouveau_hw_pllvals_to_clk | |
578 | (&dev_priv->saved_reg.crtc_reg[head].pllvals); | |
579 | ||
580 | run_tmds_table(dev, nv_encoder->dcb, head, clock); | |
581 | } | |
582 | ||
583 | nv_encoder->last_dpms = NV_DPMS_CLEARED; | |
584 | } | |
585 | ||
586 | static void nv04_dfp_destroy(struct drm_encoder *encoder) | |
587 | { | |
588 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
589 | ||
ef2bb506 | 590 | NV_DEBUG_KMS(encoder->dev, "\n"); |
6ee73861 | 591 | |
4a9f822f FJ |
592 | if (get_slave_funcs(encoder)) |
593 | get_slave_funcs(encoder)->destroy(encoder); | |
594 | ||
6ee73861 BS |
595 | drm_encoder_cleanup(encoder); |
596 | kfree(nv_encoder); | |
597 | } | |
598 | ||
4a9f822f FJ |
599 | static void nv04_tmds_slave_init(struct drm_encoder *encoder) |
600 | { | |
601 | struct drm_device *dev = encoder->dev; | |
602 | struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb; | |
603 | struct nouveau_i2c_chan *i2c = nouveau_i2c_find(dev, 2); | |
604 | struct i2c_board_info info[] = { | |
605 | { | |
606 | .type = "sil164", | |
607 | .addr = (dcb->tmdsconf.slave_addr == 0x7 ? 0x3a : 0x38), | |
608 | .platform_data = &(struct sil164_encoder_params) { | |
609 | SIL164_INPUT_EDGE_RISING | |
610 | } | |
611 | }, | |
612 | { } | |
613 | }; | |
614 | int type; | |
615 | ||
2d14e35c FJ |
616 | if (!nv_gf4_disp_arch(dev) || !i2c || |
617 | get_tmds_slave(encoder)) | |
4a9f822f FJ |
618 | return; |
619 | ||
620 | type = nouveau_i2c_identify(dev, "TMDS transmitter", info, 2); | |
621 | if (type < 0) | |
622 | return; | |
623 | ||
624 | drm_i2c_encoder_init(dev, to_encoder_slave(encoder), | |
625 | &i2c->adapter, &info[type]); | |
626 | } | |
627 | ||
6ee73861 BS |
628 | static const struct drm_encoder_helper_funcs nv04_lvds_helper_funcs = { |
629 | .dpms = nv04_lvds_dpms, | |
630 | .save = nv04_dfp_save, | |
631 | .restore = nv04_dfp_restore, | |
632 | .mode_fixup = nv04_dfp_mode_fixup, | |
633 | .prepare = nv04_dfp_prepare, | |
634 | .commit = nv04_dfp_commit, | |
635 | .mode_set = nv04_dfp_mode_set, | |
636 | .detect = NULL, | |
637 | }; | |
638 | ||
639 | static const struct drm_encoder_helper_funcs nv04_tmds_helper_funcs = { | |
640 | .dpms = nv04_tmds_dpms, | |
641 | .save = nv04_dfp_save, | |
642 | .restore = nv04_dfp_restore, | |
643 | .mode_fixup = nv04_dfp_mode_fixup, | |
644 | .prepare = nv04_dfp_prepare, | |
645 | .commit = nv04_dfp_commit, | |
646 | .mode_set = nv04_dfp_mode_set, | |
647 | .detect = NULL, | |
648 | }; | |
649 | ||
650 | static const struct drm_encoder_funcs nv04_dfp_funcs = { | |
651 | .destroy = nv04_dfp_destroy, | |
652 | }; | |
653 | ||
8f1a6086 BS |
654 | int |
655 | nv04_dfp_create(struct drm_connector *connector, struct dcb_entry *entry) | |
6ee73861 BS |
656 | { |
657 | const struct drm_encoder_helper_funcs *helper; | |
6ee73861 | 658 | struct nouveau_encoder *nv_encoder = NULL; |
8f1a6086 | 659 | struct drm_encoder *encoder; |
6ee73861 BS |
660 | int type; |
661 | ||
662 | switch (entry->type) { | |
663 | case OUTPUT_TMDS: | |
664 | type = DRM_MODE_ENCODER_TMDS; | |
665 | helper = &nv04_tmds_helper_funcs; | |
666 | break; | |
667 | case OUTPUT_LVDS: | |
668 | type = DRM_MODE_ENCODER_LVDS; | |
669 | helper = &nv04_lvds_helper_funcs; | |
670 | break; | |
671 | default: | |
672 | return -EINVAL; | |
673 | } | |
674 | ||
675 | nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); | |
676 | if (!nv_encoder) | |
677 | return -ENOMEM; | |
678 | ||
679 | encoder = to_drm_encoder(nv_encoder); | |
680 | ||
681 | nv_encoder->dcb = entry; | |
682 | nv_encoder->or = ffs(entry->or) - 1; | |
683 | ||
8f1a6086 | 684 | drm_encoder_init(connector->dev, encoder, &nv04_dfp_funcs, type); |
6ee73861 BS |
685 | drm_encoder_helper_add(encoder, helper); |
686 | ||
687 | encoder->possible_crtcs = entry->heads; | |
688 | encoder->possible_clones = 0; | |
689 | ||
4a9f822f FJ |
690 | if (entry->type == OUTPUT_TMDS && |
691 | entry->location != DCB_LOC_ON_CHIP) | |
692 | nv04_tmds_slave_init(encoder); | |
693 | ||
8f1a6086 | 694 | drm_mode_connector_attach_encoder(connector, encoder); |
6ee73861 BS |
695 | return 0; |
696 | } |