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drm/nouveau: fix pcirom vbios shadow breakage from acpi rom patch
[net-next-2.6.git] / drivers / gpu / drm / nouveau / nouveau_bios.c
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2005-2006 Erik Waling
3 * Copyright 2006 Stephane Marchesin
4 * Copyright 2007-2009 Stuart Bennett
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24
25#include "drmP.h"
26#define NV_DEBUG_NOTRACE
27#include "nouveau_drv.h"
28#include "nouveau_hw.h"
25908b77 29#include "nouveau_encoder.h"
6ee73861
BS		 30
31/* these defines are made up */
32#define NV_CIO_CRE_44_HEADA 0x0
33#define NV_CIO_CRE_44_HEADB 0x3
34#define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */
35#define LEGACY_I2C_CRT 0x80
36#define LEGACY_I2C_PANEL 0x81
37#define LEGACY_I2C_TV 0x82
38
39#define EDID1_LEN 128
40
41#define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg)
42#define LOG_OLD_VALUE(x)
43
44#define ROM16(x) le16_to_cpu(*(uint16_t *)&(x))
45#define ROM32(x) le32_to_cpu(*(uint32_t *)&(x))
46
47struct init_exec {
48 bool execute;
49 bool repeat;
50};
51
52static bool nv_cksum(const uint8_t *data, unsigned int length)
53{
54 /*
55 * There's a few checksums in the BIOS, so here's a generic checking
56 * function.
57 */
58 int i;
59 uint8_t sum = 0;
60
61 for (i = 0; i < length; i++)
62 sum += data[i];
63
64 if (sum)
65 return true;
66
67 return false;
68}
69
70static int
71score_vbios(struct drm_device *dev, const uint8_t *data, const bool writeable)
72{
73 if (!(data[0] == 0x55 && data[1] == 0xAA)) {
74 NV_TRACEWARN(dev, "... BIOS signature not found\n");
75 return 0;
76 }
77
78 if (nv_cksum(data, data[2] * 512)) {
79 NV_TRACEWARN(dev, "... BIOS checksum invalid\n");
80 /* if a ro image is somewhat bad, it's probably all rubbish */
81 return writeable ? 2 : 1;
82 } else
83 NV_TRACE(dev, "... appears to be valid\n");
84
85 return 3;
86}
87
88static void load_vbios_prom(struct drm_device *dev, uint8_t *data)
89{
90 struct drm_nouveau_private *dev_priv = dev->dev_private;
91 uint32_t pci_nv_20, save_pci_nv_20;
92 int pcir_ptr;
93 int i;
94
95 if (dev_priv->card_type >= NV_50)
96 pci_nv_20 = 0x88050;
97 else
98 pci_nv_20 = NV_PBUS_PCI_NV_20;
99
100 /* enable ROM access */
101 save_pci_nv_20 = nvReadMC(dev, pci_nv_20);
102 nvWriteMC(dev, pci_nv_20,
103 save_pci_nv_20 & ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
104
105 /* bail if no rom signature */
106 if (nv_rd08(dev, NV_PROM_OFFSET) != 0x55 ||
107 nv_rd08(dev, NV_PROM_OFFSET + 1) != 0xaa)
108 goto out;
109
110 /* additional check (see note below) - read PCI record header */
111 pcir_ptr = nv_rd08(dev, NV_PROM_OFFSET + 0x18) |
112 nv_rd08(dev, NV_PROM_OFFSET + 0x19) << 8;
113 if (nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr) != 'P' ||
114 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 1) != 'C' ||
115 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 2) != 'I' ||
116 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 3) != 'R')
117 goto out;
118
119 /* on some 6600GT/6800LE prom reads are messed up. nvclock alleges a
120 * a good read may be obtained by waiting or re-reading (cargocult: 5x)
121 * each byte. we'll hope pramin has something usable instead
122 */
123 for (i = 0; i < NV_PROM_SIZE; i++)
124 data[i] = nv_rd08(dev, NV_PROM_OFFSET + i);
125
126out:
127 /* disable ROM access */
128 nvWriteMC(dev, pci_nv_20,
129 save_pci_nv_20 | NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
130}
131
132static void load_vbios_pramin(struct drm_device *dev, uint8_t *data)
133{
134 struct drm_nouveau_private *dev_priv = dev->dev_private;
135 uint32_t old_bar0_pramin = 0;
136 int i;
137
138 if (dev_priv->card_type >= NV_50) {
139 uint32_t vbios_vram = (nv_rd32(dev, 0x619f04) & ~0xff) << 8;
140
141 if (!vbios_vram)
142 vbios_vram = (nv_rd32(dev, 0x1700) << 16) + 0xf0000;
143
144 old_bar0_pramin = nv_rd32(dev, 0x1700);
145 nv_wr32(dev, 0x1700, vbios_vram >> 16);
146 }
147
148 /* bail if no rom signature */
149 if (nv_rd08(dev, NV_PRAMIN_OFFSET) != 0x55 ||
150 nv_rd08(dev, NV_PRAMIN_OFFSET + 1) != 0xaa)
151 goto out;
152
153 for (i = 0; i < NV_PROM_SIZE; i++)
154 data[i] = nv_rd08(dev, NV_PRAMIN_OFFSET + i);
155
156out:
157 if (dev_priv->card_type >= NV_50)
158 nv_wr32(dev, 0x1700, old_bar0_pramin);
159}
160
161static void load_vbios_pci(struct drm_device *dev, uint8_t *data)
162{
163 void __iomem *rom = NULL;
164 size_t rom_len;
165 int ret;
166
167 ret = pci_enable_rom(dev->pdev);
168 if (ret)
169 return;
170
171 rom = pci_map_rom(dev->pdev, &rom_len);
172 if (!rom)
173 goto out;
174 memcpy_fromio(data, rom, rom_len);
175 pci_unmap_rom(dev->pdev, rom);
176
177out:
178 pci_disable_rom(dev->pdev);
179}
180
afeb3e11
DA		 181static void load_vbios_acpi(struct drm_device *dev, uint8_t *data)
182{
183 int i;
184 int ret;
185 int size = 64 * 1024;
186
187 if (!nouveau_acpi_rom_supported(dev->pdev))
188 return;
189
190 for (i = 0; i < (size / ROM_BIOS_PAGE); i++) {
191 ret = nouveau_acpi_get_bios_chunk(data,
192 (i * ROM_BIOS_PAGE),
193 ROM_BIOS_PAGE);
194 if (ret <= 0)
195 break;
196 }
197 return;
198}
199
6ee73861
BS		 200struct methods {
201 const char desc[8];
202 void (*loadbios)(struct drm_device *, uint8_t *);
203 const bool rw;
6ee73861
BS		 204};
205
14d7ec11 206static struct methods shadow_methods[] = {
6ee73861
BS		 207 { "PRAMIN", load_vbios_pramin, true },
208 { "PROM", load_vbios_prom, false },
209 { "PCIROM", load_vbios_pci, true },
14d7ec11 210 { "ACPI", load_vbios_acpi, true },
6ee73861
BS		 211};
212
213static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
214{
14d7ec11
BS		 215 const int nr_methods = ARRAY_SIZE(shadow_methods);
216 struct methods *methods = shadow_methods;
6ee73861 217 int testscore = 3;
14d7ec11 218 int scores[nr_methods], i;
6ee73861
BS		 219
220 if (nouveau_vbios) {
14d7ec11 221 for (i = 0; i < nr_methods; i++)
657b6245 222 if (!strcasecmp(nouveau_vbios, methods[i].desc))
6ee73861 223 break;
6ee73861 224
14d7ec11 225 if (i < nr_methods) {
6ee73861 226 NV_INFO(dev, "Attempting to use BIOS image from %s\n",
657b6245 227 methods[i].desc);
6ee73861 228
657b6245
MK		 229 methods[i].loadbios(dev, data);
230 if (score_vbios(dev, data, methods[i].rw))
6ee73861
BS		 231 return true;
232 }
233
234 NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios);
235 }
236
14d7ec11 237 for (i = 0; i < nr_methods; i++) {
6ee73861 238 NV_TRACE(dev, "Attempting to load BIOS image from %s\n",
657b6245 239 methods[i].desc);
6ee73861 240 data[0] = data[1] = 0; /* avoid reuse of previous image */
657b6245
MK		 241 methods[i].loadbios(dev, data);
242 scores[i] = score_vbios(dev, data, methods[i].rw);
243 if (scores[i] == testscore)
6ee73861 244 return true;
6ee73861
BS		 245 }
246
247 while (--testscore > 0) {
14d7ec11 248 for (i = 0; i < nr_methods; i++) {
657b6245 249 if (scores[i] == testscore) {
6ee73861 250 NV_TRACE(dev, "Using BIOS image from %s\n",
657b6245
MK		 251 methods[i].desc);
252 methods[i].loadbios(dev, data);
6ee73861
BS		 253 return true;
254 }
6ee73861
BS		 255 }
256 }
257
258 NV_ERROR(dev, "No valid BIOS image found\n");
259 return false;
260}
261
262struct init_tbl_entry {
263 char *name;
264 uint8_t id;
9170a824
BS		 265 /* Return:
266 * > 0: success, length of opcode
267 * 0: success, but abort further parsing of table (INIT_DONE etc)
268 * < 0: failure, table parsing will be aborted
269 */
37383650 270 int (*handler)(struct nvbios *, uint16_t, struct init_exec *);
6ee73861
BS		 271};
272
273struct bit_entry {
274 uint8_t id[2];
275 uint16_t length;
276 uint16_t offset;
277};
278
279static int parse_init_table(struct nvbios *, unsigned int, struct init_exec *);
280
281#define MACRO_INDEX_SIZE 2
282#define MACRO_SIZE 8
283#define CONDITION_SIZE 12
284#define IO_FLAG_CONDITION_SIZE 9
285#define IO_CONDITION_SIZE 5
286#define MEM_INIT_SIZE 66
287
288static void still_alive(void)
289{
290#if 0
291 sync();
292 msleep(2);
293#endif
294}
295
296static uint32_t
297munge_reg(struct nvbios *bios, uint32_t reg)
298{
299 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
300 struct dcb_entry *dcbent = bios->display.output;
301
302 if (dev_priv->card_type < NV_50)
303 return reg;
304
305 if (reg & 0x40000000) {
306 BUG_ON(!dcbent);
307
308 reg += (ffs(dcbent->or) - 1) * 0x800;
309 if ((reg & 0x20000000) && !(dcbent->sorconf.link & 1))
310 reg += 0x00000080;
311 }
312
313 reg &= ~0x60000000;
314 return reg;
315}
316
317static int
318valid_reg(struct nvbios *bios, uint32_t reg)
319{
320 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
321 struct drm_device *dev = bios->dev;
322
323 /* C51 has misaligned regs on purpose. Marvellous */
9855e584 324 if (reg & 0x2 ||
04a39c57 325 (reg & 0x1 && dev_priv->vbios.chip_version != 0x51))
9855e584
BS		 326 NV_ERROR(dev, "======= misaligned reg 0x%08X =======\n", reg);
327
328 /* warn on C51 regs that haven't been verified accessible in tracing */
04a39c57 329 if (reg & 0x1 && dev_priv->vbios.chip_version == 0x51 &&
6ee73861
BS		 330 reg != 0x130d && reg != 0x1311 && reg != 0x60081d)
331 NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n",
332 reg);
333
9855e584
BS		 334 if (reg >= (8*1024*1024)) {
335 NV_ERROR(dev, "=== reg 0x%08x out of mapped bounds ===\n", reg);
336 return 0;
6ee73861 337 }
9855e584
BS		 338
339 return 1;
6ee73861
BS		 340}
341
342static bool
343valid_idx_port(struct nvbios *bios, uint16_t port)
344{
345 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
346 struct drm_device *dev = bios->dev;
347
348 /*
349 * If adding more ports here, the read/write functions below will need
350 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
351 * used for the port in question
352 */
353 if (dev_priv->card_type < NV_50) {
354 if (port == NV_CIO_CRX__COLOR)
355 return true;
356 if (port == NV_VIO_SRX)
357 return true;
358 } else {
359 if (port == NV_CIO_CRX__COLOR)
360 return true;
361 }
362
363 NV_ERROR(dev, "========== unknown indexed io port 0x%04X ==========\n",
364 port);
365
366 return false;
367}
368
369static bool
370valid_port(struct nvbios *bios, uint16_t port)
371{
372 struct drm_device *dev = bios->dev;
373
374 /*
375 * If adding more ports here, the read/write functions below will need
376 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
377 * used for the port in question
378 */
379 if (port == NV_VIO_VSE2)
380 return true;
381
382 NV_ERROR(dev, "========== unknown io port 0x%04X ==========\n", port);
383
384 return false;
385}
386
387static uint32_t
388bios_rd32(struct nvbios *bios, uint32_t reg)
389{
390 uint32_t data;
391
392 reg = munge_reg(bios, reg);
393 if (!valid_reg(bios, reg))
394 return 0;
395
396 /*
397 * C51 sometimes uses regs with bit0 set in the address. For these
398 * cases there should exist a translation in a BIOS table to an IO
399 * port address which the BIOS uses for accessing the reg
400 *
401 * These only seem to appear for the power control regs to a flat panel,
402 * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs
403 * for 0x1308 and 0x1310 are used - hence the mask below. An S3
404 * suspend-resume mmio trace from a C51 will be required to see if this
405 * is true for the power microcode in 0x14.., or whether the direct IO
406 * port access method is needed
407 */
408 if (reg & 0x1)
409 reg &= ~0x1;
410
411 data = nv_rd32(bios->dev, reg);
412
413 BIOSLOG(bios, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
414
415 return data;
416}
417
418static void
419bios_wr32(struct nvbios *bios, uint32_t reg, uint32_t data)
420{
421 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
422
423 reg = munge_reg(bios, reg);
424 if (!valid_reg(bios, reg))
425 return;
426
427 /* see note in bios_rd32 */
428 if (reg & 0x1)
429 reg &= 0xfffffffe;
430
431 LOG_OLD_VALUE(bios_rd32(bios, reg));
432 BIOSLOG(bios, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
433
04a39c57 434 if (dev_priv->vbios.execute) {
6ee73861
BS		 435 still_alive();
436 nv_wr32(bios->dev, reg, data);
437 }
438}
439
440static uint8_t
441bios_idxprt_rd(struct nvbios *bios, uint16_t port, uint8_t index)
442{
443 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
444 struct drm_device *dev = bios->dev;
445 uint8_t data;
446
447 if (!valid_idx_port(bios, port))
448 return 0;
449
450 if (dev_priv->card_type < NV_50) {
451 if (port == NV_VIO_SRX)
452 data = NVReadVgaSeq(dev, bios->state.crtchead, index);
453 else /* assume NV_CIO_CRX__COLOR */
454 data = NVReadVgaCrtc(dev, bios->state.crtchead, index);
455 } else {
456 uint32_t data32;
457
458 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
459 data = (data32 >> ((index & 3) << 3)) & 0xff;
460 }
461
462 BIOSLOG(bios, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, "
463 "Head: 0x%02X, Data: 0x%02X\n",
464 port, index, bios->state.crtchead, data);
465 return data;
466}
467
468static void
469bios_idxprt_wr(struct nvbios *bios, uint16_t port, uint8_t index, uint8_t data)
470{
471 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
472 struct drm_device *dev = bios->dev;
473
474 if (!valid_idx_port(bios, port))
475 return;
476
477 /*
478 * The current head is maintained in the nvbios member state.crtchead.
479 * We trap changes to CR44 and update the head variable and hence the
480 * register set written.
481 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance
482 * of the write, and to head1 after the write
483 */
484 if (port == NV_CIO_CRX__COLOR && index == NV_CIO_CRE_44 &&
485 data != NV_CIO_CRE_44_HEADB)
486 bios->state.crtchead = 0;
487
488 LOG_OLD_VALUE(bios_idxprt_rd(bios, port, index));
489 BIOSLOG(bios, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, "
490 "Head: 0x%02X, Data: 0x%02X\n",
491 port, index, bios->state.crtchead, data);
492
493 if (bios->execute && dev_priv->card_type < NV_50) {
494 still_alive();
495 if (port == NV_VIO_SRX)
496 NVWriteVgaSeq(dev, bios->state.crtchead, index, data);
497 else /* assume NV_CIO_CRX__COLOR */
498 NVWriteVgaCrtc(dev, bios->state.crtchead, index, data);
499 } else
500 if (bios->execute) {
501 uint32_t data32, shift = (index & 3) << 3;
502
503 still_alive();
504
505 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
506 data32 &= ~(0xff << shift);
507 data32 |= (data << shift);
508 bios_wr32(bios, NV50_PDISPLAY_VGACRTC(index & ~3), data32);
509 }
510
511 if (port == NV_CIO_CRX__COLOR &&
512 index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB)
513 bios->state.crtchead = 1;
514}
515
516static uint8_t
517bios_port_rd(struct nvbios *bios, uint16_t port)
518{
519 uint8_t data, head = bios->state.crtchead;
520
521 if (!valid_port(bios, port))
522 return 0;
523
524 data = NVReadPRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port);
525
526 BIOSLOG(bios, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
527 port, head, data);
528
529 return data;
530}
531
532static void
533bios_port_wr(struct nvbios *bios, uint16_t port, uint8_t data)
534{
535 int head = bios->state.crtchead;
536
537 if (!valid_port(bios, port))
538 return;
539
540 LOG_OLD_VALUE(bios_port_rd(bios, port));
541 BIOSLOG(bios, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
542 port, head, data);
543
544 if (!bios->execute)
545 return;
546
547 still_alive();
548 NVWritePRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port, data);
549}
550
551static bool
552io_flag_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
553{
554 /*
555 * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
556 * for the CRTC index; 1 byte for the mask to apply to the value
557 * retrieved from the CRTC; 1 byte for the shift right to apply to the
558 * masked CRTC value; 2 bytes for the offset to the flag array, to
559 * which the shifted value is added; 1 byte for the mask applied to the
560 * value read from the flag array; and 1 byte for the value to compare
561 * against the masked byte from the flag table.
562 */
563
564 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE;
565 uint16_t crtcport = ROM16(bios->data[condptr]);
566 uint8_t crtcindex = bios->data[condptr + 2];
567 uint8_t mask = bios->data[condptr + 3];
568 uint8_t shift = bios->data[condptr + 4];
569 uint16_t flagarray = ROM16(bios->data[condptr + 5]);
570 uint8_t flagarraymask = bios->data[condptr + 7];
571 uint8_t cmpval = bios->data[condptr + 8];
572 uint8_t data;
573
574 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
575 "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, "
576 "Cmpval: 0x%02X\n",
577 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval);
578
579 data = bios_idxprt_rd(bios, crtcport, crtcindex);
580
581 data = bios->data[flagarray + ((data & mask) >> shift)];
582 data &= flagarraymask;
583
584 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
585 offset, data, cmpval);
586
587 return (data == cmpval);
588}
589
590static bool
591bios_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
592{
593 /*
594 * The condition table entry has 4 bytes for the address of the
595 * register to check, 4 bytes for a mask to apply to the register and
596 * 4 for a test comparison value
597 */
598
599 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
600 uint32_t reg = ROM32(bios->data[condptr]);
601 uint32_t mask = ROM32(bios->data[condptr + 4]);
602 uint32_t cmpval = ROM32(bios->data[condptr + 8]);
603 uint32_t data;
604
605 BIOSLOG(bios, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n",
606 offset, cond, reg, mask);
607
608 data = bios_rd32(bios, reg) & mask;
609
610 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
611 offset, data, cmpval);
612
613 return (data == cmpval);
614}
615
616static bool
617io_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
618{
619 /*
620 * The IO condition entry has 2 bytes for the IO port address; 1 byte
621 * for the index to write to io_port; 1 byte for the mask to apply to
622 * the byte read from io_port+1; and 1 byte for the value to compare
623 * against the masked byte.
624 */
625
626 uint16_t condptr = bios->io_condition_tbl_ptr + cond * IO_CONDITION_SIZE;
627 uint16_t io_port = ROM16(bios->data[condptr]);
628 uint8_t port_index = bios->data[condptr + 2];
629 uint8_t mask = bios->data[condptr + 3];
630 uint8_t cmpval = bios->data[condptr + 4];
631
632 uint8_t data = bios_idxprt_rd(bios, io_port, port_index) & mask;
633
634 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
635 offset, data, cmpval);
636
637 return (data == cmpval);
638}
639
640static int
641nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk)
642{
643 struct drm_nouveau_private *dev_priv = dev->dev_private;
644 uint32_t reg0 = nv_rd32(dev, reg + 0);
645 uint32_t reg1 = nv_rd32(dev, reg + 4);
646 struct nouveau_pll_vals pll;
647 struct pll_lims pll_limits;
648 int ret;
649
650 ret = get_pll_limits(dev, reg, &pll_limits);
651 if (ret)
652 return ret;
653
654 clk = nouveau_calc_pll_mnp(dev, &pll_limits, clk, &pll);
655 if (!clk)
656 return -ERANGE;
657
658 reg0 = (reg0 & 0xfff8ffff) | (pll.log2P << 16);
659 reg1 = (reg1 & 0xffff0000) | (pll.N1 << 8) | pll.M1;
660
04a39c57 661 if (dev_priv->vbios.execute) {
6ee73861
BS		 662 still_alive();
663 nv_wr32(dev, reg + 4, reg1);
664 nv_wr32(dev, reg + 0, reg0);
665 }
666
667 return 0;
668}
669
670static int
671setPLL(struct nvbios *bios, uint32_t reg, uint32_t clk)
672{
673 struct drm_device *dev = bios->dev;
674 struct drm_nouveau_private *dev_priv = dev->dev_private;
675 /* clk in kHz */
676 struct pll_lims pll_lim;
677 struct nouveau_pll_vals pllvals;
678 int ret;
679
680 if (dev_priv->card_type >= NV_50)
681 return nv50_pll_set(dev, reg, clk);
682
683 /* high regs (such as in the mac g5 table) are not -= 4 */
684 ret = get_pll_limits(dev, reg > 0x405c ? reg : reg - 4, &pll_lim);
685 if (ret)
686 return ret;
687
688 clk = nouveau_calc_pll_mnp(dev, &pll_lim, clk, &pllvals);
689 if (!clk)
690 return -ERANGE;
691
692 if (bios->execute) {
693 still_alive();
694 nouveau_hw_setpll(dev, reg, &pllvals);
695 }
696
697 return 0;
698}
699
700static int dcb_entry_idx_from_crtchead(struct drm_device *dev)
701{
702 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 703 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 704
705 /*
706 * For the results of this function to be correct, CR44 must have been
707 * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0,
708 * and the DCB table parsed, before the script calling the function is
709 * run. run_digital_op_script is example of how to do such setup
710 */
711
712 uint8_t dcb_entry = NVReadVgaCrtc5758(dev, bios->state.crtchead, 0);
713
7f245b20 714 if (dcb_entry > bios->dcb.entries) {
6ee73861
BS		 715 NV_ERROR(dev, "CR58 doesn't have a valid DCB entry currently "
716 "(%02X)\n", dcb_entry);
717 dcb_entry = 0x7f; /* unused / invalid marker */
718 }
719
720 return dcb_entry;
721}
722
f8b0be1a
BS		 723static int
724read_dcb_i2c_entry(struct drm_device *dev, int dcb_version, uint8_t *i2ctable, int index, struct dcb_i2c_entry *i2c)
725{
726 uint8_t dcb_i2c_ver = dcb_version, headerlen = 0, entry_len = 4;
727 int i2c_entries = DCB_MAX_NUM_I2C_ENTRIES;
728 int recordoffset = 0, rdofs = 1, wrofs = 0;
729 uint8_t port_type = 0;
730
731 if (!i2ctable)
732 return -EINVAL;
733
734 if (dcb_version >= 0x30) {
735 if (i2ctable[0] != dcb_version) /* necessary? */
736 NV_WARN(dev,
737 "DCB I2C table version mismatch (%02X vs %02X)\n",
738 i2ctable[0], dcb_version);
739 dcb_i2c_ver = i2ctable[0];
740 headerlen = i2ctable[1];
741 if (i2ctable[2] <= DCB_MAX_NUM_I2C_ENTRIES)
742 i2c_entries = i2ctable[2];
743 else
744 NV_WARN(dev,
745 "DCB I2C table has more entries than indexable "
746 "(%d entries, max %d)\n", i2ctable[2],
747 DCB_MAX_NUM_I2C_ENTRIES);
748 entry_len = i2ctable[3];
749 /* [4] is i2c_default_indices, read in parse_dcb_table() */
750 }
751 /*
752 * It's your own fault if you call this function on a DCB 1.1 BIOS --
753 * the test below is for DCB 1.2
754 */
755 if (dcb_version < 0x14) {
756 recordoffset = 2;
757 rdofs = 0;
758 wrofs = 1;
759 }
760
761 if (index == 0xf)
762 return 0;
763 if (index >= i2c_entries) {
764 NV_ERROR(dev, "DCB I2C index too big (%d >= %d)\n",
765 index, i2ctable[2]);
766 return -ENOENT;
767 }
768 if (i2ctable[headerlen + entry_len * index + 3] == 0xff) {
769 NV_ERROR(dev, "DCB I2C entry invalid\n");
770 return -EINVAL;
771 }
772
773 if (dcb_i2c_ver >= 0x30) {
774 port_type = i2ctable[headerlen + recordoffset + 3 + entry_len * index];
775
776 /*
777 * Fixup for chips using same address offset for read and
778 * write.
779 */
780 if (port_type == 4) /* seen on C51 */
781 rdofs = wrofs = 1;
782 if (port_type >= 5) /* G80+ */
783 rdofs = wrofs = 0;
784 }
785
786 if (dcb_i2c_ver >= 0x40) {
787 if (port_type != 5 && port_type != 6)
788 NV_WARN(dev, "DCB I2C table has port type %d\n", port_type);
789
790 i2c->entry = ROM32(i2ctable[headerlen + recordoffset + entry_len * index]);
791 }
792
793 i2c->port_type = port_type;
794 i2c->read = i2ctable[headerlen + recordoffset + rdofs + entry_len * index];
795 i2c->write = i2ctable[headerlen + recordoffset + wrofs + entry_len * index];
796
797 return 0;
798}
799
6ee73861
BS		 800static struct nouveau_i2c_chan *
801init_i2c_device_find(struct drm_device *dev, int i2c_index)
802{
803 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 804 struct dcb_table *dcb = &dev_priv->vbios.dcb;
6ee73861
BS		 805
806 if (i2c_index == 0xff) {
807 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
808 int idx = dcb_entry_idx_from_crtchead(dev), shift = 0;
7f245b20 809 int default_indices = dcb->i2c_default_indices;
6ee73861 810
7f245b20 811 if (idx != 0x7f && dcb->entry[idx].i2c_upper_default)
6ee73861
BS		 812 shift = 4;
813
814 i2c_index = (default_indices >> shift) & 0xf;
815 }
816 if (i2c_index == 0x80) /* g80+ */
7f245b20 817 i2c_index = dcb->i2c_default_indices & 0xf;
04f542c0
BS		 818 else
819 if (i2c_index == 0x81)
820 i2c_index = (dcb->i2c_default_indices & 0xf0) >> 4;
6ee73861 821
75047944 822 if (i2c_index >= DCB_MAX_NUM_I2C_ENTRIES) {
f8b0be1a
BS		 823 NV_ERROR(dev, "invalid i2c_index 0x%x\n", i2c_index);
824 return NULL;
825 }
826
827 /* Make sure i2c table entry has been parsed, it may not
828 * have been if this is a bus not referenced by a DCB encoder
829 */
830 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table,
831 i2c_index, &dcb->i2c[i2c_index]);
832
6ee73861
BS		 833 return nouveau_i2c_find(dev, i2c_index);
834}
835
7f245b20
BS		 836static uint32_t
837get_tmds_index_reg(struct drm_device *dev, uint8_t mlv)
6ee73861
BS		 838{
839 /*
840 * For mlv < 0x80, it is an index into a table of TMDS base addresses.
841 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
842 * CR58 for CR57 = 0 to index a table of offsets to the basic
843 * 0x6808b0 address.
844 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
845 * CR58 for CR57 = 0 to index a table of offsets to the basic
846 * 0x6808b0 address, and then flip the offset by 8.
847 */
848
849 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 850 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 851 const int pramdac_offset[13] = {
852 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
853 const uint32_t pramdac_table[4] = {
854 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
855
856 if (mlv >= 0x80) {
857 int dcb_entry, dacoffset;
858
859 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
860 dcb_entry = dcb_entry_idx_from_crtchead(dev);
861 if (dcb_entry == 0x7f)
862 return 0;
7f245b20 863 dacoffset = pramdac_offset[bios->dcb.entry[dcb_entry].or];
6ee73861
BS		 864 if (mlv == 0x81)
865 dacoffset ^= 8;
866 return 0x6808b0 + dacoffset;
867 } else {
df31ef4d 868 if (mlv >= ARRAY_SIZE(pramdac_table)) {
6ee73861
BS		 869 NV_ERROR(dev, "Magic Lookup Value too big (%02X)\n",
870 mlv);
871 return 0;
872 }
873 return pramdac_table[mlv];
874 }
875}
876
37383650 877static int
6ee73861
BS		 878init_io_restrict_prog(struct nvbios *bios, uint16_t offset,
879 struct init_exec *iexec)
880{
881 /*
882 * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2')
883 *
884 * offset (8 bit): opcode
885 * offset + 1 (16 bit): CRTC port
886 * offset + 3 (8 bit): CRTC index
887 * offset + 4 (8 bit): mask
888 * offset + 5 (8 bit): shift
889 * offset + 6 (8 bit): count
890 * offset + 7 (32 bit): register
891 * offset + 11 (32 bit): configuration 1
892 * ...
893 *
894 * Starting at offset + 11 there are "count" 32 bit values.
895 * To find out which value to use read index "CRTC index" on "CRTC
896 * port", AND this value with "mask" and then bit shift right "shift"
897 * bits. Read the appropriate value using this index and write to
898 * "register"
899 */
900
901 uint16_t crtcport = ROM16(bios->data[offset + 1]);
902 uint8_t crtcindex = bios->data[offset + 3];
903 uint8_t mask = bios->data[offset + 4];
904 uint8_t shift = bios->data[offset + 5];
905 uint8_t count = bios->data[offset + 6];
906 uint32_t reg = ROM32(bios->data[offset + 7]);
907 uint8_t config;
908 uint32_t configval;
37383650 909 int len = 11 + count * 4;
6ee73861
BS		 910
911 if (!iexec->execute)
37383650 912 return len;
6ee73861
BS		 913
914 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
915 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
916 offset, crtcport, crtcindex, mask, shift, count, reg);
917
918 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
919 if (config > count) {
920 NV_ERROR(bios->dev,
921 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
922 offset, config, count);
9170a824 923 return -EINVAL;
6ee73861
BS		 924 }
925
926 configval = ROM32(bios->data[offset + 11 + config * 4]);
927
928 BIOSLOG(bios, "0x%04X: Writing config %02X\n", offset, config);
929
930 bios_wr32(bios, reg, configval);
931
37383650 932 return len;
6ee73861
BS		 933}
934
37383650 935static int
6ee73861
BS		 936init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
937{
938 /*
939 * INIT_REPEAT opcode: 0x33 ('3')
940 *
941 * offset (8 bit): opcode
942 * offset + 1 (8 bit): count
943 *
944 * Execute script following this opcode up to INIT_REPEAT_END
945 * "count" times
946 */
947
948 uint8_t count = bios->data[offset + 1];
949 uint8_t i;
950
951 /* no iexec->execute check by design */
952
953 BIOSLOG(bios, "0x%04X: Repeating following segment %d times\n",
954 offset, count);
955
956 iexec->repeat = true;
957
958 /*
959 * count - 1, as the script block will execute once when we leave this
960 * opcode -- this is compatible with bios behaviour as:
961 * a) the block is always executed at least once, even if count == 0
962 * b) the bios interpreter skips to the op following INIT_END_REPEAT,
963 * while we don't
964 */
965 for (i = 0; i < count - 1; i++)
966 parse_init_table(bios, offset + 2, iexec);
967
968 iexec->repeat = false;
969
37383650 970 return 2;
6ee73861
BS		 971}
972
37383650 973static int
6ee73861
BS		 974init_io_restrict_pll(struct nvbios *bios, uint16_t offset,
975 struct init_exec *iexec)
976{
977 /*
978 * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4')
979 *
980 * offset (8 bit): opcode
981 * offset + 1 (16 bit): CRTC port
982 * offset + 3 (8 bit): CRTC index
983 * offset + 4 (8 bit): mask
984 * offset + 5 (8 bit): shift
985 * offset + 6 (8 bit): IO flag condition index
986 * offset + 7 (8 bit): count
987 * offset + 8 (32 bit): register
988 * offset + 12 (16 bit): frequency 1
989 * ...
990 *
991 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
992 * Set PLL register "register" to coefficients for frequency n,
993 * selected by reading index "CRTC index" of "CRTC port" ANDed with
994 * "mask" and shifted right by "shift".
995 *
996 * If "IO flag condition index" > 0, and condition met, double
997 * frequency before setting it.
998 */
999
1000 uint16_t crtcport = ROM16(bios->data[offset + 1]);
1001 uint8_t crtcindex = bios->data[offset + 3];
1002 uint8_t mask = bios->data[offset + 4];
1003 uint8_t shift = bios->data[offset + 5];
1004 int8_t io_flag_condition_idx = bios->data[offset + 6];
1005 uint8_t count = bios->data[offset + 7];
1006 uint32_t reg = ROM32(bios->data[offset + 8]);
1007 uint8_t config;
1008 uint16_t freq;
37383650 1009 int len = 12 + count * 2;
6ee73861
BS		 1010
1011 if (!iexec->execute)
37383650 1012 return len;
6ee73861
BS		 1013
1014 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1015 "Shift: 0x%02X, IO Flag Condition: 0x%02X, "
1016 "Count: 0x%02X, Reg: 0x%08X\n",
1017 offset, crtcport, crtcindex, mask, shift,
1018 io_flag_condition_idx, count, reg);
1019
1020 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
1021 if (config > count) {
1022 NV_ERROR(bios->dev,
1023 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1024 offset, config, count);
9170a824 1025 return -EINVAL;
6ee73861
BS		 1026 }
1027
1028 freq = ROM16(bios->data[offset + 12 + config * 2]);
1029
1030 if (io_flag_condition_idx > 0) {
1031 if (io_flag_condition_met(bios, offset, io_flag_condition_idx)) {
1032 BIOSLOG(bios, "0x%04X: Condition fulfilled -- "
1033 "frequency doubled\n", offset);
1034 freq *= 2;
1035 } else
1036 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- "
1037 "frequency unchanged\n", offset);
1038 }
1039
1040 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
1041 offset, reg, config, freq);
1042
1043 setPLL(bios, reg, freq * 10);
1044
37383650 1045 return len;
6ee73861
BS		 1046}
1047
37383650 1048static int
6ee73861
BS		 1049init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1050{
1051 /*
1052 * INIT_END_REPEAT opcode: 0x36 ('6')
1053 *
1054 * offset (8 bit): opcode
1055 *
1056 * Marks the end of the block for INIT_REPEAT to repeat
1057 */
1058
1059 /* no iexec->execute check by design */
1060
1061 /*
1062 * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
1063 * we're not in repeat mode
1064 */
1065 if (iexec->repeat)
37383650 1066 return 0;
6ee73861 1067
37383650 1068 return 1;
6ee73861
BS		 1069}
1070
37383650 1071static int
6ee73861
BS		 1072init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1073{
1074 /*
1075 * INIT_COPY opcode: 0x37 ('7')
1076 *
1077 * offset (8 bit): opcode
1078 * offset + 1 (32 bit): register
1079 * offset + 5 (8 bit): shift
1080 * offset + 6 (8 bit): srcmask
1081 * offset + 7 (16 bit): CRTC port
1082 * offset + 9 (8 bit): CRTC index
1083 * offset + 10 (8 bit): mask
1084 *
1085 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
1086 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC
1087 * port
1088 */
1089
1090 uint32_t reg = ROM32(bios->data[offset + 1]);
1091 uint8_t shift = bios->data[offset + 5];
1092 uint8_t srcmask = bios->data[offset + 6];
1093 uint16_t crtcport = ROM16(bios->data[offset + 7]);
1094 uint8_t crtcindex = bios->data[offset + 9];
1095 uint8_t mask = bios->data[offset + 10];
1096 uint32_t data;
1097 uint8_t crtcdata;
1098
1099 if (!iexec->execute)
37383650 1100 return 11;
6ee73861
BS		 1101
1102 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, "
1103 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
1104 offset, reg, shift, srcmask, crtcport, crtcindex, mask);
1105
1106 data = bios_rd32(bios, reg);
1107
1108 if (shift < 0x80)
1109 data >>= shift;
1110 else
1111 data <<= (0x100 - shift);
1112
1113 data &= srcmask;
1114
1115 crtcdata = bios_idxprt_rd(bios, crtcport, crtcindex) & mask;
1116 crtcdata |= (uint8_t)data;
1117 bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata);
1118
37383650 1119 return 11;
6ee73861
BS		 1120}
1121
37383650 1122static int
6ee73861
BS		 1123init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1124{
1125 /*
1126 * INIT_NOT opcode: 0x38 ('8')
1127 *
1128 * offset (8 bit): opcode
1129 *
1130 * Invert the current execute / no-execute condition (i.e. "else")
1131 */
1132 if (iexec->execute)
1133 BIOSLOG(bios, "0x%04X: ------ Skipping following commands ------\n", offset);
1134 else
1135 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset);
1136
1137 iexec->execute = !iexec->execute;
37383650 1138 return 1;
6ee73861
BS		 1139}
1140
37383650 1141static int
6ee73861
BS		 1142init_io_flag_condition(struct nvbios *bios, uint16_t offset,
1143 struct init_exec *iexec)
1144{
1145 /*
1146 * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9')
1147 *
1148 * offset (8 bit): opcode
1149 * offset + 1 (8 bit): condition number
1150 *
1151 * Check condition "condition number" in the IO flag condition table.
1152 * If condition not met skip subsequent opcodes until condition is
1153 * inverted (INIT_NOT), or we hit INIT_RESUME
1154 */
1155
1156 uint8_t cond = bios->data[offset + 1];
1157
1158 if (!iexec->execute)
37383650 1159 return 2;
6ee73861
BS		 1160
1161 if (io_flag_condition_met(bios, offset, cond))
1162 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
1163 else {
1164 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
1165 iexec->execute = false;
1166 }
1167
37383650 1168 return 2;
6ee73861
BS		 1169}
1170
25908b77
BS		 1171static int
1172init_dp_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1173{
1174 /*
1175 * INIT_DP_CONDITION opcode: 0x3A ('')
1176 *
1177 * offset (8 bit): opcode
1178 * offset + 1 (8 bit): "sub" opcode
1179 * offset + 2 (8 bit): unknown
1180 *
1181 */
1182
1183 struct bit_displayport_encoder_table *dpe = NULL;
1184 struct dcb_entry *dcb = bios->display.output;
1185 struct drm_device *dev = bios->dev;
1186 uint8_t cond = bios->data[offset + 1];
1187 int dummy;
1188
1189 BIOSLOG(bios, "0x%04X: subop 0x%02X\n", offset, cond);
1190
1191 if (!iexec->execute)
1192 return 3;
1193
1194 dpe = nouveau_bios_dp_table(dev, dcb, &dummy);
1195 if (!dpe) {
1196 NV_ERROR(dev, "0x%04X: INIT_3A: no encoder table!!\n", offset);
1197 return -EINVAL;
1198 }
1199
1200 switch (cond) {
1201 case 0:
1202 {
1203 struct dcb_connector_table_entry *ent =
1204 &bios->dcb.connector.entry[dcb->connector];
1205
1206 if (ent->type != DCB_CONNECTOR_eDP)
1207 iexec->execute = false;
1208 }
1209 break;
1210 case 1:
1211 case 2:
1212 if (!(dpe->unknown & cond))
1213 iexec->execute = false;
1214 break;
1215 case 5:
1216 {
1217 struct nouveau_i2c_chan *auxch;
1218 int ret;
1219
1220 auxch = nouveau_i2c_find(dev, bios->display.output->i2c_index);
1221 if (!auxch)
1222 return -ENODEV;
1223
1224 ret = nouveau_dp_auxch(auxch, 9, 0xd, &cond, 1);
1225 if (ret)
1226 return ret;
1227
1228 if (cond & 1)
1229 iexec->execute = false;
1230 }
1231 break;
1232 default:
1233 NV_WARN(dev, "0x%04X: unknown INIT_3A op: %d\n", offset, cond);
1234 break;
1235 }
1236
1237 if (iexec->execute)
1238 BIOSLOG(bios, "0x%04X: continuing to execute\n", offset);
1239 else
1240 BIOSLOG(bios, "0x%04X: skipping following commands\n", offset);
1241
1242 return 3;
1243}
1244
1245static int
1246init_op_3b(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1247{
1248 /*
1249 * INIT_3B opcode: 0x3B ('')
1250 *
1251 * offset (8 bit): opcode
1252 * offset + 1 (8 bit): crtc index
1253 *
1254 */
1255
1256 uint8_t or = ffs(bios->display.output->or) - 1;
1257 uint8_t index = bios->data[offset + 1];
1258 uint8_t data;
1259
1260 if (!iexec->execute)
1261 return 2;
1262
1263 data = bios_idxprt_rd(bios, 0x3d4, index);
1264 bios_idxprt_wr(bios, 0x3d4, index, data & ~(1 << or));
1265 return 2;
1266}
1267
1268static int
1269init_op_3c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1270{
1271 /*
1272 * INIT_3C opcode: 0x3C ('')
1273 *
1274 * offset (8 bit): opcode
1275 * offset + 1 (8 bit): crtc index
1276 *
1277 */
1278
1279 uint8_t or = ffs(bios->display.output->or) - 1;
1280 uint8_t index = bios->data[offset + 1];
1281 uint8_t data;
1282
1283 if (!iexec->execute)
1284 return 2;
1285
1286 data = bios_idxprt_rd(bios, 0x3d4, index);
1287 bios_idxprt_wr(bios, 0x3d4, index, data | (1 << or));
1288 return 2;
1289}
1290
37383650 1291static int
6ee73861
BS		 1292init_idx_addr_latched(struct nvbios *bios, uint16_t offset,
1293 struct init_exec *iexec)
1294{
1295 /*
1296 * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I')
1297 *
1298 * offset (8 bit): opcode
1299 * offset + 1 (32 bit): control register
1300 * offset + 5 (32 bit): data register
1301 * offset + 9 (32 bit): mask
1302 * offset + 13 (32 bit): data
1303 * offset + 17 (8 bit): count
1304 * offset + 18 (8 bit): address 1
1305 * offset + 19 (8 bit): data 1
1306 * ...
1307 *
1308 * For each of "count" address and data pairs, write "data n" to
1309 * "data register", read the current value of "control register",
1310 * and write it back once ANDed with "mask", ORed with "data",
1311 * and ORed with "address n"
1312 */
1313
1314 uint32_t controlreg = ROM32(bios->data[offset + 1]);
1315 uint32_t datareg = ROM32(bios->data[offset + 5]);
1316 uint32_t mask = ROM32(bios->data[offset + 9]);
1317 uint32_t data = ROM32(bios->data[offset + 13]);
1318 uint8_t count = bios->data[offset + 17];
37383650 1319 int len = 18 + count * 2;
6ee73861
BS		 1320 uint32_t value;
1321 int i;
1322
1323 if (!iexec->execute)
37383650 1324 return len;
6ee73861
BS		 1325
1326 BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, "
1327 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
1328 offset, controlreg, datareg, mask, data, count);
1329
1330 for (i = 0; i < count; i++) {
1331 uint8_t instaddress = bios->data[offset + 18 + i * 2];
1332 uint8_t instdata = bios->data[offset + 19 + i * 2];
1333
1334 BIOSLOG(bios, "0x%04X: Address: 0x%02X, Data: 0x%02X\n",
1335 offset, instaddress, instdata);
1336
1337 bios_wr32(bios, datareg, instdata);
1338 value = bios_rd32(bios, controlreg) & mask;
1339 value |= data;
1340 value |= instaddress;
1341 bios_wr32(bios, controlreg, value);
1342 }
1343
37383650 1344 return len;
6ee73861
BS		 1345}
1346
37383650 1347static int
6ee73861
BS		 1348init_io_restrict_pll2(struct nvbios *bios, uint16_t offset,
1349 struct init_exec *iexec)
1350{
1351 /*
1352 * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J')
1353 *
1354 * offset (8 bit): opcode
1355 * offset + 1 (16 bit): CRTC port
1356 * offset + 3 (8 bit): CRTC index
1357 * offset + 4 (8 bit): mask
1358 * offset + 5 (8 bit): shift
1359 * offset + 6 (8 bit): count
1360 * offset + 7 (32 bit): register
1361 * offset + 11 (32 bit): frequency 1
1362 * ...
1363 *
1364 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
1365 * Set PLL register "register" to coefficients for frequency n,
1366 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1367 * "mask" and shifted right by "shift".
1368 */
1369
1370 uint16_t crtcport = ROM16(bios->data[offset + 1]);
1371 uint8_t crtcindex = bios->data[offset + 3];
1372 uint8_t mask = bios->data[offset + 4];
1373 uint8_t shift = bios->data[offset + 5];
1374 uint8_t count = bios->data[offset + 6];
1375 uint32_t reg = ROM32(bios->data[offset + 7]);
37383650 1376 int len = 11 + count * 4;
6ee73861
BS		 1377 uint8_t config;
1378 uint32_t freq;
1379
1380 if (!iexec->execute)
37383650 1381 return len;
6ee73861
BS		 1382
1383 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1384 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1385 offset, crtcport, crtcindex, mask, shift, count, reg);
1386
1387 if (!reg)
37383650 1388 return len;
6ee73861
BS		 1389
1390 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
1391 if (config > count) {
1392 NV_ERROR(bios->dev,
1393 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1394 offset, config, count);
9170a824 1395 return -EINVAL;
6ee73861
BS		 1396 }
1397
1398 freq = ROM32(bios->data[offset + 11 + config * 4]);
1399
1400 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
1401 offset, reg, config, freq);
1402
1403 setPLL(bios, reg, freq);
1404
37383650 1405 return len;
6ee73861
BS		 1406}
1407
37383650 1408static int
6ee73861
BS		 1409init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1410{
1411 /*
1412 * INIT_PLL2 opcode: 0x4B ('K')
1413 *
1414 * offset (8 bit): opcode
1415 * offset + 1 (32 bit): register
1416 * offset + 5 (32 bit): freq
1417 *
1418 * Set PLL register "register" to coefficients for frequency "freq"
1419 */
1420
1421 uint32_t reg = ROM32(bios->data[offset + 1]);
1422 uint32_t freq = ROM32(bios->data[offset + 5]);
1423
1424 if (!iexec->execute)
37383650 1425 return 9;
6ee73861
BS		 1426
1427 BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
1428 offset, reg, freq);
1429
1430 setPLL(bios, reg, freq);
37383650 1431 return 9;
6ee73861
BS		 1432}
1433
37383650 1434static int
6ee73861
BS		 1435init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1436{
1437 /*
1438 * INIT_I2C_BYTE opcode: 0x4C ('L')
1439 *
1440 * offset (8 bit): opcode
1441 * offset + 1 (8 bit): DCB I2C table entry index
1442 * offset + 2 (8 bit): I2C slave address
1443 * offset + 3 (8 bit): count
1444 * offset + 4 (8 bit): I2C register 1
1445 * offset + 5 (8 bit): mask 1
1446 * offset + 6 (8 bit): data 1
1447 * ...
1448 *
1449 * For each of "count" registers given by "I2C register n" on the device
1450 * addressed by "I2C slave address" on the I2C bus given by
1451 * "DCB I2C table entry index", read the register, AND the result with
1452 * "mask n" and OR it with "data n" before writing it back to the device
1453 */
1454
1455 uint8_t i2c_index = bios->data[offset + 1];
893887ed 1456 uint8_t i2c_address = bios->data[offset + 2] >> 1;
6ee73861
BS		 1457 uint8_t count = bios->data[offset + 3];
1458 struct nouveau_i2c_chan *chan;
893887ed
BS		 1459 int len = 4 + count * 3;
1460 int ret, i;
6ee73861
BS		 1461
1462 if (!iexec->execute)
37383650 1463 return len;
6ee73861
BS		 1464
1465 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1466 "Count: 0x%02X\n",
1467 offset, i2c_index, i2c_address, count);
1468
1469 chan = init_i2c_device_find(bios->dev, i2c_index);
1470 if (!chan)
9170a824 1471 return -ENODEV;
6ee73861
BS		 1472
1473 for (i = 0; i < count; i++) {
893887ed 1474 uint8_t reg = bios->data[offset + 4 + i * 3];
6ee73861
BS		 1475 uint8_t mask = bios->data[offset + 5 + i * 3];
1476 uint8_t data = bios->data[offset + 6 + i * 3];
893887ed 1477 union i2c_smbus_data val;
6ee73861 1478
893887ed
BS		 1479 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1480 I2C_SMBUS_READ, reg,
1481 I2C_SMBUS_BYTE_DATA, &val);
1482 if (ret < 0)
1483 return ret;
6ee73861
BS		 1484
1485 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
1486 "Mask: 0x%02X, Data: 0x%02X\n",
893887ed 1487 offset, reg, val.byte, mask, data);
6ee73861 1488
893887ed
BS		 1489 if (!bios->execute)
1490 continue;
6ee73861 1491
893887ed
BS		 1492 val.byte &= mask;
1493 val.byte |= data;
1494 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1495 I2C_SMBUS_WRITE, reg,
1496 I2C_SMBUS_BYTE_DATA, &val);
1497 if (ret < 0)
1498 return ret;
6ee73861
BS		 1499 }
1500
37383650 1501 return len;
6ee73861
BS		 1502}
1503
37383650 1504static int
6ee73861
BS		 1505init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1506{
1507 /*
1508 * INIT_ZM_I2C_BYTE opcode: 0x4D ('M')
1509 *
1510 * offset (8 bit): opcode
1511 * offset + 1 (8 bit): DCB I2C table entry index
1512 * offset + 2 (8 bit): I2C slave address
1513 * offset + 3 (8 bit): count
1514 * offset + 4 (8 bit): I2C register 1
1515 * offset + 5 (8 bit): data 1
1516 * ...
1517 *
1518 * For each of "count" registers given by "I2C register n" on the device
1519 * addressed by "I2C slave address" on the I2C bus given by
1520 * "DCB I2C table entry index", set the register to "data n"
1521 */
1522
1523 uint8_t i2c_index = bios->data[offset + 1];
893887ed 1524 uint8_t i2c_address = bios->data[offset + 2] >> 1;
6ee73861
BS		 1525 uint8_t count = bios->data[offset + 3];
1526 struct nouveau_i2c_chan *chan;
893887ed
BS		 1527 int len = 4 + count * 2;
1528 int ret, i;
6ee73861
BS		 1529
1530 if (!iexec->execute)
37383650 1531 return len;
6ee73861
BS		 1532
1533 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1534 "Count: 0x%02X\n",
1535 offset, i2c_index, i2c_address, count);
1536
1537 chan = init_i2c_device_find(bios->dev, i2c_index);
1538 if (!chan)
9170a824 1539 return -ENODEV;
6ee73861
BS		 1540
1541 for (i = 0; i < count; i++) {
893887ed
BS		 1542 uint8_t reg = bios->data[offset + 4 + i * 2];
1543 union i2c_smbus_data val;
1544
1545 val.byte = bios->data[offset + 5 + i * 2];
6ee73861
BS		 1546
1547 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n",
893887ed
BS		 1548 offset, reg, val.byte);
1549
1550 if (!bios->execute)
1551 continue;
1552
1553 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1554 I2C_SMBUS_WRITE, reg,
1555 I2C_SMBUS_BYTE_DATA, &val);
1556 if (ret < 0)
1557 return ret;
6ee73861
BS		 1558 }
1559
37383650 1560 return len;
6ee73861
BS		 1561}
1562
37383650 1563static int
6ee73861
BS		 1564init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1565{
1566 /*
1567 * INIT_ZM_I2C opcode: 0x4E ('N')
1568 *
1569 * offset (8 bit): opcode
1570 * offset + 1 (8 bit): DCB I2C table entry index
1571 * offset + 2 (8 bit): I2C slave address
1572 * offset + 3 (8 bit): count
1573 * offset + 4 (8 bit): data 1
1574 * ...
1575 *
1576 * Send "count" bytes ("data n") to the device addressed by "I2C slave
1577 * address" on the I2C bus given by "DCB I2C table entry index"
1578 */
1579
1580 uint8_t i2c_index = bios->data[offset + 1];
893887ed 1581 uint8_t i2c_address = bios->data[offset + 2] >> 1;
6ee73861 1582 uint8_t count = bios->data[offset + 3];
37383650 1583 int len = 4 + count;
6ee73861
BS		 1584 struct nouveau_i2c_chan *chan;
1585 struct i2c_msg msg;
1586 uint8_t data[256];
1587 int i;
1588
1589 if (!iexec->execute)
37383650 1590 return len;
6ee73861
BS		 1591
1592 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1593 "Count: 0x%02X\n",
1594 offset, i2c_index, i2c_address, count);
1595
1596 chan = init_i2c_device_find(bios->dev, i2c_index);
1597 if (!chan)
9170a824 1598 return -ENODEV;
6ee73861
BS		 1599
1600 for (i = 0; i < count; i++) {
1601 data[i] = bios->data[offset + 4 + i];
1602
1603 BIOSLOG(bios, "0x%04X: Data: 0x%02X\n", offset, data[i]);
1604 }
1605
1606 if (bios->execute) {
1607 msg.addr = i2c_address;
1608 msg.flags = 0;
1609 msg.len = count;
1610 msg.buf = data;
1611 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
9170a824 1612 return -EIO;
6ee73861
BS		 1613 }
1614
37383650 1615 return len;
6ee73861
BS		 1616}
1617
37383650 1618static int
6ee73861
BS		 1619init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1620{
1621 /*
1622 * INIT_TMDS opcode: 0x4F ('O') (non-canon name)
1623 *
1624 * offset (8 bit): opcode
1625 * offset + 1 (8 bit): magic lookup value
1626 * offset + 2 (8 bit): TMDS address
1627 * offset + 3 (8 bit): mask
1628 * offset + 4 (8 bit): data
1629 *
1630 * Read the data reg for TMDS address "TMDS address", AND it with mask
1631 * and OR it with data, then write it back
1632 * "magic lookup value" determines which TMDS base address register is
1633 * used -- see get_tmds_index_reg()
1634 */
1635
1636 uint8_t mlv = bios->data[offset + 1];
1637 uint32_t tmdsaddr = bios->data[offset + 2];
1638 uint8_t mask = bios->data[offset + 3];
1639 uint8_t data = bios->data[offset + 4];
1640 uint32_t reg, value;
1641
1642 if (!iexec->execute)
37383650 1643 return 5;
6ee73861
BS		 1644
1645 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, "
1646 "Mask: 0x%02X, Data: 0x%02X\n",
1647 offset, mlv, tmdsaddr, mask, data);
1648
1649 reg = get_tmds_index_reg(bios->dev, mlv);
1650 if (!reg)
9170a824 1651 return -EINVAL;
6ee73861
BS		 1652
1653 bios_wr32(bios, reg,
1654 tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
1655 value = (bios_rd32(bios, reg + 4) & mask) | data;
1656 bios_wr32(bios, reg + 4, value);
1657 bios_wr32(bios, reg, tmdsaddr);
1658
37383650 1659 return 5;
6ee73861
BS		 1660}
1661
37383650 1662static int
6ee73861
BS		 1663init_zm_tmds_group(struct nvbios *bios, uint16_t offset,
1664 struct init_exec *iexec)
1665{
1666 /*
1667 * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name)
1668 *
1669 * offset (8 bit): opcode
1670 * offset + 1 (8 bit): magic lookup value
1671 * offset + 2 (8 bit): count
1672 * offset + 3 (8 bit): addr 1
1673 * offset + 4 (8 bit): data 1
1674 * ...
1675 *
1676 * For each of "count" TMDS address and data pairs write "data n" to
1677 * "addr n". "magic lookup value" determines which TMDS base address
1678 * register is used -- see get_tmds_index_reg()
1679 */
1680
1681 uint8_t mlv = bios->data[offset + 1];
1682 uint8_t count = bios->data[offset + 2];
37383650 1683 int len = 3 + count * 2;
6ee73861
BS		 1684 uint32_t reg;
1685 int i;
1686
1687 if (!iexec->execute)
37383650 1688 return len;
6ee73861
BS		 1689
1690 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
1691 offset, mlv, count);
1692
1693 reg = get_tmds_index_reg(bios->dev, mlv);
1694 if (!reg)
9170a824 1695 return -EINVAL;
6ee73861
BS		 1696
1697 for (i = 0; i < count; i++) {
1698 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2];
1699 uint8_t tmdsdata = bios->data[offset + 4 + i * 2];
1700
1701 bios_wr32(bios, reg + 4, tmdsdata);
1702 bios_wr32(bios, reg, tmdsaddr);
1703 }
1704
37383650 1705 return len;
6ee73861
BS		 1706}
1707
37383650 1708static int
6ee73861
BS		 1709init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset,
1710 struct init_exec *iexec)
1711{
1712 /*
1713 * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q')
1714 *
1715 * offset (8 bit): opcode
1716 * offset + 1 (8 bit): CRTC index1
1717 * offset + 2 (8 bit): CRTC index2
1718 * offset + 3 (8 bit): baseaddr
1719 * offset + 4 (8 bit): count
1720 * offset + 5 (8 bit): data 1
1721 * ...
1722 *
1723 * For each of "count" address and data pairs, write "baseaddr + n" to
1724 * "CRTC index1" and "data n" to "CRTC index2"
1725 * Once complete, restore initial value read from "CRTC index1"
1726 */
1727 uint8_t crtcindex1 = bios->data[offset + 1];
1728 uint8_t crtcindex2 = bios->data[offset + 2];
1729 uint8_t baseaddr = bios->data[offset + 3];
1730 uint8_t count = bios->data[offset + 4];
37383650 1731 int len = 5 + count;
6ee73861
BS		 1732 uint8_t oldaddr, data;
1733 int i;
1734
1735 if (!iexec->execute)
37383650 1736 return len;
6ee73861
BS		 1737
1738 BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, "
1739 "BaseAddr: 0x%02X, Count: 0x%02X\n",
1740 offset, crtcindex1, crtcindex2, baseaddr, count);
1741
1742 oldaddr = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex1);
1743
1744 for (i = 0; i < count; i++) {
1745 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1,
1746 baseaddr + i);
1747 data = bios->data[offset + 5 + i];
1748 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex2, data);
1749 }
1750
1751 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr);
1752
37383650 1753 return len;
6ee73861
BS		 1754}
1755
37383650 1756static int
6ee73861
BS		 1757init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1758{
1759 /*
1760 * INIT_CR opcode: 0x52 ('R')
1761 *
1762 * offset (8 bit): opcode
1763 * offset + 1 (8 bit): CRTC index
1764 * offset + 2 (8 bit): mask
1765 * offset + 3 (8 bit): data
1766 *
1767 * Assign the value of at "CRTC index" ANDed with mask and ORed with
1768 * data back to "CRTC index"
1769 */
1770
1771 uint8_t crtcindex = bios->data[offset + 1];
1772 uint8_t mask = bios->data[offset + 2];
1773 uint8_t data = bios->data[offset + 3];
1774 uint8_t value;
1775
1776 if (!iexec->execute)
37383650 1777 return 4;
6ee73861
BS		 1778
1779 BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1780 offset, crtcindex, mask, data);
1781
1782 value = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex) & mask;
1783 value |= data;
1784 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value);
1785
37383650 1786 return 4;
6ee73861
BS		 1787}
1788
37383650 1789static int
6ee73861
BS		 1790init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1791{
1792 /*
1793 * INIT_ZM_CR opcode: 0x53 ('S')
1794 *
1795 * offset (8 bit): opcode
1796 * offset + 1 (8 bit): CRTC index
1797 * offset + 2 (8 bit): value
1798 *
1799 * Assign "value" to CRTC register with index "CRTC index".
1800 */
1801
1802 uint8_t crtcindex = ROM32(bios->data[offset + 1]);
1803 uint8_t data = bios->data[offset + 2];
1804
1805 if (!iexec->execute)
37383650 1806 return 3;
6ee73861
BS		 1807
1808 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data);
1809
37383650 1810 return 3;
6ee73861
BS		 1811}
1812
37383650 1813static int
6ee73861
BS		 1814init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1815{
1816 /*
1817 * INIT_ZM_CR_GROUP opcode: 0x54 ('T')
1818 *
1819 * offset (8 bit): opcode
1820 * offset + 1 (8 bit): count
1821 * offset + 2 (8 bit): CRTC index 1
1822 * offset + 3 (8 bit): value 1
1823 * ...
1824 *
1825 * For "count", assign "value n" to CRTC register with index
1826 * "CRTC index n".
1827 */
1828
1829 uint8_t count = bios->data[offset + 1];
37383650 1830 int len = 2 + count * 2;
6ee73861
BS		 1831 int i;
1832
1833 if (!iexec->execute)
37383650 1834 return len;
6ee73861
BS		 1835
1836 for (i = 0; i < count; i++)
1837 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec);
1838
37383650 1839 return len;
6ee73861
BS		 1840}
1841
37383650 1842static int
6ee73861
BS		 1843init_condition_time(struct nvbios *bios, uint16_t offset,
1844 struct init_exec *iexec)
1845{
1846 /*
1847 * INIT_CONDITION_TIME opcode: 0x56 ('V')
1848 *
1849 * offset (8 bit): opcode
1850 * offset + 1 (8 bit): condition number
1851 * offset + 2 (8 bit): retries / 50
1852 *
1853 * Check condition "condition number" in the condition table.
1854 * Bios code then sleeps for 2ms if the condition is not met, and
1855 * repeats up to "retries" times, but on one C51 this has proved
1856 * insufficient. In mmiotraces the driver sleeps for 20ms, so we do
1857 * this, and bail after "retries" times, or 2s, whichever is less.
1858 * If still not met after retries, clear execution flag for this table.
1859 */
1860
1861 uint8_t cond = bios->data[offset + 1];
1862 uint16_t retries = bios->data[offset + 2] * 50;
1863 unsigned cnt;
1864
1865 if (!iexec->execute)
37383650 1866 return 3;
6ee73861
BS		 1867
1868 if (retries > 100)
1869 retries = 100;
1870
1871 BIOSLOG(bios, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n",
1872 offset, cond, retries);
1873
1874 if (!bios->execute) /* avoid 2s delays when "faking" execution */
1875 retries = 1;
1876
1877 for (cnt = 0; cnt < retries; cnt++) {
1878 if (bios_condition_met(bios, offset, cond)) {
1879 BIOSLOG(bios, "0x%04X: Condition met, continuing\n",
1880 offset);
1881 break;
1882 } else {
1883 BIOSLOG(bios, "0x%04X: "
1884 "Condition not met, sleeping for 20ms\n",
1885 offset);
1886 msleep(20);
1887 }
1888 }
1889
1890 if (!bios_condition_met(bios, offset, cond)) {
1891 NV_WARN(bios->dev,
1892 "0x%04X: Condition still not met after %dms, "
1893 "skipping following opcodes\n", offset, 20 * retries);
1894 iexec->execute = false;
1895 }
1896
37383650 1897 return 3;
6ee73861
BS		 1898}
1899
37383650 1900static int
6ee73861
BS		 1901init_zm_reg_sequence(struct nvbios *bios, uint16_t offset,
1902 struct init_exec *iexec)
1903{
1904 /*
1905 * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X')
1906 *
1907 * offset (8 bit): opcode
1908 * offset + 1 (32 bit): base register
1909 * offset + 5 (8 bit): count
1910 * offset + 6 (32 bit): value 1
1911 * ...
1912 *
1913 * Starting at offset + 6 there are "count" 32 bit values.
1914 * For "count" iterations set "base register" + 4 * current_iteration
1915 * to "value current_iteration"
1916 */
1917
1918 uint32_t basereg = ROM32(bios->data[offset + 1]);
1919 uint32_t count = bios->data[offset + 5];
37383650 1920 int len = 6 + count * 4;
6ee73861
BS		 1921 int i;
1922
1923 if (!iexec->execute)
37383650 1924 return len;
6ee73861
BS		 1925
1926 BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
1927 offset, basereg, count);
1928
1929 for (i = 0; i < count; i++) {
1930 uint32_t reg = basereg + i * 4;
1931 uint32_t data = ROM32(bios->data[offset + 6 + i * 4]);
1932
1933 bios_wr32(bios, reg, data);
1934 }
1935
37383650 1936 return len;
6ee73861
BS		 1937}
1938
37383650 1939static int
6ee73861
BS		 1940init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1941{
1942 /*
1943 * INIT_SUB_DIRECT opcode: 0x5B ('[')
1944 *
1945 * offset (8 bit): opcode
1946 * offset + 1 (16 bit): subroutine offset (in bios)
1947 *
1948 * Calls a subroutine that will execute commands until INIT_DONE
1949 * is found.
1950 */
1951
1952 uint16_t sub_offset = ROM16(bios->data[offset + 1]);
1953
1954 if (!iexec->execute)
37383650 1955 return 3;
6ee73861
BS		 1956
1957 BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n",
1958 offset, sub_offset);
1959
1960 parse_init_table(bios, sub_offset, iexec);
1961
1962 BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset);
1963
37383650 1964 return 3;
6ee73861
BS		 1965}
1966
37383650 1967static int
6ee73861
BS		 1968init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1969{
1970 /*
1971 * INIT_COPY_NV_REG opcode: 0x5F ('_')
1972 *
1973 * offset (8 bit): opcode
1974 * offset + 1 (32 bit): src reg
1975 * offset + 5 (8 bit): shift
1976 * offset + 6 (32 bit): src mask
1977 * offset + 10 (32 bit): xor
1978 * offset + 14 (32 bit): dst reg
1979 * offset + 18 (32 bit): dst mask
1980 *
1981 * Shift REGVAL("src reg") right by (signed) "shift", AND result with
1982 * "src mask", then XOR with "xor". Write this OR'd with
1983 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg"
1984 */
1985
1986 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1]));
1987 uint8_t shift = bios->data[offset + 5];
1988 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6]));
1989 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10]));
1990 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14]));
1991 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18]));
1992 uint32_t srcvalue, dstvalue;
1993
1994 if (!iexec->execute)
37383650 1995 return 22;
6ee73861
BS		 1996
1997 BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, "
1998 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
1999 offset, srcreg, shift, srcmask, xor, dstreg, dstmask);
2000
2001 srcvalue = bios_rd32(bios, srcreg);
2002
2003 if (shift < 0x80)
2004 srcvalue >>= shift;
2005 else
2006 srcvalue <<= (0x100 - shift);
2007
2008 srcvalue = (srcvalue & srcmask) ^ xor;
2009
2010 dstvalue = bios_rd32(bios, dstreg) & dstmask;
2011
2012 bios_wr32(bios, dstreg, dstvalue | srcvalue);
2013
37383650 2014 return 22;
6ee73861
BS		 2015}
2016
37383650 2017static int
6ee73861
BS		 2018init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2019{
2020 /*
2021 * INIT_ZM_INDEX_IO opcode: 0x62 ('b')
2022 *
2023 * offset (8 bit): opcode
2024 * offset + 1 (16 bit): CRTC port
2025 * offset + 3 (8 bit): CRTC index
2026 * offset + 4 (8 bit): data
2027 *
2028 * Write "data" to index "CRTC index" of "CRTC port"
2029 */
2030 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2031 uint8_t crtcindex = bios->data[offset + 3];
2032 uint8_t data = bios->data[offset + 4];
2033
2034 if (!iexec->execute)
37383650 2035 return 5;
6ee73861
BS		 2036
2037 bios_idxprt_wr(bios, crtcport, crtcindex, data);
2038
37383650 2039 return 5;
6ee73861
BS		 2040}
2041
37383650 2042static int
6ee73861
BS		 2043init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2044{
2045 /*
2046 * INIT_COMPUTE_MEM opcode: 0x63 ('c')
2047 *
2048 * offset (8 bit): opcode
2049 *
2050 * This opcode is meant to set NV_PFB_CFG0 (0x100200) appropriately so
2051 * that the hardware can correctly calculate how much VRAM it has
2052 * (and subsequently report that value in NV_PFB_CSTATUS (0x10020C))
2053 *
2054 * The implementation of this opcode in general consists of two parts:
2055 * 1) determination of the memory bus width
2056 * 2) determination of how many of the card's RAM pads have ICs attached
2057 *
2058 * 1) is done by a cunning combination of writes to offsets 0x1c and
2059 * 0x3c in the framebuffer, and seeing whether the written values are
2060 * read back correctly. This then affects bits 4-7 of NV_PFB_CFG0
2061 *
2062 * 2) is done by a cunning combination of writes to an offset slightly
2063 * less than the maximum memory reported by NV_PFB_CSTATUS, then seeing
2064 * if the test pattern can be read back. This then affects bits 12-15 of
2065 * NV_PFB_CFG0
2066 *
2067 * In this context a "cunning combination" may include multiple reads
2068 * and writes to varying locations, often alternating the test pattern
2069 * and 0, doubtless to make sure buffers are filled, residual charges
2070 * on tracks are removed etc.
2071 *
2072 * Unfortunately, the "cunning combination"s mentioned above, and the
2073 * changes to the bits in NV_PFB_CFG0 differ with nearly every bios
2074 * trace I have.
2075 *
2076 * Therefore, we cheat and assume the value of NV_PFB_CFG0 with which
2077 * we started was correct, and use that instead
2078 */
2079
2080 /* no iexec->execute check by design */
2081
2082 /*
2083 * This appears to be a NOP on G8x chipsets, both io logs of the VBIOS
2084 * and kmmio traces of the binary driver POSTing the card show nothing
2085 * being done for this opcode. why is it still listed in the table?!
2086 */
2087
2088 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2089
e235c1f3 2090 if (dev_priv->card_type >= NV_40)
37383650 2091 return 1;
6ee73861
BS		 2092
2093 /*
2094 * On every card I've seen, this step gets done for us earlier in
2095 * the init scripts
2096 uint8_t crdata = bios_idxprt_rd(dev, NV_VIO_SRX, 0x01);
2097 bios_idxprt_wr(dev, NV_VIO_SRX, 0x01, crdata | 0x20);
2098 */
2099
2100 /*
2101 * This also has probably been done in the scripts, but an mmio trace of
2102 * s3 resume shows nvidia doing it anyway (unlike the NV_VIO_SRX write)
2103 */
2104 bios_wr32(bios, NV_PFB_REFCTRL, NV_PFB_REFCTRL_VALID_1);
2105
2106 /* write back the saved configuration value */
2107 bios_wr32(bios, NV_PFB_CFG0, bios->state.saved_nv_pfb_cfg0);
2108
37383650 2109 return 1;
6ee73861
BS		 2110}
2111
37383650 2112static int
6ee73861
BS		 2113init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2114{
2115 /*
2116 * INIT_RESET opcode: 0x65 ('e')
2117 *
2118 * offset (8 bit): opcode
2119 * offset + 1 (32 bit): register
2120 * offset + 5 (32 bit): value1
2121 * offset + 9 (32 bit): value2
2122 *
2123 * Assign "value1" to "register", then assign "value2" to "register"
2124 */
2125
2126 uint32_t reg = ROM32(bios->data[offset + 1]);
2127 uint32_t value1 = ROM32(bios->data[offset + 5]);
2128 uint32_t value2 = ROM32(bios->data[offset + 9]);
2129 uint32_t pci_nv_19, pci_nv_20;
2130
2131 /* no iexec->execute check by design */
2132
2133 pci_nv_19 = bios_rd32(bios, NV_PBUS_PCI_NV_19);
2134 bios_wr32(bios, NV_PBUS_PCI_NV_19, 0);
2135 bios_wr32(bios, reg, value1);
2136
2137 udelay(10);
2138
2139 bios_wr32(bios, reg, value2);
2140 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19);
2141
2142 pci_nv_20 = bios_rd32(bios, NV_PBUS_PCI_NV_20);
2143 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */
2144 bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20);
2145
37383650 2146 return 13;
6ee73861
BS		 2147}
2148
37383650 2149static int
6ee73861
BS		 2150init_configure_mem(struct nvbios *bios, uint16_t offset,
2151 struct init_exec *iexec)
2152{
2153 /*
2154 * INIT_CONFIGURE_MEM opcode: 0x66 ('f')
2155 *
2156 * offset (8 bit): opcode
2157 *
2158 * Equivalent to INIT_DONE on bios version 3 or greater.
2159 * For early bios versions, sets up the memory registers, using values
2160 * taken from the memory init table
2161 */
2162
2163 /* no iexec->execute check by design */
2164
2165 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2166 uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6;
2167 uint32_t reg, data;
2168
2169 if (bios->major_version > 2)
9170a824 2170 return -ENODEV;
6ee73861
BS		 2171
2172 bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd(
2173 bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20);
2174
2175 if (bios->data[meminitoffs] & 1)
2176 seqtbloffs = bios->legacy.ddr_seq_tbl_ptr;
2177
2178 for (reg = ROM32(bios->data[seqtbloffs]);
2179 reg != 0xffffffff;
2180 reg = ROM32(bios->data[seqtbloffs += 4])) {
2181
2182 switch (reg) {
2183 case NV_PFB_PRE:
2184 data = NV_PFB_PRE_CMD_PRECHARGE;
2185 break;
2186 case NV_PFB_PAD:
2187 data = NV_PFB_PAD_CKE_NORMAL;
2188 break;
2189 case NV_PFB_REF:
2190 data = NV_PFB_REF_CMD_REFRESH;
2191 break;
2192 default:
2193 data = ROM32(bios->data[meminitdata]);
2194 meminitdata += 4;
2195 if (data == 0xffffffff)
2196 continue;
2197 }
2198
2199 bios_wr32(bios, reg, data);
2200 }
2201
37383650 2202 return 1;
6ee73861
BS		 2203}
2204
37383650 2205static int
6ee73861
BS		 2206init_configure_clk(struct nvbios *bios, uint16_t offset,
2207 struct init_exec *iexec)
2208{
2209 /*
2210 * INIT_CONFIGURE_CLK opcode: 0x67 ('g')
2211 *
2212 * offset (8 bit): opcode
2213 *
2214 * Equivalent to INIT_DONE on bios version 3 or greater.
2215 * For early bios versions, sets up the NVClk and MClk PLLs, using
2216 * values taken from the memory init table
2217 */
2218
2219 /* no iexec->execute check by design */
2220
2221 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2222 int clock;
2223
2224 if (bios->major_version > 2)
9170a824 2225 return -ENODEV;
6ee73861
BS		 2226
2227 clock = ROM16(bios->data[meminitoffs + 4]) * 10;
2228 setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock);
2229
2230 clock = ROM16(bios->data[meminitoffs + 2]) * 10;
2231 if (bios->data[meminitoffs] & 1) /* DDR */
2232 clock *= 2;
2233 setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock);
2234
37383650 2235 return 1;
6ee73861
BS		 2236}
2237
37383650 2238static int
6ee73861
BS		 2239init_configure_preinit(struct nvbios *bios, uint16_t offset,
2240 struct init_exec *iexec)
2241{
2242 /*
2243 * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h')
2244 *
2245 * offset (8 bit): opcode
2246 *
2247 * Equivalent to INIT_DONE on bios version 3 or greater.
2248 * For early bios versions, does early init, loading ram and crystal
2249 * configuration from straps into CR3C
2250 */
2251
2252 /* no iexec->execute check by design */
2253
2254 uint32_t straps = bios_rd32(bios, NV_PEXTDEV_BOOT_0);
2255 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & (1 << 6));
2256
2257 if (bios->major_version > 2)
9170a824 2258 return -ENODEV;
6ee73861
BS		 2259
2260 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR,
2261 NV_CIO_CRE_SCRATCH4__INDEX, cr3c);
2262
37383650 2263 return 1;
6ee73861
BS		 2264}
2265
37383650 2266static int
6ee73861
BS		 2267init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2268{
2269 /*
2270 * INIT_IO opcode: 0x69 ('i')
2271 *
2272 * offset (8 bit): opcode
2273 * offset + 1 (16 bit): CRTC port
2274 * offset + 3 (8 bit): mask
2275 * offset + 4 (8 bit): data
2276 *
2277 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port"
2278 */
2279
2280 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2281 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2282 uint8_t mask = bios->data[offset + 3];
2283 uint8_t data = bios->data[offset + 4];
2284
2285 if (!iexec->execute)
37383650 2286 return 5;
6ee73861
BS		 2287
2288 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n",
2289 offset, crtcport, mask, data);
2290
2291 /*
2292 * I have no idea what this does, but NVIDIA do this magic sequence
2293 * in the places where this INIT_IO happens..
2294 */
2295 if (dev_priv->card_type >= NV_50 && crtcport == 0x3c3 && data == 1) {
2296 int i;
2297
2298 bios_wr32(bios, 0x614100, (bios_rd32(
2299 bios, 0x614100) & 0x0fffffff) | 0x00800000);
2300
2301 bios_wr32(bios, 0x00e18c, bios_rd32(
2302 bios, 0x00e18c) | 0x00020000);
2303
2304 bios_wr32(bios, 0x614900, (bios_rd32(
2305 bios, 0x614900) & 0x0fffffff) | 0x00800000);
2306
2307 bios_wr32(bios, 0x000200, bios_rd32(
2308 bios, 0x000200) & ~0x40000000);
2309
2310 mdelay(10);
2311
2312 bios_wr32(bios, 0x00e18c, bios_rd32(
2313 bios, 0x00e18c) & ~0x00020000);
2314
2315 bios_wr32(bios, 0x000200, bios_rd32(
2316 bios, 0x000200) | 0x40000000);
2317
2318 bios_wr32(bios, 0x614100, 0x00800018);
2319 bios_wr32(bios, 0x614900, 0x00800018);
2320
2321 mdelay(10);
2322
2323 bios_wr32(bios, 0x614100, 0x10000018);
2324 bios_wr32(bios, 0x614900, 0x10000018);
2325
2326 for (i = 0; i < 3; i++)
2327 bios_wr32(bios, 0x614280 + (i*0x800), bios_rd32(
2328 bios, 0x614280 + (i*0x800)) & 0xf0f0f0f0);
2329
2330 for (i = 0; i < 2; i++)
2331 bios_wr32(bios, 0x614300 + (i*0x800), bios_rd32(
2332 bios, 0x614300 + (i*0x800)) & 0xfffff0f0);
2333
2334 for (i = 0; i < 3; i++)
2335 bios_wr32(bios, 0x614380 + (i*0x800), bios_rd32(
2336 bios, 0x614380 + (i*0x800)) & 0xfffff0f0);
2337
2338 for (i = 0; i < 2; i++)
2339 bios_wr32(bios, 0x614200 + (i*0x800), bios_rd32(
2340 bios, 0x614200 + (i*0x800)) & 0xfffffff0);
2341
2342 for (i = 0; i < 2; i++)
2343 bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32(
2344 bios, 0x614108 + (i*0x800)) & 0x0fffffff);
37383650 2345 return 5;
6ee73861
BS		 2346 }
2347
2348 bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) |
2349 data);
37383650 2350 return 5;
6ee73861
BS		 2351}
2352
37383650 2353static int
6ee73861
BS		 2354init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2355{
2356 /*
2357 * INIT_SUB opcode: 0x6B ('k')
2358 *
2359 * offset (8 bit): opcode
2360 * offset + 1 (8 bit): script number
2361 *
2362 * Execute script number "script number", as a subroutine
2363 */
2364
2365 uint8_t sub = bios->data[offset + 1];
2366
2367 if (!iexec->execute)
37383650 2368 return 2;
6ee73861
BS		 2369
2370 BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub);
2371
2372 parse_init_table(bios,
2373 ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]),
2374 iexec);
2375
2376 BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub);
2377
37383650 2378 return 2;
6ee73861
BS		 2379}
2380
37383650 2381static int
6ee73861
BS		 2382init_ram_condition(struct nvbios *bios, uint16_t offset,
2383 struct init_exec *iexec)
2384{
2385 /*
2386 * INIT_RAM_CONDITION opcode: 0x6D ('m')
2387 *
2388 * offset (8 bit): opcode
2389 * offset + 1 (8 bit): mask
2390 * offset + 2 (8 bit): cmpval
2391 *
2392 * Test if (NV_PFB_BOOT_0 & "mask") equals "cmpval".
2393 * If condition not met skip subsequent opcodes until condition is
2394 * inverted (INIT_NOT), or we hit INIT_RESUME
2395 */
2396
2397 uint8_t mask = bios->data[offset + 1];
2398 uint8_t cmpval = bios->data[offset + 2];
2399 uint8_t data;
2400
2401 if (!iexec->execute)
37383650 2402 return 3;
6ee73861
BS		 2403
2404 data = bios_rd32(bios, NV_PFB_BOOT_0) & mask;
2405
2406 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
2407 offset, data, cmpval);
2408
2409 if (data == cmpval)
2410 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2411 else {
2412 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2413 iexec->execute = false;
2414 }
2415
37383650 2416 return 3;
6ee73861
BS		 2417}
2418
37383650 2419static int
6ee73861
BS		 2420init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2421{
2422 /*
2423 * INIT_NV_REG opcode: 0x6E ('n')
2424 *
2425 * offset (8 bit): opcode
2426 * offset + 1 (32 bit): register
2427 * offset + 5 (32 bit): mask
2428 * offset + 9 (32 bit): data
2429 *
2430 * Assign ((REGVAL("register") & "mask") | "data") to "register"
2431 */
2432
2433 uint32_t reg = ROM32(bios->data[offset + 1]);
2434 uint32_t mask = ROM32(bios->data[offset + 5]);
2435 uint32_t data = ROM32(bios->data[offset + 9]);
2436
2437 if (!iexec->execute)
37383650 2438 return 13;
6ee73861
BS		 2439
2440 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
2441 offset, reg, mask, data);
2442
2443 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data);
2444
37383650 2445 return 13;
6ee73861
BS		 2446}
2447
37383650 2448static int
6ee73861
BS		 2449init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2450{
2451 /*
2452 * INIT_MACRO opcode: 0x6F ('o')
2453 *
2454 * offset (8 bit): opcode
2455 * offset + 1 (8 bit): macro number
2456 *
2457 * Look up macro index "macro number" in the macro index table.
2458 * The macro index table entry has 1 byte for the index in the macro
2459 * table, and 1 byte for the number of times to repeat the macro.
2460 * The macro table entry has 4 bytes for the register address and
2461 * 4 bytes for the value to write to that register
2462 */
2463
2464 uint8_t macro_index_tbl_idx = bios->data[offset + 1];
2465 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE);
2466 uint8_t macro_tbl_idx = bios->data[tmp];
2467 uint8_t count = bios->data[tmp + 1];
2468 uint32_t reg, data;
2469 int i;
2470
2471 if (!iexec->execute)
37383650 2472 return 2;
6ee73861
BS		 2473
2474 BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, "
2475 "Count: 0x%02X\n",
2476 offset, macro_index_tbl_idx, macro_tbl_idx, count);
2477
2478 for (i = 0; i < count; i++) {
2479 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE;
2480
2481 reg = ROM32(bios->data[macroentryptr]);
2482 data = ROM32(bios->data[macroentryptr + 4]);
2483
2484 bios_wr32(bios, reg, data);
2485 }
2486
37383650 2487 return 2;
6ee73861
BS		 2488}
2489
37383650 2490static int
6ee73861
BS		 2491init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2492{
2493 /*
2494 * INIT_DONE opcode: 0x71 ('q')
2495 *
2496 * offset (8 bit): opcode
2497 *
2498 * End the current script
2499 */
2500
2501 /* mild retval abuse to stop parsing this table */
37383650 2502 return 0;
6ee73861
BS		 2503}
2504
37383650 2505static int
6ee73861
BS		 2506init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2507{
2508 /*
2509 * INIT_RESUME opcode: 0x72 ('r')
2510 *
2511 * offset (8 bit): opcode
2512 *
2513 * End the current execute / no-execute condition
2514 */
2515
2516 if (iexec->execute)
37383650 2517 return 1;
6ee73861
BS		 2518
2519 iexec->execute = true;
2520 BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset);
2521
37383650 2522 return 1;
6ee73861
BS		 2523}
2524
37383650 2525static int
6ee73861
BS		 2526init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2527{
2528 /*
2529 * INIT_TIME opcode: 0x74 ('t')
2530 *
2531 * offset (8 bit): opcode
2532 * offset + 1 (16 bit): time
2533 *
2534 * Sleep for "time" microseconds.
2535 */
2536
2537 unsigned time = ROM16(bios->data[offset + 1]);
2538
2539 if (!iexec->execute)
37383650 2540 return 3;
6ee73861
BS		 2541
2542 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n",
2543 offset, time);
2544
2545 if (time < 1000)
2546 udelay(time);
2547 else
2548 msleep((time + 900) / 1000);
2549
37383650 2550 return 3;
6ee73861
BS		 2551}
2552
37383650 2553static int
6ee73861
BS		 2554init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2555{
2556 /*
2557 * INIT_CONDITION opcode: 0x75 ('u')
2558 *
2559 * offset (8 bit): opcode
2560 * offset + 1 (8 bit): condition number
2561 *
2562 * Check condition "condition number" in the condition table.
2563 * If condition not met skip subsequent opcodes until condition is
2564 * inverted (INIT_NOT), or we hit INIT_RESUME
2565 */
2566
2567 uint8_t cond = bios->data[offset + 1];
2568
2569 if (!iexec->execute)
37383650 2570 return 2;
6ee73861
BS		 2571
2572 BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond);
2573
2574 if (bios_condition_met(bios, offset, cond))
2575 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2576 else {
2577 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2578 iexec->execute = false;
2579 }
2580
37383650 2581 return 2;
6ee73861
BS		 2582}
2583
37383650 2584static int
6ee73861
BS		 2585init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2586{
2587 /*
2588 * INIT_IO_CONDITION opcode: 0x76
2589 *
2590 * offset (8 bit): opcode
2591 * offset + 1 (8 bit): condition number
2592 *
2593 * Check condition "condition number" in the io condition table.
2594 * If condition not met skip subsequent opcodes until condition is
2595 * inverted (INIT_NOT), or we hit INIT_RESUME
2596 */
2597
2598 uint8_t cond = bios->data[offset + 1];
2599
2600 if (!iexec->execute)
37383650 2601 return 2;
6ee73861
BS		 2602
2603 BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond);
2604
2605 if (io_condition_met(bios, offset, cond))
2606 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2607 else {
2608 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2609 iexec->execute = false;
2610 }
2611
37383650 2612 return 2;
6ee73861
BS		 2613}
2614
37383650 2615static int
6ee73861
BS		 2616init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2617{
2618 /*
2619 * INIT_INDEX_IO opcode: 0x78 ('x')
2620 *
2621 * offset (8 bit): opcode
2622 * offset + 1 (16 bit): CRTC port
2623 * offset + 3 (8 bit): CRTC index
2624 * offset + 4 (8 bit): mask
2625 * offset + 5 (8 bit): data
2626 *
2627 * Read value at index "CRTC index" on "CRTC port", AND with "mask",
2628 * OR with "data", write-back
2629 */
2630
2631 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2632 uint8_t crtcindex = bios->data[offset + 3];
2633 uint8_t mask = bios->data[offset + 4];
2634 uint8_t data = bios->data[offset + 5];
2635 uint8_t value;
2636
2637 if (!iexec->execute)
37383650 2638 return 6;
6ee73861
BS		 2639
2640 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
2641 "Data: 0x%02X\n",
2642 offset, crtcport, crtcindex, mask, data);
2643
2644 value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data;
2645 bios_idxprt_wr(bios, crtcport, crtcindex, value);
2646
37383650 2647 return 6;
6ee73861
BS		 2648}
2649
37383650 2650static int
6ee73861
BS		 2651init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2652{
2653 /*
2654 * INIT_PLL opcode: 0x79 ('y')
2655 *
2656 * offset (8 bit): opcode
2657 * offset + 1 (32 bit): register
2658 * offset + 5 (16 bit): freq
2659 *
2660 * Set PLL register "register" to coefficients for frequency (10kHz)
2661 * "freq"
2662 */
2663
2664 uint32_t reg = ROM32(bios->data[offset + 1]);
2665 uint16_t freq = ROM16(bios->data[offset + 5]);
2666
2667 if (!iexec->execute)
37383650 2668 return 7;
6ee73861
BS		 2669
2670 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq);
2671
2672 setPLL(bios, reg, freq * 10);
2673
37383650 2674 return 7;
6ee73861
BS		 2675}
2676
37383650 2677static int
6ee73861
BS		 2678init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2679{
2680 /*
2681 * INIT_ZM_REG opcode: 0x7A ('z')
2682 *
2683 * offset (8 bit): opcode
2684 * offset + 1 (32 bit): register
2685 * offset + 5 (32 bit): value
2686 *
2687 * Assign "value" to "register"
2688 */
2689
2690 uint32_t reg = ROM32(bios->data[offset + 1]);
2691 uint32_t value = ROM32(bios->data[offset + 5]);
2692
2693 if (!iexec->execute)
37383650 2694 return 9;
6ee73861
BS		 2695
2696 if (reg == 0x000200)
2697 value |= 1;
2698
2699 bios_wr32(bios, reg, value);
2700
37383650 2701 return 9;
6ee73861
BS		 2702}
2703
37383650 2704static int
6ee73861
BS		 2705init_ram_restrict_pll(struct nvbios *bios, uint16_t offset,
2706 struct init_exec *iexec)
2707{
2708 /*
2709 * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('')
2710 *
2711 * offset (8 bit): opcode
2712 * offset + 1 (8 bit): PLL type
2713 * offset + 2 (32 bit): frequency 0
2714 *
2715 * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
2716 * ram_restrict_table_ptr. The value read from there is used to select
2717 * a frequency from the table starting at 'frequency 0' to be
2718 * programmed into the PLL corresponding to 'type'.
2719 *
2720 * The PLL limits table on cards using this opcode has a mapping of
2721 * 'type' to the relevant registers.
2722 */
2723
2724 struct drm_device *dev = bios->dev;
2725 uint32_t strap = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2;
2726 uint8_t index = bios->data[bios->ram_restrict_tbl_ptr + strap];
2727 uint8_t type = bios->data[offset + 1];
2728 uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]);
2729 uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry;
37383650 2730 int len = 2 + bios->ram_restrict_group_count * 4;
6ee73861
BS		 2731 int i;
2732
2733 if (!iexec->execute)
37383650 2734 return len;
6ee73861
BS		 2735
2736 if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) {
2737 NV_ERROR(dev, "PLL limits table not version 3.x\n");
37383650 2738 return len; /* deliberate, allow default clocks to remain */
6ee73861
BS		 2739 }
2740
2741 entry = pll_limits + pll_limits[1];
2742 for (i = 0; i < pll_limits[3]; i++, entry += pll_limits[2]) {
2743 if (entry[0] == type) {
2744 uint32_t reg = ROM32(entry[3]);
2745
2746 BIOSLOG(bios, "0x%04X: "
2747 "Type %02x Reg 0x%08x Freq %dKHz\n",
2748 offset, type, reg, freq);
2749
2750 setPLL(bios, reg, freq);
37383650 2751 return len;
6ee73861
BS		 2752 }
2753 }
2754
2755 NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type);
37383650 2756 return len;
6ee73861
BS		 2757}
2758
37383650 2759static int
6ee73861
BS		 2760init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2761{
2762 /*
2763 * INIT_8C opcode: 0x8C ('')
2764 *
2765 * NOP so far....
2766 *
2767 */
2768
37383650 2769 return 1;
6ee73861
BS		 2770}
2771
37383650 2772static int
6ee73861
BS		 2773init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2774{
2775 /*
2776 * INIT_8D opcode: 0x8D ('')
2777 *
2778 * NOP so far....
2779 *
2780 */
2781
37383650 2782 return 1;
6ee73861
BS		 2783}
2784
37383650 2785static int
6ee73861
BS		 2786init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2787{
2788 /*
2789 * INIT_GPIO opcode: 0x8E ('')
2790 *
2791 * offset (8 bit): opcode
2792 *
2793 * Loop over all entries in the DCB GPIO table, and initialise
2794 * each GPIO according to various values listed in each entry
2795 */
2796
2535d71c 2797 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
6ee73861 2798 const uint32_t nv50_gpio_ctl[2] = { 0xe100, 0xe28c };
6ee73861
BS		 2799 int i;
2800
2535d71c
BS		 2801 if (dev_priv->card_type != NV_50) {
2802 NV_ERROR(bios->dev, "INIT_GPIO on unsupported chipset\n");
2803 return -ENODEV;
6ee73861
BS		 2804 }
2805
2535d71c
BS		 2806 if (!iexec->execute)
2807 return 1;
6ee73861 2808
2535d71c
BS		 2809 for (i = 0; i < bios->dcb.gpio.entries; i++) {
2810 struct dcb_gpio_entry *gpio = &bios->dcb.gpio.entry[i];
2811 uint32_t r, s, v;
6ee73861 2812
2535d71c 2813 BIOSLOG(bios, "0x%04X: Entry: 0x%08X\n", offset, gpio->entry);
6ee73861 2814
73db4bed
BS		 2815 BIOSLOG(bios, "0x%04X: set gpio 0x%02x, state %d\n",
2816 offset, gpio->tag, gpio->state_default);
2817 if (bios->execute)
2818 nv50_gpio_set(bios->dev, gpio->tag, gpio->state_default);
6ee73861 2819
45284162
BS		 2820 /* The NVIDIA binary driver doesn't appear to actually do
2821 * any of this, my VBIOS does however.
2822 */
2823 /* Not a clue, needs de-magicing */
2535d71c
BS		 2824 r = nv50_gpio_ctl[gpio->line >> 4];
2825 s = (gpio->line & 0x0f);
6ee73861 2826 v = bios_rd32(bios, r) & ~(0x00010001 << s);
2535d71c 2827 switch ((gpio->entry & 0x06000000) >> 25) {
6ee73861
BS		 2828 case 1:
2829 v |= (0x00000001 << s);
2830 break;
2831 case 2:
2832 v |= (0x00010000 << s);
2833 break;
2834 default:
2835 break;
2836 }
2837 bios_wr32(bios, r, v);
2838 }
2839
37383650 2840 return 1;
6ee73861
BS		 2841}
2842
37383650 2843static int
6ee73861
BS		 2844init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset,
2845 struct init_exec *iexec)
2846{
2847 /*
2848 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('')
2849 *
2850 * offset (8 bit): opcode
2851 * offset + 1 (32 bit): reg
2852 * offset + 5 (8 bit): regincrement
2853 * offset + 6 (8 bit): count
2854 * offset + 7 (32 bit): value 1,1
2855 * ...
2856 *
2857 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
2858 * ram_restrict_table_ptr. The value read from here is 'n', and
2859 * "value 1,n" gets written to "reg". This repeats "count" times and on
2860 * each iteration 'm', "reg" increases by "regincrement" and
2861 * "value m,n" is used. The extent of n is limited by a number read
2862 * from the 'M' BIT table, herein called "blocklen"
2863 */
2864
2865 uint32_t reg = ROM32(bios->data[offset + 1]);
2866 uint8_t regincrement = bios->data[offset + 5];
2867 uint8_t count = bios->data[offset + 6];
2868 uint32_t strap_ramcfg, data;
37383650
MK		 2869 /* previously set by 'M' BIT table */
2870 uint16_t blocklen = bios->ram_restrict_group_count * 4;
2871 int len = 7 + count * blocklen;
6ee73861
BS		 2872 uint8_t index;
2873 int i;
2874
6ee73861
BS		 2875
2876 if (!iexec->execute)
37383650 2877 return len;
6ee73861
BS		 2878
2879 if (!blocklen) {
2880 NV_ERROR(bios->dev,
2881 "0x%04X: Zero block length - has the M table "
2882 "been parsed?\n", offset);
9170a824 2883 return -EINVAL;
6ee73861
BS		 2884 }
2885
2886 strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf;
2887 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg];
2888
2889 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, "
2890 "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n",
2891 offset, reg, regincrement, count, strap_ramcfg, index);
2892
2893 for (i = 0; i < count; i++) {
2894 data = ROM32(bios->data[offset + 7 + index * 4 + blocklen * i]);
2895
2896 bios_wr32(bios, reg, data);
2897
2898 reg += regincrement;
2899 }
2900
37383650 2901 return len;
6ee73861
BS		 2902}
2903
37383650 2904static int
6ee73861
BS		 2905init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2906{
2907 /*
2908 * INIT_COPY_ZM_REG opcode: 0x90 ('')
2909 *
2910 * offset (8 bit): opcode
2911 * offset + 1 (32 bit): src reg
2912 * offset + 5 (32 bit): dst reg
2913 *
2914 * Put contents of "src reg" into "dst reg"
2915 */
2916
2917 uint32_t srcreg = ROM32(bios->data[offset + 1]);
2918 uint32_t dstreg = ROM32(bios->data[offset + 5]);
2919
2920 if (!iexec->execute)
37383650 2921 return 9;
6ee73861
BS		 2922
2923 bios_wr32(bios, dstreg, bios_rd32(bios, srcreg));
2924
37383650 2925 return 9;
6ee73861
BS		 2926}
2927
37383650 2928static int
6ee73861
BS		 2929init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset,
2930 struct init_exec *iexec)
2931{
2932 /*
2933 * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('')
2934 *
2935 * offset (8 bit): opcode
2936 * offset + 1 (32 bit): dst reg
2937 * offset + 5 (8 bit): count
2938 * offset + 6 (32 bit): data 1
2939 * ...
2940 *
2941 * For each of "count" values write "data n" to "dst reg"
2942 */
2943
2944 uint32_t reg = ROM32(bios->data[offset + 1]);
2945 uint8_t count = bios->data[offset + 5];
37383650 2946 int len = 6 + count * 4;
6ee73861
BS		 2947 int i;
2948
2949 if (!iexec->execute)
37383650 2950 return len;
6ee73861
BS		 2951
2952 for (i = 0; i < count; i++) {
2953 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]);
2954 bios_wr32(bios, reg, data);
2955 }
2956
37383650 2957 return len;
6ee73861
BS		 2958}
2959
37383650 2960static int
6ee73861
BS		 2961init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2962{
2963 /*
2964 * INIT_RESERVED opcode: 0x92 ('')
2965 *
2966 * offset (8 bit): opcode
2967 *
2968 * Seemingly does nothing
2969 */
2970
37383650 2971 return 1;
6ee73861
BS		 2972}
2973
37383650 2974static int
6ee73861
BS		 2975init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2976{
2977 /*
2978 * INIT_96 opcode: 0x96 ('')
2979 *
2980 * offset (8 bit): opcode
2981 * offset + 1 (32 bit): sreg
2982 * offset + 5 (8 bit): sshift
2983 * offset + 6 (8 bit): smask
2984 * offset + 7 (8 bit): index
2985 * offset + 8 (32 bit): reg
2986 * offset + 12 (32 bit): mask
2987 * offset + 16 (8 bit): shift
2988 *
2989 */
2990
2991 uint16_t xlatptr = bios->init96_tbl_ptr + (bios->data[offset + 7] * 2);
2992 uint32_t reg = ROM32(bios->data[offset + 8]);
2993 uint32_t mask = ROM32(bios->data[offset + 12]);
2994 uint32_t val;
2995
2996 val = bios_rd32(bios, ROM32(bios->data[offset + 1]));
2997 if (bios->data[offset + 5] < 0x80)
2998 val >>= bios->data[offset + 5];
2999 else
3000 val <<= (0x100 - bios->data[offset + 5]);
3001 val &= bios->data[offset + 6];
3002
3003 val = bios->data[ROM16(bios->data[xlatptr]) + val];
3004 val <<= bios->data[offset + 16];
3005
3006 if (!iexec->execute)
37383650 3007 return 17;
6ee73861
BS		 3008
3009 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val);
37383650 3010 return 17;
6ee73861
BS		 3011}
3012
37383650 3013static int
6ee73861
BS		 3014init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3015{
3016 /*
3017 * INIT_97 opcode: 0x97 ('')
3018 *
3019 * offset (8 bit): opcode
3020 * offset + 1 (32 bit): register
3021 * offset + 5 (32 bit): mask
3022 * offset + 9 (32 bit): value
3023 *
3024 * Adds "value" to "register" preserving the fields specified
3025 * by "mask"
3026 */
3027
3028 uint32_t reg = ROM32(bios->data[offset + 1]);
3029 uint32_t mask = ROM32(bios->data[offset + 5]);
3030 uint32_t add = ROM32(bios->data[offset + 9]);
3031 uint32_t val;
3032
3033 val = bios_rd32(bios, reg);
3034 val = (val & mask) | ((val + add) & ~mask);
3035
3036 if (!iexec->execute)
37383650 3037 return 13;
6ee73861
BS		 3038
3039 bios_wr32(bios, reg, val);
37383650 3040 return 13;
6ee73861
BS		 3041}
3042
37383650 3043static int
6ee73861
BS		 3044init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3045{
3046 /*
3047 * INIT_AUXCH opcode: 0x98 ('')
3048 *
3049 * offset (8 bit): opcode
3050 * offset + 1 (32 bit): address
3051 * offset + 5 (8 bit): count
3052 * offset + 6 (8 bit): mask 0
3053 * offset + 7 (8 bit): data 0
3054 * ...
3055 *
3056 */
3057
3058 struct drm_device *dev = bios->dev;
3059 struct nouveau_i2c_chan *auxch;
3060 uint32_t addr = ROM32(bios->data[offset + 1]);
37383650
MK		 3061 uint8_t count = bios->data[offset + 5];
3062 int len = 6 + count * 2;
6ee73861
BS		 3063 int ret, i;
3064
3065 if (!bios->display.output) {
3066 NV_ERROR(dev, "INIT_AUXCH: no active output\n");
9170a824 3067 return -EINVAL;
6ee73861
BS		 3068 }
3069
3070 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
3071 if (!auxch) {
3072 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n",
3073 bios->display.output->i2c_index);
9170a824 3074 return -ENODEV;
6ee73861
BS		 3075 }
3076
3077 if (!iexec->execute)
37383650 3078 return len;
6ee73861
BS		 3079
3080 offset += 6;
37383650 3081 for (i = 0; i < count; i++, offset += 2) {
6ee73861
BS		 3082 uint8_t data;
3083
3084 ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1);
3085 if (ret) {
3086 NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret);
9170a824 3087 return ret;
6ee73861
BS		 3088 }
3089
3090 data &= bios->data[offset + 0];
3091 data |= bios->data[offset + 1];
3092
3093 ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1);
3094 if (ret) {
3095 NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret);
9170a824 3096 return ret;
6ee73861
BS		 3097 }
3098 }
3099
37383650 3100 return len;
6ee73861
BS		 3101}
3102
37383650 3103static int
6ee73861
BS		 3104init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3105{
3106 /*
3107 * INIT_ZM_AUXCH opcode: 0x99 ('')
3108 *
3109 * offset (8 bit): opcode
3110 * offset + 1 (32 bit): address
3111 * offset + 5 (8 bit): count
3112 * offset + 6 (8 bit): data 0
3113 * ...
3114 *
3115 */
3116
3117 struct drm_device *dev = bios->dev;
3118 struct nouveau_i2c_chan *auxch;
3119 uint32_t addr = ROM32(bios->data[offset + 1]);
37383650
MK		 3120 uint8_t count = bios->data[offset + 5];
3121 int len = 6 + count;
6ee73861
BS		 3122 int ret, i;
3123
3124 if (!bios->display.output) {
3125 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n");
9170a824 3126 return -EINVAL;
6ee73861
BS		 3127 }
3128
3129 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
3130 if (!auxch) {
3131 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n",
3132 bios->display.output->i2c_index);
9170a824 3133 return -ENODEV;
6ee73861
BS		 3134 }
3135
3136 if (!iexec->execute)
37383650 3137 return len;
6ee73861
BS		 3138
3139 offset += 6;
37383650 3140 for (i = 0; i < count; i++, offset++) {
6ee73861
BS		 3141 ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1);
3142 if (ret) {
3143 NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret);
9170a824 3144 return ret;
6ee73861
BS		 3145 }
3146 }
3147
37383650 3148 return len;
6ee73861
BS		 3149}
3150
3151static struct init_tbl_entry itbl_entry[] = {
3152 /* command name , id , length , offset , mult , command handler */
3153 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */
37383650
MK		 3154 { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog },
3155 { "INIT_REPEAT" , 0x33, init_repeat },
3156 { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll },
3157 { "INIT_END_REPEAT" , 0x36, init_end_repeat },
3158 { "INIT_COPY" , 0x37, init_copy },
3159 { "INIT_NOT" , 0x38, init_not },
3160 { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition },
25908b77
BS		 3161 { "INIT_DP_CONDITION" , 0x3A, init_dp_condition },
3162 { "INIT_OP_3B" , 0x3B, init_op_3b },
3163 { "INIT_OP_3C" , 0x3C, init_op_3c },
37383650
MK		 3164 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched },
3165 { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2 },
3166 { "INIT_PLL2" , 0x4B, init_pll2 },
3167 { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte },
3168 { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte },
3169 { "INIT_ZM_I2C" , 0x4E, init_zm_i2c },
3170 { "INIT_TMDS" , 0x4F, init_tmds },
3171 { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group },
3172 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch },
3173 { "INIT_CR" , 0x52, init_cr },
3174 { "INIT_ZM_CR" , 0x53, init_zm_cr },
3175 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group },
3176 { "INIT_CONDITION_TIME" , 0x56, init_condition_time },
3177 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence },
6ee73861 3178 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */
37383650
MK		 3179 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct },
3180 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg },
3181 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io },
3182 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem },
3183 { "INIT_RESET" , 0x65, init_reset },
3184 { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem },
3185 { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk },
3186 { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit },
3187 { "INIT_IO" , 0x69, init_io },
3188 { "INIT_SUB" , 0x6B, init_sub },
3189 { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition },
3190 { "INIT_NV_REG" , 0x6E, init_nv_reg },
3191 { "INIT_MACRO" , 0x6F, init_macro },
3192 { "INIT_DONE" , 0x71, init_done },
3193 { "INIT_RESUME" , 0x72, init_resume },
6ee73861 3194 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */
37383650
MK		 3195 { "INIT_TIME" , 0x74, init_time },
3196 { "INIT_CONDITION" , 0x75, init_condition },
3197 { "INIT_IO_CONDITION" , 0x76, init_io_condition },
3198 { "INIT_INDEX_IO" , 0x78, init_index_io },
3199 { "INIT_PLL" , 0x79, init_pll },
3200 { "INIT_ZM_REG" , 0x7A, init_zm_reg },
3201 { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll },
3202 { "INIT_8C" , 0x8C, init_8c },
3203 { "INIT_8D" , 0x8D, init_8d },
3204 { "INIT_GPIO" , 0x8E, init_gpio },
3205 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group },
3206 { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg },
3207 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched },
3208 { "INIT_RESERVED" , 0x92, init_reserved },
3209 { "INIT_96" , 0x96, init_96 },
3210 { "INIT_97" , 0x97, init_97 },
3211 { "INIT_AUXCH" , 0x98, init_auxch },
3212 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch },
3213 { NULL , 0 , NULL }
6ee73861
BS		 3214};
3215
6ee73861
BS		 3216#define MAX_TABLE_OPS 1000
3217
3218static int
3219parse_init_table(struct nvbios *bios, unsigned int offset,
3220 struct init_exec *iexec)
3221{
3222 /*
3223 * Parses all commands in an init table.
3224 *
3225 * We start out executing all commands found in the init table. Some
3226 * opcodes may change the status of iexec->execute to SKIP, which will
3227 * cause the following opcodes to perform no operation until the value
3228 * is changed back to EXECUTE.
3229 */
3230
92b96187 3231 int count = 0, i, ret;
6ee73861
BS		 3232 uint8_t id;
3233
3234 /*
3235 * Loop until INIT_DONE causes us to break out of the loop
3236 * (or until offset > bios length just in case... )
3237 * (and no more than MAX_TABLE_OPS iterations, just in case... )
3238 */
3239 while ((offset < bios->length) && (count++ < MAX_TABLE_OPS)) {
3240 id = bios->data[offset];
3241
3242 /* Find matching id in itbl_entry */
3243 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++)
3244 ;
3245
92b96187 3246 if (!itbl_entry[i].name) {
6ee73861
BS		 3247 NV_ERROR(bios->dev,
3248 "0x%04X: Init table command not found: "
3249 "0x%02X\n", offset, id);
3250 return -ENOENT;
3251 }
92b96187
BS		 3252
3253 BIOSLOG(bios, "0x%04X: [ (0x%02X) - %s ]\n", offset,
3254 itbl_entry[i].id, itbl_entry[i].name);
3255
3256 /* execute eventual command handler */
3257 ret = (*itbl_entry[i].handler)(bios, offset, iexec);
3258 if (ret < 0) {
3259 NV_ERROR(bios->dev, "0x%04X: Failed parsing init "
3260 "table opcode: %s %d\n", offset,
3261 itbl_entry[i].name, ret);
3262 }
3263
3264 if (ret <= 0)
3265 break;
3266
3267 /*
3268 * Add the offset of the current command including all data
3269 * of that command. The offset will then be pointing on the
3270 * next op code.
3271 */
3272 offset += ret;
6ee73861
BS		 3273 }
3274
3275 if (offset >= bios->length)
3276 NV_WARN(bios->dev,
3277 "Offset 0x%04X greater than known bios image length. "
3278 "Corrupt image?\n", offset);
3279 if (count >= MAX_TABLE_OPS)
3280 NV_WARN(bios->dev,
3281 "More than %d opcodes to a table is unlikely, "
3282 "is the bios image corrupt?\n", MAX_TABLE_OPS);
3283
3284 return 0;
3285}
3286
3287static void
3288parse_init_tables(struct nvbios *bios)
3289{
3290 /* Loops and calls parse_init_table() for each present table. */
3291
3292 int i = 0;
3293 uint16_t table;
3294 struct init_exec iexec = {true, false};
3295
3296 if (bios->old_style_init) {
3297 if (bios->init_script_tbls_ptr)
3298 parse_init_table(bios, bios->init_script_tbls_ptr, &iexec);
3299 if (bios->extra_init_script_tbl_ptr)
3300 parse_init_table(bios, bios->extra_init_script_tbl_ptr, &iexec);
3301
3302 return;
3303 }
3304
3305 while ((table = ROM16(bios->data[bios->init_script_tbls_ptr + i]))) {
3306 NV_INFO(bios->dev,
3307 "Parsing VBIOS init table %d at offset 0x%04X\n",
3308 i / 2, table);
3309 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", table);
3310
3311 parse_init_table(bios, table, &iexec);
3312 i += 2;
3313 }
3314}
3315
3316static uint16_t clkcmptable(struct nvbios *bios, uint16_t clktable, int pxclk)
3317{
3318 int compare_record_len, i = 0;
3319 uint16_t compareclk, scriptptr = 0;
3320
3321 if (bios->major_version < 5) /* pre BIT */
3322 compare_record_len = 3;
3323 else
3324 compare_record_len = 4;
3325
3326 do {
3327 compareclk = ROM16(bios->data[clktable + compare_record_len * i]);
3328 if (pxclk >= compareclk * 10) {
3329 if (bios->major_version < 5) {
3330 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i];
3331 scriptptr = ROM16(bios->data[bios->init_script_tbls_ptr + tmdssub * 2]);
3332 } else
3333 scriptptr = ROM16(bios->data[clktable + 2 + compare_record_len * i]);
3334 break;
3335 }
3336 i++;
3337 } while (compareclk);
3338
3339 return scriptptr;
3340}
3341
3342static void
3343run_digital_op_script(struct drm_device *dev, uint16_t scriptptr,
3344 struct dcb_entry *dcbent, int head, bool dl)
3345{
3346 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3347 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3348 struct init_exec iexec = {true, false};
3349
3350 NV_TRACE(dev, "0x%04X: Parsing digital output script table\n",
3351 scriptptr);
3352 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_44,
3353 head ? NV_CIO_CRE_44_HEADB : NV_CIO_CRE_44_HEADA);
3354 /* note: if dcb entries have been merged, index may be misleading */
3355 NVWriteVgaCrtc5758(dev, head, 0, dcbent->index);
3356 parse_init_table(bios, scriptptr, &iexec);
3357
3358 nv04_dfp_bind_head(dev, dcbent, head, dl);
3359}
3360
3361static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script)
3362{
3363 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3364 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3365 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & OUTPUT_C ? 1 : 0);
3366 uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]);
3367
3368 if (!bios->fp.xlated_entry || !sub || !scriptofs)
3369 return -EINVAL;
3370
3371 run_digital_op_script(dev, scriptofs, dcbent, head, bios->fp.dual_link);
3372
3373 if (script == LVDS_PANEL_OFF) {
3374 /* off-on delay in ms */
3375 msleep(ROM16(bios->data[bios->fp.xlated_entry + 7]));
3376 }
3377#ifdef __powerpc__
3378 /* Powerbook specific quirks */
3d9aefb8
FJ		 3379 if ((dev->pci_device & 0xffff) == 0x0179 ||
3380 (dev->pci_device & 0xffff) == 0x0189 ||
3381 (dev->pci_device & 0xffff) == 0x0329) {
3382 if (script == LVDS_RESET) {
3383 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72);
3384
3385 } else if (script == LVDS_PANEL_ON) {
3386 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL,
3387 bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL)
3388 | (1 << 31));
3389 bios_wr32(bios, NV_PCRTC_GPIO_EXT,
3390 bios_rd32(bios, NV_PCRTC_GPIO_EXT) | 1);
3391
3392 } else if (script == LVDS_PANEL_OFF) {
3393 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL,
3394 bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL)
3395 & ~(1 << 31));
3396 bios_wr32(bios, NV_PCRTC_GPIO_EXT,
3397 bios_rd32(bios, NV_PCRTC_GPIO_EXT) & ~3);
6ee73861
BS		 3398 }
3399 }
3400#endif
3401
3402 return 0;
3403}
3404
3405static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3406{
3407 /*
3408 * The BIT LVDS table's header has the information to setup the
3409 * necessary registers. Following the standard 4 byte header are:
3410 * A bitmask byte and a dual-link transition pxclk value for use in
3411 * selecting the init script when not using straps; 4 script pointers
3412 * for panel power, selected by output and on/off; and 8 table pointers
3413 * for panel init, the needed one determined by output, and bits in the
3414 * conf byte. These tables are similar to the TMDS tables, consisting
3415 * of a list of pxclks and script pointers.
3416 */
3417 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3418 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3419 unsigned int outputset = (dcbent->or == 4) ? 1 : 0;
3420 uint16_t scriptptr = 0, clktable;
6ee73861
BS		 3421
3422 /*
3423 * For now we assume version 3.0 table - g80 support will need some
3424 * changes
3425 */
3426
3427 switch (script) {
3428 case LVDS_INIT:
3429 return -ENOSYS;
3430 case LVDS_BACKLIGHT_ON:
3431 case LVDS_PANEL_ON:
3432 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]);
3433 break;
3434 case LVDS_BACKLIGHT_OFF:
3435 case LVDS_PANEL_OFF:
3436 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]);
3437 break;
3438 case LVDS_RESET:
f3bbb9cc
BS		 3439 clktable = bios->fp.lvdsmanufacturerpointer + 15;
3440 if (dcbent->or == 4)
3441 clktable += 8;
3442
6ee73861
BS		 3443 if (dcbent->lvdsconf.use_straps_for_mode) {
3444 if (bios->fp.dual_link)
f3bbb9cc
BS		 3445 clktable += 4;
3446 if (bios->fp.if_is_24bit)
3447 clktable += 2;
6ee73861
BS		 3448 } else {
3449 /* using EDID */
f3bbb9cc 3450 int cmpval_24bit = (dcbent->or == 4) ? 4 : 1;
6ee73861
BS		 3451
3452 if (bios->fp.dual_link) {
f3bbb9cc
BS		 3453 clktable += 4;
3454 cmpval_24bit <<= 1;
6ee73861 3455 }
f3bbb9cc
BS		 3456
3457 if (bios->fp.strapless_is_24bit & cmpval_24bit)
3458 clktable += 2;
6ee73861
BS		 3459 }
3460
f3bbb9cc 3461 clktable = ROM16(bios->data[clktable]);
6ee73861
BS		 3462 if (!clktable) {
3463 NV_ERROR(dev, "Pixel clock comparison table not found\n");
3464 return -ENOENT;
3465 }
3466 scriptptr = clkcmptable(bios, clktable, pxclk);
3467 }
3468
3469 if (!scriptptr) {
3470 NV_ERROR(dev, "LVDS output init script not found\n");
3471 return -ENOENT;
3472 }
3473 run_digital_op_script(dev, scriptptr, dcbent, head, bios->fp.dual_link);
3474
3475 return 0;
3476}
3477
3478int call_lvds_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3479{
3480 /*
3481 * LVDS operations are multiplexed in an effort to present a single API
3482 * which works with two vastly differing underlying structures.
3483 * This acts as the demux
3484 */
3485
3486 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3487 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3488 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3489 uint32_t sel_clk_binding, sel_clk;
3490 int ret;
3491
3492 if (bios->fp.last_script_invoc == (script << 1 | head) || !lvds_ver ||
3493 (lvds_ver >= 0x30 && script == LVDS_INIT))
3494 return 0;
3495
3496 if (!bios->fp.lvds_init_run) {
3497 bios->fp.lvds_init_run = true;
3498 call_lvds_script(dev, dcbent, head, LVDS_INIT, pxclk);
3499 }
3500
3501 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change)
3502 call_lvds_script(dev, dcbent, head, LVDS_RESET, pxclk);
3503 if (script == LVDS_RESET && bios->fp.power_off_for_reset)
3504 call_lvds_script(dev, dcbent, head, LVDS_PANEL_OFF, pxclk);
3505
3506 NV_TRACE(dev, "Calling LVDS script %d:\n", script);
3507
3508 /* don't let script change pll->head binding */
3509 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
3510
3511 if (lvds_ver < 0x30)
3512 ret = call_lvds_manufacturer_script(dev, dcbent, head, script);
3513 else
3514 ret = run_lvds_table(dev, dcbent, head, script, pxclk);
3515
3516 bios->fp.last_script_invoc = (script << 1 | head);
3517
3518 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
3519 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
3520 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */
3521 nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0);
3522
3523 return ret;
3524}
3525
3526struct lvdstableheader {
3527 uint8_t lvds_ver, headerlen, recordlen;
3528};
3529
3530static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct nvbios *bios, struct lvdstableheader *lth)
3531{
3532 /*
3533 * BMP version (0xa) LVDS table has a simple header of version and
3534 * record length. The BIT LVDS table has the typical BIT table header:
3535 * version byte, header length byte, record length byte, and a byte for
3536 * the maximum number of records that can be held in the table.
3537 */
3538
3539 uint8_t lvds_ver, headerlen, recordlen;
3540
3541 memset(lth, 0, sizeof(struct lvdstableheader));
3542
3543 if (bios->fp.lvdsmanufacturerpointer == 0x0) {
3544 NV_ERROR(dev, "Pointer to LVDS manufacturer table invalid\n");
3545 return -EINVAL;
3546 }
3547
3548 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3549
3550 switch (lvds_ver) {
3551 case 0x0a: /* pre NV40 */
3552 headerlen = 2;
3553 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3554 break;
3555 case 0x30: /* NV4x */
3556 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3557 if (headerlen < 0x1f) {
3558 NV_ERROR(dev, "LVDS table header not understood\n");
3559 return -EINVAL;
3560 }
3561 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3562 break;
3563 case 0x40: /* G80/G90 */
3564 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3565 if (headerlen < 0x7) {
3566 NV_ERROR(dev, "LVDS table header not understood\n");
3567 return -EINVAL;
3568 }
3569 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3570 break;
3571 default:
3572 NV_ERROR(dev,
3573 "LVDS table revision %d.%d not currently supported\n",
3574 lvds_ver >> 4, lvds_ver & 0xf);
3575 return -ENOSYS;
3576 }
3577
3578 lth->lvds_ver = lvds_ver;
3579 lth->headerlen = headerlen;
3580 lth->recordlen = recordlen;
3581
3582 return 0;
3583}
3584
3585static int
3586get_fp_strap(struct drm_device *dev, struct nvbios *bios)
3587{
3588 struct drm_nouveau_private *dev_priv = dev->dev_private;
3589
3590 /*
3591 * The fp strap is normally dictated by the "User Strap" in
3592 * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the
3593 * Internal_Flags struct at 0x48 is set, the user strap gets overriden
3594 * by the PCI subsystem ID during POST, but not before the previous user
3595 * strap has been committed to CR58 for CR57=0xf on head A, which may be
3596 * read and used instead
3597 */
3598
3599 if (bios->major_version < 5 && bios->data[0x48] & 0x4)
3600 return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf;
3601
3602 if (dev_priv->card_type >= NV_50)
3603 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 24) & 0xf;
3604 else
3605 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
3606}
3607
3608static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios)
3609{
3610 uint8_t *fptable;
3611 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex;
3612 int ret, ofs, fpstrapping;
3613 struct lvdstableheader lth;
3614
3615 if (bios->fp.fptablepointer == 0x0) {
3616 /* Apple cards don't have the fp table; the laptops use DDC */
3617 /* The table is also missing on some x86 IGPs */
3618#ifndef __powerpc__
3619 NV_ERROR(dev, "Pointer to flat panel table invalid\n");
3620#endif
04a39c57 3621 bios->digital_min_front_porch = 0x4b;
6ee73861
BS		 3622 return 0;
3623 }
3624
3625 fptable = &bios->data[bios->fp.fptablepointer];
3626 fptable_ver = fptable[0];
3627
3628 switch (fptable_ver) {
3629 /*
3630 * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no
3631 * version field, and miss one of the spread spectrum/PWM bytes.
3632 * This could affect early GF2Go parts (not seen any appropriate ROMs
3633 * though). Here we assume that a version of 0x05 matches this case
3634 * (combining with a BMP version check would be better), as the
3635 * common case for the panel type field is 0x0005, and that is in
3636 * fact what we are reading the first byte of.
3637 */
3638 case 0x05: /* some NV10, 11, 15, 16 */
3639 recordlen = 42;
3640 ofs = -1;
3641 break;
3642 case 0x10: /* some NV15/16, and NV11+ */
3643 recordlen = 44;
3644 ofs = 0;
3645 break;
3646 case 0x20: /* NV40+ */
3647 headerlen = fptable[1];
3648 recordlen = fptable[2];
3649 fpentries = fptable[3];
3650 /*
3651 * fptable[4] is the minimum
3652 * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap
3653 */
04a39c57 3654 bios->digital_min_front_porch = fptable[4];
6ee73861
BS		 3655 ofs = -7;
3656 break;
3657 default:
3658 NV_ERROR(dev,
3659 "FP table revision %d.%d not currently supported\n",
3660 fptable_ver >> 4, fptable_ver & 0xf);
3661 return -ENOSYS;
3662 }
3663
3664 if (!bios->is_mobile) /* !mobile only needs digital_min_front_porch */
3665 return 0;
3666
3667 ret = parse_lvds_manufacturer_table_header(dev, bios, &lth);
3668 if (ret)
3669 return ret;
3670
3671 if (lth.lvds_ver == 0x30 || lth.lvds_ver == 0x40) {
3672 bios->fp.fpxlatetableptr = bios->fp.lvdsmanufacturerpointer +
3673 lth.headerlen + 1;
3674 bios->fp.xlatwidth = lth.recordlen;
3675 }
3676 if (bios->fp.fpxlatetableptr == 0x0) {
3677 NV_ERROR(dev, "Pointer to flat panel xlat table invalid\n");
3678 return -EINVAL;
3679 }
3680
3681 fpstrapping = get_fp_strap(dev, bios);
3682
3683 fpindex = bios->data[bios->fp.fpxlatetableptr +
3684 fpstrapping * bios->fp.xlatwidth];
3685
3686 if (fpindex > fpentries) {
3687 NV_ERROR(dev, "Bad flat panel table index\n");
3688 return -ENOENT;
3689 }
3690
3691 /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */
3692 if (lth.lvds_ver > 0x10)
04a39c57 3693 bios->fp_no_ddc = fpstrapping != 0xf || fpindex != 0xf;
6ee73861
BS		 3694
3695 /*
3696 * If either the strap or xlated fpindex value are 0xf there is no
3697 * panel using a strap-derived bios mode present. this condition
3698 * includes, but is different from, the DDC panel indicator above
3699 */
3700 if (fpstrapping == 0xf || fpindex == 0xf)
3701 return 0;
3702
3703 bios->fp.mode_ptr = bios->fp.fptablepointer + headerlen +
3704 recordlen * fpindex + ofs;
3705
3706 NV_TRACE(dev, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n",
3707 ROM16(bios->data[bios->fp.mode_ptr + 11]) + 1,
3708 ROM16(bios->data[bios->fp.mode_ptr + 25]) + 1,
3709 ROM16(bios->data[bios->fp.mode_ptr + 7]) * 10);
3710
3711 return 0;
3712}
3713
3714bool nouveau_bios_fp_mode(struct drm_device *dev, struct drm_display_mode *mode)
3715{
3716 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3717 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3718 uint8_t *mode_entry = &bios->data[bios->fp.mode_ptr];
3719
3720 if (!mode) /* just checking whether we can produce a mode */
3721 return bios->fp.mode_ptr;
3722
3723 memset(mode, 0, sizeof(struct drm_display_mode));
3724 /*
3725 * For version 1.0 (version in byte 0):
3726 * bytes 1-2 are "panel type", including bits on whether Colour/mono,
3727 * single/dual link, and type (TFT etc.)
3728 * bytes 3-6 are bits per colour in RGBX
3729 */
3730 mode->clock = ROM16(mode_entry[7]) * 10;
3731 /* bytes 9-10 is HActive */
3732 mode->hdisplay = ROM16(mode_entry[11]) + 1;
3733 /*
3734 * bytes 13-14 is HValid Start
3735 * bytes 15-16 is HValid End
3736 */
3737 mode->hsync_start = ROM16(mode_entry[17]) + 1;
3738 mode->hsync_end = ROM16(mode_entry[19]) + 1;
3739 mode->htotal = ROM16(mode_entry[21]) + 1;
3740 /* bytes 23-24, 27-30 similarly, but vertical */
3741 mode->vdisplay = ROM16(mode_entry[25]) + 1;
3742 mode->vsync_start = ROM16(mode_entry[31]) + 1;
3743 mode->vsync_end = ROM16(mode_entry[33]) + 1;
3744 mode->vtotal = ROM16(mode_entry[35]) + 1;
3745 mode->flags |= (mode_entry[37] & 0x10) ?
3746 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
3747 mode->flags |= (mode_entry[37] & 0x1) ?
3748 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
3749 /*
3750 * bytes 38-39 relate to spread spectrum settings
3751 * bytes 40-43 are something to do with PWM
3752 */
3753
3754 mode->status = MODE_OK;
3755 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
3756 drm_mode_set_name(mode);
3757 return bios->fp.mode_ptr;
3758}
3759
3760int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, bool *if_is_24bit)
3761{
3762 /*
3763 * The LVDS table header is (mostly) described in
3764 * parse_lvds_manufacturer_table_header(): the BIT header additionally
3765 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if
3766 * straps are not being used for the panel, this specifies the frequency
3767 * at which modes should be set up in the dual link style.
3768 *
3769 * Following the header, the BMP (ver 0xa) table has several records,
3ad2f3fb 3770 * indexed by a separate xlat table, indexed in turn by the fp strap in
6ee73861
BS		 3771 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script
3772 * numbers for use by INIT_SUB which controlled panel init and power,
3773 * and finally a dword of ms to sleep between power off and on
3774 * operations.
3775 *
3776 * In the BIT versions, the table following the header serves as an
3777 * integrated config and xlat table: the records in the table are
3778 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has
3779 * two bytes - the first as a config byte, the second for indexing the
3780 * fp mode table pointed to by the BIT 'D' table
3781 *
3782 * DDC is not used until after card init, so selecting the correct table
3783 * entry and setting the dual link flag for EDID equipped panels,
3784 * requiring tests against the native-mode pixel clock, cannot be done
3785 * until later, when this function should be called with non-zero pxclk
3786 */
3787 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3788 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3789 int fpstrapping = get_fp_strap(dev, bios), lvdsmanufacturerindex = 0;
3790 struct lvdstableheader lth;
3791 uint16_t lvdsofs;
04a39c57 3792 int ret, chip_version = bios->chip_version;
6ee73861
BS		 3793
3794 ret = parse_lvds_manufacturer_table_header(dev, bios, &lth);
3795 if (ret)
3796 return ret;
3797
3798 switch (lth.lvds_ver) {
3799 case 0x0a: /* pre NV40 */
3800 lvdsmanufacturerindex = bios->data[
3801 bios->fp.fpxlatemanufacturertableptr +
3802 fpstrapping];
3803
3804 /* we're done if this isn't the EDID panel case */
3805 if (!pxclk)
3806 break;
3807
3808 if (chip_version < 0x25) {
3809 /* nv17 behaviour
3810 *
3811 * It seems the old style lvds script pointer is reused
3812 * to select 18/24 bit colour depth for EDID panels.
3813 */
3814 lvdsmanufacturerindex =
3815 (bios->legacy.lvds_single_a_script_ptr & 1) ?
3816 2 : 0;
3817 if (pxclk >= bios->fp.duallink_transition_clk)
3818 lvdsmanufacturerindex++;
3819 } else if (chip_version < 0x30) {
3820 /* nv28 behaviour (off-chip encoder)
3821 *
3822 * nv28 does a complex dance of first using byte 121 of
3823 * the EDID to choose the lvdsmanufacturerindex, then
3824 * later attempting to match the EDID manufacturer and
3825 * product IDs in a table (signature 'pidt' (panel id
3826 * table?)), setting an lvdsmanufacturerindex of 0 and
3827 * an fp strap of the match index (or 0xf if none)
3828 */
3829 lvdsmanufacturerindex = 0;
3830 } else {
3831 /* nv31, nv34 behaviour */
3832 lvdsmanufacturerindex = 0;
3833 if (pxclk >= bios->fp.duallink_transition_clk)
3834 lvdsmanufacturerindex = 2;
3835 if (pxclk >= 140000)
3836 lvdsmanufacturerindex = 3;
3837 }
3838
3839 /*
3840 * nvidia set the high nibble of (cr57=f, cr58) to
3841 * lvdsmanufacturerindex in this case; we don't
3842 */
3843 break;
3844 case 0x30: /* NV4x */
3845 case 0x40: /* G80/G90 */
3846 lvdsmanufacturerindex = fpstrapping;
3847 break;
3848 default:
3849 NV_ERROR(dev, "LVDS table revision not currently supported\n");
3850 return -ENOSYS;
3851 }
3852
3853 lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + lth.headerlen + lth.recordlen * lvdsmanufacturerindex;
3854 switch (lth.lvds_ver) {
3855 case 0x0a:
3856 bios->fp.power_off_for_reset = bios->data[lvdsofs] & 1;
3857 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2;
3858 bios->fp.dual_link = bios->data[lvdsofs] & 4;
3859 bios->fp.link_c_increment = bios->data[lvdsofs] & 8;
3860 *if_is_24bit = bios->data[lvdsofs] & 16;
3861 break;
3862 case 0x30:
f3bbb9cc 3863 case 0x40:
6ee73861
BS		 3864 /*
3865 * No sign of the "power off for reset" or "reset for panel
3866 * on" bits, but it's safer to assume we should
3867 */
3868 bios->fp.power_off_for_reset = true;
3869 bios->fp.reset_after_pclk_change = true;
f3bbb9cc 3870
6ee73861
BS		 3871 /*
3872 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is
f3bbb9cc 3873 * over-written, and if_is_24bit isn't used
6ee73861
BS		 3874 */
3875 bios->fp.dual_link = bios->data[lvdsofs] & 1;
6ee73861
BS		 3876 bios->fp.if_is_24bit = bios->data[lvdsofs] & 2;
3877 bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4];
3878 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
3879 break;
3880 }
3881
2eb92c80
BS		 3882 /* Dell Latitude D620 reports a too-high value for the dual-link
3883 * transition freq, causing us to program the panel incorrectly.
3884 *
3885 * It doesn't appear the VBIOS actually uses its transition freq
3886 * (90000kHz), instead it uses the "Number of LVDS channels" field
3887 * out of the panel ID structure (http://www.spwg.org/).
3888 *
3889 * For the moment, a quirk will do :)
3890 */
3891 if ((dev->pdev->device == 0x01d7) &&
3892 (dev->pdev->subsystem_vendor == 0x1028) &&
3893 (dev->pdev->subsystem_device == 0x01c2)) {
3894 bios->fp.duallink_transition_clk = 80000;
3895 }
3896
6ee73861
BS		 3897 /* set dual_link flag for EDID case */
3898 if (pxclk && (chip_version < 0x25 || chip_version > 0x28))
3899 bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk);
3900
3901 *dl = bios->fp.dual_link;
3902
3903 return 0;
3904}
3905
3906static uint8_t *
3907bios_output_config_match(struct drm_device *dev, struct dcb_entry *dcbent,
1eb38100
BS		 3908 uint16_t record, int record_len, int record_nr,
3909 bool match_link)
6ee73861
BS		 3910{
3911 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3912 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3913 uint32_t entry;
3914 uint16_t table;
3915 int i, v;
3916
1eb38100
BS		 3917 switch (dcbent->type) {
3918 case OUTPUT_TMDS:
3919 case OUTPUT_LVDS:
3920 case OUTPUT_DP:
3921 break;
3922 default:
3923 match_link = false;
3924 break;
3925 }
3926
6ee73861
BS		 3927 for (i = 0; i < record_nr; i++, record += record_len) {
3928 table = ROM16(bios->data[record]);
3929 if (!table)
3930 continue;
3931 entry = ROM32(bios->data[table]);
3932
1eb38100
BS		 3933 if (match_link) {
3934 v = (entry & 0x00c00000) >> 22;
3935 if (!(v & dcbent->sorconf.link))
3936 continue;
3937 }
3938
6ee73861
BS		 3939 v = (entry & 0x000f0000) >> 16;
3940 if (!(v & dcbent->or))
3941 continue;
3942
3943 v = (entry & 0x000000f0) >> 4;
3944 if (v != dcbent->location)
3945 continue;
3946
3947 v = (entry & 0x0000000f);
3948 if (v != dcbent->type)
3949 continue;
3950
3951 return &bios->data[table];
3952 }
3953
3954 return NULL;
3955}
3956
3957void *
3958nouveau_bios_dp_table(struct drm_device *dev, struct dcb_entry *dcbent,
3959 int *length)
3960{
3961 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3962 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3963 uint8_t *table;
3964
3965 if (!bios->display.dp_table_ptr) {
3966 NV_ERROR(dev, "No pointer to DisplayPort table\n");
3967 return NULL;
3968 }
3969 table = &bios->data[bios->display.dp_table_ptr];
3970
c52e53fd 3971 if (table[0] != 0x20 && table[0] != 0x21) {
6ee73861
BS		 3972 NV_ERROR(dev, "DisplayPort table version 0x%02x unknown\n",
3973 table[0]);
3974 return NULL;
3975 }
3976
3977 *length = table[4];
3978 return bios_output_config_match(dev, dcbent,
3979 bios->display.dp_table_ptr + table[1],
1eb38100 3980 table[2], table[3], table[0] >= 0x21);
6ee73861
BS		 3981}
3982
3983int
3984nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
3985 uint32_t sub, int pxclk)
3986{
3987 /*
3988 * The display script table is located by the BIT 'U' table.
3989 *
3990 * It contains an array of pointers to various tables describing
3991 * a particular output type. The first 32-bits of the output
3992 * tables contains similar information to a DCB entry, and is
3993 * used to decide whether that particular table is suitable for
3994 * the output you want to access.
3995 *
3996 * The "record header length" field here seems to indicate the
3997 * offset of the first configuration entry in the output tables.
3998 * This is 10 on most cards I've seen, but 12 has been witnessed
3999 * on DP cards, and there's another script pointer within the
4000 * header.
4001 *
4002 * offset + 0 ( 8 bits): version
4003 * offset + 1 ( 8 bits): header length
4004 * offset + 2 ( 8 bits): record length
4005 * offset + 3 ( 8 bits): number of records
4006 * offset + 4 ( 8 bits): record header length
4007 * offset + 5 (16 bits): pointer to first output script table
4008 */
4009
4010 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 4011 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 4012 uint8_t *table = &bios->data[bios->display.script_table_ptr];
4013 uint8_t *otable = NULL;
4014 uint16_t script;
4015 int i = 0;
4016
4017 if (!bios->display.script_table_ptr) {
4018 NV_ERROR(dev, "No pointer to output script table\n");
4019 return 1;
4020 }
4021
4022 /*
4023 * Nothing useful has been in any of the pre-2.0 tables I've seen,
4024 * so until they are, we really don't need to care.
4025 */
4026 if (table[0] < 0x20)
4027 return 1;
4028
4029 if (table[0] != 0x20 && table[0] != 0x21) {
4030 NV_ERROR(dev, "Output script table version 0x%02x unknown\n",
4031 table[0]);
4032 return 1;
4033 }
4034
4035 /*
4036 * The output script tables describing a particular output type
4037 * look as follows:
4038 *
4039 * offset + 0 (32 bits): output this table matches (hash of DCB)
4040 * offset + 4 ( 8 bits): unknown
4041 * offset + 5 ( 8 bits): number of configurations
4042 * offset + 6 (16 bits): pointer to some script
4043 * offset + 8 (16 bits): pointer to some script
4044 *
4045 * headerlen == 10
4046 * offset + 10 : configuration 0
4047 *
4048 * headerlen == 12
4049 * offset + 10 : pointer to some script
4050 * offset + 12 : configuration 0
4051 *
4052 * Each config entry is as follows:
4053 *
4054 * offset + 0 (16 bits): unknown, assumed to be a match value
4055 * offset + 2 (16 bits): pointer to script table (clock set?)
4056 * offset + 4 (16 bits): pointer to script table (reset?)
4057 *
4058 * There doesn't appear to be a count value to say how many
4059 * entries exist in each script table, instead, a 0 value in
4060 * the first 16-bit word seems to indicate both the end of the
4061 * list and the default entry. The second 16-bit word in the
4062 * script tables is a pointer to the script to execute.
4063 */
4064
ef2bb506 4065 NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n",
6ee73861
BS		 4066 dcbent->type, dcbent->location, dcbent->or);
4067 otable = bios_output_config_match(dev, dcbent, table[1] +
4068 bios->display.script_table_ptr,
1eb38100 4069 table[2], table[3], table[0] >= 0x21);
6ee73861
BS		 4070 if (!otable) {
4071 NV_ERROR(dev, "Couldn't find matching output script table\n");
4072 return 1;
4073 }
4074
4075 if (pxclk < -2 || pxclk > 0) {
4076 /* Try to find matching script table entry */
4077 for (i = 0; i < otable[5]; i++) {
4078 if (ROM16(otable[table[4] + i*6]) == sub)
4079 break;
4080 }
4081
4082 if (i == otable[5]) {
4083 NV_ERROR(dev, "Table 0x%04x not found for %d/%d, "
4084 "using first\n",
4085 sub, dcbent->type, dcbent->or);
4086 i = 0;
4087 }
4088 }
4089
6ee73861
BS		 4090 if (pxclk == 0) {
4091 script = ROM16(otable[6]);
4092 if (!script) {
ef2bb506 4093 NV_DEBUG_KMS(dev, "output script 0 not found\n");
6ee73861
BS		 4094 return 1;
4095 }
4096
4097 NV_TRACE(dev, "0x%04X: parsing output script 0\n", script);
39c9bfb4 4098 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 4099 } else
4100 if (pxclk == -1) {
4101 script = ROM16(otable[8]);
4102 if (!script) {
ef2bb506 4103 NV_DEBUG_KMS(dev, "output script 1 not found\n");
6ee73861
BS		 4104 return 1;
4105 }
4106
4107 NV_TRACE(dev, "0x%04X: parsing output script 1\n", script);
39c9bfb4 4108 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 4109 } else
4110 if (pxclk == -2) {
4111 if (table[4] >= 12)
4112 script = ROM16(otable[10]);
4113 else
4114 script = 0;
4115 if (!script) {
ef2bb506 4116 NV_DEBUG_KMS(dev, "output script 2 not found\n");
6ee73861
BS		 4117 return 1;
4118 }
4119
4120 NV_TRACE(dev, "0x%04X: parsing output script 2\n", script);
39c9bfb4 4121 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 4122 } else
4123 if (pxclk > 0) {
4124 script = ROM16(otable[table[4] + i*6 + 2]);
4125 if (script)
4126 script = clkcmptable(bios, script, pxclk);
4127 if (!script) {
4128 NV_ERROR(dev, "clock script 0 not found\n");
4129 return 1;
4130 }
4131
4132 NV_TRACE(dev, "0x%04X: parsing clock script 0\n", script);
39c9bfb4 4133 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 4134 } else
4135 if (pxclk < 0) {
4136 script = ROM16(otable[table[4] + i*6 + 4]);
4137 if (script)
4138 script = clkcmptable(bios, script, -pxclk);
4139 if (!script) {
ef2bb506 4140 NV_DEBUG_KMS(dev, "clock script 1 not found\n");
6ee73861
BS		 4141 return 1;
4142 }
4143
4144 NV_TRACE(dev, "0x%04X: parsing clock script 1\n", script);
39c9bfb4 4145 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 4146 }
4147
4148 return 0;
4149}
4150
4151
4152int run_tmds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, int pxclk)
4153{
4154 /*
4155 * the pxclk parameter is in kHz
4156 *
4157 * This runs the TMDS regs setting code found on BIT bios cards
4158 *
4159 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and
4160 * ffs(or) == 3, use the second.
4161 */
4162
4163 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57
BS		 4164 struct nvbios *bios = &dev_priv->vbios;
4165 int cv = bios->chip_version;
6ee73861
BS		 4166 uint16_t clktable = 0, scriptptr;
4167 uint32_t sel_clk_binding, sel_clk;
4168
4169 /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */
4170 if (cv >= 0x17 && cv != 0x1a && cv != 0x20 &&
4171 dcbent->location != DCB_LOC_ON_CHIP)
4172 return 0;
4173
4174 switch (ffs(dcbent->or)) {
4175 case 1:
4176 clktable = bios->tmds.output0_script_ptr;
4177 break;
4178 case 2:
4179 case 3:
4180 clktable = bios->tmds.output1_script_ptr;
4181 break;
4182 }
4183
4184 if (!clktable) {
4185 NV_ERROR(dev, "Pixel clock comparison table not found\n");
4186 return -EINVAL;
4187 }
4188
4189 scriptptr = clkcmptable(bios, clktable, pxclk);
4190
4191 if (!scriptptr) {
4192 NV_ERROR(dev, "TMDS output init script not found\n");
4193 return -ENOENT;
4194 }
4195
4196 /* don't let script change pll->head binding */
4197 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
4198 run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000);
4199 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
4200 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
4201
4202 return 0;
4203}
4204
4205int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims *pll_lim)
4206{
4207 /*
4208 * PLL limits table
4209 *
4210 * Version 0x10: NV30, NV31
4211 * One byte header (version), one record of 24 bytes
4212 * Version 0x11: NV36 - Not implemented
4213 * Seems to have same record style as 0x10, but 3 records rather than 1
4214 * Version 0x20: Found on Geforce 6 cards
4215 * Trivial 4 byte BIT header. 31 (0x1f) byte record length
4216 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards
4217 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record
4218 * length in general, some (integrated) have an extra configuration byte
4219 * Version 0x30: Found on Geforce 8, separates the register mapping
4220 * from the limits tables.
4221 */
4222
4223 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57
BS		 4224 struct nvbios *bios = &dev_priv->vbios;
4225 int cv = bios->chip_version, pllindex = 0;
6ee73861
BS		 4226 uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0;
4227 uint32_t crystal_strap_mask, crystal_straps;
4228
4229 if (!bios->pll_limit_tbl_ptr) {
4230 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
4231 cv >= 0x40) {
4232 NV_ERROR(dev, "Pointer to PLL limits table invalid\n");
4233 return -EINVAL;
4234 }
4235 } else
4236 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr];
4237
4238 crystal_strap_mask = 1 << 6;
4239 /* open coded dev->twoHeads test */
4240 if (cv > 0x10 && cv != 0x15 && cv != 0x1a && cv != 0x20)
4241 crystal_strap_mask |= 1 << 22;
4242 crystal_straps = nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) &
4243 crystal_strap_mask;
4244
4245 switch (pll_lim_ver) {
4246 /*
4247 * We use version 0 to indicate a pre limit table bios (single stage
4248 * pll) and load the hard coded limits instead.
4249 */
4250 case 0:
4251 break;
4252 case 0x10:
4253 case 0x11:
4254 /*
4255 * Strictly v0x11 has 3 entries, but the last two don't seem
4256 * to get used.
4257 */
4258 headerlen = 1;
4259 recordlen = 0x18;
4260 entries = 1;
4261 pllindex = 0;
4262 break;
4263 case 0x20:
4264 case 0x21:
4265 case 0x30:
4266 case 0x40:
4267 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1];
4268 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2];
4269 entries = bios->data[bios->pll_limit_tbl_ptr + 3];
4270 break;
4271 default:
4272 NV_ERROR(dev, "PLL limits table revision 0x%X not currently "
4273 "supported\n", pll_lim_ver);
4274 return -ENOSYS;
4275 }
4276
4277 /* initialize all members to zero */
4278 memset(pll_lim, 0, sizeof(struct pll_lims));
4279
4280 if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) {
4281 uint8_t *pll_rec = &bios->data[bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex];
4282
4283 pll_lim->vco1.minfreq = ROM32(pll_rec[0]);
4284 pll_lim->vco1.maxfreq = ROM32(pll_rec[4]);
4285 pll_lim->vco2.minfreq = ROM32(pll_rec[8]);
4286 pll_lim->vco2.maxfreq = ROM32(pll_rec[12]);
4287 pll_lim->vco1.min_inputfreq = ROM32(pll_rec[16]);
4288 pll_lim->vco2.min_inputfreq = ROM32(pll_rec[20]);
4289 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX;
4290
4291 /* these values taken from nv30/31/36 */
4292 pll_lim->vco1.min_n = 0x1;
4293 if (cv == 0x36)
4294 pll_lim->vco1.min_n = 0x5;
4295 pll_lim->vco1.max_n = 0xff;
4296 pll_lim->vco1.min_m = 0x1;
4297 pll_lim->vco1.max_m = 0xd;
4298 pll_lim->vco2.min_n = 0x4;
4299 /*
4300 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this
4301 * table version (apart from nv35)), N2 is compared to
4302 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and
4303 * save a comparison
4304 */
4305 pll_lim->vco2.max_n = 0x28;
4306 if (cv == 0x30 || cv == 0x35)
4307 /* only 5 bits available for N2 on nv30/35 */
4308 pll_lim->vco2.max_n = 0x1f;
4309 pll_lim->vco2.min_m = 0x1;
4310 pll_lim->vco2.max_m = 0x4;
4311 pll_lim->max_log2p = 0x7;
4312 pll_lim->max_usable_log2p = 0x6;
4313 } else if (pll_lim_ver == 0x20 || pll_lim_ver == 0x21) {
4314 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen;
4315 uint32_t reg = 0; /* default match */
4316 uint8_t *pll_rec;
4317 int i;
4318
4319 /*
4320 * First entry is default match, if nothing better. warn if
4321 * reg field nonzero
4322 */
4323 if (ROM32(bios->data[plloffs]))
4324 NV_WARN(dev, "Default PLL limit entry has non-zero "
4325 "register field\n");
4326
4327 if (limit_match > MAX_PLL_TYPES)
4328 /* we've been passed a reg as the match */
4329 reg = limit_match;
4330 else /* limit match is a pll type */
4331 for (i = 1; i < entries && !reg; i++) {
4332 uint32_t cmpreg = ROM32(bios->data[plloffs + recordlen * i]);
4333
4334 if (limit_match == NVPLL &&
4335 (cmpreg == NV_PRAMDAC_NVPLL_COEFF || cmpreg == 0x4000))
4336 reg = cmpreg;
4337 if (limit_match == MPLL &&
4338 (cmpreg == NV_PRAMDAC_MPLL_COEFF || cmpreg == 0x4020))
4339 reg = cmpreg;
4340 if (limit_match == VPLL1 &&
4341 (cmpreg == NV_PRAMDAC_VPLL_COEFF || cmpreg == 0x4010))
4342 reg = cmpreg;
4343 if (limit_match == VPLL2 &&
4344 (cmpreg == NV_RAMDAC_VPLL2 || cmpreg == 0x4018))
4345 reg = cmpreg;
4346 }
4347
4348 for (i = 1; i < entries; i++)
4349 if (ROM32(bios->data[plloffs + recordlen * i]) == reg) {
4350 pllindex = i;
4351 break;
4352 }
4353
4354 pll_rec = &bios->data[plloffs + recordlen * pllindex];
4355
4356 BIOSLOG(bios, "Loading PLL limits for reg 0x%08x\n",
4357 pllindex ? reg : 0);
4358
4359 /*
4360 * Frequencies are stored in tables in MHz, kHz are more
4361 * useful, so we convert.
4362 */
4363
4364 /* What output frequencies can each VCO generate? */
4365 pll_lim->vco1.minfreq = ROM16(pll_rec[4]) * 1000;
4366 pll_lim->vco1.maxfreq = ROM16(pll_rec[6]) * 1000;
4367 pll_lim->vco2.minfreq = ROM16(pll_rec[8]) * 1000;
4368 pll_lim->vco2.maxfreq = ROM16(pll_rec[10]) * 1000;
4369
4370 /* What input frequencies they accept (past the m-divider)? */
4371 pll_lim->vco1.min_inputfreq = ROM16(pll_rec[12]) * 1000;
4372 pll_lim->vco2.min_inputfreq = ROM16(pll_rec[14]) * 1000;
4373 pll_lim->vco1.max_inputfreq = ROM16(pll_rec[16]) * 1000;
4374 pll_lim->vco2.max_inputfreq = ROM16(pll_rec[18]) * 1000;
4375
4376 /* What values are accepted as multiplier and divider? */
4377 pll_lim->vco1.min_n = pll_rec[20];
4378 pll_lim->vco1.max_n = pll_rec[21];
4379 pll_lim->vco1.min_m = pll_rec[22];
4380 pll_lim->vco1.max_m = pll_rec[23];
4381 pll_lim->vco2.min_n = pll_rec[24];
4382 pll_lim->vco2.max_n = pll_rec[25];
4383 pll_lim->vco2.min_m = pll_rec[26];
4384 pll_lim->vco2.max_m = pll_rec[27];
4385
4386 pll_lim->max_usable_log2p = pll_lim->max_log2p = pll_rec[29];
4387 if (pll_lim->max_log2p > 0x7)
4388 /* pll decoding in nv_hw.c assumes never > 7 */
4389 NV_WARN(dev, "Max log2 P value greater than 7 (%d)\n",
4390 pll_lim->max_log2p);
4391 if (cv < 0x60)
4392 pll_lim->max_usable_log2p = 0x6;
4393 pll_lim->log2p_bias = pll_rec[30];
4394
4395 if (recordlen > 0x22)
4396 pll_lim->refclk = ROM32(pll_rec[31]);
4397
4398 if (recordlen > 0x23 && pll_rec[35])
4399 NV_WARN(dev,
4400 "Bits set in PLL configuration byte (%x)\n",
4401 pll_rec[35]);
4402
4403 /* C51 special not seen elsewhere */
4404 if (cv == 0x51 && !pll_lim->refclk) {
4405 uint32_t sel_clk = bios_rd32(bios, NV_PRAMDAC_SEL_CLK);
4406
4407 if (((limit_match == NV_PRAMDAC_VPLL_COEFF || limit_match == VPLL1) && sel_clk & 0x20) ||
4408 ((limit_match == NV_RAMDAC_VPLL2 || limit_match == VPLL2) && sel_clk & 0x80)) {
4409 if (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_CHIP_ID_INDEX) < 0xa3)
4410 pll_lim->refclk = 200000;
4411 else
4412 pll_lim->refclk = 25000;
4413 }
4414 }
4415 } else if (pll_lim_ver == 0x30) { /* ver 0x30 */
4416 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
4417 uint8_t *record = NULL;
4418 int i;
4419
4420 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
4421 limit_match);
4422
4423 for (i = 0; i < entries; i++, entry += recordlen) {
4424 if (ROM32(entry[3]) == limit_match) {
4425 record = &bios->data[ROM16(entry[1])];
4426 break;
4427 }
4428 }
4429
4430 if (!record) {
4431 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4432 "limits table", limit_match);
4433 return -ENOENT;
4434 }
4435
4436 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
4437 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
4438 pll_lim->vco2.minfreq = ROM16(record[4]) * 1000;
4439 pll_lim->vco2.maxfreq = ROM16(record[6]) * 1000;
4440 pll_lim->vco1.min_inputfreq = ROM16(record[8]) * 1000;
4441 pll_lim->vco2.min_inputfreq = ROM16(record[10]) * 1000;
4442 pll_lim->vco1.max_inputfreq = ROM16(record[12]) * 1000;
4443 pll_lim->vco2.max_inputfreq = ROM16(record[14]) * 1000;
4444 pll_lim->vco1.min_n = record[16];
4445 pll_lim->vco1.max_n = record[17];
4446 pll_lim->vco1.min_m = record[18];
4447 pll_lim->vco1.max_m = record[19];
4448 pll_lim->vco2.min_n = record[20];
4449 pll_lim->vco2.max_n = record[21];
4450 pll_lim->vco2.min_m = record[22];
4451 pll_lim->vco2.max_m = record[23];
4452 pll_lim->max_usable_log2p = pll_lim->max_log2p = record[25];
4453 pll_lim->log2p_bias = record[27];
4454 pll_lim->refclk = ROM32(record[28]);
4455 } else if (pll_lim_ver) { /* ver 0x40 */
4456 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
4457 uint8_t *record = NULL;
4458 int i;
4459
4460 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
4461 limit_match);
4462
4463 for (i = 0; i < entries; i++, entry += recordlen) {
4464 if (ROM32(entry[3]) == limit_match) {
4465 record = &bios->data[ROM16(entry[1])];
4466 break;
4467 }
4468 }
4469
4470 if (!record) {
4471 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4472 "limits table", limit_match);
4473 return -ENOENT;
4474 }
4475
4476 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
4477 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
4478 pll_lim->vco1.min_inputfreq = ROM16(record[4]) * 1000;
4479 pll_lim->vco1.max_inputfreq = ROM16(record[6]) * 1000;
4480 pll_lim->vco1.min_m = record[8];
4481 pll_lim->vco1.max_m = record[9];
4482 pll_lim->vco1.min_n = record[10];
4483 pll_lim->vco1.max_n = record[11];
4484 pll_lim->min_p = record[12];
4485 pll_lim->max_p = record[13];
4486 /* where did this go to?? */
4487 if (limit_match == 0x00614100 || limit_match == 0x00614900)
4488 pll_lim->refclk = 27000;
4489 else
4490 pll_lim->refclk = 100000;
4491 }
4492
4493 /*
4494 * By now any valid limit table ought to have set a max frequency for
4495 * vco1, so if it's zero it's either a pre limit table bios, or one
4496 * with an empty limit table (seen on nv18)
4497 */
4498 if (!pll_lim->vco1.maxfreq) {
4499 pll_lim->vco1.minfreq = bios->fminvco;
4500 pll_lim->vco1.maxfreq = bios->fmaxvco;
4501 pll_lim->vco1.min_inputfreq = 0;
4502 pll_lim->vco1.max_inputfreq = INT_MAX;
4503 pll_lim->vco1.min_n = 0x1;
4504 pll_lim->vco1.max_n = 0xff;
4505 pll_lim->vco1.min_m = 0x1;
4506 if (crystal_straps == 0) {
4507 /* nv05 does this, nv11 doesn't, nv10 unknown */
4508 if (cv < 0x11)
4509 pll_lim->vco1.min_m = 0x7;
4510 pll_lim->vco1.max_m = 0xd;
4511 } else {
4512 if (cv < 0x11)
4513 pll_lim->vco1.min_m = 0x8;
4514 pll_lim->vco1.max_m = 0xe;
4515 }
4516 if (cv < 0x17 || cv == 0x1a || cv == 0x20)
4517 pll_lim->max_log2p = 4;
4518 else
4519 pll_lim->max_log2p = 5;
4520 pll_lim->max_usable_log2p = pll_lim->max_log2p;
4521 }
4522
4523 if (!pll_lim->refclk)
4524 switch (crystal_straps) {
4525 case 0:
4526 pll_lim->refclk = 13500;
4527 break;
4528 case (1 << 6):
4529 pll_lim->refclk = 14318;
4530 break;
4531 case (1 << 22):
4532 pll_lim->refclk = 27000;
4533 break;
4534 case (1 << 22 | 1 << 6):
4535 pll_lim->refclk = 25000;
4536 break;
4537 }
4538
4c389f00
BS		 4539 NV_DEBUG(dev, "pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq);
4540 NV_DEBUG(dev, "pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq);
4541 NV_DEBUG(dev, "pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq);
4542 NV_DEBUG(dev, "pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq);
4543 NV_DEBUG(dev, "pll.vco1.min_n: %d\n", pll_lim->vco1.min_n);
4544 NV_DEBUG(dev, "pll.vco1.max_n: %d\n", pll_lim->vco1.max_n);
4545 NV_DEBUG(dev, "pll.vco1.min_m: %d\n", pll_lim->vco1.min_m);
4546 NV_DEBUG(dev, "pll.vco1.max_m: %d\n", pll_lim->vco1.max_m);
4547 if (pll_lim->vco2.maxfreq) {
4548 NV_DEBUG(dev, "pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq);
4549 NV_DEBUG(dev, "pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq);
4550 NV_DEBUG(dev, "pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq);
4551 NV_DEBUG(dev, "pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq);
4552 NV_DEBUG(dev, "pll.vco2.min_n: %d\n", pll_lim->vco2.min_n);
4553 NV_DEBUG(dev, "pll.vco2.max_n: %d\n", pll_lim->vco2.max_n);
4554 NV_DEBUG(dev, "pll.vco2.min_m: %d\n", pll_lim->vco2.min_m);
4555 NV_DEBUG(dev, "pll.vco2.max_m: %d\n", pll_lim->vco2.max_m);
4556 }
4557 if (!pll_lim->max_p) {
4558 NV_DEBUG(dev, "pll.max_log2p: %d\n", pll_lim->max_log2p);
4559 NV_DEBUG(dev, "pll.log2p_bias: %d\n", pll_lim->log2p_bias);
4560 } else {
4561 NV_DEBUG(dev, "pll.min_p: %d\n", pll_lim->min_p);
4562 NV_DEBUG(dev, "pll.max_p: %d\n", pll_lim->max_p);
4563 }
4564 NV_DEBUG(dev, "pll.refclk: %d\n", pll_lim->refclk);
6ee73861
BS		 4565
4566 return 0;
4567}
4568
4569static void parse_bios_version(struct drm_device *dev, struct nvbios *bios, uint16_t offset)
4570{
4571 /*
4572 * offset + 0 (8 bits): Micro version
4573 * offset + 1 (8 bits): Minor version
4574 * offset + 2 (8 bits): Chip version
4575 * offset + 3 (8 bits): Major version
4576 */
4577
4578 bios->major_version = bios->data[offset + 3];
04a39c57 4579 bios->chip_version = bios->data[offset + 2];
6ee73861
BS		 4580 NV_TRACE(dev, "Bios version %02x.%02x.%02x.%02x\n",
4581 bios->data[offset + 3], bios->data[offset + 2],
4582 bios->data[offset + 1], bios->data[offset]);
4583}
4584
4585static void parse_script_table_pointers(struct nvbios *bios, uint16_t offset)
4586{
4587 /*
4588 * Parses the init table segment for pointers used in script execution.
4589 *
4590 * offset + 0 (16 bits): init script tables pointer
4591 * offset + 2 (16 bits): macro index table pointer
4592 * offset + 4 (16 bits): macro table pointer
4593 * offset + 6 (16 bits): condition table pointer
4594 * offset + 8 (16 bits): io condition table pointer
4595 * offset + 10 (16 bits): io flag condition table pointer
4596 * offset + 12 (16 bits): init function table pointer
4597 */
4598
4599 bios->init_script_tbls_ptr = ROM16(bios->data[offset]);
4600 bios->macro_index_tbl_ptr = ROM16(bios->data[offset + 2]);
4601 bios->macro_tbl_ptr = ROM16(bios->data[offset + 4]);
4602 bios->condition_tbl_ptr = ROM16(bios->data[offset + 6]);
4603 bios->io_condition_tbl_ptr = ROM16(bios->data[offset + 8]);
4604 bios->io_flag_condition_tbl_ptr = ROM16(bios->data[offset + 10]);
4605 bios->init_function_tbl_ptr = ROM16(bios->data[offset + 12]);
4606}
4607
4608static int parse_bit_A_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4609{
4610 /*
4611 * Parses the load detect values for g80 cards.
4612 *
4613 * offset + 0 (16 bits): loadval table pointer
4614 */
4615
4616 uint16_t load_table_ptr;
4617 uint8_t version, headerlen, entrylen, num_entries;
4618
4619 if (bitentry->length != 3) {
4620 NV_ERROR(dev, "Do not understand BIT A table\n");
4621 return -EINVAL;
4622 }
4623
4624 load_table_ptr = ROM16(bios->data[bitentry->offset]);
4625
4626 if (load_table_ptr == 0x0) {
4627 NV_ERROR(dev, "Pointer to BIT loadval table invalid\n");
4628 return -EINVAL;
4629 }
4630
4631 version = bios->data[load_table_ptr];
4632
4633 if (version != 0x10) {
4634 NV_ERROR(dev, "BIT loadval table version %d.%d not supported\n",
4635 version >> 4, version & 0xF);
4636 return -ENOSYS;
4637 }
4638
4639 headerlen = bios->data[load_table_ptr + 1];
4640 entrylen = bios->data[load_table_ptr + 2];
4641 num_entries = bios->data[load_table_ptr + 3];
4642
4643 if (headerlen != 4 || entrylen != 4 || num_entries != 2) {
4644 NV_ERROR(dev, "Do not understand BIT loadval table\n");
4645 return -EINVAL;
4646 }
4647
4648 /* First entry is normal dac, 2nd tv-out perhaps? */
04a39c57 4649 bios->dactestval = ROM32(bios->data[load_table_ptr + headerlen]) & 0x3ff;
6ee73861
BS		 4650
4651 return 0;
4652}
4653
4654static int parse_bit_C_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4655{
4656 /*
4657 * offset + 8 (16 bits): PLL limits table pointer
4658 *
4659 * There's more in here, but that's unknown.
4660 */
4661
4662 if (bitentry->length < 10) {
4663 NV_ERROR(dev, "Do not understand BIT C table\n");
4664 return -EINVAL;
4665 }
4666
4667 bios->pll_limit_tbl_ptr = ROM16(bios->data[bitentry->offset + 8]);
4668
4669 return 0;
4670}
4671
4672static int parse_bit_display_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4673{
4674 /*
4675 * Parses the flat panel table segment that the bit entry points to.
4676 * Starting at bitentry->offset:
4677 *
4678 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte
4679 * records beginning with a freq.
4680 * offset + 2 (16 bits): mode table pointer
4681 */
4682
4683 if (bitentry->length != 4) {
4684 NV_ERROR(dev, "Do not understand BIT display table\n");
4685 return -EINVAL;
4686 }
4687
4688 bios->fp.fptablepointer = ROM16(bios->data[bitentry->offset + 2]);
4689
4690 return 0;
4691}
4692
4693static int parse_bit_init_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4694{
4695 /*
4696 * Parses the init table segment that the bit entry points to.
4697 *
4698 * See parse_script_table_pointers for layout
4699 */
4700
4701 if (bitentry->length < 14) {
4702 NV_ERROR(dev, "Do not understand init table\n");
4703 return -EINVAL;
4704 }
4705
4706 parse_script_table_pointers(bios, bitentry->offset);
4707
4708 if (bitentry->length >= 16)
4709 bios->some_script_ptr = ROM16(bios->data[bitentry->offset + 14]);
4710 if (bitentry->length >= 18)
4711 bios->init96_tbl_ptr = ROM16(bios->data[bitentry->offset + 16]);
4712
4713 return 0;
4714}
4715
4716static int parse_bit_i_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4717{
4718 /*
4719 * BIT 'i' (info?) table
4720 *
4721 * offset + 0 (32 bits): BIOS version dword (as in B table)
4722 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?)
4723 * offset + 13 (16 bits): pointer to table containing DAC load
4724 * detection comparison values
4725 *
4726 * There's other things in the table, purpose unknown
4727 */
4728
4729 uint16_t daccmpoffset;
4730 uint8_t dacver, dacheaderlen;
4731
4732 if (bitentry->length < 6) {
4733 NV_ERROR(dev, "BIT i table too short for needed information\n");
4734 return -EINVAL;
4735 }
4736
4737 parse_bios_version(dev, bios, bitentry->offset);
4738
4739 /*
4740 * bit 4 seems to indicate a mobile bios (doesn't suffer from BMP's
4741 * Quadro identity crisis), other bits possibly as for BMP feature byte
4742 */
4743 bios->feature_byte = bios->data[bitentry->offset + 5];
4744 bios->is_mobile = bios->feature_byte & FEATURE_MOBILE;
4745
4746 if (bitentry->length < 15) {
4747 NV_WARN(dev, "BIT i table not long enough for DAC load "
4748 "detection comparison table\n");
4749 return -EINVAL;
4750 }
4751
4752 daccmpoffset = ROM16(bios->data[bitentry->offset + 13]);
4753
4754 /* doesn't exist on g80 */
4755 if (!daccmpoffset)
4756 return 0;
4757
4758 /*
4759 * The first value in the table, following the header, is the
4760 * comparison value, the second entry is a comparison value for
4761 * TV load detection.
4762 */
4763
4764 dacver = bios->data[daccmpoffset];
4765 dacheaderlen = bios->data[daccmpoffset + 1];
4766
4767 if (dacver != 0x00 && dacver != 0x10) {
4768 NV_WARN(dev, "DAC load detection comparison table version "
4769 "%d.%d not known\n", dacver >> 4, dacver & 0xf);
4770 return -ENOSYS;
4771 }
4772
04a39c57
BS		 4773 bios->dactestval = ROM32(bios->data[daccmpoffset + dacheaderlen]);
4774 bios->tvdactestval = ROM32(bios->data[daccmpoffset + dacheaderlen + 4]);
6ee73861
BS		 4775
4776 return 0;
4777}
4778
4779static int parse_bit_lvds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4780{
4781 /*
4782 * Parses the LVDS table segment that the bit entry points to.
4783 * Starting at bitentry->offset:
4784 *
4785 * offset + 0 (16 bits): LVDS strap xlate table pointer
4786 */
4787
4788 if (bitentry->length != 2) {
4789 NV_ERROR(dev, "Do not understand BIT LVDS table\n");
4790 return -EINVAL;
4791 }
4792
4793 /*
4794 * No idea if it's still called the LVDS manufacturer table, but
4795 * the concept's close enough.
4796 */
4797 bios->fp.lvdsmanufacturerpointer = ROM16(bios->data[bitentry->offset]);
4798
4799 return 0;
4800}
4801
4802static int
4803parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios,
4804 struct bit_entry *bitentry)
4805{
4806 /*
4807 * offset + 2 (8 bits): number of options in an
4808 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set
4809 * offset + 3 (16 bits): pointer to strap xlate table for RAM
4810 * restrict option selection
4811 *
4812 * There's a bunch of bits in this table other than the RAM restrict
4813 * stuff that we don't use - their use currently unknown
4814 */
4815
6ee73861
BS		 4816 /*
4817 * Older bios versions don't have a sufficiently long table for
4818 * what we want
4819 */
4820 if (bitentry->length < 0x5)
4821 return 0;
4822
4823 if (bitentry->id[1] < 2) {
37383650
MK		 4824 bios->ram_restrict_group_count = bios->data[bitentry->offset + 2];
4825 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]);
6ee73861 4826 } else {
37383650
MK		 4827 bios->ram_restrict_group_count = bios->data[bitentry->offset + 0];
4828 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 1]);
6ee73861
BS		 4829 }
4830
6ee73861
BS		 4831 return 0;
4832}
4833
4834static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4835{
4836 /*
4837 * Parses the pointer to the TMDS table
4838 *
4839 * Starting at bitentry->offset:
4840 *
4841 * offset + 0 (16 bits): TMDS table pointer
4842 *
4843 * The TMDS table is typically found just before the DCB table, with a
4844 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being
4845 * length?)
4846 *
4847 * At offset +7 is a pointer to a script, which I don't know how to
4848 * run yet.
4849 * At offset +9 is a pointer to another script, likewise
4850 * Offset +11 has a pointer to a table where the first word is a pxclk
4851 * frequency and the second word a pointer to a script, which should be
4852 * run if the comparison pxclk frequency is less than the pxclk desired.
4853 * This repeats for decreasing comparison frequencies
4854 * Offset +13 has a pointer to a similar table
4855 * The selection of table (and possibly +7/+9 script) is dictated by
4856 * "or" from the DCB.
4857 */
4858
4859 uint16_t tmdstableptr, script1, script2;
4860
4861 if (bitentry->length != 2) {
4862 NV_ERROR(dev, "Do not understand BIT TMDS table\n");
4863 return -EINVAL;
4864 }
4865
4866 tmdstableptr = ROM16(bios->data[bitentry->offset]);
4867
4868 if (tmdstableptr == 0x0) {
4869 NV_ERROR(dev, "Pointer to TMDS table invalid\n");
4870 return -EINVAL;
4871 }
4872
4873 /* nv50+ has v2.0, but we don't parse it atm */
4874 if (bios->data[tmdstableptr] != 0x11) {
4875 NV_WARN(dev,
4876 "TMDS table revision %d.%d not currently supported\n",
4877 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf);
4878 return -ENOSYS;
4879 }
4880
4881 /*
4882 * These two scripts are odd: they don't seem to get run even when
4883 * they are not stubbed.
4884 */
4885 script1 = ROM16(bios->data[tmdstableptr + 7]);
4886 script2 = ROM16(bios->data[tmdstableptr + 9]);
4887 if (bios->data[script1] != 'q' || bios->data[script2] != 'q')
4888 NV_WARN(dev, "TMDS table script pointers not stubbed\n");
4889
4890 bios->tmds.output0_script_ptr = ROM16(bios->data[tmdstableptr + 11]);
4891 bios->tmds.output1_script_ptr = ROM16(bios->data[tmdstableptr + 13]);
4892
4893 return 0;
4894}
4895
4896static int
4897parse_bit_U_tbl_entry(struct drm_device *dev, struct nvbios *bios,
4898 struct bit_entry *bitentry)
4899{
4900 /*
4901 * Parses the pointer to the G80 output script tables
4902 *
4903 * Starting at bitentry->offset:
4904 *
4905 * offset + 0 (16 bits): output script table pointer
4906 */
4907
4908 uint16_t outputscripttableptr;
4909
4910 if (bitentry->length != 3) {
4911 NV_ERROR(dev, "Do not understand BIT U table\n");
4912 return -EINVAL;
4913 }
4914
4915 outputscripttableptr = ROM16(bios->data[bitentry->offset]);
4916 bios->display.script_table_ptr = outputscripttableptr;
4917 return 0;
4918}
4919
4920static int
4921parse_bit_displayport_tbl_entry(struct drm_device *dev, struct nvbios *bios,
4922 struct bit_entry *bitentry)
4923{
4924 bios->display.dp_table_ptr = ROM16(bios->data[bitentry->offset]);
4925 return 0;
4926}
4927
4928struct bit_table {
4929 const char id;
4930 int (* const parse_fn)(struct drm_device *, struct nvbios *, struct bit_entry *);
4931};
4932
4933#define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry })
4934
4935static int
4936parse_bit_table(struct nvbios *bios, const uint16_t bitoffset,
4937 struct bit_table *table)
4938{
4939 struct drm_device *dev = bios->dev;
4940 uint8_t maxentries = bios->data[bitoffset + 4];
4941 int i, offset;
4942 struct bit_entry bitentry;
4943
4944 for (i = 0, offset = bitoffset + 6; i < maxentries; i++, offset += 6) {
4945 bitentry.id[0] = bios->data[offset];
4946
4947 if (bitentry.id[0] != table->id)
4948 continue;
4949
4950 bitentry.id[1] = bios->data[offset + 1];
4951 bitentry.length = ROM16(bios->data[offset + 2]);
4952 bitentry.offset = ROM16(bios->data[offset + 4]);
4953
4954 return table->parse_fn(dev, bios, &bitentry);
4955 }
4956
4957 NV_INFO(dev, "BIT table '%c' not found\n", table->id);
4958 return -ENOSYS;
4959}
4960
4961static int
4962parse_bit_structure(struct nvbios *bios, const uint16_t bitoffset)
4963{
4964 int ret;
4965
4966 /*
4967 * The only restriction on parsing order currently is having 'i' first
4968 * for use of bios->*_version or bios->feature_byte while parsing;
4969 * functions shouldn't be actually *doing* anything apart from pulling
4970 * data from the image into the bios struct, thus no interdependencies
4971 */
4972 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('i', i));
4973 if (ret) /* info? */
4974 return ret;
4975 if (bios->major_version >= 0x60) /* g80+ */
4976 parse_bit_table(bios, bitoffset, &BIT_TABLE('A', A));
4977 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('C', C));
4978 if (ret)
4979 return ret;
4980 parse_bit_table(bios, bitoffset, &BIT_TABLE('D', display));
4981 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('I', init));
4982 if (ret)
4983 return ret;
4984 parse_bit_table(bios, bitoffset, &BIT_TABLE('M', M)); /* memory? */
4985 parse_bit_table(bios, bitoffset, &BIT_TABLE('L', lvds));
4986 parse_bit_table(bios, bitoffset, &BIT_TABLE('T', tmds));
4987 parse_bit_table(bios, bitoffset, &BIT_TABLE('U', U));
4988 parse_bit_table(bios, bitoffset, &BIT_TABLE('d', displayport));
4989
4990 return 0;
4991}
4992
4993static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsigned int offset)
4994{
4995 /*
4996 * Parses the BMP structure for useful things, but does not act on them
4997 *
4998 * offset + 5: BMP major version
4999 * offset + 6: BMP minor version
5000 * offset + 9: BMP feature byte
5001 * offset + 10: BCD encoded BIOS version
5002 *
5003 * offset + 18: init script table pointer (for bios versions < 5.10h)
5004 * offset + 20: extra init script table pointer (for bios
5005 * versions < 5.10h)
5006 *
5007 * offset + 24: memory init table pointer (used on early bios versions)
5008 * offset + 26: SDR memory sequencing setup data table
5009 * offset + 28: DDR memory sequencing setup data table
5010 *
5011 * offset + 54: index of I2C CRTC pair to use for CRT output
5012 * offset + 55: index of I2C CRTC pair to use for TV output
5013 * offset + 56: index of I2C CRTC pair to use for flat panel output
5014 * offset + 58: write CRTC index for I2C pair 0
5015 * offset + 59: read CRTC index for I2C pair 0
5016 * offset + 60: write CRTC index for I2C pair 1
5017 * offset + 61: read CRTC index for I2C pair 1
5018 *
5019 * offset + 67: maximum internal PLL frequency (single stage PLL)
5020 * offset + 71: minimum internal PLL frequency (single stage PLL)
5021 *
5022 * offset + 75: script table pointers, as described in
5023 * parse_script_table_pointers
5024 *
5025 * offset + 89: TMDS single link output A table pointer
5026 * offset + 91: TMDS single link output B table pointer
5027 * offset + 95: LVDS single link output A table pointer
5028 * offset + 105: flat panel timings table pointer
5029 * offset + 107: flat panel strapping translation table pointer
5030 * offset + 117: LVDS manufacturer panel config table pointer
5031 * offset + 119: LVDS manufacturer strapping translation table pointer
5032 *
5033 * offset + 142: PLL limits table pointer
5034 *
5035 * offset + 156: minimum pixel clock for LVDS dual link
5036 */
5037
5038 uint8_t *bmp = &bios->data[offset], bmp_version_major, bmp_version_minor;
5039 uint16_t bmplength;
5040 uint16_t legacy_scripts_offset, legacy_i2c_offset;
5041
5042 /* load needed defaults in case we can't parse this info */
7f245b20
BS		 5043 bios->dcb.i2c[0].write = NV_CIO_CRE_DDC_WR__INDEX;
5044 bios->dcb.i2c[0].read = NV_CIO_CRE_DDC_STATUS__INDEX;
5045 bios->dcb.i2c[1].write = NV_CIO_CRE_DDC0_WR__INDEX;
5046 bios->dcb.i2c[1].read = NV_CIO_CRE_DDC0_STATUS__INDEX;
04a39c57 5047 bios->digital_min_front_porch = 0x4b;
6ee73861
BS		 5048 bios->fmaxvco = 256000;
5049 bios->fminvco = 128000;
5050 bios->fp.duallink_transition_clk = 90000;
5051
5052 bmp_version_major = bmp[5];
5053 bmp_version_minor = bmp[6];
5054
5055 NV_TRACE(dev, "BMP version %d.%d\n",
5056 bmp_version_major, bmp_version_minor);
5057
5058 /*
5059 * Make sure that 0x36 is blank and can't be mistaken for a DCB
5060 * pointer on early versions
5061 */
5062 if (bmp_version_major < 5)
5063 *(uint16_t *)&bios->data[0x36] = 0;
5064
5065 /*
5066 * Seems that the minor version was 1 for all major versions prior
5067 * to 5. Version 6 could theoretically exist, but I suspect BIT
5068 * happened instead.
5069 */
5070 if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) {
5071 NV_ERROR(dev, "You have an unsupported BMP version. "
5072 "Please send in your bios\n");
5073 return -ENOSYS;
5074 }
5075
5076 if (bmp_version_major == 0)
5077 /* nothing that's currently useful in this version */
5078 return 0;
5079 else if (bmp_version_major == 1)
5080 bmplength = 44; /* exact for 1.01 */
5081 else if (bmp_version_major == 2)
5082 bmplength = 48; /* exact for 2.01 */
5083 else if (bmp_version_major == 3)
5084 bmplength = 54;
5085 /* guessed - mem init tables added in this version */
5086 else if (bmp_version_major == 4 || bmp_version_minor < 0x1)
5087 /* don't know if 5.0 exists... */
5088 bmplength = 62;
5089 /* guessed - BMP I2C indices added in version 4*/
5090 else if (bmp_version_minor < 0x6)
5091 bmplength = 67; /* exact for 5.01 */
5092 else if (bmp_version_minor < 0x10)
5093 bmplength = 75; /* exact for 5.06 */
5094 else if (bmp_version_minor == 0x10)
5095 bmplength = 89; /* exact for 5.10h */
5096 else if (bmp_version_minor < 0x14)
5097 bmplength = 118; /* exact for 5.11h */
5098 else if (bmp_version_minor < 0x24)
5099 /*
5100 * Not sure of version where pll limits came in;
5101 * certainly exist by 0x24 though.
5102 */
5103 /* length not exact: this is long enough to get lvds members */
5104 bmplength = 123;
5105 else if (bmp_version_minor < 0x27)
5106 /*
5107 * Length not exact: this is long enough to get pll limit
5108 * member
5109 */
5110 bmplength = 144;
5111 else
5112 /*
5113 * Length not exact: this is long enough to get dual link
5114 * transition clock.
5115 */
5116 bmplength = 158;
5117
5118 /* checksum */
5119 if (nv_cksum(bmp, 8)) {
5120 NV_ERROR(dev, "Bad BMP checksum\n");
5121 return -EINVAL;
5122 }
5123
5124 /*
5125 * Bit 4 seems to indicate either a mobile bios or a quadro card --
5126 * mobile behaviour consistent (nv11+), quadro only seen nv18gl-nv36gl
5127 * (not nv10gl), bit 5 that the flat panel tables are present, and
5128 * bit 6 a tv bios.
5129 */
5130 bios->feature_byte = bmp[9];
5131
5132 parse_bios_version(dev, bios, offset + 10);
5133
5134 if (bmp_version_major < 5 || bmp_version_minor < 0x10)
5135 bios->old_style_init = true;
5136 legacy_scripts_offset = 18;
5137 if (bmp_version_major < 2)
5138 legacy_scripts_offset -= 4;
5139 bios->init_script_tbls_ptr = ROM16(bmp[legacy_scripts_offset]);
5140 bios->extra_init_script_tbl_ptr = ROM16(bmp[legacy_scripts_offset + 2]);
5141
5142 if (bmp_version_major > 2) { /* appears in BMP 3 */
5143 bios->legacy.mem_init_tbl_ptr = ROM16(bmp[24]);
5144 bios->legacy.sdr_seq_tbl_ptr = ROM16(bmp[26]);
5145 bios->legacy.ddr_seq_tbl_ptr = ROM16(bmp[28]);
5146 }
5147
5148 legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */
5149 if (bmplength > 61)
5150 legacy_i2c_offset = offset + 54;
5151 bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset];
5152 bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1];
5153 bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2];
7f245b20
BS		 5154 bios->dcb.i2c[0].write = bios->data[legacy_i2c_offset + 4];
5155 bios->dcb.i2c[0].read = bios->data[legacy_i2c_offset + 5];
5156 bios->dcb.i2c[1].write = bios->data[legacy_i2c_offset + 6];
5157 bios->dcb.i2c[1].read = bios->data[legacy_i2c_offset + 7];
6ee73861
BS		 5158
5159 if (bmplength > 74) {
5160 bios->fmaxvco = ROM32(bmp[67]);
5161 bios->fminvco = ROM32(bmp[71]);
5162 }
5163 if (bmplength > 88)
5164 parse_script_table_pointers(bios, offset + 75);
5165 if (bmplength > 94) {
5166 bios->tmds.output0_script_ptr = ROM16(bmp[89]);
5167 bios->tmds.output1_script_ptr = ROM16(bmp[91]);
5168 /*
5169 * Never observed in use with lvds scripts, but is reused for
5170 * 18/24 bit panel interface default for EDID equipped panels
5171 * (if_is_24bit not set directly to avoid any oscillation).
5172 */
5173 bios->legacy.lvds_single_a_script_ptr = ROM16(bmp[95]);
5174 }
5175 if (bmplength > 108) {
5176 bios->fp.fptablepointer = ROM16(bmp[105]);
5177 bios->fp.fpxlatetableptr = ROM16(bmp[107]);
5178 bios->fp.xlatwidth = 1;
5179 }
5180 if (bmplength > 120) {
5181 bios->fp.lvdsmanufacturerpointer = ROM16(bmp[117]);
5182 bios->fp.fpxlatemanufacturertableptr = ROM16(bmp[119]);
5183 }
5184 if (bmplength > 143)
5185 bios->pll_limit_tbl_ptr = ROM16(bmp[142]);
5186
5187 if (bmplength > 157)
5188 bios->fp.duallink_transition_clk = ROM16(bmp[156]) * 10;
5189
5190 return 0;
5191}
5192
5193static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len)
5194{
5195 int i, j;
5196
5197 for (i = 0; i <= (n - len); i++) {
5198 for (j = 0; j < len; j++)
5199 if (data[i + j] != str[j])
5200 break;
5201 if (j == len)
5202 return i;
5203 }
5204
5205 return 0;
5206}
5207
6ee73861
BS		 5208static struct dcb_gpio_entry *
5209new_gpio_entry(struct nvbios *bios)
5210{
7f245b20 5211 struct dcb_gpio_table *gpio = &bios->dcb.gpio;
6ee73861
BS		 5212
5213 return &gpio->entry[gpio->entries++];
5214}
5215
5216struct dcb_gpio_entry *
5217nouveau_bios_gpio_entry(struct drm_device *dev, enum dcb_gpio_tag tag)
5218{
5219 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 5220 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 5221 int i;
5222
7f245b20
BS		 5223 for (i = 0; i < bios->dcb.gpio.entries; i++) {
5224 if (bios->dcb.gpio.entry[i].tag != tag)
6ee73861
BS		 5225 continue;
5226
7f245b20 5227 return &bios->dcb.gpio.entry[i];
6ee73861
BS		 5228 }
5229
5230 return NULL;
5231}
5232
5233static void
5234parse_dcb30_gpio_entry(struct nvbios *bios, uint16_t offset)
5235{
5236 struct dcb_gpio_entry *gpio;
5237 uint16_t ent = ROM16(bios->data[offset]);
5238 uint8_t line = ent & 0x1f,
5239 tag = ent >> 5 & 0x3f,
5240 flags = ent >> 11 & 0x1f;
5241
5242 if (tag == 0x3f)
5243 return;
5244
5245 gpio = new_gpio_entry(bios);
5246
5247 gpio->tag = tag;
5248 gpio->line = line;
5249 gpio->invert = flags != 4;
2535d71c 5250 gpio->entry = ent;
6ee73861
BS		 5251}
5252
5253static void
5254parse_dcb40_gpio_entry(struct nvbios *bios, uint16_t offset)
5255{
02faec09 5256 uint32_t entry = ROM32(bios->data[offset]);
6ee73861 5257 struct dcb_gpio_entry *gpio;
6ee73861 5258
02faec09 5259 if ((entry & 0x0000ff00) == 0x0000ff00)
6ee73861
BS		 5260 return;
5261
5262 gpio = new_gpio_entry(bios);
02faec09
BS		 5263 gpio->tag = (entry & 0x0000ff00) >> 8;
5264 gpio->line = (entry & 0x0000001f) >> 0;
5265 gpio->state_default = (entry & 0x01000000) >> 24;
5266 gpio->state[0] = (entry & 0x18000000) >> 27;
5267 gpio->state[1] = (entry & 0x60000000) >> 29;
5268 gpio->entry = entry;
6ee73861
BS		 5269}
5270
5271static void
5272parse_dcb_gpio_table(struct nvbios *bios)
5273{
5274 struct drm_device *dev = bios->dev;
7f245b20 5275 uint16_t gpio_table_ptr = bios->dcb.gpio_table_ptr;
6ee73861
BS		 5276 uint8_t *gpio_table = &bios->data[gpio_table_ptr];
5277 int header_len = gpio_table[1],
5278 entries = gpio_table[2],
5279 entry_len = gpio_table[3];
5280 void (*parse_entry)(struct nvbios *, uint16_t) = NULL;
5281 int i;
5282
7f245b20 5283 if (bios->dcb.version >= 0x40) {
6ee73861
BS		 5284 if (gpio_table_ptr && entry_len != 4) {
5285 NV_WARN(dev, "Invalid DCB GPIO table entry length.\n");
5286 return;
5287 }
5288
5289 parse_entry = parse_dcb40_gpio_entry;
5290
7f245b20 5291 } else if (bios->dcb.version >= 0x30) {
6ee73861
BS		 5292 if (gpio_table_ptr && entry_len != 2) {
5293 NV_WARN(dev, "Invalid DCB GPIO table entry length.\n");
5294 return;
5295 }
5296
5297 parse_entry = parse_dcb30_gpio_entry;
5298
7f245b20 5299 } else if (bios->dcb.version >= 0x22) {
6ee73861
BS		 5300 /*
5301 * DCBs older than v3.0 don't really have a GPIO
5302 * table, instead they keep some GPIO info at fixed
5303 * locations.
5304 */
5305 uint16_t dcbptr = ROM16(bios->data[0x36]);
5306 uint8_t *tvdac_gpio = &bios->data[dcbptr - 5];
5307
5308 if (tvdac_gpio[0] & 1) {
5309 struct dcb_gpio_entry *gpio = new_gpio_entry(bios);
5310
5311 gpio->tag = DCB_GPIO_TVDAC0;
5312 gpio->line = tvdac_gpio[1] >> 4;
5313 gpio->invert = tvdac_gpio[0] & 2;
5314 }
5315 }
5316
5317 if (!gpio_table_ptr)
5318 return;
5319
5320 if (entries > DCB_MAX_NUM_GPIO_ENTRIES) {
5321 NV_WARN(dev, "Too many entries in the DCB GPIO table.\n");
5322 entries = DCB_MAX_NUM_GPIO_ENTRIES;
5323 }
5324
5325 for (i = 0; i < entries; i++)
5326 parse_entry(bios, gpio_table_ptr + header_len + entry_len * i);
5327}
5328
5329struct dcb_connector_table_entry *
5330nouveau_bios_connector_entry(struct drm_device *dev, int index)
5331{
5332 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 5333 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 5334 struct dcb_connector_table_entry *cte;
5335
7f245b20 5336 if (index >= bios->dcb.connector.entries)
6ee73861
BS		 5337 return NULL;
5338
7f245b20 5339 cte = &bios->dcb.connector.entry[index];
6ee73861
BS		 5340 if (cte->type == 0xff)
5341 return NULL;
5342
5343 return cte;
5344}
5345
f66fa771
BS		 5346static enum dcb_connector_type
5347divine_connector_type(struct nvbios *bios, int index)
5348{
5349 struct dcb_table *dcb = &bios->dcb;
5350 unsigned encoders = 0, type = DCB_CONNECTOR_NONE;
5351 int i;
5352
5353 for (i = 0; i < dcb->entries; i++) {
5354 if (dcb->entry[i].connector == index)
5355 encoders |= (1 << dcb->entry[i].type);
5356 }
5357
5358 if (encoders & (1 << OUTPUT_DP)) {
5359 if (encoders & (1 << OUTPUT_TMDS))
5360 type = DCB_CONNECTOR_DP;
5361 else
5362 type = DCB_CONNECTOR_eDP;
5363 } else
5364 if (encoders & (1 << OUTPUT_TMDS)) {
5365 if (encoders & (1 << OUTPUT_ANALOG))
5366 type = DCB_CONNECTOR_DVI_I;
5367 else
5368 type = DCB_CONNECTOR_DVI_D;
5369 } else
5370 if (encoders & (1 << OUTPUT_ANALOG)) {
5371 type = DCB_CONNECTOR_VGA;
5372 } else
5373 if (encoders & (1 << OUTPUT_LVDS)) {
5374 type = DCB_CONNECTOR_LVDS;
5375 } else
5376 if (encoders & (1 << OUTPUT_TV)) {
5377 type = DCB_CONNECTOR_TV_0;
5378 }
5379
5380 return type;
5381}
5382
53c44c3a
BS		 5383static void
5384apply_dcb_connector_quirks(struct nvbios *bios, int idx)
5385{
5386 struct dcb_connector_table_entry *cte = &bios->dcb.connector.entry[idx];
5387 struct drm_device *dev = bios->dev;
5388
5389 /* Gigabyte NX85T */
5390 if ((dev->pdev->device == 0x0421) &&
5391 (dev->pdev->subsystem_vendor == 0x1458) &&
5392 (dev->pdev->subsystem_device == 0x344c)) {
5393 if (cte->type == DCB_CONNECTOR_HDMI_1)
5394 cte->type = DCB_CONNECTOR_DVI_I;
5395 }
5396}
5397
6ee73861
BS		 5398static void
5399parse_dcb_connector_table(struct nvbios *bios)
5400{
5401 struct drm_device *dev = bios->dev;
7f245b20 5402 struct dcb_connector_table *ct = &bios->dcb.connector;
6ee73861 5403 struct dcb_connector_table_entry *cte;
7f245b20 5404 uint8_t *conntab = &bios->data[bios->dcb.connector_table_ptr];
6ee73861
BS		 5405 uint8_t *entry;
5406 int i;
5407
7f245b20 5408 if (!bios->dcb.connector_table_ptr) {
ef2bb506 5409 NV_DEBUG_KMS(dev, "No DCB connector table present\n");
6ee73861
BS		 5410 return;
5411 }
5412
5413 NV_INFO(dev, "DCB connector table: VHER 0x%02x %d %d %d\n",
5414 conntab[0], conntab[1], conntab[2], conntab[3]);
5415 if ((conntab[0] != 0x30 && conntab[0] != 0x40) ||
5416 (conntab[3] != 2 && conntab[3] != 4)) {
5417 NV_ERROR(dev, " Unknown! Please report.\n");
5418 return;
5419 }
5420
5421 ct->entries = conntab[2];
5422
5423 entry = conntab + conntab[1];
5424 cte = &ct->entry[0];
5425 for (i = 0; i < conntab[2]; i++, entry += conntab[3], cte++) {
d544d623 5426 cte->index = i;
6ee73861
BS		 5427 if (conntab[3] == 2)
5428 cte->entry = ROM16(entry[0]);
5429 else
5430 cte->entry = ROM32(entry[0]);
f66fa771 5431
6ee73861 5432 cte->type = (cte->entry & 0x000000ff) >> 0;
d544d623 5433 cte->index2 = (cte->entry & 0x00000f00) >> 8;
6ee73861
BS		 5434 switch (cte->entry & 0x00033000) {
5435 case 0x00001000:
5436 cte->gpio_tag = 0x07;
5437 break;
5438 case 0x00002000:
5439 cte->gpio_tag = 0x08;
5440 break;
5441 case 0x00010000:
5442 cte->gpio_tag = 0x51;
5443 break;
5444 case 0x00020000:
5445 cte->gpio_tag = 0x52;
5446 break;
5447 default:
5448 cte->gpio_tag = 0xff;
5449 break;
5450 }
5451
5452 if (cte->type == 0xff)
5453 continue;
5454
53c44c3a
BS		 5455 apply_dcb_connector_quirks(bios, i);
5456
6ee73861
BS		 5457 NV_INFO(dev, " %d: 0x%08x: type 0x%02x idx %d tag 0x%02x\n",
5458 i, cte->entry, cte->type, cte->index, cte->gpio_tag);
f66fa771
BS		 5459
5460 /* check for known types, fallback to guessing the type
5461 * from attached encoders if we hit an unknown.
5462 */
5463 switch (cte->type) {
5464 case DCB_CONNECTOR_VGA:
5465 case DCB_CONNECTOR_TV_0:
5466 case DCB_CONNECTOR_TV_1:
5467 case DCB_CONNECTOR_TV_3:
5468 case DCB_CONNECTOR_DVI_I:
5469 case DCB_CONNECTOR_DVI_D:
5470 case DCB_CONNECTOR_LVDS:
5471 case DCB_CONNECTOR_DP:
5472 case DCB_CONNECTOR_eDP:
5473 case DCB_CONNECTOR_HDMI_0:
5474 case DCB_CONNECTOR_HDMI_1:
5475 break;
5476 default:
5477 cte->type = divine_connector_type(bios, cte->index);
da647d5b 5478 NV_WARN(dev, "unknown type, using 0x%02x\n", cte->type);
f66fa771
BS		 5479 break;
5480 }
5481
da647d5b
BS		 5482 if (nouveau_override_conntype) {
5483 int type = divine_connector_type(bios, cte->index);
5484 if (type != cte->type)
5485 NV_WARN(dev, " -> type 0x%02x\n", cte->type);
5486 }
5487
6ee73861
BS		 5488 }
5489}
5490
7f245b20 5491static struct dcb_entry *new_dcb_entry(struct dcb_table *dcb)
6ee73861
BS		 5492{
5493 struct dcb_entry *entry = &dcb->entry[dcb->entries];
5494
5495 memset(entry, 0, sizeof(struct dcb_entry));
5496 entry->index = dcb->entries++;
5497
5498 return entry;
5499}
5500
7f245b20 5501static void fabricate_vga_output(struct dcb_table *dcb, int i2c, int heads)
6ee73861
BS		 5502{
5503 struct dcb_entry *entry = new_dcb_entry(dcb);
5504
5505 entry->type = 0;
5506 entry->i2c_index = i2c;
5507 entry->heads = heads;
5508 entry->location = DCB_LOC_ON_CHIP;
5509 /* "or" mostly unused in early gen crt modesetting, 0 is fine */
5510}
5511
7f245b20 5512static void fabricate_dvi_i_output(struct dcb_table *dcb, bool twoHeads)
6ee73861
BS		 5513{
5514 struct dcb_entry *entry = new_dcb_entry(dcb);
5515
5516 entry->type = 2;
5517 entry->i2c_index = LEGACY_I2C_PANEL;
5518 entry->heads = twoHeads ? 3 : 1;
5519 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */
5520 entry->or = 1; /* means |0x10 gets set on CRE_LCD__INDEX */
5521 entry->duallink_possible = false; /* SiI164 and co. are single link */
5522
5523#if 0
5524 /*
5525 * For dvi-a either crtc probably works, but my card appears to only
5526 * support dvi-d. "nvidia" still attempts to program it for dvi-a,
5527 * doing the full fp output setup (program 0x6808.. fp dimension regs,
5528 * setting 0x680848 to 0x10000111 to enable, maybe setting 0x680880);
5529 * the monitor picks up the mode res ok and lights up, but no pixel
5530 * data appears, so the board manufacturer probably connected up the
5531 * sync lines, but missed the video traces / components
5532 *
5533 * with this introduction, dvi-a left as an exercise for the reader.
5534 */
5535 fabricate_vga_output(dcb, LEGACY_I2C_PANEL, entry->heads);
5536#endif
5537}
5538
7f245b20 5539static void fabricate_tv_output(struct dcb_table *dcb, bool twoHeads)
6ee73861
BS		 5540{
5541 struct dcb_entry *entry = new_dcb_entry(dcb);
5542
5543 entry->type = 1;
5544 entry->i2c_index = LEGACY_I2C_TV;
5545 entry->heads = twoHeads ? 3 : 1;
5546 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */
5547}
5548
5549static bool
7f245b20 5550parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb,
6ee73861
BS		 5551 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
5552{
5553 entry->type = conn & 0xf;
5554 entry->i2c_index = (conn >> 4) & 0xf;
5555 entry->heads = (conn >> 8) & 0xf;
7f245b20 5556 if (dcb->version >= 0x40)
6ee73861
BS		 5557 entry->connector = (conn >> 12) & 0xf;
5558 entry->bus = (conn >> 16) & 0xf;
5559 entry->location = (conn >> 20) & 0x3;
5560 entry->or = (conn >> 24) & 0xf;
6ee73861
BS		 5561
5562 switch (entry->type) {
5563 case OUTPUT_ANALOG:
5564 /*
5565 * Although the rest of a CRT conf dword is usually
5566 * zeros, mac biosen have stuff there so we must mask
5567 */
7f245b20 5568 entry->crtconf.maxfreq = (dcb->version < 0x30) ?
6ee73861
BS		 5569 (conf & 0xffff) * 10 :
5570 (conf & 0xff) * 10000;
5571 break;
5572 case OUTPUT_LVDS:
5573 {
5574 uint32_t mask;
5575 if (conf & 0x1)
5576 entry->lvdsconf.use_straps_for_mode = true;
7f245b20 5577 if (dcb->version < 0x22) {
6ee73861
BS		 5578 mask = ~0xd;
5579 /*
5580 * The laptop in bug 14567 lies and claims to not use
5581 * straps when it does, so assume all DCB 2.0 laptops
5582 * use straps, until a broken EDID using one is produced
5583 */
5584 entry->lvdsconf.use_straps_for_mode = true;
5585 /*
5586 * Both 0x4 and 0x8 show up in v2.0 tables; assume they
5587 * mean the same thing (probably wrong, but might work)
5588 */
5589 if (conf & 0x4 || conf & 0x8)
5590 entry->lvdsconf.use_power_scripts = true;
5591 } else {
5592 mask = ~0x5;
5593 if (conf & 0x4)
5594 entry->lvdsconf.use_power_scripts = true;
5595 }
5596 if (conf & mask) {
5597 /*
5598 * Until we even try to use these on G8x, it's
5599 * useless reporting unknown bits. They all are.
5600 */
7f245b20 5601 if (dcb->version >= 0x40)
6ee73861
BS		 5602 break;
5603
5604 NV_ERROR(dev, "Unknown LVDS configuration bits, "
5605 "please report\n");
5606 }
5607 break;
5608 }
5609 case OUTPUT_TV:
5610 {
7f245b20 5611 if (dcb->version >= 0x30)
6ee73861
BS		 5612 entry->tvconf.has_component_output = conf & (0x8 << 4);
5613 else
5614 entry->tvconf.has_component_output = false;
5615
5616 break;
5617 }
5618 case OUTPUT_DP:
5619 entry->dpconf.sor.link = (conf & 0x00000030) >> 4;
5620 entry->dpconf.link_bw = (conf & 0x00e00000) >> 21;
5621 switch ((conf & 0x0f000000) >> 24) {
5622 case 0xf:
5623 entry->dpconf.link_nr = 4;
5624 break;
5625 case 0x3:
5626 entry->dpconf.link_nr = 2;
5627 break;
5628 default:
5629 entry->dpconf.link_nr = 1;
5630 break;
5631 }
5632 break;
5633 case OUTPUT_TMDS:
5634 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4;
5635 break;
5636 case 0xe:
5637 /* weird g80 mobile type that "nv" treats as a terminator */
7f245b20 5638 dcb->entries--;
6ee73861 5639 return false;
e7cc51c5
BS		 5640 default:
5641 break;
6ee73861
BS		 5642 }
5643
23484874
BS		 5644 if (dcb->version < 0x40) {
5645 /* Normal entries consist of a single bit, but dual link has
5646 * the next most significant bit set too
5647 */
5648 entry->duallink_possible =
5649 ((1 << (ffs(entry->or) - 1)) * 3 == entry->or);
5650 } else {
5651 entry->duallink_possible = (entry->sorconf.link == 3);
5652 }
5653
6ee73861
BS		 5654 /* unsure what DCB version introduces this, 3.0? */
5655 if (conf & 0x100000)
5656 entry->i2c_upper_default = true;
5657
5658 return true;
5659}
5660
5661static bool
7f245b20 5662parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb,
6ee73861
BS		 5663 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
5664{
b0d2de86
BS		 5665 switch (conn & 0x0000000f) {
5666 case 0:
5667 entry->type = OUTPUT_ANALOG;
5668 break;
5669 case 1:
5670 entry->type = OUTPUT_TV;
5671 break;
5672 case 2:
5673 case 3:
6ee73861 5674 entry->type = OUTPUT_LVDS;
b0d2de86
BS		 5675 break;
5676 case 4:
5677 switch ((conn & 0x000000f0) >> 4) {
5678 case 0:
6ee73861 5679 entry->type = OUTPUT_TMDS;
b0d2de86
BS		 5680 break;
5681 case 1:
5682 entry->type = OUTPUT_LVDS;
5683 break;
5684 default:
5685 NV_ERROR(dev, "Unknown DCB subtype 4/%d\n",
5686 (conn & 0x000000f0) >> 4);
5687 return false;
5688 }
5689 break;
5690 default:
5691 NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f);
5692 return false;
6ee73861 5693 }
b0d2de86
BS		 5694
5695 entry->i2c_index = (conn & 0x0003c000) >> 14;
5696 entry->heads = ((conn & 0x001c0000) >> 18) + 1;
5697 entry->or = entry->heads; /* same as heads, hopefully safe enough */
5698 entry->location = (conn & 0x01e00000) >> 21;
5699 entry->bus = (conn & 0x0e000000) >> 25;
6ee73861
BS		 5700 entry->duallink_possible = false;
5701
5702 switch (entry->type) {
5703 case OUTPUT_ANALOG:
5704 entry->crtconf.maxfreq = (conf & 0xffff) * 10;
5705 break;
b0d2de86
BS		 5706 case OUTPUT_TV:
5707 entry->tvconf.has_component_output = false;
6ee73861
BS		 5708 break;
5709 case OUTPUT_TMDS:
5710 /*
5711 * Invent a DVI-A output, by copying the fields of the DVI-D
5712 * output; reported to work by math_b on an NV20(!).
5713 */
5714 fabricate_vga_output(dcb, entry->i2c_index, entry->heads);
5715 break;
b0d2de86
BS		 5716 case OUTPUT_LVDS:
5717 if ((conn & 0x00003f00) != 0x10)
5718 entry->lvdsconf.use_straps_for_mode = true;
5719 entry->lvdsconf.use_power_scripts = true;
5720 break;
5721 default:
6ee73861
BS		 5722 break;
5723 }
5724
5725 return true;
5726}
5727
7f245b20 5728static bool parse_dcb_entry(struct drm_device *dev, struct dcb_table *dcb,
6ee73861
BS		 5729 uint32_t conn, uint32_t conf)
5730{
7f245b20 5731 struct dcb_entry *entry = new_dcb_entry(dcb);
6ee73861
BS		 5732 bool ret;
5733
7f245b20
BS		 5734 if (dcb->version >= 0x20)
5735 ret = parse_dcb20_entry(dev, dcb, conn, conf, entry);
6ee73861 5736 else
7f245b20 5737 ret = parse_dcb15_entry(dev, dcb, conn, conf, entry);
6ee73861
BS		 5738 if (!ret)
5739 return ret;
5740
7f245b20
BS		 5741 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table,
5742 entry->i2c_index, &dcb->i2c[entry->i2c_index]);
6ee73861
BS		 5743
5744 return true;
5745}
5746
5747static
7f245b20 5748void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb)
6ee73861
BS		 5749{
5750 /*
5751 * DCB v2.0 lists each output combination separately.
5752 * Here we merge compatible entries to have fewer outputs, with
5753 * more options
5754 */
5755
5756 int i, newentries = 0;
5757
5758 for (i = 0; i < dcb->entries; i++) {
5759 struct dcb_entry *ient = &dcb->entry[i];
5760 int j;
5761
5762 for (j = i + 1; j < dcb->entries; j++) {
5763 struct dcb_entry *jent = &dcb->entry[j];
5764
5765 if (jent->type == 100) /* already merged entry */
5766 continue;
5767
5768 /* merge heads field when all other fields the same */
5769 if (jent->i2c_index == ient->i2c_index &&
5770 jent->type == ient->type &&
5771 jent->location == ient->location &&
5772 jent->or == ient->or) {
5773 NV_TRACE(dev, "Merging DCB entries %d and %d\n",
5774 i, j);
5775 ient->heads |= jent->heads;
5776 jent->type = 100; /* dummy value */
5777 }
5778 }
5779 }
5780
5781 /* Compact entries merged into others out of dcb */
5782 for (i = 0; i < dcb->entries; i++) {
5783 if (dcb->entry[i].type == 100)
5784 continue;
5785
5786 if (newentries != i) {
5787 dcb->entry[newentries] = dcb->entry[i];
5788 dcb->entry[newentries].index = newentries;
5789 }
5790 newentries++;
5791 }
5792
5793 dcb->entries = newentries;
5794}
5795
ed42f824
BS		 5796static int
5797parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool twoHeads)
6ee73861 5798{
ed42f824 5799 struct drm_nouveau_private *dev_priv = dev->dev_private;
7f245b20 5800 struct dcb_table *dcb = &bios->dcb;
ed42f824 5801 uint16_t dcbptr = 0, i2ctabptr = 0;
6ee73861
BS		 5802 uint8_t *dcbtable;
5803 uint8_t headerlen = 0x4, entries = DCB_MAX_NUM_ENTRIES;
5804 bool configblock = true;
5805 int recordlength = 8, confofs = 4;
5806 int i;
5807
6ee73861 5808 /* get the offset from 0x36 */
ed42f824
BS		 5809 if (dev_priv->card_type > NV_04) {
5810 dcbptr = ROM16(bios->data[0x36]);
5811 if (dcbptr == 0x0000)
5812 NV_WARN(dev, "No output data (DCB) found in BIOS\n");
5813 }
6ee73861 5814
ed42f824 5815 /* this situation likely means a really old card, pre DCB */
6ee73861 5816 if (dcbptr == 0x0) {
ed42f824 5817 NV_INFO(dev, "Assuming a CRT output exists\n");
6ee73861
BS		 5818 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1);
5819
ed42f824 5820 if (nv04_tv_identify(dev, bios->legacy.i2c_indices.tv) >= 0)
6ee73861
BS		 5821 fabricate_tv_output(dcb, twoHeads);
5822
5823 return 0;
5824 }
5825
5826 dcbtable = &bios->data[dcbptr];
5827
5828 /* get DCB version */
7f245b20 5829 dcb->version = dcbtable[0];
6ee73861 5830 NV_TRACE(dev, "Found Display Configuration Block version %d.%d\n",
7f245b20 5831 dcb->version >> 4, dcb->version & 0xf);
6ee73861 5832
7f245b20 5833 if (dcb->version >= 0x20) { /* NV17+ */
6ee73861
BS		 5834 uint32_t sig;
5835
7f245b20 5836 if (dcb->version >= 0x30) { /* NV40+ */
6ee73861
BS		 5837 headerlen = dcbtable[1];
5838 entries = dcbtable[2];
5839 recordlength = dcbtable[3];
5840 i2ctabptr = ROM16(dcbtable[4]);
5841 sig = ROM32(dcbtable[6]);
7f245b20
BS		 5842 dcb->gpio_table_ptr = ROM16(dcbtable[10]);
5843 dcb->connector_table_ptr = ROM16(dcbtable[20]);
6ee73861
BS		 5844 } else {
5845 i2ctabptr = ROM16(dcbtable[2]);
5846 sig = ROM32(dcbtable[4]);
5847 headerlen = 8;
5848 }
5849
5850 if (sig != 0x4edcbdcb) {
5851 NV_ERROR(dev, "Bad Display Configuration Block "
5852 "signature (%08X)\n", sig);
5853 return -EINVAL;
5854 }
7f245b20 5855 } else if (dcb->version >= 0x15) { /* some NV11 and NV20 */
6ee73861
BS		 5856 char sig[8] = { 0 };
5857
5858 strncpy(sig, (char *)&dcbtable[-7], 7);
5859 i2ctabptr = ROM16(dcbtable[2]);
5860 recordlength = 10;
5861 confofs = 6;
5862
5863 if (strcmp(sig, "DEV_REC")) {
5864 NV_ERROR(dev, "Bad Display Configuration Block "
5865 "signature (%s)\n", sig);
5866 return -EINVAL;
5867 }
5868 } else {
5869 /*
5870 * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but always
5871 * has the same single (crt) entry, even when tv-out present, so
5872 * the conclusion is this version cannot really be used.
5873 * v1.2 tables (some NV6/10, and NV15+) normally have the same
5874 * 5 entries, which are not specific to the card and so no use.
5875 * v1.2 does have an I2C table that read_dcb_i2c_table can
5876 * handle, but cards exist (nv11 in #14821) with a bad i2c table
5877 * pointer, so use the indices parsed in parse_bmp_structure.
5878 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful
5879 */
5880 NV_TRACEWARN(dev, "No useful information in BIOS output table; "
5881 "adding all possible outputs\n");
5882 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1);
5883
5884 /*
5885 * Attempt to detect TV before DVI because the test
5886 * for the former is more accurate and it rules the
5887 * latter out.
5888 */
5889 if (nv04_tv_identify(dev,
5890 bios->legacy.i2c_indices.tv) >= 0)
5891 fabricate_tv_output(dcb, twoHeads);
5892
5893 else if (bios->tmds.output0_script_ptr ||
5894 bios->tmds.output1_script_ptr)
5895 fabricate_dvi_i_output(dcb, twoHeads);
5896
5897 return 0;
5898 }
5899
5900 if (!i2ctabptr)
5901 NV_WARN(dev, "No pointer to DCB I2C port table\n");
5902 else {
7f245b20
BS		 5903 dcb->i2c_table = &bios->data[i2ctabptr];
5904 if (dcb->version >= 0x30)
5905 dcb->i2c_default_indices = dcb->i2c_table[4];
6ee73861
BS		 5906 }
5907
6ee73861
BS		 5908 if (entries > DCB_MAX_NUM_ENTRIES)
5909 entries = DCB_MAX_NUM_ENTRIES;
5910
5911 for (i = 0; i < entries; i++) {
5912 uint32_t connection, config = 0;
5913
5914 connection = ROM32(dcbtable[headerlen + recordlength * i]);
5915 if (configblock)
5916 config = ROM32(dcbtable[headerlen + confofs + recordlength * i]);
5917
5918 /* seen on an NV11 with DCB v1.5 */
5919 if (connection == 0x00000000)
5920 break;
5921
5922 /* seen on an NV17 with DCB v2.0 */
5923 if (connection == 0xffffffff)
5924 break;
5925
5926 if ((connection & 0x0000000f) == 0x0000000f)
5927 continue;
5928
5929 NV_TRACEWARN(dev, "Raw DCB entry %d: %08x %08x\n",
5930 dcb->entries, connection, config);
5931
7f245b20 5932 if (!parse_dcb_entry(dev, dcb, connection, config))
6ee73861
BS		 5933 break;
5934 }
5935
5936 /*
5937 * apart for v2.1+ not being known for requiring merging, this
5938 * guarantees dcbent->index is the index of the entry in the rom image
5939 */
7f245b20 5940 if (dcb->version < 0x21)
6ee73861
BS		 5941 merge_like_dcb_entries(dev, dcb);
5942
54abb5dd
BS		 5943 if (!dcb->entries)
5944 return -ENXIO;
5945
5946 parse_dcb_gpio_table(bios);
5947 parse_dcb_connector_table(bios);
5948 return 0;
6ee73861
BS		 5949}
5950
5951static void
5952fixup_legacy_connector(struct nvbios *bios)
5953{
7f245b20 5954 struct dcb_table *dcb = &bios->dcb;
dc5bc4ed 5955 int i, i2c, i2c_conn[DCB_MAX_NUM_I2C_ENTRIES] = { };
6ee73861
BS		 5956
5957 /*
5958 * DCB 3.0 also has the table in most cases, but there are some cards
5959 * where the table is filled with stub entries, and the DCB entriy
5960 * indices are all 0. We don't need the connector indices on pre-G80
5961 * chips (yet?) so limit the use to DCB 4.0 and above.
5962 */
7f245b20 5963 if (dcb->version >= 0x40)
6ee73861
BS		 5964 return;
5965
dc5bc4ed
BS		 5966 dcb->connector.entries = 0;
5967
6ee73861
BS		 5968 /*
5969 * No known connector info before v3.0, so make it up. the rule here
5970 * is: anything on the same i2c bus is considered to be on the same
5971 * connector. any output without an associated i2c bus is assigned
5972 * its own unique connector index.
5973 */
5974 for (i = 0; i < dcb->entries; i++) {
6ee73861
BS		 5975 /*
5976 * Ignore the I2C index for on-chip TV-out, as there
5977 * are cards with bogus values (nv31m in bug 23212),
5978 * and it's otherwise useless.
5979 */
5980 if (dcb->entry[i].type == OUTPUT_TV &&
dc5bc4ed 5981 dcb->entry[i].location == DCB_LOC_ON_CHIP)
6ee73861 5982 dcb->entry[i].i2c_index = 0xf;
dc5bc4ed
BS		 5983 i2c = dcb->entry[i].i2c_index;
5984
5985 if (i2c_conn[i2c]) {
5986 dcb->entry[i].connector = i2c_conn[i2c] - 1;
6ee73861
BS		 5987 continue;
5988 }
5989
dc5bc4ed
BS		 5990 dcb->entry[i].connector = dcb->connector.entries++;
5991 if (i2c != 0xf)
5992 i2c_conn[i2c] = dcb->connector.entries;
6ee73861
BS		 5993 }
5994
dc5bc4ed
BS		 5995 /* Fake the connector table as well as just connector indices */
5996 for (i = 0; i < dcb->connector.entries; i++) {
5997 dcb->connector.entry[i].index = i;
5998 dcb->connector.entry[i].type = divine_connector_type(bios, i);
5999 dcb->connector.entry[i].gpio_tag = 0xff;
6ee73861
BS		 6000 }
6001}
6002
6003static void
6004fixup_legacy_i2c(struct nvbios *bios)
6005{
7f245b20 6006 struct dcb_table *dcb = &bios->dcb;
6ee73861
BS		 6007 int i;
6008
6009 for (i = 0; i < dcb->entries; i++) {
6010 if (dcb->entry[i].i2c_index == LEGACY_I2C_CRT)
6011 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.crt;
6012 if (dcb->entry[i].i2c_index == LEGACY_I2C_PANEL)
6013 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.panel;
6014 if (dcb->entry[i].i2c_index == LEGACY_I2C_TV)
6015 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.tv;
6016 }
6017}
6018
6019static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bios, uint16_t hwsq_offset, int entry)
6020{
6021 /*
6022 * The header following the "HWSQ" signature has the number of entries,
6023 * and the entry size
6024 *
6025 * An entry consists of a dword to write to the sequencer control reg
6026 * (0x00001304), followed by the ucode bytes, written sequentially,
6027 * starting at reg 0x00001400
6028 */
6029
6030 uint8_t bytes_to_write;
6031 uint16_t hwsq_entry_offset;
6032 int i;
6033
6034 if (bios->data[hwsq_offset] <= entry) {
6035 NV_ERROR(dev, "Too few entries in HW sequencer table for "
6036 "requested entry\n");
6037 return -ENOENT;
6038 }
6039
6040 bytes_to_write = bios->data[hwsq_offset + 1];
6041
6042 if (bytes_to_write != 36) {
6043 NV_ERROR(dev, "Unknown HW sequencer entry size\n");
6044 return -EINVAL;
6045 }
6046
6047 NV_TRACE(dev, "Loading NV17 power sequencing microcode\n");
6048
6049 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write;
6050
6051 /* set sequencer control */
6052 bios_wr32(bios, 0x00001304, ROM32(bios->data[hwsq_entry_offset]));
6053 bytes_to_write -= 4;
6054
6055 /* write ucode */
6056 for (i = 0; i < bytes_to_write; i += 4)
6057 bios_wr32(bios, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4]));
6058
6059 /* twiddle NV_PBUS_DEBUG_4 */
6060 bios_wr32(bios, NV_PBUS_DEBUG_4, bios_rd32(bios, NV_PBUS_DEBUG_4) | 0x18);
6061
6062 return 0;
6063}
6064
6065static int load_nv17_hw_sequencer_ucode(struct drm_device *dev,
6066 struct nvbios *bios)
6067{
6068 /*
6069 * BMP based cards, from NV17, need a microcode loading to correctly
6070 * control the GPIO etc for LVDS panels
6071 *
6072 * BIT based cards seem to do this directly in the init scripts
6073 *
6074 * The microcode entries are found by the "HWSQ" signature.
6075 */
6076
6077 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' };
6078 const int sz = sizeof(hwsq_signature);
6079 int hwsq_offset;
6080
6081 hwsq_offset = findstr(bios->data, bios->length, hwsq_signature, sz);
6082 if (!hwsq_offset)
6083 return 0;
6084
6085 /* always use entry 0? */
6086 return load_nv17_hwsq_ucode_entry(dev, bios, hwsq_offset + sz, 0);
6087}
6088
6089uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev)
6090{
6091 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6092 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6093 const uint8_t edid_sig[] = {
6094 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 };
6095 uint16_t offset = 0;
6096 uint16_t newoffset;
6097 int searchlen = NV_PROM_SIZE;
6098
6099 if (bios->fp.edid)
6100 return bios->fp.edid;
6101
6102 while (searchlen) {
6103 newoffset = findstr(&bios->data[offset], searchlen,
6104 edid_sig, 8);
6105 if (!newoffset)
6106 return NULL;
6107 offset += newoffset;
6108 if (!nv_cksum(&bios->data[offset], EDID1_LEN))
6109 break;
6110
6111 searchlen -= offset;
6112 offset++;
6113 }
6114
6115 NV_TRACE(dev, "Found EDID in BIOS\n");
6116
6117 return bios->fp.edid = &bios->data[offset];
6118}
6119
6120void
6121nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table,
6122 struct dcb_entry *dcbent)
6123{
6124 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6125 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6126 struct init_exec iexec = { true, false };
6127
d9184fa9 6128 mutex_lock(&bios->lock);
6ee73861
BS		 6129 bios->display.output = dcbent;
6130 parse_init_table(bios, table, &iexec);
6131 bios->display.output = NULL;
d9184fa9 6132 mutex_unlock(&bios->lock);
6ee73861
BS		 6133}
6134
6135static bool NVInitVBIOS(struct drm_device *dev)
6136{
6137 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6138 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6139
6140 memset(bios, 0, sizeof(struct nvbios));
d9184fa9 6141 mutex_init(&bios->lock);
6ee73861
BS		 6142 bios->dev = dev;
6143
6144 if (!NVShadowVBIOS(dev, bios->data))
6145 return false;
6146
6147 bios->length = NV_PROM_SIZE;
6148 return true;
6149}
6150
6151static int nouveau_parse_vbios_struct(struct drm_device *dev)
6152{
6153 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6154 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6155 const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' };
6156 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 };
6157 int offset;
6158
6159 offset = findstr(bios->data, bios->length,
6160 bit_signature, sizeof(bit_signature));
6161 if (offset) {
6162 NV_TRACE(dev, "BIT BIOS found\n");
6163 return parse_bit_structure(bios, offset + 6);
6164 }
6165
6166 offset = findstr(bios->data, bios->length,
6167 bmp_signature, sizeof(bmp_signature));
6168 if (offset) {
6169 NV_TRACE(dev, "BMP BIOS found\n");
6170 return parse_bmp_structure(dev, bios, offset);
6171 }
6172
6173 NV_ERROR(dev, "No known BIOS signature found\n");
6174 return -ENODEV;
6175}
6176
6177int
6178nouveau_run_vbios_init(struct drm_device *dev)
6179{
6180 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6181 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6182 int i, ret = 0;
6183
6184 NVLockVgaCrtcs(dev, false);
6185 if (nv_two_heads(dev))
6186 NVSetOwner(dev, bios->state.crtchead);
6187
6188 if (bios->major_version < 5) /* BMP only */
6189 load_nv17_hw_sequencer_ucode(dev, bios);
6190
6191 if (bios->execute) {
6192 bios->fp.last_script_invoc = 0;
6193 bios->fp.lvds_init_run = false;
6194 }
6195
6196 parse_init_tables(bios);
6197
6198 /*
6199 * Runs some additional script seen on G8x VBIOSen. The VBIOS'
6200 * parser will run this right after the init tables, the binary
6201 * driver appears to run it at some point later.
6202 */
6203 if (bios->some_script_ptr) {
6204 struct init_exec iexec = {true, false};
6205
6206 NV_INFO(dev, "Parsing VBIOS init table at offset 0x%04X\n",
6207 bios->some_script_ptr);
6208 parse_init_table(bios, bios->some_script_ptr, &iexec);
6209 }
6210
6211 if (dev_priv->card_type >= NV_50) {
7f245b20 6212 for (i = 0; i < bios->dcb.entries; i++) {
6ee73861 6213 nouveau_bios_run_display_table(dev,
7f245b20 6214 &bios->dcb.entry[i],
6ee73861
BS		 6215 0, 0);
6216 }
6217 }
6218
6219 NVLockVgaCrtcs(dev, true);
6220
6221 return ret;
6222}
6223
6224static void
6225nouveau_bios_i2c_devices_takedown(struct drm_device *dev)
6226{
6227 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6228 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6229 struct dcb_i2c_entry *entry;
6230 int i;
6231
7f245b20 6232 entry = &bios->dcb.i2c[0];
6ee73861
BS		 6233 for (i = 0; i < DCB_MAX_NUM_I2C_ENTRIES; i++, entry++)
6234 nouveau_i2c_fini(dev, entry);
6235}
6236
d13102c6
BS		 6237static bool
6238nouveau_bios_posted(struct drm_device *dev)
6239{
6240 struct drm_nouveau_private *dev_priv = dev->dev_private;
6241 bool was_locked;
6242 unsigned htotal;
6243
6244 if (dev_priv->chipset >= NV_50) {
6245 if (NVReadVgaCrtc(dev, 0, 0x00) == 0 &&
6246 NVReadVgaCrtc(dev, 0, 0x1a) == 0)
6247 return false;
6248 return true;
6249 }
6250
6251 was_locked = NVLockVgaCrtcs(dev, false);
6252 htotal = NVReadVgaCrtc(dev, 0, 0x06);
6253 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x01) << 8;
6254 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x20) << 4;
6255 htotal |= (NVReadVgaCrtc(dev, 0, 0x25) & 0x01) << 10;
6256 htotal |= (NVReadVgaCrtc(dev, 0, 0x41) & 0x01) << 11;
6257 NVLockVgaCrtcs(dev, was_locked);
6258 return (htotal != 0);
6259}
6260
6ee73861
BS		 6261int
6262nouveau_bios_init(struct drm_device *dev)
6263{
6264 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6265 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6266 uint32_t saved_nv_pextdev_boot_0;
6267 bool was_locked;
6268 int ret;
6269
6ee73861
BS		 6270 if (!NVInitVBIOS(dev))
6271 return -ENODEV;
6272
6273 ret = nouveau_parse_vbios_struct(dev);
6274 if (ret)
6275 return ret;
6276
6277 ret = parse_dcb_table(dev, bios, nv_two_heads(dev));
6278 if (ret)
6279 return ret;
6280
6281 fixup_legacy_i2c(bios);
6282 fixup_legacy_connector(bios);
6283
6284 if (!bios->major_version) /* we don't run version 0 bios */
6285 return 0;
6286
6287 /* these will need remembering across a suspend */
6288 saved_nv_pextdev_boot_0 = bios_rd32(bios, NV_PEXTDEV_BOOT_0);
6289 bios->state.saved_nv_pfb_cfg0 = bios_rd32(bios, NV_PFB_CFG0);
6290
6291 /* init script execution disabled */
6292 bios->execute = false;
6293
6294 /* ... unless card isn't POSTed already */
d13102c6 6295 if (!nouveau_bios_posted(dev)) {
6ee73861 6296 NV_INFO(dev, "Adaptor not initialised\n");
f50c0b91 6297 if (dev_priv->card_type < NV_40) {
6ee73861
BS		 6298 NV_ERROR(dev, "Unable to POST this chipset\n");
6299 return -ENODEV;
6300 }
6301
6302 NV_INFO(dev, "Running VBIOS init tables\n");
6303 bios->execute = true;
6304 }
6305
6306 bios_wr32(bios, NV_PEXTDEV_BOOT_0, saved_nv_pextdev_boot_0);
6307
6308 ret = nouveau_run_vbios_init(dev);
04a39c57 6309 if (ret)
6ee73861 6310 return ret;
6ee73861
BS		 6311
6312 /* feature_byte on BMP is poor, but init always sets CR4B */
6313 was_locked = NVLockVgaCrtcs(dev, false);
6314 if (bios->major_version < 5)
6315 bios->is_mobile = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_4B) & 0x40;
6316
6317 /* all BIT systems need p_f_m_t for digital_min_front_porch */
6318 if (bios->is_mobile || bios->major_version >= 5)
6319 ret = parse_fp_mode_table(dev, bios);
6320 NVLockVgaCrtcs(dev, was_locked);
6321
6322 /* allow subsequent scripts to execute */
6323 bios->execute = true;
6324
6325 return 0;
6326}
6327
6328void
6329nouveau_bios_takedown(struct drm_device *dev)
6330{
6331 nouveau_bios_i2c_devices_takedown(dev);
6332}
Clone of davem's net-next-2.6 tree