]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/gpu/drm/i915/i915_gem.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: add 'reclaimable' to i915 self-reclaimable page allocations
[net-next-2.6.git] / drivers / gpu / drm / i915 / i915_gem.c
CommitLineData
673a394b
EA		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include "drmP.h"
29#include "drm.h"
30#include "i915_drm.h"
31#include "i915_drv.h"
1c5d22f7 32#include "i915_trace.h"
652c393a 33#include "intel_drv.h"
5a0e3ad6 34#include <linux/slab.h>
673a394b 35#include <linux/swap.h>
79e53945 36#include <linux/pci.h>
673a394b 37
e47c68e9
EA		 38static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
39static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
40static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
e47c68e9
EA		 41static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
42 int write);
43static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
44 uint64_t offset,
45 uint64_t size);
46static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
673a394b 47static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
de151cf6
JB		 48static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
49 unsigned alignment);
de151cf6 50static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
07f73f69 51static int i915_gem_evict_something(struct drm_device *dev, int min_size);
ab5ee576 52static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
71acb5eb
DA		 53static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
54 struct drm_i915_gem_pwrite *args,
55 struct drm_file *file_priv);
673a394b 56
31169714
CW		 57static LIST_HEAD(shrink_list);
58static DEFINE_SPINLOCK(shrink_list_lock);
59
79e53945
JB		 60int i915_gem_do_init(struct drm_device *dev, unsigned long start,
61 unsigned long end)
673a394b
EA		 62{
63 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 64
79e53945
JB		 65 if (start >= end ||
66 (start & (PAGE_SIZE - 1)) != 0 ||
67 (end & (PAGE_SIZE - 1)) != 0) {
673a394b
EA		 68 return -EINVAL;
69 }
70
79e53945
JB		 71 drm_mm_init(&dev_priv->mm.gtt_space, start,
72 end - start);
673a394b 73
79e53945
JB		 74 dev->gtt_total = (uint32_t) (end - start);
75
76 return 0;
77}
673a394b 78
79e53945
JB		 79int
80i915_gem_init_ioctl(struct drm_device *dev, void *data,
81 struct drm_file *file_priv)
82{
83 struct drm_i915_gem_init *args = data;
84 int ret;
85
86 mutex_lock(&dev->struct_mutex);
87 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
673a394b
EA		 88 mutex_unlock(&dev->struct_mutex);
89
79e53945 90 return ret;
673a394b
EA		 91}
92
5a125c3c
EA		 93int
94i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
95 struct drm_file *file_priv)
96{
5a125c3c 97 struct drm_i915_gem_get_aperture *args = data;
5a125c3c
EA		 98
99 if (!(dev->driver->driver_features & DRIVER_GEM))
100 return -ENODEV;
101
102 args->aper_size = dev->gtt_total;
2678d9d6
KP		 103 args->aper_available_size = (args->aper_size -
104 atomic_read(&dev->pin_memory));
5a125c3c
EA		 105
106 return 0;
107}
108
673a394b
EA		 109
110/**
111 * Creates a new mm object and returns a handle to it.
112 */
113int
114i915_gem_create_ioctl(struct drm_device *dev, void *data,
115 struct drm_file *file_priv)
116{
117 struct drm_i915_gem_create *args = data;
118 struct drm_gem_object *obj;
a1a2d1d3
PP		 119 int ret;
120 u32 handle;
673a394b
EA		 121
122 args->size = roundup(args->size, PAGE_SIZE);
123
124 /* Allocate the new object */
ac52bc56 125 obj = i915_gem_alloc_object(dev, args->size);
673a394b
EA		 126 if (obj == NULL)
127 return -ENOMEM;
128
129 ret = drm_gem_handle_create(file_priv, obj, &handle);
bc9025bd 130 drm_gem_object_handle_unreference_unlocked(obj);
673a394b
EA		 131
132 if (ret)
133 return ret;
134
135 args->handle = handle;
136
137 return 0;
138}
139
eb01459f
EA		 140static inline int
141fast_shmem_read(struct page **pages,
142 loff_t page_base, int page_offset,
143 char __user *data,
144 int length)
145{
146 char __iomem *vaddr;
2bc43b5c 147 int unwritten;
eb01459f
EA		 148
149 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
150 if (vaddr == NULL)
151 return -ENOMEM;
2bc43b5c 152 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
eb01459f
EA		 153 kunmap_atomic(vaddr, KM_USER0);
154
2bc43b5c
FM		 155 if (unwritten)
156 return -EFAULT;
157
158 return 0;
eb01459f
EA		 159}
160
280b713b
EA		 161static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
162{
163 drm_i915_private_t *dev_priv = obj->dev->dev_private;
23010e43 164 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
280b713b
EA		 165
166 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
167 obj_priv->tiling_mode != I915_TILING_NONE;
168}
169
99a03df5 170static inline void
40123c1f
EA		 171slow_shmem_copy(struct page *dst_page,
172 int dst_offset,
173 struct page *src_page,
174 int src_offset,
175 int length)
176{
177 char *dst_vaddr, *src_vaddr;
178
99a03df5
CW		 179 dst_vaddr = kmap(dst_page);
180 src_vaddr = kmap(src_page);
40123c1f
EA		 181
182 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
183
99a03df5
CW		 184 kunmap(src_page);
185 kunmap(dst_page);
40123c1f
EA		 186}
187
99a03df5 188static inline void
280b713b
EA		 189slow_shmem_bit17_copy(struct page *gpu_page,
190 int gpu_offset,
191 struct page *cpu_page,
192 int cpu_offset,
193 int length,
194 int is_read)
195{
196 char *gpu_vaddr, *cpu_vaddr;
197
198 /* Use the unswizzled path if this page isn't affected. */
199 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
200 if (is_read)
201 return slow_shmem_copy(cpu_page, cpu_offset,
202 gpu_page, gpu_offset, length);
203 else
204 return slow_shmem_copy(gpu_page, gpu_offset,
205 cpu_page, cpu_offset, length);
206 }
207
99a03df5
CW		 208 gpu_vaddr = kmap(gpu_page);
209 cpu_vaddr = kmap(cpu_page);
280b713b
EA		 210
211 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
212 * XORing with the other bits (A9 for Y, A9 and A10 for X)
213 */
214 while (length > 0) {
215 int cacheline_end = ALIGN(gpu_offset + 1, 64);
216 int this_length = min(cacheline_end - gpu_offset, length);
217 int swizzled_gpu_offset = gpu_offset ^ 64;
218
219 if (is_read) {
220 memcpy(cpu_vaddr + cpu_offset,
221 gpu_vaddr + swizzled_gpu_offset,
222 this_length);
223 } else {
224 memcpy(gpu_vaddr + swizzled_gpu_offset,
225 cpu_vaddr + cpu_offset,
226 this_length);
227 }
228 cpu_offset += this_length;
229 gpu_offset += this_length;
230 length -= this_length;
231 }
232
99a03df5
CW		 233 kunmap(cpu_page);
234 kunmap(gpu_page);
280b713b
EA		 235}
236
eb01459f
EA		 237/**
238 * This is the fast shmem pread path, which attempts to copy_from_user directly
239 * from the backing pages of the object to the user's address space. On a
240 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
241 */
242static int
243i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
244 struct drm_i915_gem_pread *args,
245 struct drm_file *file_priv)
246{
23010e43 247 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
eb01459f
EA		 248 ssize_t remain;
249 loff_t offset, page_base;
250 char __user *user_data;
251 int page_offset, page_length;
252 int ret;
253
254 user_data = (char __user *) (uintptr_t) args->data_ptr;
255 remain = args->size;
256
257 mutex_lock(&dev->struct_mutex);
258
4bdadb97 259 ret = i915_gem_object_get_pages(obj, 0);
eb01459f
EA		 260 if (ret != 0)
261 goto fail_unlock;
262
263 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
264 args->size);
265 if (ret != 0)
266 goto fail_put_pages;
267
23010e43 268 obj_priv = to_intel_bo(obj);
eb01459f
EA		 269 offset = args->offset;
270
271 while (remain > 0) {
272 /* Operation in this page
273 *
274 * page_base = page offset within aperture
275 * page_offset = offset within page
276 * page_length = bytes to copy for this page
277 */
278 page_base = (offset & ~(PAGE_SIZE-1));
279 page_offset = offset & (PAGE_SIZE-1);
280 page_length = remain;
281 if ((page_offset + remain) > PAGE_SIZE)
282 page_length = PAGE_SIZE - page_offset;
283
284 ret = fast_shmem_read(obj_priv->pages,
285 page_base, page_offset,
286 user_data, page_length);
287 if (ret)
288 goto fail_put_pages;
289
290 remain -= page_length;
291 user_data += page_length;
292 offset += page_length;
293 }
294
295fail_put_pages:
296 i915_gem_object_put_pages(obj);
297fail_unlock:
298 mutex_unlock(&dev->struct_mutex);
299
300 return ret;
301}
302
07f73f69
CW		 303static int
304i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
305{
306 int ret;
307
4bdadb97 308 ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
07f73f69
CW		 309
310 /* If we've insufficient memory to map in the pages, attempt
311 * to make some space by throwing out some old buffers.
312 */
313 if (ret == -ENOMEM) {
314 struct drm_device *dev = obj->dev;
07f73f69
CW		 315
316 ret = i915_gem_evict_something(dev, obj->size);
317 if (ret)
318 return ret;
319
4bdadb97 320 ret = i915_gem_object_get_pages(obj, 0);
07f73f69
CW		 321 }
322
323 return ret;
324}
325
eb01459f
EA		 326/**
327 * This is the fallback shmem pread path, which allocates temporary storage
328 * in kernel space to copy_to_user into outside of the struct_mutex, so we
329 * can copy out of the object's backing pages while holding the struct mutex
330 * and not take page faults.
331 */
332static int
333i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
334 struct drm_i915_gem_pread *args,
335 struct drm_file *file_priv)
336{
23010e43 337 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
eb01459f
EA		 338 struct mm_struct *mm = current->mm;
339 struct page **user_pages;
340 ssize_t remain;
341 loff_t offset, pinned_pages, i;
342 loff_t first_data_page, last_data_page, num_pages;
343 int shmem_page_index, shmem_page_offset;
344 int data_page_index, data_page_offset;
345 int page_length;
346 int ret;
347 uint64_t data_ptr = args->data_ptr;
280b713b 348 int do_bit17_swizzling;
eb01459f
EA		 349
350 remain = args->size;
351
352 /* Pin the user pages containing the data. We can't fault while
353 * holding the struct mutex, yet we want to hold it while
354 * dereferencing the user data.
355 */
356 first_data_page = data_ptr / PAGE_SIZE;
357 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
358 num_pages = last_data_page - first_data_page + 1;
359
8e7d2b2c 360 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
eb01459f
EA		 361 if (user_pages == NULL)
362 return -ENOMEM;
363
364 down_read(&mm->mmap_sem);
365 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
e5e9ecde 366 num_pages, 1, 0, user_pages, NULL);
eb01459f
EA		 367 up_read(&mm->mmap_sem);
368 if (pinned_pages < num_pages) {
369 ret = -EFAULT;
370 goto fail_put_user_pages;
371 }
372
280b713b
EA		 373 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
374
eb01459f
EA		 375 mutex_lock(&dev->struct_mutex);
376
07f73f69
CW		 377 ret = i915_gem_object_get_pages_or_evict(obj);
378 if (ret)
eb01459f
EA		 379 goto fail_unlock;
380
381 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
382 args->size);
383 if (ret != 0)
384 goto fail_put_pages;
385
23010e43 386 obj_priv = to_intel_bo(obj);
eb01459f
EA		 387 offset = args->offset;
388
389 while (remain > 0) {
390 /* Operation in this page
391 *
392 * shmem_page_index = page number within shmem file
393 * shmem_page_offset = offset within page in shmem file
394 * data_page_index = page number in get_user_pages return
395 * data_page_offset = offset with data_page_index page.
396 * page_length = bytes to copy for this page
397 */
398 shmem_page_index = offset / PAGE_SIZE;
399 shmem_page_offset = offset & ~PAGE_MASK;
400 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
401 data_page_offset = data_ptr & ~PAGE_MASK;
402
403 page_length = remain;
404 if ((shmem_page_offset + page_length) > PAGE_SIZE)
405 page_length = PAGE_SIZE - shmem_page_offset;
406 if ((data_page_offset + page_length) > PAGE_SIZE)
407 page_length = PAGE_SIZE - data_page_offset;
408
280b713b 409 if (do_bit17_swizzling) {
99a03df5 410 slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
280b713b 411 shmem_page_offset,
99a03df5
CW		 412 user_pages[data_page_index],
413 data_page_offset,
414 page_length,
415 1);
416 } else {
417 slow_shmem_copy(user_pages[data_page_index],
418 data_page_offset,
419 obj_priv->pages[shmem_page_index],
420 shmem_page_offset,
421 page_length);
280b713b 422 }
eb01459f
EA		 423
424 remain -= page_length;
425 data_ptr += page_length;
426 offset += page_length;
427 }
428
429fail_put_pages:
430 i915_gem_object_put_pages(obj);
431fail_unlock:
432 mutex_unlock(&dev->struct_mutex);
433fail_put_user_pages:
434 for (i = 0; i < pinned_pages; i++) {
435 SetPageDirty(user_pages[i]);
436 page_cache_release(user_pages[i]);
437 }
8e7d2b2c 438 drm_free_large(user_pages);
eb01459f
EA		 439
440 return ret;
441}
442
673a394b
EA		 443/**
444 * Reads data from the object referenced by handle.
445 *
446 * On error, the contents of *data are undefined.
447 */
448int
449i915_gem_pread_ioctl(struct drm_device *dev, void *data,
450 struct drm_file *file_priv)
451{
452 struct drm_i915_gem_pread *args = data;
453 struct drm_gem_object *obj;
454 struct drm_i915_gem_object *obj_priv;
673a394b
EA		 455 int ret;
456
457 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
458 if (obj == NULL)
459 return -EBADF;
23010e43 460 obj_priv = to_intel_bo(obj);
673a394b
EA		 461
462 /* Bounds check source.
463 *
464 * XXX: This could use review for overflow issues...
465 */
466 if (args->offset > obj->size || args->size > obj->size ||
467 args->offset + args->size > obj->size) {
bc9025bd 468 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 469 return -EINVAL;
470 }
471
280b713b 472 if (i915_gem_object_needs_bit17_swizzle(obj)) {
eb01459f 473 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
280b713b
EA		 474 } else {
475 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
476 if (ret != 0)
477 ret = i915_gem_shmem_pread_slow(dev, obj, args,
478 file_priv);
479 }
673a394b 480
bc9025bd 481 drm_gem_object_unreference_unlocked(obj);
673a394b 482
eb01459f 483 return ret;
673a394b
EA		 484}
485
0839ccb8
KP		 486/* This is the fast write path which cannot handle
487 * page faults in the source data
9b7530cc 488 */
0839ccb8
KP		 489
490static inline int
491fast_user_write(struct io_mapping *mapping,
492 loff_t page_base, int page_offset,
493 char __user *user_data,
494 int length)
9b7530cc 495{
9b7530cc 496 char *vaddr_atomic;
0839ccb8 497 unsigned long unwritten;
9b7530cc 498
0839ccb8
KP		 499 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
500 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
501 user_data, length);
502 io_mapping_unmap_atomic(vaddr_atomic);
503 if (unwritten)
504 return -EFAULT;
505 return 0;
506}
507
508/* Here's the write path which can sleep for
509 * page faults
510 */
511
ab34c226 512static inline void
3de09aa3
EA		 513slow_kernel_write(struct io_mapping *mapping,
514 loff_t gtt_base, int gtt_offset,
515 struct page *user_page, int user_offset,
516 int length)
0839ccb8 517{
ab34c226
CW		 518 char __iomem *dst_vaddr;
519 char *src_vaddr;
0839ccb8 520
ab34c226
CW		 521 dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
522 src_vaddr = kmap(user_page);
523
524 memcpy_toio(dst_vaddr + gtt_offset,
525 src_vaddr + user_offset,
526 length);
527
528 kunmap(user_page);
529 io_mapping_unmap(dst_vaddr);
9b7530cc
LT		 530}
531
40123c1f
EA		 532static inline int
533fast_shmem_write(struct page **pages,
534 loff_t page_base, int page_offset,
535 char __user *data,
536 int length)
537{
538 char __iomem *vaddr;
d0088775 539 unsigned long unwritten;
40123c1f
EA		 540
541 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
542 if (vaddr == NULL)
543 return -ENOMEM;
d0088775 544 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
40123c1f
EA		 545 kunmap_atomic(vaddr, KM_USER0);
546
d0088775
DA		 547 if (unwritten)
548 return -EFAULT;
40123c1f
EA		 549 return 0;
550}
551
3de09aa3
EA		 552/**
553 * This is the fast pwrite path, where we copy the data directly from the
554 * user into the GTT, uncached.
555 */
673a394b 556static int
3de09aa3
EA		 557i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
558 struct drm_i915_gem_pwrite *args,
559 struct drm_file *file_priv)
673a394b 560{
23010e43 561 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
0839ccb8 562 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 563 ssize_t remain;
0839ccb8 564 loff_t offset, page_base;
673a394b 565 char __user *user_data;
0839ccb8
KP		 566 int page_offset, page_length;
567 int ret;
673a394b
EA		 568
569 user_data = (char __user *) (uintptr_t) args->data_ptr;
570 remain = args->size;
571 if (!access_ok(VERIFY_READ, user_data, remain))
572 return -EFAULT;
573
574
575 mutex_lock(&dev->struct_mutex);
576 ret = i915_gem_object_pin(obj, 0);
577 if (ret) {
578 mutex_unlock(&dev->struct_mutex);
579 return ret;
580 }
2ef7eeaa 581 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
673a394b
EA		 582 if (ret)
583 goto fail;
584
23010e43 585 obj_priv = to_intel_bo(obj);
673a394b 586 offset = obj_priv->gtt_offset + args->offset;
673a394b
EA		 587
588 while (remain > 0) {
589 /* Operation in this page
590 *
0839ccb8
KP		 591 * page_base = page offset within aperture
592 * page_offset = offset within page
593 * page_length = bytes to copy for this page
673a394b 594 */
0839ccb8
KP		 595 page_base = (offset & ~(PAGE_SIZE-1));
596 page_offset = offset & (PAGE_SIZE-1);
597 page_length = remain;
598 if ((page_offset + remain) > PAGE_SIZE)
599 page_length = PAGE_SIZE - page_offset;
600
601 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
602 page_offset, user_data, page_length);
603
604 /* If we get a fault while copying data, then (presumably) our
3de09aa3
EA		 605 * source page isn't available. Return the error and we'll
606 * retry in the slow path.
0839ccb8 607 */
3de09aa3
EA		 608 if (ret)
609 goto fail;
673a394b 610
0839ccb8
KP		 611 remain -= page_length;
612 user_data += page_length;
613 offset += page_length;
673a394b 614 }
673a394b
EA		 615
616fail:
617 i915_gem_object_unpin(obj);
618 mutex_unlock(&dev->struct_mutex);
619
620 return ret;
621}
622
3de09aa3
EA		 623/**
624 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
625 * the memory and maps it using kmap_atomic for copying.
626 *
627 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
628 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
629 */
3043c60c 630static int
3de09aa3
EA		 631i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
632 struct drm_i915_gem_pwrite *args,
633 struct drm_file *file_priv)
673a394b 634{
23010e43 635 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3de09aa3
EA		 636 drm_i915_private_t *dev_priv = dev->dev_private;
637 ssize_t remain;
638 loff_t gtt_page_base, offset;
639 loff_t first_data_page, last_data_page, num_pages;
640 loff_t pinned_pages, i;
641 struct page **user_pages;
642 struct mm_struct *mm = current->mm;
643 int gtt_page_offset, data_page_offset, data_page_index, page_length;
673a394b 644 int ret;
3de09aa3
EA		 645 uint64_t data_ptr = args->data_ptr;
646
647 remain = args->size;
648
649 /* Pin the user pages containing the data. We can't fault while
650 * holding the struct mutex, and all of the pwrite implementations
651 * want to hold it while dereferencing the user data.
652 */
653 first_data_page = data_ptr / PAGE_SIZE;
654 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
655 num_pages = last_data_page - first_data_page + 1;
656
8e7d2b2c 657 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
3de09aa3
EA		 658 if (user_pages == NULL)
659 return -ENOMEM;
660
661 down_read(&mm->mmap_sem);
662 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
663 num_pages, 0, 0, user_pages, NULL);
664 up_read(&mm->mmap_sem);
665 if (pinned_pages < num_pages) {
666 ret = -EFAULT;
667 goto out_unpin_pages;
668 }
673a394b
EA		 669
670 mutex_lock(&dev->struct_mutex);
3de09aa3
EA		 671 ret = i915_gem_object_pin(obj, 0);
672 if (ret)
673 goto out_unlock;
674
675 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
676 if (ret)
677 goto out_unpin_object;
678
23010e43 679 obj_priv = to_intel_bo(obj);
3de09aa3
EA		 680 offset = obj_priv->gtt_offset + args->offset;
681
682 while (remain > 0) {
683 /* Operation in this page
684 *
685 * gtt_page_base = page offset within aperture
686 * gtt_page_offset = offset within page in aperture
687 * data_page_index = page number in get_user_pages return
688 * data_page_offset = offset with data_page_index page.
689 * page_length = bytes to copy for this page
690 */
691 gtt_page_base = offset & PAGE_MASK;
692 gtt_page_offset = offset & ~PAGE_MASK;
693 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
694 data_page_offset = data_ptr & ~PAGE_MASK;
695
696 page_length = remain;
697 if ((gtt_page_offset + page_length) > PAGE_SIZE)
698 page_length = PAGE_SIZE - gtt_page_offset;
699 if ((data_page_offset + page_length) > PAGE_SIZE)
700 page_length = PAGE_SIZE - data_page_offset;
701
ab34c226
CW		 702 slow_kernel_write(dev_priv->mm.gtt_mapping,
703 gtt_page_base, gtt_page_offset,
704 user_pages[data_page_index],
705 data_page_offset,
706 page_length);
3de09aa3
EA		 707
708 remain -= page_length;
709 offset += page_length;
710 data_ptr += page_length;
711 }
712
713out_unpin_object:
714 i915_gem_object_unpin(obj);
715out_unlock:
716 mutex_unlock(&dev->struct_mutex);
717out_unpin_pages:
718 for (i = 0; i < pinned_pages; i++)
719 page_cache_release(user_pages[i]);
8e7d2b2c 720 drm_free_large(user_pages);
3de09aa3
EA		 721
722 return ret;
723}
724
40123c1f
EA		 725/**
726 * This is the fast shmem pwrite path, which attempts to directly
727 * copy_from_user into the kmapped pages backing the object.
728 */
3043c60c 729static int
40123c1f
EA		 730i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
731 struct drm_i915_gem_pwrite *args,
732 struct drm_file *file_priv)
673a394b 733{
23010e43 734 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
40123c1f
EA		 735 ssize_t remain;
736 loff_t offset, page_base;
737 char __user *user_data;
738 int page_offset, page_length;
673a394b 739 int ret;
40123c1f
EA		 740
741 user_data = (char __user *) (uintptr_t) args->data_ptr;
742 remain = args->size;
673a394b
EA		 743
744 mutex_lock(&dev->struct_mutex);
745
4bdadb97 746 ret = i915_gem_object_get_pages(obj, 0);
40123c1f
EA		 747 if (ret != 0)
748 goto fail_unlock;
673a394b 749
e47c68e9 750 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
40123c1f
EA		 751 if (ret != 0)
752 goto fail_put_pages;
753
23010e43 754 obj_priv = to_intel_bo(obj);
40123c1f
EA		 755 offset = args->offset;
756 obj_priv->dirty = 1;
757
758 while (remain > 0) {
759 /* Operation in this page
760 *
761 * page_base = page offset within aperture
762 * page_offset = offset within page
763 * page_length = bytes to copy for this page
764 */
765 page_base = (offset & ~(PAGE_SIZE-1));
766 page_offset = offset & (PAGE_SIZE-1);
767 page_length = remain;
768 if ((page_offset + remain) > PAGE_SIZE)
769 page_length = PAGE_SIZE - page_offset;
770
771 ret = fast_shmem_write(obj_priv->pages,
772 page_base, page_offset,
773 user_data, page_length);
774 if (ret)
775 goto fail_put_pages;
776
777 remain -= page_length;
778 user_data += page_length;
779 offset += page_length;
780 }
781
782fail_put_pages:
783 i915_gem_object_put_pages(obj);
784fail_unlock:
785 mutex_unlock(&dev->struct_mutex);
786
787 return ret;
788}
789
790/**
791 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
792 * the memory and maps it using kmap_atomic for copying.
793 *
794 * This avoids taking mmap_sem for faulting on the user's address while the
795 * struct_mutex is held.
796 */
797static int
798i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
799 struct drm_i915_gem_pwrite *args,
800 struct drm_file *file_priv)
801{
23010e43 802 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
40123c1f
EA		 803 struct mm_struct *mm = current->mm;
804 struct page **user_pages;
805 ssize_t remain;
806 loff_t offset, pinned_pages, i;
807 loff_t first_data_page, last_data_page, num_pages;
808 int shmem_page_index, shmem_page_offset;
809 int data_page_index, data_page_offset;
810 int page_length;
811 int ret;
812 uint64_t data_ptr = args->data_ptr;
280b713b 813 int do_bit17_swizzling;
40123c1f
EA		 814
815 remain = args->size;
816
817 /* Pin the user pages containing the data. We can't fault while
818 * holding the struct mutex, and all of the pwrite implementations
819 * want to hold it while dereferencing the user data.
820 */
821 first_data_page = data_ptr / PAGE_SIZE;
822 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
823 num_pages = last_data_page - first_data_page + 1;
824
8e7d2b2c 825 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
40123c1f
EA		 826 if (user_pages == NULL)
827 return -ENOMEM;
828
829 down_read(&mm->mmap_sem);
830 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
831 num_pages, 0, 0, user_pages, NULL);
832 up_read(&mm->mmap_sem);
833 if (pinned_pages < num_pages) {
834 ret = -EFAULT;
835 goto fail_put_user_pages;
673a394b
EA		 836 }
837
280b713b
EA		 838 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
839
40123c1f
EA		 840 mutex_lock(&dev->struct_mutex);
841
07f73f69
CW		 842 ret = i915_gem_object_get_pages_or_evict(obj);
843 if (ret)
40123c1f
EA		 844 goto fail_unlock;
845
846 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
847 if (ret != 0)
848 goto fail_put_pages;
849
23010e43 850 obj_priv = to_intel_bo(obj);
673a394b 851 offset = args->offset;
40123c1f 852 obj_priv->dirty = 1;
673a394b 853
40123c1f
EA		 854 while (remain > 0) {
855 /* Operation in this page
856 *
857 * shmem_page_index = page number within shmem file
858 * shmem_page_offset = offset within page in shmem file
859 * data_page_index = page number in get_user_pages return
860 * data_page_offset = offset with data_page_index page.
861 * page_length = bytes to copy for this page
862 */
863 shmem_page_index = offset / PAGE_SIZE;
864 shmem_page_offset = offset & ~PAGE_MASK;
865 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
866 data_page_offset = data_ptr & ~PAGE_MASK;
867
868 page_length = remain;
869 if ((shmem_page_offset + page_length) > PAGE_SIZE)
870 page_length = PAGE_SIZE - shmem_page_offset;
871 if ((data_page_offset + page_length) > PAGE_SIZE)
872 page_length = PAGE_SIZE - data_page_offset;
873
280b713b 874 if (do_bit17_swizzling) {
99a03df5 875 slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
280b713b
EA		 876 shmem_page_offset,
877 user_pages[data_page_index],
878 data_page_offset,
99a03df5
CW		 879 page_length,
880 0);
881 } else {
882 slow_shmem_copy(obj_priv->pages[shmem_page_index],
883 shmem_page_offset,
884 user_pages[data_page_index],
885 data_page_offset,
886 page_length);
280b713b 887 }
40123c1f
EA		 888
889 remain -= page_length;
890 data_ptr += page_length;
891 offset += page_length;
673a394b
EA		 892 }
893
40123c1f
EA		 894fail_put_pages:
895 i915_gem_object_put_pages(obj);
896fail_unlock:
673a394b 897 mutex_unlock(&dev->struct_mutex);
40123c1f
EA		 898fail_put_user_pages:
899 for (i = 0; i < pinned_pages; i++)
900 page_cache_release(user_pages[i]);
8e7d2b2c 901 drm_free_large(user_pages);
673a394b 902
40123c1f 903 return ret;
673a394b
EA		 904}
905
906/**
907 * Writes data to the object referenced by handle.
908 *
909 * On error, the contents of the buffer that were to be modified are undefined.
910 */
911int
912i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
913 struct drm_file *file_priv)
914{
915 struct drm_i915_gem_pwrite *args = data;
916 struct drm_gem_object *obj;
917 struct drm_i915_gem_object *obj_priv;
918 int ret = 0;
919
920 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
921 if (obj == NULL)
922 return -EBADF;
23010e43 923 obj_priv = to_intel_bo(obj);
673a394b
EA		 924
925 /* Bounds check destination.
926 *
927 * XXX: This could use review for overflow issues...
928 */
929 if (args->offset > obj->size || args->size > obj->size ||
930 args->offset + args->size > obj->size) {
bc9025bd 931 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 932 return -EINVAL;
933 }
934
935 /* We can only do the GTT pwrite on untiled buffers, as otherwise
936 * it would end up going through the fenced access, and we'll get
937 * different detiling behavior between reading and writing.
938 * pread/pwrite currently are reading and writing from the CPU
939 * perspective, requiring manual detiling by the client.
940 */
71acb5eb
DA		 941 if (obj_priv->phys_obj)
942 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
943 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
9b8c4a0b
CW		 944 dev->gtt_total != 0 &&
945 obj->write_domain != I915_GEM_DOMAIN_CPU) {
3de09aa3
EA		 946 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
947 if (ret == -EFAULT) {
948 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
949 file_priv);
950 }
280b713b
EA		 951 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
952 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
40123c1f
EA		 953 } else {
954 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
955 if (ret == -EFAULT) {
956 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
957 file_priv);
958 }
959 }
673a394b
EA		 960
961#if WATCH_PWRITE
962 if (ret)
963 DRM_INFO("pwrite failed %d\n", ret);
964#endif
965
bc9025bd 966 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 967
968 return ret;
969}
970
971/**
2ef7eeaa
EA		 972 * Called when user space prepares to use an object with the CPU, either
973 * through the mmap ioctl's mapping or a GTT mapping.
673a394b
EA		 974 */
975int
976i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
977 struct drm_file *file_priv)
978{
a09ba7fa 979 struct drm_i915_private *dev_priv = dev->dev_private;
673a394b
EA		 980 struct drm_i915_gem_set_domain *args = data;
981 struct drm_gem_object *obj;
652c393a 982 struct drm_i915_gem_object *obj_priv;
2ef7eeaa
EA		 983 uint32_t read_domains = args->read_domains;
984 uint32_t write_domain = args->write_domain;
673a394b
EA		 985 int ret;
986
987 if (!(dev->driver->driver_features & DRIVER_GEM))
988 return -ENODEV;
989
2ef7eeaa 990 /* Only handle setting domains to types used by the CPU. */
21d509e3 991 if (write_domain & I915_GEM_GPU_DOMAINS)
2ef7eeaa
EA		 992 return -EINVAL;
993
21d509e3 994 if (read_domains & I915_GEM_GPU_DOMAINS)
2ef7eeaa
EA		 995 return -EINVAL;
996
997 /* Having something in the write domain implies it's in the read
998 * domain, and only that read domain. Enforce that in the request.
999 */
1000 if (write_domain != 0 && read_domains != write_domain)
1001 return -EINVAL;
1002
673a394b
EA		 1003 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1004 if (obj == NULL)
1005 return -EBADF;
23010e43 1006 obj_priv = to_intel_bo(obj);
673a394b
EA		 1007
1008 mutex_lock(&dev->struct_mutex);
652c393a
JB		 1009
1010 intel_mark_busy(dev, obj);
1011
673a394b 1012#if WATCH_BUF
cfd43c02 1013 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
2ef7eeaa 1014 obj, obj->size, read_domains, write_domain);
673a394b 1015#endif
2ef7eeaa
EA		 1016 if (read_domains & I915_GEM_DOMAIN_GTT) {
1017 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
02354392 1018
a09ba7fa
EA		 1019 /* Update the LRU on the fence for the CPU access that's
1020 * about to occur.
1021 */
1022 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
007cc8ac
DV		 1023 struct drm_i915_fence_reg *reg =
1024 &dev_priv->fence_regs[obj_priv->fence_reg];
1025 list_move_tail(&reg->lru_list,
a09ba7fa
EA		 1026 &dev_priv->mm.fence_list);
1027 }
1028
02354392
EA		 1029 /* Silently promote "you're not bound, there was nothing to do"
1030 * to success, since the client was just asking us to
1031 * make sure everything was done.
1032 */
1033 if (ret == -EINVAL)
1034 ret = 0;
2ef7eeaa 1035 } else {
e47c68e9 1036 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
2ef7eeaa
EA		 1037 }
1038
673a394b
EA		 1039 drm_gem_object_unreference(obj);
1040 mutex_unlock(&dev->struct_mutex);
1041 return ret;
1042}
1043
1044/**
1045 * Called when user space has done writes to this buffer
1046 */
1047int
1048i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1049 struct drm_file *file_priv)
1050{
1051 struct drm_i915_gem_sw_finish *args = data;
1052 struct drm_gem_object *obj;
1053 struct drm_i915_gem_object *obj_priv;
1054 int ret = 0;
1055
1056 if (!(dev->driver->driver_features & DRIVER_GEM))
1057 return -ENODEV;
1058
1059 mutex_lock(&dev->struct_mutex);
1060 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1061 if (obj == NULL) {
1062 mutex_unlock(&dev->struct_mutex);
1063 return -EBADF;
1064 }
1065
1066#if WATCH_BUF
cfd43c02 1067 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
673a394b
EA		 1068 __func__, args->handle, obj, obj->size);
1069#endif
23010e43 1070 obj_priv = to_intel_bo(obj);
673a394b
EA		 1071
1072 /* Pinned buffers may be scanout, so flush the cache */
e47c68e9
EA		 1073 if (obj_priv->pin_count)
1074 i915_gem_object_flush_cpu_write_domain(obj);
1075
673a394b
EA		 1076 drm_gem_object_unreference(obj);
1077 mutex_unlock(&dev->struct_mutex);
1078 return ret;
1079}
1080
1081/**
1082 * Maps the contents of an object, returning the address it is mapped
1083 * into.
1084 *
1085 * While the mapping holds a reference on the contents of the object, it doesn't
1086 * imply a ref on the object itself.
1087 */
1088int
1089i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1090 struct drm_file *file_priv)
1091{
1092 struct drm_i915_gem_mmap *args = data;
1093 struct drm_gem_object *obj;
1094 loff_t offset;
1095 unsigned long addr;
1096
1097 if (!(dev->driver->driver_features & DRIVER_GEM))
1098 return -ENODEV;
1099
1100 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1101 if (obj == NULL)
1102 return -EBADF;
1103
1104 offset = args->offset;
1105
1106 down_write(&current->mm->mmap_sem);
1107 addr = do_mmap(obj->filp, 0, args->size,
1108 PROT_READ | PROT_WRITE, MAP_SHARED,
1109 args->offset);
1110 up_write(&current->mm->mmap_sem);
bc9025bd 1111 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 1112 if (IS_ERR((void *)addr))
1113 return addr;
1114
1115 args->addr_ptr = (uint64_t) addr;
1116
1117 return 0;
1118}
1119
de151cf6
JB		 1120/**
1121 * i915_gem_fault - fault a page into the GTT
1122 * vma: VMA in question
1123 * vmf: fault info
1124 *
1125 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1126 * from userspace. The fault handler takes care of binding the object to
1127 * the GTT (if needed), allocating and programming a fence register (again,
1128 * only if needed based on whether the old reg is still valid or the object
1129 * is tiled) and inserting a new PTE into the faulting process.
1130 *
1131 * Note that the faulting process may involve evicting existing objects
1132 * from the GTT and/or fence registers to make room. So performance may
1133 * suffer if the GTT working set is large or there are few fence registers
1134 * left.
1135 */
1136int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1137{
1138 struct drm_gem_object *obj = vma->vm_private_data;
1139 struct drm_device *dev = obj->dev;
1140 struct drm_i915_private *dev_priv = dev->dev_private;
23010e43 1141 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 1142 pgoff_t page_offset;
1143 unsigned long pfn;
1144 int ret = 0;
0f973f27 1145 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
de151cf6
JB		 1146
1147 /* We don't use vmf->pgoff since that has the fake offset */
1148 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1149 PAGE_SHIFT;
1150
1151 /* Now bind it into the GTT if needed */
1152 mutex_lock(&dev->struct_mutex);
1153 if (!obj_priv->gtt_space) {
e67b8ce1 1154 ret = i915_gem_object_bind_to_gtt(obj, 0);
c715089f
CW		 1155 if (ret)
1156 goto unlock;
07f4f3e8 1157
14b60391 1158 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
07f4f3e8
KH		 1159
1160 ret = i915_gem_object_set_to_gtt_domain(obj, write);
c715089f
CW		 1161 if (ret)
1162 goto unlock;
de151cf6
JB		 1163 }
1164
1165 /* Need a new fence register? */
a09ba7fa 1166 if (obj_priv->tiling_mode != I915_TILING_NONE) {
8c4b8c3f 1167 ret = i915_gem_object_get_fence_reg(obj);
c715089f
CW		 1168 if (ret)
1169 goto unlock;
d9ddcb96 1170 }
de151cf6
JB		 1171
1172 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1173 page_offset;
1174
1175 /* Finally, remap it using the new GTT offset */
1176 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
c715089f 1177unlock:
de151cf6
JB		 1178 mutex_unlock(&dev->struct_mutex);
1179
1180 switch (ret) {
c715089f
CW		 1181 case 0:
1182 case -ERESTARTSYS:
1183 return VM_FAULT_NOPAGE;
de151cf6
JB		 1184 case -ENOMEM:
1185 case -EAGAIN:
1186 return VM_FAULT_OOM;
de151cf6 1187 default:
c715089f 1188 return VM_FAULT_SIGBUS;
de151cf6
JB		 1189 }
1190}
1191
1192/**
1193 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1194 * @obj: obj in question
1195 *
1196 * GEM memory mapping works by handing back to userspace a fake mmap offset
1197 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1198 * up the object based on the offset and sets up the various memory mapping
1199 * structures.
1200 *
1201 * This routine allocates and attaches a fake offset for @obj.
1202 */
1203static int
1204i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1205{
1206 struct drm_device *dev = obj->dev;
1207 struct drm_gem_mm *mm = dev->mm_private;
23010e43 1208 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6 1209 struct drm_map_list *list;
f77d390c 1210 struct drm_local_map *map;
de151cf6
JB		 1211 int ret = 0;
1212
1213 /* Set the object up for mmap'ing */
1214 list = &obj->map_list;
9a298b2a 1215 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
de151cf6
JB		 1216 if (!list->map)
1217 return -ENOMEM;
1218
1219 map = list->map;
1220 map->type = _DRM_GEM;
1221 map->size = obj->size;
1222 map->handle = obj;
1223
1224 /* Get a DRM GEM mmap offset allocated... */
1225 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1226 obj->size / PAGE_SIZE, 0, 0);
1227 if (!list->file_offset_node) {
1228 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1229 ret = -ENOMEM;
1230 goto out_free_list;
1231 }
1232
1233 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1234 obj->size / PAGE_SIZE, 0);
1235 if (!list->file_offset_node) {
1236 ret = -ENOMEM;
1237 goto out_free_list;
1238 }
1239
1240 list->hash.key = list->file_offset_node->start;
1241 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1242 DRM_ERROR("failed to add to map hash\n");
5618ca6a 1243 ret = -ENOMEM;
de151cf6
JB		 1244 goto out_free_mm;
1245 }
1246
1247 /* By now we should be all set, any drm_mmap request on the offset
1248 * below will get to our mmap & fault handler */
1249 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1250
1251 return 0;
1252
1253out_free_mm:
1254 drm_mm_put_block(list->file_offset_node);
1255out_free_list:
9a298b2a 1256 kfree(list->map);
de151cf6
JB		 1257
1258 return ret;
1259}
1260
901782b2
CW		 1261/**
1262 * i915_gem_release_mmap - remove physical page mappings
1263 * @obj: obj in question
1264 *
af901ca1 1265 * Preserve the reservation of the mmapping with the DRM core code, but
901782b2
CW		 1266 * relinquish ownership of the pages back to the system.
1267 *
1268 * It is vital that we remove the page mapping if we have mapped a tiled
1269 * object through the GTT and then lose the fence register due to
1270 * resource pressure. Similarly if the object has been moved out of the
1271 * aperture, than pages mapped into userspace must be revoked. Removing the
1272 * mapping will then trigger a page fault on the next user access, allowing
1273 * fixup by i915_gem_fault().
1274 */
d05ca301 1275void
901782b2
CW		 1276i915_gem_release_mmap(struct drm_gem_object *obj)
1277{
1278 struct drm_device *dev = obj->dev;
23010e43 1279 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
901782b2
CW		 1280
1281 if (dev->dev_mapping)
1282 unmap_mapping_range(dev->dev_mapping,
1283 obj_priv->mmap_offset, obj->size, 1);
1284}
1285
ab00b3e5
JB		 1286static void
1287i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1288{
1289 struct drm_device *dev = obj->dev;
23010e43 1290 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
ab00b3e5
JB		 1291 struct drm_gem_mm *mm = dev->mm_private;
1292 struct drm_map_list *list;
1293
1294 list = &obj->map_list;
1295 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1296
1297 if (list->file_offset_node) {
1298 drm_mm_put_block(list->file_offset_node);
1299 list->file_offset_node = NULL;
1300 }
1301
1302 if (list->map) {
9a298b2a 1303 kfree(list->map);
ab00b3e5
JB		 1304 list->map = NULL;
1305 }
1306
1307 obj_priv->mmap_offset = 0;
1308}
1309
de151cf6
JB		 1310/**
1311 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1312 * @obj: object to check
1313 *
1314 * Return the required GTT alignment for an object, taking into account
1315 * potential fence register mapping if needed.
1316 */
1317static uint32_t
1318i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1319{
1320 struct drm_device *dev = obj->dev;
23010e43 1321 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 1322 int start, i;
1323
1324 /*
1325 * Minimum alignment is 4k (GTT page size), but might be greater
1326 * if a fence register is needed for the object.
1327 */
1328 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1329 return 4096;
1330
1331 /*
1332 * Previous chips need to be aligned to the size of the smallest
1333 * fence register that can contain the object.
1334 */
1335 if (IS_I9XX(dev))
1336 start = 1024*1024;
1337 else
1338 start = 512*1024;
1339
1340 for (i = start; i < obj->size; i <<= 1)
1341 ;
1342
1343 return i;
1344}
1345
1346/**
1347 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1348 * @dev: DRM device
1349 * @data: GTT mapping ioctl data
1350 * @file_priv: GEM object info
1351 *
1352 * Simply returns the fake offset to userspace so it can mmap it.
1353 * The mmap call will end up in drm_gem_mmap(), which will set things
1354 * up so we can get faults in the handler above.
1355 *
1356 * The fault handler will take care of binding the object into the GTT
1357 * (since it may have been evicted to make room for something), allocating
1358 * a fence register, and mapping the appropriate aperture address into
1359 * userspace.
1360 */
1361int
1362i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1363 struct drm_file *file_priv)
1364{
1365 struct drm_i915_gem_mmap_gtt *args = data;
1366 struct drm_i915_private *dev_priv = dev->dev_private;
1367 struct drm_gem_object *obj;
1368 struct drm_i915_gem_object *obj_priv;
1369 int ret;
1370
1371 if (!(dev->driver->driver_features & DRIVER_GEM))
1372 return -ENODEV;
1373
1374 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1375 if (obj == NULL)
1376 return -EBADF;
1377
1378 mutex_lock(&dev->struct_mutex);
1379
23010e43 1380 obj_priv = to_intel_bo(obj);
de151cf6 1381
ab18282d
CW		 1382 if (obj_priv->madv != I915_MADV_WILLNEED) {
1383 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1384 drm_gem_object_unreference(obj);
1385 mutex_unlock(&dev->struct_mutex);
1386 return -EINVAL;
1387 }
1388
1389
de151cf6
JB		 1390 if (!obj_priv->mmap_offset) {
1391 ret = i915_gem_create_mmap_offset(obj);
13af1062
CW		 1392 if (ret) {
1393 drm_gem_object_unreference(obj);
1394 mutex_unlock(&dev->struct_mutex);
de151cf6 1395 return ret;
13af1062 1396 }
de151cf6
JB		 1397 }
1398
1399 args->offset = obj_priv->mmap_offset;
1400
de151cf6
JB		 1401 /*
1402 * Pull it into the GTT so that we have a page list (makes the
1403 * initial fault faster and any subsequent flushing possible).
1404 */
1405 if (!obj_priv->agp_mem) {
e67b8ce1 1406 ret = i915_gem_object_bind_to_gtt(obj, 0);
de151cf6
JB		 1407 if (ret) {
1408 drm_gem_object_unreference(obj);
1409 mutex_unlock(&dev->struct_mutex);
1410 return ret;
1411 }
14b60391 1412 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
de151cf6
JB		 1413 }
1414
1415 drm_gem_object_unreference(obj);
1416 mutex_unlock(&dev->struct_mutex);
1417
1418 return 0;
1419}
1420
6911a9b8 1421void
856fa198 1422i915_gem_object_put_pages(struct drm_gem_object *obj)
673a394b 1423{
23010e43 1424 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1425 int page_count = obj->size / PAGE_SIZE;
1426 int i;
1427
856fa198 1428 BUG_ON(obj_priv->pages_refcount == 0);
bb6baf76 1429 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
673a394b 1430
856fa198
EA		 1431 if (--obj_priv->pages_refcount != 0)
1432 return;
673a394b 1433
280b713b
EA		 1434 if (obj_priv->tiling_mode != I915_TILING_NONE)
1435 i915_gem_object_save_bit_17_swizzle(obj);
1436
3ef94daa 1437 if (obj_priv->madv == I915_MADV_DONTNEED)
13a05fd9 1438 obj_priv->dirty = 0;
3ef94daa
CW		 1439
1440 for (i = 0; i < page_count; i++) {
3ef94daa
CW		 1441 if (obj_priv->dirty)
1442 set_page_dirty(obj_priv->pages[i]);
1443
1444 if (obj_priv->madv == I915_MADV_WILLNEED)
856fa198 1445 mark_page_accessed(obj_priv->pages[i]);
3ef94daa
CW		 1446
1447 page_cache_release(obj_priv->pages[i]);
1448 }
673a394b
EA		 1449 obj_priv->dirty = 0;
1450
8e7d2b2c 1451 drm_free_large(obj_priv->pages);
856fa198 1452 obj_priv->pages = NULL;
673a394b
EA		 1453}
1454
1455static void
852835f3
ZN		 1456i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno,
1457 struct intel_ring_buffer *ring)
673a394b
EA		 1458{
1459 struct drm_device *dev = obj->dev;
1460 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1461 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
852835f3
ZN		 1462 BUG_ON(ring == NULL);
1463 obj_priv->ring = ring;
673a394b
EA		 1464
1465 /* Add a reference if we're newly entering the active list. */
1466 if (!obj_priv->active) {
1467 drm_gem_object_reference(obj);
1468 obj_priv->active = 1;
1469 }
1470 /* Move from whatever list we were on to the tail of execution. */
5e118f41 1471 spin_lock(&dev_priv->mm.active_list_lock);
852835f3 1472 list_move_tail(&obj_priv->list, &ring->active_list);
5e118f41 1473 spin_unlock(&dev_priv->mm.active_list_lock);
ce44b0ea 1474 obj_priv->last_rendering_seqno = seqno;
673a394b
EA		 1475}
1476
ce44b0ea
EA		 1477static void
1478i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1479{
1480 struct drm_device *dev = obj->dev;
1481 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1482 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
ce44b0ea
EA		 1483
1484 BUG_ON(!obj_priv->active);
1485 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1486 obj_priv->last_rendering_seqno = 0;
1487}
673a394b 1488
963b4836
CW		 1489/* Immediately discard the backing storage */
1490static void
1491i915_gem_object_truncate(struct drm_gem_object *obj)
1492{
23010e43 1493 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
bb6baf76 1494 struct inode *inode;
963b4836 1495
bb6baf76
CW		 1496 inode = obj->filp->f_path.dentry->d_inode;
1497 if (inode->i_op->truncate)
1498 inode->i_op->truncate (inode);
1499
1500 obj_priv->madv = __I915_MADV_PURGED;
963b4836
CW		 1501}
1502
1503static inline int
1504i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1505{
1506 return obj_priv->madv == I915_MADV_DONTNEED;
1507}
1508
673a394b
EA		 1509static void
1510i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1511{
1512 struct drm_device *dev = obj->dev;
1513 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1514 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1515
1516 i915_verify_inactive(dev, __FILE__, __LINE__);
1517 if (obj_priv->pin_count != 0)
1518 list_del_init(&obj_priv->list);
1519 else
1520 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1521
99fcb766
DV		 1522 BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1523
ce44b0ea 1524 obj_priv->last_rendering_seqno = 0;
852835f3 1525 obj_priv->ring = NULL;
673a394b
EA		 1526 if (obj_priv->active) {
1527 obj_priv->active = 0;
1528 drm_gem_object_unreference(obj);
1529 }
1530 i915_verify_inactive(dev, __FILE__, __LINE__);
1531}
1532
63560396
DV		 1533static void
1534i915_gem_process_flushing_list(struct drm_device *dev,
852835f3
ZN		 1535 uint32_t flush_domains, uint32_t seqno,
1536 struct intel_ring_buffer *ring)
63560396
DV		 1537{
1538 drm_i915_private_t *dev_priv = dev->dev_private;
1539 struct drm_i915_gem_object *obj_priv, *next;
1540
1541 list_for_each_entry_safe(obj_priv, next,
1542 &dev_priv->mm.gpu_write_list,
1543 gpu_write_list) {
a8089e84 1544 struct drm_gem_object *obj = &obj_priv->base;
63560396
DV		 1545
1546 if ((obj->write_domain & flush_domains) ==
852835f3
ZN		 1547 obj->write_domain &&
1548 obj_priv->ring->ring_flag == ring->ring_flag) {
63560396
DV		 1549 uint32_t old_write_domain = obj->write_domain;
1550
1551 obj->write_domain = 0;
1552 list_del_init(&obj_priv->gpu_write_list);
852835f3 1553 i915_gem_object_move_to_active(obj, seqno, ring);
63560396
DV		 1554
1555 /* update the fence lru list */
007cc8ac
DV		 1556 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1557 struct drm_i915_fence_reg *reg =
1558 &dev_priv->fence_regs[obj_priv->fence_reg];
1559 list_move_tail(&reg->lru_list,
63560396 1560 &dev_priv->mm.fence_list);
007cc8ac 1561 }
63560396
DV		 1562
1563 trace_i915_gem_object_change_domain(obj,
1564 obj->read_domains,
1565 old_write_domain);
1566 }
1567 }
1568}
8187a2b7 1569
5a5a0c64 1570uint32_t
b962442e 1571i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
852835f3 1572 uint32_t flush_domains, struct intel_ring_buffer *ring)
673a394b
EA		 1573{
1574 drm_i915_private_t *dev_priv = dev->dev_private;
b962442e 1575 struct drm_i915_file_private *i915_file_priv = NULL;
673a394b
EA		 1576 struct drm_i915_gem_request *request;
1577 uint32_t seqno;
1578 int was_empty;
673a394b 1579
b962442e
EA		 1580 if (file_priv != NULL)
1581 i915_file_priv = file_priv->driver_priv;
1582
9a298b2a 1583 request = kzalloc(sizeof(*request), GFP_KERNEL);
673a394b
EA		 1584 if (request == NULL)
1585 return 0;
1586
852835f3 1587 seqno = ring->add_request(dev, ring, file_priv, flush_domains);
673a394b
EA		 1588
1589 request->seqno = seqno;
852835f3 1590 request->ring = ring;
673a394b 1591 request->emitted_jiffies = jiffies;
852835f3
ZN		 1592 was_empty = list_empty(&ring->request_list);
1593 list_add_tail(&request->list, &ring->request_list);
1594
b962442e
EA		 1595 if (i915_file_priv) {
1596 list_add_tail(&request->client_list,
1597 &i915_file_priv->mm.request_list);
1598 } else {
1599 INIT_LIST_HEAD(&request->client_list);
1600 }
673a394b 1601
ce44b0ea
EA		 1602 /* Associate any objects on the flushing list matching the write
1603 * domain we're flushing with our flush.
1604 */
63560396 1605 if (flush_domains != 0)
852835f3 1606 i915_gem_process_flushing_list(dev, flush_domains, seqno, ring);
ce44b0ea 1607
f65d9421
BG		 1608 if (!dev_priv->mm.suspended) {
1609 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1610 if (was_empty)
1611 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1612 }
673a394b
EA		 1613 return seqno;
1614}
1615
1616/**
1617 * Command execution barrier
1618 *
1619 * Ensures that all commands in the ring are finished
1620 * before signalling the CPU
1621 */
3043c60c 1622static uint32_t
852835f3 1623i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring)
673a394b 1624{
673a394b 1625 uint32_t flush_domains = 0;
673a394b
EA		 1626
1627 /* The sampler always gets flushed on i965 (sigh) */
1628 if (IS_I965G(dev))
1629 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
852835f3
ZN		 1630
1631 ring->flush(dev, ring,
1632 I915_GEM_DOMAIN_COMMAND, flush_domains);
673a394b
EA		 1633 return flush_domains;
1634}
1635
1636/**
1637 * Moves buffers associated only with the given active seqno from the active
1638 * to inactive list, potentially freeing them.
1639 */
1640static void
1641i915_gem_retire_request(struct drm_device *dev,
1642 struct drm_i915_gem_request *request)
1643{
1644 drm_i915_private_t *dev_priv = dev->dev_private;
1645
1c5d22f7
CW		 1646 trace_i915_gem_request_retire(dev, request->seqno);
1647
673a394b
EA		 1648 /* Move any buffers on the active list that are no longer referenced
1649 * by the ringbuffer to the flushing/inactive lists as appropriate.
1650 */
5e118f41 1651 spin_lock(&dev_priv->mm.active_list_lock);
852835f3 1652 while (!list_empty(&request->ring->active_list)) {
673a394b
EA		 1653 struct drm_gem_object *obj;
1654 struct drm_i915_gem_object *obj_priv;
1655
852835f3 1656 obj_priv = list_first_entry(&request->ring->active_list,
673a394b
EA		 1657 struct drm_i915_gem_object,
1658 list);
a8089e84 1659 obj = &obj_priv->base;
673a394b
EA		 1660
1661 /* If the seqno being retired doesn't match the oldest in the
1662 * list, then the oldest in the list must still be newer than
1663 * this seqno.
1664 */
1665 if (obj_priv->last_rendering_seqno != request->seqno)
5e118f41 1666 goto out;
de151cf6 1667
673a394b
EA		 1668#if WATCH_LRU
1669 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1670 __func__, request->seqno, obj);
1671#endif
1672
ce44b0ea
EA		 1673 if (obj->write_domain != 0)
1674 i915_gem_object_move_to_flushing(obj);
68c84342
SL		 1675 else {
1676 /* Take a reference on the object so it won't be
1677 * freed while the spinlock is held. The list
1678 * protection for this spinlock is safe when breaking
1679 * the lock like this since the next thing we do
1680 * is just get the head of the list again.
1681 */
1682 drm_gem_object_reference(obj);
673a394b 1683 i915_gem_object_move_to_inactive(obj);
68c84342
SL		 1684 spin_unlock(&dev_priv->mm.active_list_lock);
1685 drm_gem_object_unreference(obj);
1686 spin_lock(&dev_priv->mm.active_list_lock);
1687 }
673a394b 1688 }
5e118f41
CW		 1689out:
1690 spin_unlock(&dev_priv->mm.active_list_lock);
673a394b
EA		 1691}
1692
1693/**
1694 * Returns true if seq1 is later than seq2.
1695 */
22be1724 1696bool
673a394b
EA		 1697i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1698{
1699 return (int32_t)(seq1 - seq2) >= 0;
1700}
1701
1702uint32_t
852835f3 1703i915_get_gem_seqno(struct drm_device *dev,
d1b851fc 1704 struct intel_ring_buffer *ring)
673a394b 1705{
852835f3 1706 return ring->get_gem_seqno(dev, ring);
673a394b
EA		 1707}
1708
1709/**
1710 * This function clears the request list as sequence numbers are passed.
1711 */
1712void
852835f3
ZN		 1713i915_gem_retire_requests(struct drm_device *dev,
1714 struct intel_ring_buffer *ring)
673a394b
EA		 1715{
1716 drm_i915_private_t *dev_priv = dev->dev_private;
1717 uint32_t seqno;
1718
8187a2b7 1719 if (!ring->status_page.page_addr
852835f3 1720 || list_empty(&ring->request_list))
6c0594a3
KW		 1721 return;
1722
852835f3 1723 seqno = i915_get_gem_seqno(dev, ring);
673a394b 1724
852835f3 1725 while (!list_empty(&ring->request_list)) {
673a394b
EA		 1726 struct drm_i915_gem_request *request;
1727 uint32_t retiring_seqno;
1728
852835f3 1729 request = list_first_entry(&ring->request_list,
673a394b
EA		 1730 struct drm_i915_gem_request,
1731 list);
1732 retiring_seqno = request->seqno;
1733
1734 if (i915_seqno_passed(seqno, retiring_seqno) ||
ba1234d1 1735 atomic_read(&dev_priv->mm.wedged)) {
673a394b
EA		 1736 i915_gem_retire_request(dev, request);
1737
1738 list_del(&request->list);
b962442e 1739 list_del(&request->client_list);
9a298b2a 1740 kfree(request);
673a394b
EA		 1741 } else
1742 break;
1743 }
9d34e5db
CW		 1744
1745 if (unlikely (dev_priv->trace_irq_seqno &&
1746 i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
8187a2b7
ZN		 1747
1748 ring->user_irq_put(dev, ring);
9d34e5db
CW		 1749 dev_priv->trace_irq_seqno = 0;
1750 }
673a394b
EA		 1751}
1752
1753void
1754i915_gem_retire_work_handler(struct work_struct *work)
1755{
1756 drm_i915_private_t *dev_priv;
1757 struct drm_device *dev;
1758
1759 dev_priv = container_of(work, drm_i915_private_t,
1760 mm.retire_work.work);
1761 dev = dev_priv->dev;
1762
1763 mutex_lock(&dev->struct_mutex);
852835f3
ZN		 1764 i915_gem_retire_requests(dev, &dev_priv->render_ring);
1765
d1b851fc
ZN		 1766 if (HAS_BSD(dev))
1767 i915_gem_retire_requests(dev, &dev_priv->bsd_ring);
1768
6dbe2772 1769 if (!dev_priv->mm.suspended &&
d1b851fc
ZN		 1770 (!list_empty(&dev_priv->render_ring.request_list) ||
1771 (HAS_BSD(dev) &&
1772 !list_empty(&dev_priv->bsd_ring.request_list))))
9c9fe1f8 1773 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
673a394b
EA		 1774 mutex_unlock(&dev->struct_mutex);
1775}
1776
5a5a0c64 1777int
852835f3
ZN		 1778i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
1779 int interruptible, struct intel_ring_buffer *ring)
673a394b
EA		 1780{
1781 drm_i915_private_t *dev_priv = dev->dev_private;
802c7eb6 1782 u32 ier;
673a394b
EA		 1783 int ret = 0;
1784
1785 BUG_ON(seqno == 0);
1786
ba1234d1 1787 if (atomic_read(&dev_priv->mm.wedged))
ffed1d09
BG		 1788 return -EIO;
1789
852835f3 1790 if (!i915_seqno_passed(ring->get_gem_seqno(dev, ring), seqno)) {
bad720ff 1791 if (HAS_PCH_SPLIT(dev))
036a4a7d
ZW		 1792 ier = I915_READ(DEIER) | I915_READ(GTIER);
1793 else
1794 ier = I915_READ(IER);
802c7eb6
JB		 1795 if (!ier) {
1796 DRM_ERROR("something (likely vbetool) disabled "
1797 "interrupts, re-enabling\n");
1798 i915_driver_irq_preinstall(dev);
1799 i915_driver_irq_postinstall(dev);
1800 }
1801
1c5d22f7
CW		 1802 trace_i915_gem_request_wait_begin(dev, seqno);
1803
852835f3 1804 ring->waiting_gem_seqno = seqno;
8187a2b7 1805 ring->user_irq_get(dev, ring);
48764bf4 1806 if (interruptible)
852835f3
ZN		 1807 ret = wait_event_interruptible(ring->irq_queue,
1808 i915_seqno_passed(
1809 ring->get_gem_seqno(dev, ring), seqno)
1810 || atomic_read(&dev_priv->mm.wedged));
48764bf4 1811 else
852835f3
ZN		 1812 wait_event(ring->irq_queue,
1813 i915_seqno_passed(
1814 ring->get_gem_seqno(dev, ring), seqno)
1815 || atomic_read(&dev_priv->mm.wedged));
48764bf4 1816
8187a2b7 1817 ring->user_irq_put(dev, ring);
852835f3 1818 ring->waiting_gem_seqno = 0;
1c5d22f7
CW		 1819
1820 trace_i915_gem_request_wait_end(dev, seqno);
673a394b 1821 }
ba1234d1 1822 if (atomic_read(&dev_priv->mm.wedged))
673a394b
EA		 1823 ret = -EIO;
1824
1825 if (ret && ret != -ERESTARTSYS)
1826 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
852835f3 1827 __func__, ret, seqno, ring->get_gem_seqno(dev, ring));
673a394b
EA		 1828
1829 /* Directly dispatch request retiring. While we have the work queue
1830 * to handle this, the waiter on a request often wants an associated
1831 * buffer to have made it to the inactive list, and we would need
1832 * a separate wait queue to handle that.
1833 */
1834 if (ret == 0)
852835f3 1835 i915_gem_retire_requests(dev, ring);
673a394b
EA		 1836
1837 return ret;
1838}
1839
48764bf4
DV		 1840/**
1841 * Waits for a sequence number to be signaled, and cleans up the
1842 * request and object lists appropriately for that event.
1843 */
1844static int
852835f3
ZN		 1845i915_wait_request(struct drm_device *dev, uint32_t seqno,
1846 struct intel_ring_buffer *ring)
48764bf4 1847{
852835f3 1848 return i915_do_wait_request(dev, seqno, 1, ring);
48764bf4
DV		 1849}
1850
8187a2b7
ZN		 1851static void
1852i915_gem_flush(struct drm_device *dev,
1853 uint32_t invalidate_domains,
1854 uint32_t flush_domains)
1855{
1856 drm_i915_private_t *dev_priv = dev->dev_private;
1857 if (flush_domains & I915_GEM_DOMAIN_CPU)
1858 drm_agp_chipset_flush(dev);
1859 dev_priv->render_ring.flush(dev, &dev_priv->render_ring,
1860 invalidate_domains,
1861 flush_domains);
d1b851fc
ZN		 1862
1863 if (HAS_BSD(dev))
1864 dev_priv->bsd_ring.flush(dev, &dev_priv->bsd_ring,
1865 invalidate_domains,
1866 flush_domains);
8187a2b7
ZN		 1867}
1868
852835f3
ZN		 1869static void
1870i915_gem_flush_ring(struct drm_device *dev,
1871 uint32_t invalidate_domains,
1872 uint32_t flush_domains,
1873 struct intel_ring_buffer *ring)
1874{
1875 if (flush_domains & I915_GEM_DOMAIN_CPU)
1876 drm_agp_chipset_flush(dev);
1877 ring->flush(dev, ring,
1878 invalidate_domains,
1879 flush_domains);
1880}
1881
673a394b
EA		 1882/**
1883 * Ensures that all rendering to the object has completed and the object is
1884 * safe to unbind from the GTT or access from the CPU.
1885 */
1886static int
1887i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1888{
1889 struct drm_device *dev = obj->dev;
23010e43 1890 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1891 int ret;
1892
e47c68e9
EA		 1893 /* This function only exists to support waiting for existing rendering,
1894 * not for emitting required flushes.
673a394b 1895 */
e47c68e9 1896 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
673a394b
EA		 1897
1898 /* If there is rendering queued on the buffer being evicted, wait for
1899 * it.
1900 */
1901 if (obj_priv->active) {
1902#if WATCH_BUF
1903 DRM_INFO("%s: object %p wait for seqno %08x\n",
1904 __func__, obj, obj_priv->last_rendering_seqno);
1905#endif
852835f3
ZN		 1906 ret = i915_wait_request(dev,
1907 obj_priv->last_rendering_seqno, obj_priv->ring);
673a394b
EA		 1908 if (ret != 0)
1909 return ret;
1910 }
1911
1912 return 0;
1913}
1914
1915/**
1916 * Unbinds an object from the GTT aperture.
1917 */
0f973f27 1918int
673a394b
EA		 1919i915_gem_object_unbind(struct drm_gem_object *obj)
1920{
1921 struct drm_device *dev = obj->dev;
4a87b8ca 1922 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1923 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1924 int ret = 0;
1925
1926#if WATCH_BUF
1927 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1928 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1929#endif
1930 if (obj_priv->gtt_space == NULL)
1931 return 0;
1932
1933 if (obj_priv->pin_count != 0) {
1934 DRM_ERROR("Attempting to unbind pinned buffer\n");
1935 return -EINVAL;
1936 }
1937
5323fd04
EA		 1938 /* blow away mappings if mapped through GTT */
1939 i915_gem_release_mmap(obj);
1940
673a394b
EA		 1941 /* Move the object to the CPU domain to ensure that
1942 * any possible CPU writes while it's not in the GTT
1943 * are flushed when we go to remap it. This will
1944 * also ensure that all pending GPU writes are finished
1945 * before we unbind.
1946 */
e47c68e9 1947 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
673a394b 1948 if (ret) {
e47c68e9
EA		 1949 if (ret != -ERESTARTSYS)
1950 DRM_ERROR("set_domain failed: %d\n", ret);
673a394b
EA		 1951 return ret;
1952 }
1953
5323fd04
EA		 1954 BUG_ON(obj_priv->active);
1955
96b47b65
DV		 1956 /* release the fence reg _after_ flushing */
1957 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1958 i915_gem_clear_fence_reg(obj);
1959
673a394b
EA		 1960 if (obj_priv->agp_mem != NULL) {
1961 drm_unbind_agp(obj_priv->agp_mem);
1962 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
1963 obj_priv->agp_mem = NULL;
1964 }
1965
856fa198 1966 i915_gem_object_put_pages(obj);
a32808c0 1967 BUG_ON(obj_priv->pages_refcount);
673a394b
EA		 1968
1969 if (obj_priv->gtt_space) {
1970 atomic_dec(&dev->gtt_count);
1971 atomic_sub(obj->size, &dev->gtt_memory);
1972
1973 drm_mm_put_block(obj_priv->gtt_space);
1974 obj_priv->gtt_space = NULL;
1975 }
1976
1977 /* Remove ourselves from the LRU list if present. */
4a87b8ca 1978 spin_lock(&dev_priv->mm.active_list_lock);
673a394b
EA		 1979 if (!list_empty(&obj_priv->list))
1980 list_del_init(&obj_priv->list);
4a87b8ca 1981 spin_unlock(&dev_priv->mm.active_list_lock);
673a394b 1982
963b4836
CW		 1983 if (i915_gem_object_is_purgeable(obj_priv))
1984 i915_gem_object_truncate(obj);
1985
1c5d22f7
CW		 1986 trace_i915_gem_object_unbind(obj);
1987
673a394b
EA		 1988 return 0;
1989}
1990
07f73f69
CW		 1991static struct drm_gem_object *
1992i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
1993{
1994 drm_i915_private_t *dev_priv = dev->dev_private;
1995 struct drm_i915_gem_object *obj_priv;
1996 struct drm_gem_object *best = NULL;
1997 struct drm_gem_object *first = NULL;
1998
1999 /* Try to find the smallest clean object */
2000 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
a8089e84 2001 struct drm_gem_object *obj = &obj_priv->base;
07f73f69 2002 if (obj->size >= min_size) {
963b4836
CW		 2003 if ((!obj_priv->dirty ||
2004 i915_gem_object_is_purgeable(obj_priv)) &&
07f73f69
CW		 2005 (!best || obj->size < best->size)) {
2006 best = obj;
2007 if (best->size == min_size)
2008 return best;
2009 }
2010 if (!first)
2011 first = obj;
2012 }
2013 }
2014
2015 return best ? best : first;
2016}
2017
4df2faf4
DV		 2018static int
2019i915_gpu_idle(struct drm_device *dev)
2020{
2021 drm_i915_private_t *dev_priv = dev->dev_private;
2022 bool lists_empty;
d1b851fc 2023 uint32_t seqno1, seqno2;
852835f3 2024 int ret;
4df2faf4
DV		 2025
2026 spin_lock(&dev_priv->mm.active_list_lock);
d1b851fc
ZN		 2027 lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2028 list_empty(&dev_priv->render_ring.active_list) &&
2029 (!HAS_BSD(dev) ||
2030 list_empty(&dev_priv->bsd_ring.active_list)));
4df2faf4
DV		 2031 spin_unlock(&dev_priv->mm.active_list_lock);
2032
2033 if (lists_empty)
2034 return 0;
2035
2036 /* Flush everything onto the inactive list. */
2037 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
d1b851fc 2038 seqno1 = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS,
852835f3 2039 &dev_priv->render_ring);
d1b851fc 2040 if (seqno1 == 0)
4df2faf4 2041 return -ENOMEM;
d1b851fc
ZN		 2042 ret = i915_wait_request(dev, seqno1, &dev_priv->render_ring);
2043
2044 if (HAS_BSD(dev)) {
2045 seqno2 = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS,
2046 &dev_priv->bsd_ring);
2047 if (seqno2 == 0)
2048 return -ENOMEM;
2049
2050 ret = i915_wait_request(dev, seqno2, &dev_priv->bsd_ring);
2051 if (ret)
2052 return ret;
2053 }
2054
4df2faf4 2055
852835f3 2056 return ret;
4df2faf4
DV		 2057}
2058
673a394b 2059static int
07f73f69
CW		 2060i915_gem_evict_everything(struct drm_device *dev)
2061{
2062 drm_i915_private_t *dev_priv = dev->dev_private;
07f73f69
CW		 2063 int ret;
2064 bool lists_empty;
2065
07f73f69
CW		 2066 spin_lock(&dev_priv->mm.active_list_lock);
2067 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2068 list_empty(&dev_priv->mm.flushing_list) &&
d1b851fc
ZN		 2069 list_empty(&dev_priv->render_ring.active_list) &&
2070 (!HAS_BSD(dev)
2071 || list_empty(&dev_priv->bsd_ring.active_list)));
07f73f69
CW		 2072 spin_unlock(&dev_priv->mm.active_list_lock);
2073
9731129c 2074 if (lists_empty)
07f73f69 2075 return -ENOSPC;
07f73f69
CW		 2076
2077 /* Flush everything (on to the inactive lists) and evict */
4df2faf4 2078 ret = i915_gpu_idle(dev);
07f73f69
CW		 2079 if (ret)
2080 return ret;
2081
99fcb766
DV		 2082 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2083
ab5ee576 2084 ret = i915_gem_evict_from_inactive_list(dev);
07f73f69
CW		 2085 if (ret)
2086 return ret;
2087
2088 spin_lock(&dev_priv->mm.active_list_lock);
2089 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2090 list_empty(&dev_priv->mm.flushing_list) &&
d1b851fc
ZN		 2091 list_empty(&dev_priv->render_ring.active_list) &&
2092 (!HAS_BSD(dev)
2093 || list_empty(&dev_priv->bsd_ring.active_list)));
07f73f69
CW		 2094 spin_unlock(&dev_priv->mm.active_list_lock);
2095 BUG_ON(!lists_empty);
2096
2097 return 0;
2098}
2099
673a394b 2100static int
07f73f69 2101i915_gem_evict_something(struct drm_device *dev, int min_size)
673a394b
EA		 2102{
2103 drm_i915_private_t *dev_priv = dev->dev_private;
2104 struct drm_gem_object *obj;
07f73f69 2105 int ret;
673a394b 2106
852835f3 2107 struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
d1b851fc 2108 struct intel_ring_buffer *bsd_ring = &dev_priv->bsd_ring;
673a394b 2109 for (;;) {
852835f3 2110 i915_gem_retire_requests(dev, render_ring);
07f73f69 2111
d1b851fc
ZN		 2112 if (HAS_BSD(dev))
2113 i915_gem_retire_requests(dev, bsd_ring);
2114
673a394b
EA		 2115 /* If there's an inactive buffer available now, grab it
2116 * and be done.
2117 */
07f73f69
CW		 2118 obj = i915_gem_find_inactive_object(dev, min_size);
2119 if (obj) {
2120 struct drm_i915_gem_object *obj_priv;
2121
673a394b
EA		 2122#if WATCH_LRU
2123 DRM_INFO("%s: evicting %p\n", __func__, obj);
2124#endif
23010e43 2125 obj_priv = to_intel_bo(obj);
07f73f69 2126 BUG_ON(obj_priv->pin_count != 0);
673a394b
EA		 2127 BUG_ON(obj_priv->active);
2128
2129 /* Wait on the rendering and unbind the buffer. */
07f73f69 2130 return i915_gem_object_unbind(obj);
673a394b
EA		 2131 }
2132
2133 /* If we didn't get anything, but the ring is still processing
07f73f69
CW		 2134 * things, wait for the next to finish and hopefully leave us
2135 * a buffer to evict.
673a394b 2136 */
852835f3 2137 if (!list_empty(&render_ring->request_list)) {
673a394b
EA		 2138 struct drm_i915_gem_request *request;
2139
852835f3 2140 request = list_first_entry(&render_ring->request_list,
673a394b
EA		 2141 struct drm_i915_gem_request,
2142 list);
2143
852835f3
ZN		 2144 ret = i915_wait_request(dev,
2145 request->seqno, request->ring);
673a394b 2146 if (ret)
07f73f69 2147 return ret;
673a394b 2148
07f73f69 2149 continue;
673a394b
EA		 2150 }
2151
d1b851fc
ZN		 2152 if (HAS_BSD(dev) && !list_empty(&bsd_ring->request_list)) {
2153 struct drm_i915_gem_request *request;
2154
2155 request = list_first_entry(&bsd_ring->request_list,
2156 struct drm_i915_gem_request,
2157 list);
2158
2159 ret = i915_wait_request(dev,
2160 request->seqno, request->ring);
2161 if (ret)
2162 return ret;
2163
2164 continue;
2165 }
2166
673a394b
EA		 2167 /* If we didn't have anything on the request list but there
2168 * are buffers awaiting a flush, emit one and try again.
2169 * When we wait on it, those buffers waiting for that flush
2170 * will get moved to inactive.
2171 */
2172 if (!list_empty(&dev_priv->mm.flushing_list)) {
07f73f69 2173 struct drm_i915_gem_object *obj_priv;
673a394b 2174
9a1e2582
CW		 2175 /* Find an object that we can immediately reuse */
2176 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
a8089e84 2177 obj = &obj_priv->base;
9a1e2582
CW		 2178 if (obj->size >= min_size)
2179 break;
673a394b 2180
9a1e2582
CW		 2181 obj = NULL;
2182 }
673a394b 2183
9a1e2582
CW		 2184 if (obj != NULL) {
2185 uint32_t seqno;
673a394b 2186
852835f3
ZN		 2187 i915_gem_flush_ring(dev,
2188 obj->write_domain,
9a1e2582 2189 obj->write_domain,
852835f3
ZN		 2190 obj_priv->ring);
2191 seqno = i915_add_request(dev, NULL,
2192 obj->write_domain,
2193 obj_priv->ring);
9a1e2582
CW		 2194 if (seqno == 0)
2195 return -ENOMEM;
9a1e2582
CW		 2196 continue;
2197 }
673a394b
EA		 2198 }
2199
07f73f69
CW		 2200 /* If we didn't do any of the above, there's no single buffer
2201 * large enough to swap out for the new one, so just evict
2202 * everything and start again. (This should be rare.)
673a394b 2203 */
9731129c 2204 if (!list_empty (&dev_priv->mm.inactive_list))
ab5ee576 2205 return i915_gem_evict_from_inactive_list(dev);
9731129c 2206 else
07f73f69 2207 return i915_gem_evict_everything(dev);
ac94a962 2208 }
ac94a962
KP		 2209}
2210
6911a9b8 2211int
4bdadb97
CW		 2212i915_gem_object_get_pages(struct drm_gem_object *obj,
2213 gfp_t gfpmask)
673a394b 2214{
23010e43 2215 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 2216 int page_count, i;
2217 struct address_space *mapping;
2218 struct inode *inode;
2219 struct page *page;
673a394b 2220
778c3544
DV		 2221 BUG_ON(obj_priv->pages_refcount
2222 == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT);
2223
856fa198 2224 if (obj_priv->pages_refcount++ != 0)
673a394b
EA		 2225 return 0;
2226
2227 /* Get the list of pages out of our struct file. They'll be pinned
2228 * at this point until we release them.
2229 */
2230 page_count = obj->size / PAGE_SIZE;
856fa198 2231 BUG_ON(obj_priv->pages != NULL);
8e7d2b2c 2232 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
856fa198 2233 if (obj_priv->pages == NULL) {
856fa198 2234 obj_priv->pages_refcount--;
673a394b
EA		 2235 return -ENOMEM;
2236 }
2237
2238 inode = obj->filp->f_path.dentry->d_inode;
2239 mapping = inode->i_mapping;
2240 for (i = 0; i < page_count; i++) {
4bdadb97 2241 page = read_cache_page_gfp(mapping, i,
985b823b 2242 GFP_HIGHUSER |
4bdadb97 2243 __GFP_COLD |
cd9f040d 2244 __GFP_RECLAIMABLE |
4bdadb97 2245 gfpmask);
1f2b1013
CW		 2246 if (IS_ERR(page))
2247 goto err_pages;
2248
856fa198 2249 obj_priv->pages[i] = page;
673a394b 2250 }
280b713b
EA		 2251
2252 if (obj_priv->tiling_mode != I915_TILING_NONE)
2253 i915_gem_object_do_bit_17_swizzle(obj);
2254
673a394b 2255 return 0;
1f2b1013
CW		 2256
2257err_pages:
2258 while (i--)
2259 page_cache_release(obj_priv->pages[i]);
2260
2261 drm_free_large(obj_priv->pages);
2262 obj_priv->pages = NULL;
2263 obj_priv->pages_refcount--;
2264 return PTR_ERR(page);
673a394b
EA		 2265}
2266
4e901fdc
EA		 2267static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
2268{
2269 struct drm_gem_object *obj = reg->obj;
2270 struct drm_device *dev = obj->dev;
2271 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2272 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4e901fdc
EA		 2273 int regnum = obj_priv->fence_reg;
2274 uint64_t val;
2275
2276 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2277 0xfffff000) << 32;
2278 val |= obj_priv->gtt_offset & 0xfffff000;
2279 val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
2280 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2281
2282 if (obj_priv->tiling_mode == I915_TILING_Y)
2283 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2284 val |= I965_FENCE_REG_VALID;
2285
2286 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
2287}
2288
de151cf6
JB		 2289static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2290{
2291 struct drm_gem_object *obj = reg->obj;
2292 struct drm_device *dev = obj->dev;
2293 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2294 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 2295 int regnum = obj_priv->fence_reg;
2296 uint64_t val;
2297
2298 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2299 0xfffff000) << 32;
2300 val |= obj_priv->gtt_offset & 0xfffff000;
2301 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2302 if (obj_priv->tiling_mode == I915_TILING_Y)
2303 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2304 val |= I965_FENCE_REG_VALID;
2305
2306 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2307}
2308
2309static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2310{
2311 struct drm_gem_object *obj = reg->obj;
2312 struct drm_device *dev = obj->dev;
2313 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2314 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6 2315 int regnum = obj_priv->fence_reg;
0f973f27 2316 int tile_width;
dc529a4f 2317 uint32_t fence_reg, val;
de151cf6
JB		 2318 uint32_t pitch_val;
2319
2320 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2321 (obj_priv->gtt_offset & (obj->size - 1))) {
f06da264 2322 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
0f973f27 2323 __func__, obj_priv->gtt_offset, obj->size);
de151cf6
JB		 2324 return;
2325 }
2326
0f973f27
JB		 2327 if (obj_priv->tiling_mode == I915_TILING_Y &&
2328 HAS_128_BYTE_Y_TILING(dev))
2329 tile_width = 128;
de151cf6 2330 else
0f973f27
JB		 2331 tile_width = 512;
2332
2333 /* Note: pitch better be a power of two tile widths */
2334 pitch_val = obj_priv->stride / tile_width;
2335 pitch_val = ffs(pitch_val) - 1;
de151cf6 2336
c36a2a6d
DV		 2337 if (obj_priv->tiling_mode == I915_TILING_Y &&
2338 HAS_128_BYTE_Y_TILING(dev))
2339 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2340 else
2341 WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
2342
de151cf6
JB		 2343 val = obj_priv->gtt_offset;
2344 if (obj_priv->tiling_mode == I915_TILING_Y)
2345 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2346 val |= I915_FENCE_SIZE_BITS(obj->size);
2347 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2348 val |= I830_FENCE_REG_VALID;
2349
dc529a4f
EA		 2350 if (regnum < 8)
2351 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2352 else
2353 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2354 I915_WRITE(fence_reg, val);
de151cf6
JB		 2355}
2356
2357static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2358{
2359 struct drm_gem_object *obj = reg->obj;
2360 struct drm_device *dev = obj->dev;
2361 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2362 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 2363 int regnum = obj_priv->fence_reg;
2364 uint32_t val;
2365 uint32_t pitch_val;
8d7773a3 2366 uint32_t fence_size_bits;
de151cf6 2367
8d7773a3 2368 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
de151cf6 2369 (obj_priv->gtt_offset & (obj->size - 1))) {
8d7773a3 2370 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
0f973f27 2371 __func__, obj_priv->gtt_offset);
de151cf6
JB		 2372 return;
2373 }
2374
e76a16de
EA		 2375 pitch_val = obj_priv->stride / 128;
2376 pitch_val = ffs(pitch_val) - 1;
2377 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2378
de151cf6
JB		 2379 val = obj_priv->gtt_offset;
2380 if (obj_priv->tiling_mode == I915_TILING_Y)
2381 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
8d7773a3
DV		 2382 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2383 WARN_ON(fence_size_bits & ~0x00000f00);
2384 val |= fence_size_bits;
de151cf6
JB		 2385 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2386 val |= I830_FENCE_REG_VALID;
2387
2388 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
de151cf6
JB		 2389}
2390
ae3db24a
DV		 2391static int i915_find_fence_reg(struct drm_device *dev)
2392{
2393 struct drm_i915_fence_reg *reg = NULL;
2394 struct drm_i915_gem_object *obj_priv = NULL;
2395 struct drm_i915_private *dev_priv = dev->dev_private;
2396 struct drm_gem_object *obj = NULL;
2397 int i, avail, ret;
2398
2399 /* First try to find a free reg */
2400 avail = 0;
2401 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2402 reg = &dev_priv->fence_regs[i];
2403 if (!reg->obj)
2404 return i;
2405
23010e43 2406 obj_priv = to_intel_bo(reg->obj);
ae3db24a
DV		 2407 if (!obj_priv->pin_count)
2408 avail++;
2409 }
2410
2411 if (avail == 0)
2412 return -ENOSPC;
2413
2414 /* None available, try to steal one or wait for a user to finish */
2415 i = I915_FENCE_REG_NONE;
007cc8ac
DV		 2416 list_for_each_entry(reg, &dev_priv->mm.fence_list,
2417 lru_list) {
2418 obj = reg->obj;
2419 obj_priv = to_intel_bo(obj);
ae3db24a
DV		 2420
2421 if (obj_priv->pin_count)
2422 continue;
2423
2424 /* found one! */
2425 i = obj_priv->fence_reg;
2426 break;
2427 }
2428
2429 BUG_ON(i == I915_FENCE_REG_NONE);
2430
2431 /* We only have a reference on obj from the active list. put_fence_reg
2432 * might drop that one, causing a use-after-free in it. So hold a
2433 * private reference to obj like the other callers of put_fence_reg
2434 * (set_tiling ioctl) do. */
2435 drm_gem_object_reference(obj);
2436 ret = i915_gem_object_put_fence_reg(obj);
2437 drm_gem_object_unreference(obj);
2438 if (ret != 0)
2439 return ret;
2440
2441 return i;
2442}
2443
de151cf6
JB		 2444/**
2445 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2446 * @obj: object to map through a fence reg
2447 *
2448 * When mapping objects through the GTT, userspace wants to be able to write
2449 * to them without having to worry about swizzling if the object is tiled.
2450 *
2451 * This function walks the fence regs looking for a free one for @obj,
2452 * stealing one if it can't find any.
2453 *
2454 * It then sets up the reg based on the object's properties: address, pitch
2455 * and tiling format.
2456 */
8c4b8c3f
CW		 2457int
2458i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
de151cf6
JB		 2459{
2460 struct drm_device *dev = obj->dev;
79e53945 2461 struct drm_i915_private *dev_priv = dev->dev_private;
23010e43 2462 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6 2463 struct drm_i915_fence_reg *reg = NULL;
ae3db24a 2464 int ret;
de151cf6 2465
a09ba7fa
EA		 2466 /* Just update our place in the LRU if our fence is getting used. */
2467 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
007cc8ac
DV		 2468 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2469 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
a09ba7fa
EA		 2470 return 0;
2471 }
2472
de151cf6
JB		 2473 switch (obj_priv->tiling_mode) {
2474 case I915_TILING_NONE:
2475 WARN(1, "allocating a fence for non-tiled object?\n");
2476 break;
2477 case I915_TILING_X:
0f973f27
JB		 2478 if (!obj_priv->stride)
2479 return -EINVAL;
2480 WARN((obj_priv->stride & (512 - 1)),
2481 "object 0x%08x is X tiled but has non-512B pitch\n",
2482 obj_priv->gtt_offset);
de151cf6
JB		 2483 break;
2484 case I915_TILING_Y:
0f973f27
JB		 2485 if (!obj_priv->stride)
2486 return -EINVAL;
2487 WARN((obj_priv->stride & (128 - 1)),
2488 "object 0x%08x is Y tiled but has non-128B pitch\n",
2489 obj_priv->gtt_offset);
de151cf6
JB		 2490 break;
2491 }
2492
ae3db24a
DV		 2493 ret = i915_find_fence_reg(dev);
2494 if (ret < 0)
2495 return ret;
de151cf6 2496
ae3db24a
DV		 2497 obj_priv->fence_reg = ret;
2498 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
007cc8ac 2499 list_add_tail(&reg->lru_list, &dev_priv->mm.fence_list);
a09ba7fa 2500
de151cf6
JB		 2501 reg->obj = obj;
2502
4e901fdc
EA		 2503 if (IS_GEN6(dev))
2504 sandybridge_write_fence_reg(reg);
2505 else if (IS_I965G(dev))
de151cf6
JB		 2506 i965_write_fence_reg(reg);
2507 else if (IS_I9XX(dev))
2508 i915_write_fence_reg(reg);
2509 else
2510 i830_write_fence_reg(reg);
d9ddcb96 2511
ae3db24a
DV		 2512 trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
2513 obj_priv->tiling_mode);
1c5d22f7 2514
d9ddcb96 2515 return 0;
de151cf6
JB		 2516}
2517
2518/**
2519 * i915_gem_clear_fence_reg - clear out fence register info
2520 * @obj: object to clear
2521 *
2522 * Zeroes out the fence register itself and clears out the associated
2523 * data structures in dev_priv and obj_priv.
2524 */
2525static void
2526i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2527{
2528 struct drm_device *dev = obj->dev;
79e53945 2529 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2530 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
007cc8ac
DV		 2531 struct drm_i915_fence_reg *reg =
2532 &dev_priv->fence_regs[obj_priv->fence_reg];
de151cf6 2533
4e901fdc
EA		 2534 if (IS_GEN6(dev)) {
2535 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2536 (obj_priv->fence_reg * 8), 0);
2537 } else if (IS_I965G(dev)) {
de151cf6 2538 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
4e901fdc 2539 } else {
dc529a4f
EA		 2540 uint32_t fence_reg;
2541
2542 if (obj_priv->fence_reg < 8)
2543 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2544 else
2545 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2546 8) * 4;
2547
2548 I915_WRITE(fence_reg, 0);
2549 }
de151cf6 2550
007cc8ac 2551 reg->obj = NULL;
de151cf6 2552 obj_priv->fence_reg = I915_FENCE_REG_NONE;
007cc8ac 2553 list_del_init(&reg->lru_list);
de151cf6
JB		 2554}
2555
52dc7d32
CW		 2556/**
2557 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2558 * to the buffer to finish, and then resets the fence register.
2559 * @obj: tiled object holding a fence register.
2560 *
2561 * Zeroes out the fence register itself and clears out the associated
2562 * data structures in dev_priv and obj_priv.
2563 */
2564int
2565i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2566{
2567 struct drm_device *dev = obj->dev;
23010e43 2568 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
52dc7d32
CW		 2569
2570 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2571 return 0;
2572
10ae9bd2
DV		 2573 /* If we've changed tiling, GTT-mappings of the object
2574 * need to re-fault to ensure that the correct fence register
2575 * setup is in place.
2576 */
2577 i915_gem_release_mmap(obj);
2578
52dc7d32
CW		 2579 /* On the i915, GPU access to tiled buffers is via a fence,
2580 * therefore we must wait for any outstanding access to complete
2581 * before clearing the fence.
2582 */
2583 if (!IS_I965G(dev)) {
2584 int ret;
2585
2586 i915_gem_object_flush_gpu_write_domain(obj);
52dc7d32
CW		 2587 ret = i915_gem_object_wait_rendering(obj);
2588 if (ret != 0)
2589 return ret;
2590 }
2591
4a726612 2592 i915_gem_object_flush_gtt_write_domain(obj);
52dc7d32
CW		 2593 i915_gem_clear_fence_reg (obj);
2594
2595 return 0;
2596}
2597
673a394b
EA		 2598/**
2599 * Finds free space in the GTT aperture and binds the object there.
2600 */
2601static int
2602i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2603{
2604 struct drm_device *dev = obj->dev;
2605 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2606 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 2607 struct drm_mm_node *free_space;
4bdadb97 2608 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
07f73f69 2609 int ret;
673a394b 2610
bb6baf76 2611 if (obj_priv->madv != I915_MADV_WILLNEED) {
3ef94daa
CW		 2612 DRM_ERROR("Attempting to bind a purgeable object\n");
2613 return -EINVAL;
2614 }
2615
673a394b 2616 if (alignment == 0)
0f973f27 2617 alignment = i915_gem_get_gtt_alignment(obj);
8d7773a3 2618 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
673a394b
EA		 2619 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2620 return -EINVAL;
2621 }
2622
654fc607
CW		 2623 /* If the object is bigger than the entire aperture, reject it early
2624 * before evicting everything in a vain attempt to find space.
2625 */
2626 if (obj->size > dev->gtt_total) {
2627 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2628 return -E2BIG;
2629 }
2630
673a394b
EA		 2631 search_free:
2632 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2633 obj->size, alignment, 0);
2634 if (free_space != NULL) {
2635 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2636 alignment);
2637 if (obj_priv->gtt_space != NULL) {
2638 obj_priv->gtt_space->private = obj;
2639 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2640 }
2641 }
2642 if (obj_priv->gtt_space == NULL) {
2643 /* If the gtt is empty and we're still having trouble
2644 * fitting our object in, we're out of memory.
2645 */
2646#if WATCH_LRU
2647 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2648#endif
07f73f69 2649 ret = i915_gem_evict_something(dev, obj->size);
9731129c 2650 if (ret)
673a394b 2651 return ret;
9731129c 2652
673a394b
EA		 2653 goto search_free;
2654 }
2655
2656#if WATCH_BUF
cfd43c02 2657 DRM_INFO("Binding object of size %zd at 0x%08x\n",
673a394b
EA		 2658 obj->size, obj_priv->gtt_offset);
2659#endif
4bdadb97 2660 ret = i915_gem_object_get_pages(obj, gfpmask);
673a394b
EA		 2661 if (ret) {
2662 drm_mm_put_block(obj_priv->gtt_space);
2663 obj_priv->gtt_space = NULL;
07f73f69
CW		 2664
2665 if (ret == -ENOMEM) {
2666 /* first try to clear up some space from the GTT */
2667 ret = i915_gem_evict_something(dev, obj->size);
2668 if (ret) {
07f73f69 2669 /* now try to shrink everyone else */
4bdadb97
CW		 2670 if (gfpmask) {
2671 gfpmask = 0;
2672 goto search_free;
07f73f69
CW		 2673 }
2674
2675 return ret;
2676 }
2677
2678 goto search_free;
2679 }
2680
673a394b
EA		 2681 return ret;
2682 }
2683
673a394b
EA		 2684 /* Create an AGP memory structure pointing at our pages, and bind it
2685 * into the GTT.
2686 */
2687 obj_priv->agp_mem = drm_agp_bind_pages(dev,
856fa198 2688 obj_priv->pages,
07f73f69 2689 obj->size >> PAGE_SHIFT,
ba1eb1d8
KP		 2690 obj_priv->gtt_offset,
2691 obj_priv->agp_type);
673a394b 2692 if (obj_priv->agp_mem == NULL) {
856fa198 2693 i915_gem_object_put_pages(obj);
673a394b
EA		 2694 drm_mm_put_block(obj_priv->gtt_space);
2695 obj_priv->gtt_space = NULL;
07f73f69
CW		 2696
2697 ret = i915_gem_evict_something(dev, obj->size);
9731129c 2698 if (ret)
07f73f69 2699 return ret;
07f73f69
CW		 2700
2701 goto search_free;
673a394b
EA		 2702 }
2703 atomic_inc(&dev->gtt_count);
2704 atomic_add(obj->size, &dev->gtt_memory);
2705
2706 /* Assert that the object is not currently in any GPU domain. As it
2707 * wasn't in the GTT, there shouldn't be any way it could have been in
2708 * a GPU cache
2709 */
21d509e3
CW		 2710 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2711 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
673a394b 2712
1c5d22f7
CW		 2713 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2714
673a394b
EA		 2715 return 0;
2716}
2717
2718void
2719i915_gem_clflush_object(struct drm_gem_object *obj)
2720{
23010e43 2721 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 2722
2723 /* If we don't have a page list set up, then we're not pinned
2724 * to GPU, and we can ignore the cache flush because it'll happen
2725 * again at bind time.
2726 */
856fa198 2727 if (obj_priv->pages == NULL)
673a394b
EA		 2728 return;
2729
1c5d22f7 2730 trace_i915_gem_object_clflush(obj);
cfa16a0d 2731
856fa198 2732 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
673a394b
EA		 2733}
2734
e47c68e9
EA		 2735/** Flushes any GPU write domain for the object if it's dirty. */
2736static void
2737i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2738{
2739 struct drm_device *dev = obj->dev;
1c5d22f7 2740 uint32_t old_write_domain;
852835f3 2741 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
e47c68e9
EA		 2742
2743 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2744 return;
2745
2746 /* Queue the GPU write cache flushing we need. */
1c5d22f7 2747 old_write_domain = obj->write_domain;
e47c68e9 2748 i915_gem_flush(dev, 0, obj->write_domain);
852835f3 2749 (void) i915_add_request(dev, NULL, obj->write_domain, obj_priv->ring);
99fcb766 2750 BUG_ON(obj->write_domain);
1c5d22f7
CW		 2751
2752 trace_i915_gem_object_change_domain(obj,
2753 obj->read_domains,
2754 old_write_domain);
e47c68e9
EA		 2755}
2756
2757/** Flushes the GTT write domain for the object if it's dirty. */
2758static void
2759i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2760{
1c5d22f7
CW		 2761 uint32_t old_write_domain;
2762
e47c68e9
EA		 2763 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2764 return;
2765
2766 /* No actual flushing is required for the GTT write domain. Writes
2767 * to it immediately go to main memory as far as we know, so there's
2768 * no chipset flush. It also doesn't land in render cache.
2769 */
1c5d22f7 2770 old_write_domain = obj->write_domain;
e47c68e9 2771 obj->write_domain = 0;
1c5d22f7
CW		 2772
2773 trace_i915_gem_object_change_domain(obj,
2774 obj->read_domains,
2775 old_write_domain);
e47c68e9
EA		 2776}
2777
2778/** Flushes the CPU write domain for the object if it's dirty. */
2779static void
2780i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2781{
2782 struct drm_device *dev = obj->dev;
1c5d22f7 2783 uint32_t old_write_domain;
e47c68e9
EA		 2784
2785 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2786 return;
2787
2788 i915_gem_clflush_object(obj);
2789 drm_agp_chipset_flush(dev);
1c5d22f7 2790 old_write_domain = obj->write_domain;
e47c68e9 2791 obj->write_domain = 0;
1c5d22f7
CW		 2792
2793 trace_i915_gem_object_change_domain(obj,
2794 obj->read_domains,
2795 old_write_domain);
e47c68e9
EA		 2796}
2797
6b95a207
KH		 2798void
2799i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
2800{
2801 switch (obj->write_domain) {
2802 case I915_GEM_DOMAIN_GTT:
2803 i915_gem_object_flush_gtt_write_domain(obj);
2804 break;
2805 case I915_GEM_DOMAIN_CPU:
2806 i915_gem_object_flush_cpu_write_domain(obj);
2807 break;
2808 default:
2809 i915_gem_object_flush_gpu_write_domain(obj);
2810 break;
2811 }
2812}
2813
2ef7eeaa
EA		 2814/**
2815 * Moves a single object to the GTT read, and possibly write domain.
2816 *
2817 * This function returns when the move is complete, including waiting on
2818 * flushes to occur.
2819 */
79e53945 2820int
2ef7eeaa
EA		 2821i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2822{
23010e43 2823 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1c5d22f7 2824 uint32_t old_write_domain, old_read_domains;
e47c68e9 2825 int ret;
2ef7eeaa 2826
02354392
EA		 2827 /* Not valid to be called on unbound objects. */
2828 if (obj_priv->gtt_space == NULL)
2829 return -EINVAL;
2830
e47c68e9
EA		 2831 i915_gem_object_flush_gpu_write_domain(obj);
2832 /* Wait on any GPU rendering and flushing to occur. */
2833 ret = i915_gem_object_wait_rendering(obj);
2834 if (ret != 0)
2835 return ret;
2836
1c5d22f7
CW		 2837 old_write_domain = obj->write_domain;
2838 old_read_domains = obj->read_domains;
2839
e47c68e9
EA		 2840 /* If we're writing through the GTT domain, then CPU and GPU caches
2841 * will need to be invalidated at next use.
2ef7eeaa 2842 */
e47c68e9
EA		 2843 if (write)
2844 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2ef7eeaa 2845
e47c68e9 2846 i915_gem_object_flush_cpu_write_domain(obj);
2ef7eeaa 2847
e47c68e9
EA		 2848 /* It should now be out of any other write domains, and we can update
2849 * the domain values for our changes.
2850 */
2851 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2852 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2853 if (write) {
2854 obj->write_domain = I915_GEM_DOMAIN_GTT;
2855 obj_priv->dirty = 1;
2ef7eeaa
EA		 2856 }
2857
1c5d22f7
CW		 2858 trace_i915_gem_object_change_domain(obj,
2859 old_read_domains,
2860 old_write_domain);
2861
e47c68e9
EA		 2862 return 0;
2863}
2864
b9241ea3
ZW		 2865/*
2866 * Prepare buffer for display plane. Use uninterruptible for possible flush
2867 * wait, as in modesetting process we're not supposed to be interrupted.
2868 */
2869int
2870i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
2871{
2872 struct drm_device *dev = obj->dev;
23010e43 2873 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
b9241ea3
ZW		 2874 uint32_t old_write_domain, old_read_domains;
2875 int ret;
2876
2877 /* Not valid to be called on unbound objects. */
2878 if (obj_priv->gtt_space == NULL)
2879 return -EINVAL;
2880
2881 i915_gem_object_flush_gpu_write_domain(obj);
2882
2883 /* Wait on any GPU rendering and flushing to occur. */
2884 if (obj_priv->active) {
2885#if WATCH_BUF
2886 DRM_INFO("%s: object %p wait for seqno %08x\n",
2887 __func__, obj, obj_priv->last_rendering_seqno);
2888#endif
852835f3
ZN		 2889 ret = i915_do_wait_request(dev,
2890 obj_priv->last_rendering_seqno,
2891 0,
2892 obj_priv->ring);
b9241ea3
ZW		 2893 if (ret != 0)
2894 return ret;
2895 }
2896
b118c1e3
CW		 2897 i915_gem_object_flush_cpu_write_domain(obj);
2898
b9241ea3
ZW		 2899 old_write_domain = obj->write_domain;
2900 old_read_domains = obj->read_domains;
2901
b9241ea3
ZW		 2902 /* It should now be out of any other write domains, and we can update
2903 * the domain values for our changes.
2904 */
2905 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
b118c1e3 2906 obj->read_domains = I915_GEM_DOMAIN_GTT;
b9241ea3
ZW		 2907 obj->write_domain = I915_GEM_DOMAIN_GTT;
2908 obj_priv->dirty = 1;
2909
2910 trace_i915_gem_object_change_domain(obj,
2911 old_read_domains,
2912 old_write_domain);
2913
2914 return 0;
2915}
2916
e47c68e9
EA		 2917/**
2918 * Moves a single object to the CPU read, and possibly write domain.
2919 *
2920 * This function returns when the move is complete, including waiting on
2921 * flushes to occur.
2922 */
2923static int
2924i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2925{
1c5d22f7 2926 uint32_t old_write_domain, old_read_domains;
e47c68e9
EA		 2927 int ret;
2928
2929 i915_gem_object_flush_gpu_write_domain(obj);
2ef7eeaa 2930 /* Wait on any GPU rendering and flushing to occur. */
e47c68e9
EA		 2931 ret = i915_gem_object_wait_rendering(obj);
2932 if (ret != 0)
2933 return ret;
2ef7eeaa 2934
e47c68e9 2935 i915_gem_object_flush_gtt_write_domain(obj);
2ef7eeaa 2936
e47c68e9
EA		 2937 /* If we have a partially-valid cache of the object in the CPU,
2938 * finish invalidating it and free the per-page flags.
2ef7eeaa 2939 */
e47c68e9 2940 i915_gem_object_set_to_full_cpu_read_domain(obj);
2ef7eeaa 2941
1c5d22f7
CW		 2942 old_write_domain = obj->write_domain;
2943 old_read_domains = obj->read_domains;
2944
e47c68e9
EA		 2945 /* Flush the CPU cache if it's still invalid. */
2946 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2ef7eeaa 2947 i915_gem_clflush_object(obj);
2ef7eeaa 2948
e47c68e9 2949 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2ef7eeaa
EA		 2950 }
2951
2952 /* It should now be out of any other write domains, and we can update
2953 * the domain values for our changes.
2954 */
e47c68e9
EA		 2955 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2956
2957 /* If we're writing through the CPU, then the GPU read domains will
2958 * need to be invalidated at next use.
2959 */
2960 if (write) {
2961 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2962 obj->write_domain = I915_GEM_DOMAIN_CPU;
2963 }
2ef7eeaa 2964
1c5d22f7
CW		 2965 trace_i915_gem_object_change_domain(obj,
2966 old_read_domains,
2967 old_write_domain);
2968
2ef7eeaa
EA		 2969 return 0;
2970}
2971
673a394b
EA		 2972/*
2973 * Set the next domain for the specified object. This
2974 * may not actually perform the necessary flushing/invaliding though,
2975 * as that may want to be batched with other set_domain operations
2976 *
2977 * This is (we hope) the only really tricky part of gem. The goal
2978 * is fairly simple -- track which caches hold bits of the object
2979 * and make sure they remain coherent. A few concrete examples may
2980 * help to explain how it works. For shorthand, we use the notation
2981 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2982 * a pair of read and write domain masks.
2983 *
2984 * Case 1: the batch buffer
2985 *
2986 * 1. Allocated
2987 * 2. Written by CPU
2988 * 3. Mapped to GTT
2989 * 4. Read by GPU
2990 * 5. Unmapped from GTT
2991 * 6. Freed
2992 *
2993 * Let's take these a step at a time
2994 *
2995 * 1. Allocated
2996 * Pages allocated from the kernel may still have
2997 * cache contents, so we set them to (CPU, CPU) always.
2998 * 2. Written by CPU (using pwrite)
2999 * The pwrite function calls set_domain (CPU, CPU) and
3000 * this function does nothing (as nothing changes)
3001 * 3. Mapped by GTT
3002 * This function asserts that the object is not
3003 * currently in any GPU-based read or write domains
3004 * 4. Read by GPU
3005 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
3006 * As write_domain is zero, this function adds in the
3007 * current read domains (CPU+COMMAND, 0).
3008 * flush_domains is set to CPU.
3009 * invalidate_domains is set to COMMAND
3010 * clflush is run to get data out of the CPU caches
3011 * then i915_dev_set_domain calls i915_gem_flush to
3012 * emit an MI_FLUSH and drm_agp_chipset_flush
3013 * 5. Unmapped from GTT
3014 * i915_gem_object_unbind calls set_domain (CPU, CPU)
3015 * flush_domains and invalidate_domains end up both zero
3016 * so no flushing/invalidating happens
3017 * 6. Freed
3018 * yay, done
3019 *
3020 * Case 2: The shared render buffer
3021 *
3022 * 1. Allocated
3023 * 2. Mapped to GTT
3024 * 3. Read/written by GPU
3025 * 4. set_domain to (CPU,CPU)
3026 * 5. Read/written by CPU
3027 * 6. Read/written by GPU
3028 *
3029 * 1. Allocated
3030 * Same as last example, (CPU, CPU)
3031 * 2. Mapped to GTT
3032 * Nothing changes (assertions find that it is not in the GPU)
3033 * 3. Read/written by GPU
3034 * execbuffer calls set_domain (RENDER, RENDER)
3035 * flush_domains gets CPU
3036 * invalidate_domains gets GPU
3037 * clflush (obj)
3038 * MI_FLUSH and drm_agp_chipset_flush
3039 * 4. set_domain (CPU, CPU)
3040 * flush_domains gets GPU
3041 * invalidate_domains gets CPU
3042 * wait_rendering (obj) to make sure all drawing is complete.
3043 * This will include an MI_FLUSH to get the data from GPU
3044 * to memory
3045 * clflush (obj) to invalidate the CPU cache
3046 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3047 * 5. Read/written by CPU
3048 * cache lines are loaded and dirtied
3049 * 6. Read written by GPU
3050 * Same as last GPU access
3051 *
3052 * Case 3: The constant buffer
3053 *
3054 * 1. Allocated
3055 * 2. Written by CPU
3056 * 3. Read by GPU
3057 * 4. Updated (written) by CPU again
3058 * 5. Read by GPU
3059 *
3060 * 1. Allocated
3061 * (CPU, CPU)
3062 * 2. Written by CPU
3063 * (CPU, CPU)
3064 * 3. Read by GPU
3065 * (CPU+RENDER, 0)
3066 * flush_domains = CPU
3067 * invalidate_domains = RENDER
3068 * clflush (obj)
3069 * MI_FLUSH
3070 * drm_agp_chipset_flush
3071 * 4. Updated (written) by CPU again
3072 * (CPU, CPU)
3073 * flush_domains = 0 (no previous write domain)
3074 * invalidate_domains = 0 (no new read domains)
3075 * 5. Read by GPU
3076 * (CPU+RENDER, 0)
3077 * flush_domains = CPU
3078 * invalidate_domains = RENDER
3079 * clflush (obj)
3080 * MI_FLUSH
3081 * drm_agp_chipset_flush
3082 */
c0d90829 3083static void
8b0e378a 3084i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
673a394b
EA		 3085{
3086 struct drm_device *dev = obj->dev;
23010e43 3087 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 3088 uint32_t invalidate_domains = 0;
3089 uint32_t flush_domains = 0;
1c5d22f7 3090 uint32_t old_read_domains;
e47c68e9 3091
8b0e378a
EA		 3092 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
3093 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
673a394b 3094
652c393a
JB		 3095 intel_mark_busy(dev, obj);
3096
673a394b
EA		 3097#if WATCH_BUF
3098 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
3099 __func__, obj,
8b0e378a
EA		 3100 obj->read_domains, obj->pending_read_domains,
3101 obj->write_domain, obj->pending_write_domain);
673a394b
EA		 3102#endif
3103 /*
3104 * If the object isn't moving to a new write domain,
3105 * let the object stay in multiple read domains
3106 */
8b0e378a
EA		 3107 if (obj->pending_write_domain == 0)
3108 obj->pending_read_domains |= obj->read_domains;
673a394b
EA		 3109 else
3110 obj_priv->dirty = 1;
3111
3112 /*
3113 * Flush the current write domain if
3114 * the new read domains don't match. Invalidate
3115 * any read domains which differ from the old
3116 * write domain
3117 */
8b0e378a
EA		 3118 if (obj->write_domain &&
3119 obj->write_domain != obj->pending_read_domains) {
673a394b 3120 flush_domains |= obj->write_domain;
8b0e378a
EA		 3121 invalidate_domains |=
3122 obj->pending_read_domains & ~obj->write_domain;
673a394b
EA		 3123 }
3124 /*
3125 * Invalidate any read caches which may have
3126 * stale data. That is, any new read domains.
3127 */
8b0e378a 3128 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
673a394b
EA		 3129 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3130#if WATCH_BUF
3131 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3132 __func__, flush_domains, invalidate_domains);
3133#endif
673a394b
EA		 3134 i915_gem_clflush_object(obj);
3135 }
3136
1c5d22f7
CW		 3137 old_read_domains = obj->read_domains;
3138
efbeed96
EA		 3139 /* The actual obj->write_domain will be updated with
3140 * pending_write_domain after we emit the accumulated flush for all
3141 * of our domain changes in execbuffers (which clears objects'
3142 * write_domains). So if we have a current write domain that we
3143 * aren't changing, set pending_write_domain to that.
3144 */
3145 if (flush_domains == 0 && obj->pending_write_domain == 0)
3146 obj->pending_write_domain = obj->write_domain;
8b0e378a 3147 obj->read_domains = obj->pending_read_domains;
673a394b
EA		 3148
3149 dev->invalidate_domains |= invalidate_domains;
3150 dev->flush_domains |= flush_domains;
3151#if WATCH_BUF
3152 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3153 __func__,
3154 obj->read_domains, obj->write_domain,
3155 dev->invalidate_domains, dev->flush_domains);
3156#endif
1c5d22f7
CW		 3157
3158 trace_i915_gem_object_change_domain(obj,
3159 old_read_domains,
3160 obj->write_domain);
673a394b
EA		 3161}
3162
3163/**
e47c68e9 3164 * Moves the object from a partially CPU read to a full one.
673a394b 3165 *
e47c68e9
EA		 3166 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3167 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
673a394b 3168 */
e47c68e9
EA		 3169static void
3170i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
673a394b 3171{
23010e43 3172 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 3173
e47c68e9
EA		 3174 if (!obj_priv->page_cpu_valid)
3175 return;
3176
3177 /* If we're partially in the CPU read domain, finish moving it in.
3178 */
3179 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3180 int i;
3181
3182 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3183 if (obj_priv->page_cpu_valid[i])
3184 continue;
856fa198 3185 drm_clflush_pages(obj_priv->pages + i, 1);
e47c68e9 3186 }
e47c68e9
EA		 3187 }
3188
3189 /* Free the page_cpu_valid mappings which are now stale, whether
3190 * or not we've got I915_GEM_DOMAIN_CPU.
3191 */
9a298b2a 3192 kfree(obj_priv->page_cpu_valid);
e47c68e9
EA		 3193 obj_priv->page_cpu_valid = NULL;
3194}
3195
3196/**
3197 * Set the CPU read domain on a range of the object.
3198 *
3199 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3200 * not entirely valid. The page_cpu_valid member of the object flags which
3201 * pages have been flushed, and will be respected by
3202 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3203 * of the whole object.
3204 *
3205 * This function returns when the move is complete, including waiting on
3206 * flushes to occur.
3207 */
3208static int
3209i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3210 uint64_t offset, uint64_t size)
3211{
23010e43 3212 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1c5d22f7 3213 uint32_t old_read_domains;
e47c68e9 3214 int i, ret;
673a394b 3215
e47c68e9
EA		 3216 if (offset == 0 && size == obj->size)
3217 return i915_gem_object_set_to_cpu_domain(obj, 0);
673a394b 3218
e47c68e9
EA		 3219 i915_gem_object_flush_gpu_write_domain(obj);
3220 /* Wait on any GPU rendering and flushing to occur. */
6a47baa6 3221 ret = i915_gem_object_wait_rendering(obj);
e47c68e9 3222 if (ret != 0)
6a47baa6 3223 return ret;
e47c68e9
EA		 3224 i915_gem_object_flush_gtt_write_domain(obj);
3225
3226 /* If we're already fully in the CPU read domain, we're done. */
3227 if (obj_priv->page_cpu_valid == NULL &&
3228 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3229 return 0;
673a394b 3230
e47c68e9
EA		 3231 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3232 * newly adding I915_GEM_DOMAIN_CPU
3233 */
673a394b 3234 if (obj_priv->page_cpu_valid == NULL) {
9a298b2a
EA		 3235 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3236 GFP_KERNEL);
e47c68e9
EA		 3237 if (obj_priv->page_cpu_valid == NULL)
3238 return -ENOMEM;
3239 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3240 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
673a394b
EA		 3241
3242 /* Flush the cache on any pages that are still invalid from the CPU's
3243 * perspective.
3244 */
e47c68e9
EA		 3245 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3246 i++) {
673a394b
EA		 3247 if (obj_priv->page_cpu_valid[i])
3248 continue;
3249
856fa198 3250 drm_clflush_pages(obj_priv->pages + i, 1);
673a394b
EA		 3251
3252 obj_priv->page_cpu_valid[i] = 1;
3253 }
3254
e47c68e9
EA		 3255 /* It should now be out of any other write domains, and we can update
3256 * the domain values for our changes.
3257 */
3258 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3259
1c5d22f7 3260 old_read_domains = obj->read_domains;
e47c68e9
EA		 3261 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3262
1c5d22f7
CW		 3263 trace_i915_gem_object_change_domain(obj,
3264 old_read_domains,
3265 obj->write_domain);
3266
673a394b
EA		 3267 return 0;
3268}
3269
673a394b
EA		 3270/**
3271 * Pin an object to the GTT and evaluate the relocations landing in it.
3272 */
3273static int
3274i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3275 struct drm_file *file_priv,
76446cac 3276 struct drm_i915_gem_exec_object2 *entry,
40a5f0de 3277 struct drm_i915_gem_relocation_entry *relocs)
673a394b
EA		 3278{
3279 struct drm_device *dev = obj->dev;
0839ccb8 3280 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 3281 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 3282 int i, ret;
0839ccb8 3283 void __iomem *reloc_page;
76446cac
JB		 3284 bool need_fence;
3285
3286 need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3287 obj_priv->tiling_mode != I915_TILING_NONE;
3288
3289 /* Check fence reg constraints and rebind if necessary */
808b24d6
CW		 3290 if (need_fence &&
3291 !i915_gem_object_fence_offset_ok(obj,
3292 obj_priv->tiling_mode)) {
3293 ret = i915_gem_object_unbind(obj);
3294 if (ret)
3295 return ret;
3296 }
673a394b
EA		 3297
3298 /* Choose the GTT offset for our buffer and put it there. */
3299 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3300 if (ret)
3301 return ret;
3302
76446cac
JB		 3303 /*
3304 * Pre-965 chips need a fence register set up in order to
3305 * properly handle blits to/from tiled surfaces.
3306 */
3307 if (need_fence) {
3308 ret = i915_gem_object_get_fence_reg(obj);
3309 if (ret != 0) {
76446cac
JB		 3310 i915_gem_object_unpin(obj);
3311 return ret;
3312 }
3313 }
3314
673a394b
EA		 3315 entry->offset = obj_priv->gtt_offset;
3316
673a394b
EA		 3317 /* Apply the relocations, using the GTT aperture to avoid cache
3318 * flushing requirements.
3319 */
3320 for (i = 0; i < entry->relocation_count; i++) {
40a5f0de 3321 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
673a394b
EA		 3322 struct drm_gem_object *target_obj;
3323 struct drm_i915_gem_object *target_obj_priv;
3043c60c
EA		 3324 uint32_t reloc_val, reloc_offset;
3325 uint32_t __iomem *reloc_entry;
673a394b 3326
673a394b 3327 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
40a5f0de 3328 reloc->target_handle);
673a394b
EA		 3329 if (target_obj == NULL) {
3330 i915_gem_object_unpin(obj);
3331 return -EBADF;
3332 }
23010e43 3333 target_obj_priv = to_intel_bo(target_obj);
673a394b 3334
8542a0bb
CW		 3335#if WATCH_RELOC
3336 DRM_INFO("%s: obj %p offset %08x target %d "
3337 "read %08x write %08x gtt %08x "
3338 "presumed %08x delta %08x\n",
3339 __func__,
3340 obj,
3341 (int) reloc->offset,
3342 (int) reloc->target_handle,
3343 (int) reloc->read_domains,
3344 (int) reloc->write_domain,
3345 (int) target_obj_priv->gtt_offset,
3346 (int) reloc->presumed_offset,
3347 reloc->delta);
3348#endif
3349
673a394b
EA		 3350 /* The target buffer should have appeared before us in the
3351 * exec_object list, so it should have a GTT space bound by now.
3352 */
3353 if (target_obj_priv->gtt_space == NULL) {
3354 DRM_ERROR("No GTT space found for object %d\n",
40a5f0de 3355 reloc->target_handle);
673a394b
EA		 3356 drm_gem_object_unreference(target_obj);
3357 i915_gem_object_unpin(obj);
3358 return -EINVAL;
3359 }
3360
8542a0bb 3361 /* Validate that the target is in a valid r/w GPU domain */
16edd550
DV		 3362 if (reloc->write_domain & (reloc->write_domain - 1)) {
3363 DRM_ERROR("reloc with multiple write domains: "
3364 "obj %p target %d offset %d "
3365 "read %08x write %08x",
3366 obj, reloc->target_handle,
3367 (int) reloc->offset,
3368 reloc->read_domains,
3369 reloc->write_domain);
3370 return -EINVAL;
3371 }
40a5f0de
EA		 3372 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3373 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
e47c68e9
EA		 3374 DRM_ERROR("reloc with read/write CPU domains: "
3375 "obj %p target %d offset %d "
3376 "read %08x write %08x",
40a5f0de
EA		 3377 obj, reloc->target_handle,
3378 (int) reloc->offset,
3379 reloc->read_domains,
3380 reloc->write_domain);
491152b8
CW		 3381 drm_gem_object_unreference(target_obj);
3382 i915_gem_object_unpin(obj);
e47c68e9
EA		 3383 return -EINVAL;
3384 }
40a5f0de
EA		 3385 if (reloc->write_domain && target_obj->pending_write_domain &&
3386 reloc->write_domain != target_obj->pending_write_domain) {
673a394b
EA		 3387 DRM_ERROR("Write domain conflict: "
3388 "obj %p target %d offset %d "
3389 "new %08x old %08x\n",
40a5f0de
EA		 3390 obj, reloc->target_handle,
3391 (int) reloc->offset,
3392 reloc->write_domain,
673a394b
EA		 3393 target_obj->pending_write_domain);
3394 drm_gem_object_unreference(target_obj);
3395 i915_gem_object_unpin(obj);
3396 return -EINVAL;
3397 }
3398
40a5f0de
EA		 3399 target_obj->pending_read_domains |= reloc->read_domains;
3400 target_obj->pending_write_domain |= reloc->write_domain;
673a394b
EA		 3401
3402 /* If the relocation already has the right value in it, no
3403 * more work needs to be done.
3404 */
40a5f0de 3405 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
673a394b
EA		 3406 drm_gem_object_unreference(target_obj);
3407 continue;
3408 }
3409
8542a0bb
CW		 3410 /* Check that the relocation address is valid... */
3411 if (reloc->offset > obj->size - 4) {
3412 DRM_ERROR("Relocation beyond object bounds: "
3413 "obj %p target %d offset %d size %d.\n",
3414 obj, reloc->target_handle,
3415 (int) reloc->offset, (int) obj->size);
3416 drm_gem_object_unreference(target_obj);
3417 i915_gem_object_unpin(obj);
3418 return -EINVAL;
3419 }
3420 if (reloc->offset & 3) {
3421 DRM_ERROR("Relocation not 4-byte aligned: "
3422 "obj %p target %d offset %d.\n",
3423 obj, reloc->target_handle,
3424 (int) reloc->offset);
3425 drm_gem_object_unreference(target_obj);
3426 i915_gem_object_unpin(obj);
3427 return -EINVAL;
3428 }
3429
3430 /* and points to somewhere within the target object. */
3431 if (reloc->delta >= target_obj->size) {
3432 DRM_ERROR("Relocation beyond target object bounds: "
3433 "obj %p target %d delta %d size %d.\n",
3434 obj, reloc->target_handle,
3435 (int) reloc->delta, (int) target_obj->size);
3436 drm_gem_object_unreference(target_obj);
3437 i915_gem_object_unpin(obj);
3438 return -EINVAL;
3439 }
3440
2ef7eeaa
EA		 3441 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3442 if (ret != 0) {
3443 drm_gem_object_unreference(target_obj);
3444 i915_gem_object_unpin(obj);
3445 return -EINVAL;
673a394b
EA		 3446 }
3447
3448 /* Map the page containing the relocation we're going to
3449 * perform.
3450 */
40a5f0de 3451 reloc_offset = obj_priv->gtt_offset + reloc->offset;
0839ccb8
KP		 3452 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3453 (reloc_offset &
3454 ~(PAGE_SIZE - 1)));
3043c60c 3455 reloc_entry = (uint32_t __iomem *)(reloc_page +
0839ccb8 3456 (reloc_offset & (PAGE_SIZE - 1)));
40a5f0de 3457 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
673a394b
EA		 3458
3459#if WATCH_BUF
3460 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
40a5f0de 3461 obj, (unsigned int) reloc->offset,
673a394b
EA		 3462 readl(reloc_entry), reloc_val);
3463#endif
3464 writel(reloc_val, reloc_entry);
0839ccb8 3465 io_mapping_unmap_atomic(reloc_page);
673a394b 3466
40a5f0de
EA		 3467 /* The updated presumed offset for this entry will be
3468 * copied back out to the user.
673a394b 3469 */
40a5f0de 3470 reloc->presumed_offset = target_obj_priv->gtt_offset;
673a394b
EA		 3471
3472 drm_gem_object_unreference(target_obj);
3473 }
3474
673a394b
EA		 3475#if WATCH_BUF
3476 if (0)
3477 i915_gem_dump_object(obj, 128, __func__, ~0);
3478#endif
3479 return 0;
3480}
3481
673a394b
EA		 3482/* Throttle our rendering by waiting until the ring has completed our requests
3483 * emitted over 20 msec ago.
3484 *
b962442e
EA		 3485 * Note that if we were to use the current jiffies each time around the loop,
3486 * we wouldn't escape the function with any frames outstanding if the time to
3487 * render a frame was over 20ms.
3488 *
673a394b
EA		 3489 * This should get us reasonable parallelism between CPU and GPU but also
3490 * relatively low latency when blocking on a particular request to finish.
3491 */
3492static int
3493i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3494{
3495 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3496 int ret = 0;
b962442e 3497 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
673a394b
EA		 3498
3499 mutex_lock(&dev->struct_mutex);
b962442e
EA		 3500 while (!list_empty(&i915_file_priv->mm.request_list)) {
3501 struct drm_i915_gem_request *request;
3502
3503 request = list_first_entry(&i915_file_priv->mm.request_list,
3504 struct drm_i915_gem_request,
3505 client_list);
3506
3507 if (time_after_eq(request->emitted_jiffies, recent_enough))
3508 break;
3509
852835f3 3510 ret = i915_wait_request(dev, request->seqno, request->ring);
b962442e
EA		 3511 if (ret != 0)
3512 break;
3513 }
673a394b 3514 mutex_unlock(&dev->struct_mutex);
b962442e 3515
673a394b
EA		 3516 return ret;
3517}
3518
40a5f0de 3519static int
76446cac 3520i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
40a5f0de
EA		 3521 uint32_t buffer_count,
3522 struct drm_i915_gem_relocation_entry **relocs)
3523{
3524 uint32_t reloc_count = 0, reloc_index = 0, i;
3525 int ret;
3526
3527 *relocs = NULL;
3528 for (i = 0; i < buffer_count; i++) {
3529 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3530 return -EINVAL;
3531 reloc_count += exec_list[i].relocation_count;
3532 }
3533
8e7d2b2c 3534 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
76446cac
JB		 3535 if (*relocs == NULL) {
3536 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
40a5f0de 3537 return -ENOMEM;
76446cac 3538 }
40a5f0de
EA		 3539
3540 for (i = 0; i < buffer_count; i++) {
3541 struct drm_i915_gem_relocation_entry __user *user_relocs;
3542
3543 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3544
3545 ret = copy_from_user(&(*relocs)[reloc_index],
3546 user_relocs,
3547 exec_list[i].relocation_count *
3548 sizeof(**relocs));
3549 if (ret != 0) {
8e7d2b2c 3550 drm_free_large(*relocs);
40a5f0de 3551 *relocs = NULL;
2bc43b5c 3552 return -EFAULT;
40a5f0de
EA		 3553 }
3554
3555 reloc_index += exec_list[i].relocation_count;
3556 }
3557
2bc43b5c 3558 return 0;
40a5f0de
EA		 3559}
3560
3561static int
76446cac 3562i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
40a5f0de
EA		 3563 uint32_t buffer_count,
3564 struct drm_i915_gem_relocation_entry *relocs)
3565{
3566 uint32_t reloc_count = 0, i;
2bc43b5c 3567 int ret = 0;
40a5f0de 3568
93533c29
CW		 3569 if (relocs == NULL)
3570 return 0;
3571
40a5f0de
EA		 3572 for (i = 0; i < buffer_count; i++) {
3573 struct drm_i915_gem_relocation_entry __user *user_relocs;
2bc43b5c 3574 int unwritten;
40a5f0de
EA		 3575
3576 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3577
2bc43b5c
FM		 3578 unwritten = copy_to_user(user_relocs,
3579 &relocs[reloc_count],
3580 exec_list[i].relocation_count *
3581 sizeof(*relocs));
3582
3583 if (unwritten) {
3584 ret = -EFAULT;
3585 goto err;
40a5f0de
EA		 3586 }
3587
3588 reloc_count += exec_list[i].relocation_count;
3589 }
3590
2bc43b5c 3591err:
8e7d2b2c 3592 drm_free_large(relocs);
40a5f0de
EA		 3593
3594 return ret;
3595}
3596
83d60795 3597static int
76446cac 3598i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
83d60795
CW		 3599 uint64_t exec_offset)
3600{
3601 uint32_t exec_start, exec_len;
3602
3603 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3604 exec_len = (uint32_t) exec->batch_len;
3605
3606 if ((exec_start | exec_len) & 0x7)
3607 return -EINVAL;
3608
3609 if (!exec_start)
3610 return -EINVAL;
3611
3612 return 0;
3613}
3614
6b95a207
KH		 3615static int
3616i915_gem_wait_for_pending_flip(struct drm_device *dev,
3617 struct drm_gem_object **object_list,
3618 int count)
3619{
3620 drm_i915_private_t *dev_priv = dev->dev_private;
3621 struct drm_i915_gem_object *obj_priv;
3622 DEFINE_WAIT(wait);
3623 int i, ret = 0;
3624
3625 for (;;) {
3626 prepare_to_wait(&dev_priv->pending_flip_queue,
3627 &wait, TASK_INTERRUPTIBLE);
3628 for (i = 0; i < count; i++) {
23010e43 3629 obj_priv = to_intel_bo(object_list[i]);
6b95a207
KH		 3630 if (atomic_read(&obj_priv->pending_flip) > 0)
3631 break;
3632 }
3633 if (i == count)
3634 break;
3635
3636 if (!signal_pending(current)) {
3637 mutex_unlock(&dev->struct_mutex);
3638 schedule();
3639 mutex_lock(&dev->struct_mutex);
3640 continue;
3641 }
3642 ret = -ERESTARTSYS;
3643 break;
3644 }
3645 finish_wait(&dev_priv->pending_flip_queue, &wait);
3646
3647 return ret;
3648}
3649
673a394b 3650int
76446cac
JB		 3651i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3652 struct drm_file *file_priv,
3653 struct drm_i915_gem_execbuffer2 *args,
3654 struct drm_i915_gem_exec_object2 *exec_list)
673a394b
EA		 3655{
3656 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b
EA		 3657 struct drm_gem_object **object_list = NULL;
3658 struct drm_gem_object *batch_obj;
b70d11da 3659 struct drm_i915_gem_object *obj_priv;
201361a5 3660 struct drm_clip_rect *cliprects = NULL;
93533c29 3661 struct drm_i915_gem_relocation_entry *relocs = NULL;
76446cac 3662 int ret = 0, ret2, i, pinned = 0;
673a394b 3663 uint64_t exec_offset;
40a5f0de 3664 uint32_t seqno, flush_domains, reloc_index;
6b95a207 3665 int pin_tries, flips;
673a394b 3666
852835f3
ZN		 3667 struct intel_ring_buffer *ring = NULL;
3668
673a394b
EA		 3669#if WATCH_EXEC
3670 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3671 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3672#endif
d1b851fc
ZN		 3673 if (args->flags & I915_EXEC_BSD) {
3674 if (!HAS_BSD(dev)) {
3675 DRM_ERROR("execbuf with wrong flag\n");
3676 return -EINVAL;
3677 }
3678 ring = &dev_priv->bsd_ring;
3679 } else {
3680 ring = &dev_priv->render_ring;
3681 }
3682
673a394b 3683
4f481ed2
EA		 3684 if (args->buffer_count < 1) {
3685 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3686 return -EINVAL;
3687 }
c8e0f93a 3688 object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
76446cac
JB		 3689 if (object_list == NULL) {
3690 DRM_ERROR("Failed to allocate object list for %d buffers\n",
673a394b
EA		 3691 args->buffer_count);
3692 ret = -ENOMEM;
3693 goto pre_mutex_err;
3694 }
673a394b 3695
201361a5 3696 if (args->num_cliprects != 0) {
9a298b2a
EA		 3697 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3698 GFP_KERNEL);
a40e8d31
OA		 3699 if (cliprects == NULL) {
3700 ret = -ENOMEM;
201361a5 3701 goto pre_mutex_err;
a40e8d31 3702 }
201361a5
EA		 3703
3704 ret = copy_from_user(cliprects,
3705 (struct drm_clip_rect __user *)
3706 (uintptr_t) args->cliprects_ptr,
3707 sizeof(*cliprects) * args->num_cliprects);
3708 if (ret != 0) {
3709 DRM_ERROR("copy %d cliprects failed: %d\n",
3710 args->num_cliprects, ret);
3711 goto pre_mutex_err;
3712 }
3713 }
3714
40a5f0de
EA		 3715 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3716 &relocs);
3717 if (ret != 0)
3718 goto pre_mutex_err;
3719
673a394b
EA		 3720 mutex_lock(&dev->struct_mutex);
3721
3722 i915_verify_inactive(dev, __FILE__, __LINE__);
3723
ba1234d1 3724 if (atomic_read(&dev_priv->mm.wedged)) {
673a394b 3725 mutex_unlock(&dev->struct_mutex);
a198bc80
CW		 3726 ret = -EIO;
3727 goto pre_mutex_err;
673a394b
EA		 3728 }
3729
3730 if (dev_priv->mm.suspended) {
673a394b 3731 mutex_unlock(&dev->struct_mutex);
a198bc80
CW		 3732 ret = -EBUSY;
3733 goto pre_mutex_err;
673a394b
EA		 3734 }
3735
ac94a962 3736 /* Look up object handles */
6b95a207 3737 flips = 0;
673a394b
EA		 3738 for (i = 0; i < args->buffer_count; i++) {
3739 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3740 exec_list[i].handle);
3741 if (object_list[i] == NULL) {
3742 DRM_ERROR("Invalid object handle %d at index %d\n",
3743 exec_list[i].handle, i);
0ce907f8
CW		 3744 /* prevent error path from reading uninitialized data */
3745 args->buffer_count = i + 1;
673a394b
EA		 3746 ret = -EBADF;
3747 goto err;
3748 }
b70d11da 3749
23010e43 3750 obj_priv = to_intel_bo(object_list[i]);
b70d11da
KH		 3751 if (obj_priv->in_execbuffer) {
3752 DRM_ERROR("Object %p appears more than once in object list\n",
3753 object_list[i]);
0ce907f8
CW		 3754 /* prevent error path from reading uninitialized data */
3755 args->buffer_count = i + 1;
b70d11da
KH		 3756 ret = -EBADF;
3757 goto err;
3758 }
3759 obj_priv->in_execbuffer = true;
6b95a207
KH		 3760 flips += atomic_read(&obj_priv->pending_flip);
3761 }
3762
3763 if (flips > 0) {
3764 ret = i915_gem_wait_for_pending_flip(dev, object_list,
3765 args->buffer_count);
3766 if (ret)
3767 goto err;
ac94a962 3768 }
673a394b 3769
ac94a962
KP		 3770 /* Pin and relocate */
3771 for (pin_tries = 0; ; pin_tries++) {
3772 ret = 0;
40a5f0de
EA		 3773 reloc_index = 0;
3774
ac94a962
KP		 3775 for (i = 0; i < args->buffer_count; i++) {
3776 object_list[i]->pending_read_domains = 0;
3777 object_list[i]->pending_write_domain = 0;
3778 ret = i915_gem_object_pin_and_relocate(object_list[i],
3779 file_priv,
40a5f0de
EA		 3780 &exec_list[i],
3781 &relocs[reloc_index]);
ac94a962
KP		 3782 if (ret)
3783 break;
3784 pinned = i + 1;
40a5f0de 3785 reloc_index += exec_list[i].relocation_count;
ac94a962
KP		 3786 }
3787 /* success */
3788 if (ret == 0)
3789 break;
3790
3791 /* error other than GTT full, or we've already tried again */
2939e1f5 3792 if (ret != -ENOSPC || pin_tries >= 1) {
07f73f69
CW		 3793 if (ret != -ERESTARTSYS) {
3794 unsigned long long total_size = 0;
3d1cc470
CW		 3795 int num_fences = 0;
3796 for (i = 0; i < args->buffer_count; i++) {
3797 obj_priv = object_list[i]->driver_private;
3798
07f73f69 3799 total_size += object_list[i]->size;
3d1cc470
CW		 3800 num_fences +=
3801 exec_list[i].flags & EXEC_OBJECT_NEEDS_FENCE &&
3802 obj_priv->tiling_mode != I915_TILING_NONE;
3803 }
3804 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n",
07f73f69 3805 pinned+1, args->buffer_count,
3d1cc470
CW		 3806 total_size, num_fences,
3807 ret);
07f73f69
CW		 3808 DRM_ERROR("%d objects [%d pinned], "
3809 "%d object bytes [%d pinned], "
3810 "%d/%d gtt bytes\n",
3811 atomic_read(&dev->object_count),
3812 atomic_read(&dev->pin_count),
3813 atomic_read(&dev->object_memory),
3814 atomic_read(&dev->pin_memory),
3815 atomic_read(&dev->gtt_memory),
3816 dev->gtt_total);
3817 }
673a394b
EA		 3818 goto err;
3819 }
ac94a962
KP		 3820
3821 /* unpin all of our buffers */
3822 for (i = 0; i < pinned; i++)
3823 i915_gem_object_unpin(object_list[i]);
b1177636 3824 pinned = 0;
ac94a962
KP		 3825
3826 /* evict everyone we can from the aperture */
3827 ret = i915_gem_evict_everything(dev);
07f73f69 3828 if (ret && ret != -ENOSPC)
ac94a962 3829 goto err;
673a394b
EA		 3830 }
3831
3832 /* Set the pending read domains for the batch buffer to COMMAND */
3833 batch_obj = object_list[args->buffer_count-1];
5f26a2c7
CW		 3834 if (batch_obj->pending_write_domain) {
3835 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3836 ret = -EINVAL;
3837 goto err;
3838 }
3839 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
673a394b 3840
83d60795
CW		 3841 /* Sanity check the batch buffer, prior to moving objects */
3842 exec_offset = exec_list[args->buffer_count - 1].offset;
3843 ret = i915_gem_check_execbuffer (args, exec_offset);
3844 if (ret != 0) {
3845 DRM_ERROR("execbuf with invalid offset/length\n");
3846 goto err;
3847 }
3848
673a394b
EA		 3849 i915_verify_inactive(dev, __FILE__, __LINE__);
3850
646f0f6e
KP		 3851 /* Zero the global flush/invalidate flags. These
3852 * will be modified as new domains are computed
3853 * for each object
3854 */
3855 dev->invalidate_domains = 0;
3856 dev->flush_domains = 0;
3857
673a394b
EA		 3858 for (i = 0; i < args->buffer_count; i++) {
3859 struct drm_gem_object *obj = object_list[i];
673a394b 3860
646f0f6e 3861 /* Compute new gpu domains and update invalidate/flush */
8b0e378a 3862 i915_gem_object_set_to_gpu_domain(obj);
673a394b
EA		 3863 }
3864
3865 i915_verify_inactive(dev, __FILE__, __LINE__);
3866
646f0f6e
KP		 3867 if (dev->invalidate_domains | dev->flush_domains) {
3868#if WATCH_EXEC
3869 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3870 __func__,
3871 dev->invalidate_domains,
3872 dev->flush_domains);
3873#endif
3874 i915_gem_flush(dev,
3875 dev->invalidate_domains,
3876 dev->flush_domains);
852835f3 3877 if (dev->flush_domains & I915_GEM_GPU_DOMAINS) {
b962442e 3878 (void)i915_add_request(dev, file_priv,
852835f3
ZN		 3879 dev->flush_domains,
3880 &dev_priv->render_ring);
3881
d1b851fc
ZN		 3882 if (HAS_BSD(dev))
3883 (void)i915_add_request(dev, file_priv,
3884 dev->flush_domains,
3885 &dev_priv->bsd_ring);
852835f3 3886 }
646f0f6e 3887 }
673a394b 3888
efbeed96
EA		 3889 for (i = 0; i < args->buffer_count; i++) {
3890 struct drm_gem_object *obj = object_list[i];
23010e43 3891 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1c5d22f7 3892 uint32_t old_write_domain = obj->write_domain;
efbeed96
EA		 3893
3894 obj->write_domain = obj->pending_write_domain;
99fcb766
DV		 3895 if (obj->write_domain)
3896 list_move_tail(&obj_priv->gpu_write_list,
3897 &dev_priv->mm.gpu_write_list);
3898 else
3899 list_del_init(&obj_priv->gpu_write_list);
3900
1c5d22f7
CW		 3901 trace_i915_gem_object_change_domain(obj,
3902 obj->read_domains,
3903 old_write_domain);
efbeed96
EA		 3904 }
3905
673a394b
EA		 3906 i915_verify_inactive(dev, __FILE__, __LINE__);
3907
3908#if WATCH_COHERENCY
3909 for (i = 0; i < args->buffer_count; i++) {
3910 i915_gem_object_check_coherency(object_list[i],
3911 exec_list[i].handle);
3912 }
3913#endif
3914
673a394b 3915#if WATCH_EXEC
6911a9b8 3916 i915_gem_dump_object(batch_obj,
673a394b
EA		 3917 args->batch_len,
3918 __func__,
3919 ~0);
3920#endif
3921
673a394b 3922 /* Exec the batchbuffer */
852835f3
ZN		 3923 ret = ring->dispatch_gem_execbuffer(dev, ring, args,
3924 cliprects, exec_offset);
673a394b
EA		 3925 if (ret) {
3926 DRM_ERROR("dispatch failed %d\n", ret);
3927 goto err;
3928 }
3929
3930 /*
3931 * Ensure that the commands in the batch buffer are
3932 * finished before the interrupt fires
3933 */
852835f3 3934 flush_domains = i915_retire_commands(dev, ring);
673a394b
EA		 3935
3936 i915_verify_inactive(dev, __FILE__, __LINE__);
3937
3938 /*
3939 * Get a seqno representing the execution of the current buffer,
3940 * which we can wait on. We would like to mitigate these interrupts,
3941 * likely by only creating seqnos occasionally (so that we have
3942 * *some* interrupts representing completion of buffers that we can
3943 * wait on when trying to clear up gtt space).
3944 */
852835f3 3945 seqno = i915_add_request(dev, file_priv, flush_domains, ring);
673a394b 3946 BUG_ON(seqno == 0);
673a394b
EA		 3947 for (i = 0; i < args->buffer_count; i++) {
3948 struct drm_gem_object *obj = object_list[i];
852835f3 3949 obj_priv = to_intel_bo(obj);
673a394b 3950
852835f3 3951 i915_gem_object_move_to_active(obj, seqno, ring);
673a394b
EA		 3952#if WATCH_LRU
3953 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3954#endif
3955 }
3956#if WATCH_LRU
3957 i915_dump_lru(dev, __func__);
3958#endif
3959
3960 i915_verify_inactive(dev, __FILE__, __LINE__);
3961
673a394b 3962err:
aad87dff
JL		 3963 for (i = 0; i < pinned; i++)
3964 i915_gem_object_unpin(object_list[i]);
3965
b70d11da
KH		 3966 for (i = 0; i < args->buffer_count; i++) {
3967 if (object_list[i]) {
23010e43 3968 obj_priv = to_intel_bo(object_list[i]);
b70d11da
KH		 3969 obj_priv->in_execbuffer = false;
3970 }
aad87dff 3971 drm_gem_object_unreference(object_list[i]);
b70d11da 3972 }
673a394b 3973
673a394b
EA		 3974 mutex_unlock(&dev->struct_mutex);
3975
93533c29 3976pre_mutex_err:
40a5f0de
EA		 3977 /* Copy the updated relocations out regardless of current error
3978 * state. Failure to update the relocs would mean that the next
3979 * time userland calls execbuf, it would do so with presumed offset
3980 * state that didn't match the actual object state.
3981 */
3982 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3983 relocs);
3984 if (ret2 != 0) {
3985 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3986
3987 if (ret == 0)
3988 ret = ret2;
3989 }
3990
8e7d2b2c 3991 drm_free_large(object_list);
9a298b2a 3992 kfree(cliprects);
673a394b
EA		 3993
3994 return ret;
3995}
3996
76446cac
JB		 3997/*
3998 * Legacy execbuffer just creates an exec2 list from the original exec object
3999 * list array and passes it to the real function.
4000 */
4001int
4002i915_gem_execbuffer(struct drm_device *dev, void *data,
4003 struct drm_file *file_priv)
4004{
4005 struct drm_i915_gem_execbuffer *args = data;
4006 struct drm_i915_gem_execbuffer2 exec2;
4007 struct drm_i915_gem_exec_object *exec_list = NULL;
4008 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4009 int ret, i;
4010
4011#if WATCH_EXEC
4012 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4013 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4014#endif
4015
4016 if (args->buffer_count < 1) {
4017 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
4018 return -EINVAL;
4019 }
4020
4021 /* Copy in the exec list from userland */
4022 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
4023 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4024 if (exec_list == NULL || exec2_list == NULL) {
4025 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4026 args->buffer_count);
4027 drm_free_large(exec_list);
4028 drm_free_large(exec2_list);
4029 return -ENOMEM;
4030 }
4031 ret = copy_from_user(exec_list,
4032 (struct drm_i915_relocation_entry __user *)
4033 (uintptr_t) args->buffers_ptr,
4034 sizeof(*exec_list) * args->buffer_count);
4035 if (ret != 0) {
4036 DRM_ERROR("copy %d exec entries failed %d\n",
4037 args->buffer_count, ret);
4038 drm_free_large(exec_list);
4039 drm_free_large(exec2_list);
4040 return -EFAULT;
4041 }
4042
4043 for (i = 0; i < args->buffer_count; i++) {
4044 exec2_list[i].handle = exec_list[i].handle;
4045 exec2_list[i].relocation_count = exec_list[i].relocation_count;
4046 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
4047 exec2_list[i].alignment = exec_list[i].alignment;
4048 exec2_list[i].offset = exec_list[i].offset;
4049 if (!IS_I965G(dev))
4050 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
4051 else
4052 exec2_list[i].flags = 0;
4053 }
4054
4055 exec2.buffers_ptr = args->buffers_ptr;
4056 exec2.buffer_count = args->buffer_count;
4057 exec2.batch_start_offset = args->batch_start_offset;
4058 exec2.batch_len = args->batch_len;
4059 exec2.DR1 = args->DR1;
4060 exec2.DR4 = args->DR4;
4061 exec2.num_cliprects = args->num_cliprects;
4062 exec2.cliprects_ptr = args->cliprects_ptr;
852835f3 4063 exec2.flags = I915_EXEC_RENDER;
76446cac
JB		 4064
4065 ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
4066 if (!ret) {
4067 /* Copy the new buffer offsets back to the user's exec list. */
4068 for (i = 0; i < args->buffer_count; i++)
4069 exec_list[i].offset = exec2_list[i].offset;
4070 /* ... and back out to userspace */
4071 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4072 (uintptr_t) args->buffers_ptr,
4073 exec_list,
4074 sizeof(*exec_list) * args->buffer_count);
4075 if (ret) {
4076 ret = -EFAULT;
4077 DRM_ERROR("failed to copy %d exec entries "
4078 "back to user (%d)\n",
4079 args->buffer_count, ret);
4080 }
76446cac
JB		 4081 }
4082
4083 drm_free_large(exec_list);
4084 drm_free_large(exec2_list);
4085 return ret;
4086}
4087
4088int
4089i915_gem_execbuffer2(struct drm_device *dev, void *data,
4090 struct drm_file *file_priv)
4091{
4092 struct drm_i915_gem_execbuffer2 *args = data;
4093 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4094 int ret;
4095
4096#if WATCH_EXEC
4097 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4098 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4099#endif
4100
4101 if (args->buffer_count < 1) {
4102 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
4103 return -EINVAL;
4104 }
4105
4106 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4107 if (exec2_list == NULL) {
4108 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4109 args->buffer_count);
4110 return -ENOMEM;
4111 }
4112 ret = copy_from_user(exec2_list,
4113 (struct drm_i915_relocation_entry __user *)
4114 (uintptr_t) args->buffers_ptr,
4115 sizeof(*exec2_list) * args->buffer_count);
4116 if (ret != 0) {
4117 DRM_ERROR("copy %d exec entries failed %d\n",
4118 args->buffer_count, ret);
4119 drm_free_large(exec2_list);
4120 return -EFAULT;
4121 }
4122
4123 ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4124 if (!ret) {
4125 /* Copy the new buffer offsets back to the user's exec list. */
4126 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4127 (uintptr_t) args->buffers_ptr,
4128 exec2_list,
4129 sizeof(*exec2_list) * args->buffer_count);
4130 if (ret) {
4131 ret = -EFAULT;
4132 DRM_ERROR("failed to copy %d exec entries "
4133 "back to user (%d)\n",
4134 args->buffer_count, ret);
4135 }
4136 }
4137
4138 drm_free_large(exec2_list);
4139 return ret;
4140}
4141
673a394b
EA		 4142int
4143i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4144{
4145 struct drm_device *dev = obj->dev;
23010e43 4146 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 4147 int ret;
4148
778c3544
DV		 4149 BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
4150
673a394b 4151 i915_verify_inactive(dev, __FILE__, __LINE__);
ac0c6b5a
CW		 4152
4153 if (obj_priv->gtt_space != NULL) {
4154 if (alignment == 0)
4155 alignment = i915_gem_get_gtt_alignment(obj);
4156 if (obj_priv->gtt_offset & (alignment - 1)) {
4157 ret = i915_gem_object_unbind(obj);
4158 if (ret)
4159 return ret;
4160 }
4161 }
4162
673a394b
EA		 4163 if (obj_priv->gtt_space == NULL) {
4164 ret = i915_gem_object_bind_to_gtt(obj, alignment);
9731129c 4165 if (ret)
673a394b 4166 return ret;
22c344e9 4167 }
76446cac 4168
673a394b
EA		 4169 obj_priv->pin_count++;
4170
4171 /* If the object is not active and not pending a flush,
4172 * remove it from the inactive list
4173 */
4174 if (obj_priv->pin_count == 1) {
4175 atomic_inc(&dev->pin_count);
4176 atomic_add(obj->size, &dev->pin_memory);
4177 if (!obj_priv->active &&
21d509e3 4178 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
673a394b
EA		 4179 !list_empty(&obj_priv->list))
4180 list_del_init(&obj_priv->list);
4181 }
4182 i915_verify_inactive(dev, __FILE__, __LINE__);
4183
4184 return 0;
4185}
4186
4187void
4188i915_gem_object_unpin(struct drm_gem_object *obj)
4189{
4190 struct drm_device *dev = obj->dev;
4191 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 4192 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 4193
4194 i915_verify_inactive(dev, __FILE__, __LINE__);
4195 obj_priv->pin_count--;
4196 BUG_ON(obj_priv->pin_count < 0);
4197 BUG_ON(obj_priv->gtt_space == NULL);
4198
4199 /* If the object is no longer pinned, and is
4200 * neither active nor being flushed, then stick it on
4201 * the inactive list
4202 */
4203 if (obj_priv->pin_count == 0) {
4204 if (!obj_priv->active &&
21d509e3 4205 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
673a394b
EA		 4206 list_move_tail(&obj_priv->list,
4207 &dev_priv->mm.inactive_list);
4208 atomic_dec(&dev->pin_count);
4209 atomic_sub(obj->size, &dev->pin_memory);
4210 }
4211 i915_verify_inactive(dev, __FILE__, __LINE__);
4212}
4213
4214int
4215i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4216 struct drm_file *file_priv)
4217{
4218 struct drm_i915_gem_pin *args = data;
4219 struct drm_gem_object *obj;
4220 struct drm_i915_gem_object *obj_priv;
4221 int ret;
4222
4223 mutex_lock(&dev->struct_mutex);
4224
4225 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4226 if (obj == NULL) {
4227 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4228 args->handle);
4229 mutex_unlock(&dev->struct_mutex);
4230 return -EBADF;
4231 }
23010e43 4232 obj_priv = to_intel_bo(obj);
673a394b 4233
bb6baf76
CW		 4234 if (obj_priv->madv != I915_MADV_WILLNEED) {
4235 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3ef94daa
CW		 4236 drm_gem_object_unreference(obj);
4237 mutex_unlock(&dev->struct_mutex);
4238 return -EINVAL;
4239 }
4240
79e53945
JB		 4241 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4242 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4243 args->handle);
96dec61d 4244 drm_gem_object_unreference(obj);
673a394b 4245 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 4246 return -EINVAL;
4247 }
4248
4249 obj_priv->user_pin_count++;
4250 obj_priv->pin_filp = file_priv;
4251 if (obj_priv->user_pin_count == 1) {
4252 ret = i915_gem_object_pin(obj, args->alignment);
4253 if (ret != 0) {
4254 drm_gem_object_unreference(obj);
4255 mutex_unlock(&dev->struct_mutex);
4256 return ret;
4257 }
673a394b
EA		 4258 }
4259
4260 /* XXX - flush the CPU caches for pinned objects
4261 * as the X server doesn't manage domains yet
4262 */
e47c68e9 4263 i915_gem_object_flush_cpu_write_domain(obj);
673a394b
EA		 4264 args->offset = obj_priv->gtt_offset;
4265 drm_gem_object_unreference(obj);
4266 mutex_unlock(&dev->struct_mutex);
4267
4268 return 0;
4269}
4270
4271int
4272i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4273 struct drm_file *file_priv)
4274{
4275 struct drm_i915_gem_pin *args = data;
4276 struct drm_gem_object *obj;
79e53945 4277 struct drm_i915_gem_object *obj_priv;
673a394b
EA		 4278
4279 mutex_lock(&dev->struct_mutex);
4280
4281 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4282 if (obj == NULL) {
4283 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4284 args->handle);
4285 mutex_unlock(&dev->struct_mutex);
4286 return -EBADF;
4287 }
4288
23010e43 4289 obj_priv = to_intel_bo(obj);
79e53945
JB		 4290 if (obj_priv->pin_filp != file_priv) {
4291 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4292 args->handle);
4293 drm_gem_object_unreference(obj);
4294 mutex_unlock(&dev->struct_mutex);
4295 return -EINVAL;
4296 }
4297 obj_priv->user_pin_count--;
4298 if (obj_priv->user_pin_count == 0) {
4299 obj_priv->pin_filp = NULL;
4300 i915_gem_object_unpin(obj);
4301 }
673a394b
EA		 4302
4303 drm_gem_object_unreference(obj);
4304 mutex_unlock(&dev->struct_mutex);
4305 return 0;
4306}
4307
4308int
4309i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4310 struct drm_file *file_priv)
4311{
4312 struct drm_i915_gem_busy *args = data;
4313 struct drm_gem_object *obj;
4314 struct drm_i915_gem_object *obj_priv;
852835f3 4315 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 4316
673a394b
EA		 4317 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4318 if (obj == NULL) {
4319 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4320 args->handle);
673a394b
EA		 4321 return -EBADF;
4322 }
4323
b1ce786c 4324 mutex_lock(&dev->struct_mutex);
f21289b3
EA		 4325 /* Update the active list for the hardware's current position.
4326 * Otherwise this only updates on a delayed timer or when irqs are
4327 * actually unmasked, and our working set ends up being larger than
4328 * required.
4329 */
852835f3 4330 i915_gem_retire_requests(dev, &dev_priv->render_ring);
f21289b3 4331
d1b851fc
ZN		 4332 if (HAS_BSD(dev))
4333 i915_gem_retire_requests(dev, &dev_priv->bsd_ring);
4334
23010e43 4335 obj_priv = to_intel_bo(obj);
c4de0a5d
EA		 4336 /* Don't count being on the flushing list against the object being
4337 * done. Otherwise, a buffer left on the flushing list but not getting
4338 * flushed (because nobody's flushing that domain) won't ever return
4339 * unbusy and get reused by libdrm's bo cache. The other expected
4340 * consumer of this interface, OpenGL's occlusion queries, also specs
4341 * that the objects get unbusy "eventually" without any interference.
4342 */
4343 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
673a394b
EA		 4344
4345 drm_gem_object_unreference(obj);
4346 mutex_unlock(&dev->struct_mutex);
4347 return 0;
4348}
4349
4350int
4351i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4352 struct drm_file *file_priv)
4353{
4354 return i915_gem_ring_throttle(dev, file_priv);
4355}
4356
3ef94daa
CW		 4357int
4358i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4359 struct drm_file *file_priv)
4360{
4361 struct drm_i915_gem_madvise *args = data;
4362 struct drm_gem_object *obj;
4363 struct drm_i915_gem_object *obj_priv;
4364
4365 switch (args->madv) {
4366 case I915_MADV_DONTNEED:
4367 case I915_MADV_WILLNEED:
4368 break;
4369 default:
4370 return -EINVAL;
4371 }
4372
4373 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4374 if (obj == NULL) {
4375 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4376 args->handle);
4377 return -EBADF;
4378 }
4379
4380 mutex_lock(&dev->struct_mutex);
23010e43 4381 obj_priv = to_intel_bo(obj);
3ef94daa
CW		 4382
4383 if (obj_priv->pin_count) {
4384 drm_gem_object_unreference(obj);
4385 mutex_unlock(&dev->struct_mutex);
4386
4387 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4388 return -EINVAL;
4389 }
4390
bb6baf76
CW		 4391 if (obj_priv->madv != __I915_MADV_PURGED)
4392 obj_priv->madv = args->madv;
3ef94daa 4393
2d7ef395
CW		 4394 /* if the object is no longer bound, discard its backing storage */
4395 if (i915_gem_object_is_purgeable(obj_priv) &&
4396 obj_priv->gtt_space == NULL)
4397 i915_gem_object_truncate(obj);
4398
bb6baf76
CW		 4399 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4400
3ef94daa
CW		 4401 drm_gem_object_unreference(obj);
4402 mutex_unlock(&dev->struct_mutex);
4403
4404 return 0;
4405}
4406
ac52bc56
DV		 4407struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
4408 size_t size)
4409{
c397b908 4410 struct drm_i915_gem_object *obj;
ac52bc56 4411
c397b908
DV		 4412 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
4413 if (obj == NULL)
4414 return NULL;
673a394b 4415
c397b908
DV		 4416 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4417 kfree(obj);
4418 return NULL;
4419 }
673a394b 4420
c397b908
DV		 4421 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4422 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
673a394b 4423
c397b908 4424 obj->agp_type = AGP_USER_MEMORY;
62b8b215 4425 obj->base.driver_private = NULL;
c397b908
DV		 4426 obj->fence_reg = I915_FENCE_REG_NONE;
4427 INIT_LIST_HEAD(&obj->list);
4428 INIT_LIST_HEAD(&obj->gpu_write_list);
c397b908 4429 obj->madv = I915_MADV_WILLNEED;
de151cf6 4430
c397b908
DV		 4431 trace_i915_gem_object_create(&obj->base);
4432
4433 return &obj->base;
4434}
4435
4436int i915_gem_init_object(struct drm_gem_object *obj)
4437{
4438 BUG();
de151cf6 4439
673a394b
EA		 4440 return 0;
4441}
4442
4443void i915_gem_free_object(struct drm_gem_object *obj)
4444{
de151cf6 4445 struct drm_device *dev = obj->dev;
23010e43 4446 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 4447
1c5d22f7
CW		 4448 trace_i915_gem_object_destroy(obj);
4449
673a394b
EA		 4450 while (obj_priv->pin_count > 0)
4451 i915_gem_object_unpin(obj);
4452
71acb5eb
DA		 4453 if (obj_priv->phys_obj)
4454 i915_gem_detach_phys_object(dev, obj);
4455
673a394b
EA		 4456 i915_gem_object_unbind(obj);
4457
7e616158
CW		 4458 if (obj_priv->mmap_offset)
4459 i915_gem_free_mmap_offset(obj);
de151cf6 4460
c397b908
DV		 4461 drm_gem_object_release(obj);
4462
9a298b2a 4463 kfree(obj_priv->page_cpu_valid);
280b713b 4464 kfree(obj_priv->bit_17);
c397b908 4465 kfree(obj_priv);
673a394b
EA		 4466}
4467
ab5ee576 4468/** Unbinds all inactive objects. */
673a394b 4469static int
ab5ee576 4470i915_gem_evict_from_inactive_list(struct drm_device *dev)
673a394b 4471{
ab5ee576 4472 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 4473
ab5ee576
CW		 4474 while (!list_empty(&dev_priv->mm.inactive_list)) {
4475 struct drm_gem_object *obj;
4476 int ret;
673a394b 4477
a8089e84
DV		 4478 obj = &list_first_entry(&dev_priv->mm.inactive_list,
4479 struct drm_i915_gem_object,
4480 list)->base;
673a394b
EA		 4481
4482 ret = i915_gem_object_unbind(obj);
4483 if (ret != 0) {
ab5ee576 4484 DRM_ERROR("Error unbinding object: %d\n", ret);
673a394b
EA		 4485 return ret;
4486 }
4487 }
4488
673a394b
EA		 4489 return 0;
4490}
4491
29105ccc
CW		 4492int
4493i915_gem_idle(struct drm_device *dev)
4494{
4495 drm_i915_private_t *dev_priv = dev->dev_private;
4496 int ret;
28dfe52a 4497
29105ccc 4498 mutex_lock(&dev->struct_mutex);
1c5d22f7 4499
8187a2b7 4500 if (dev_priv->mm.suspended ||
d1b851fc
ZN		 4501 (dev_priv->render_ring.gem_object == NULL) ||
4502 (HAS_BSD(dev) &&
4503 dev_priv->bsd_ring.gem_object == NULL)) {
29105ccc
CW		 4504 mutex_unlock(&dev->struct_mutex);
4505 return 0;
28dfe52a
EA		 4506 }
4507
29105ccc 4508 ret = i915_gpu_idle(dev);
6dbe2772
KP		 4509 if (ret) {
4510 mutex_unlock(&dev->struct_mutex);
673a394b 4511 return ret;
6dbe2772 4512 }
673a394b 4513
29105ccc
CW		 4514 /* Under UMS, be paranoid and evict. */
4515 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
4516 ret = i915_gem_evict_from_inactive_list(dev);
4517 if (ret) {
4518 mutex_unlock(&dev->struct_mutex);
4519 return ret;
4520 }
4521 }
4522
4523 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4524 * We need to replace this with a semaphore, or something.
4525 * And not confound mm.suspended!
4526 */
4527 dev_priv->mm.suspended = 1;
4528 del_timer(&dev_priv->hangcheck_timer);
4529
4530 i915_kernel_lost_context(dev);
6dbe2772 4531 i915_gem_cleanup_ringbuffer(dev);
29105ccc 4532
6dbe2772
KP		 4533 mutex_unlock(&dev->struct_mutex);
4534
29105ccc
CW		 4535 /* Cancel the retire work handler, which should be idle now. */
4536 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4537
673a394b
EA		 4538 return 0;
4539}
4540
e552eb70
JB		 4541/*
4542 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4543 * over cache flushing.
4544 */
8187a2b7 4545static int
e552eb70
JB		 4546i915_gem_init_pipe_control(struct drm_device *dev)
4547{
4548 drm_i915_private_t *dev_priv = dev->dev_private;
4549 struct drm_gem_object *obj;
4550 struct drm_i915_gem_object *obj_priv;
4551 int ret;
4552
34dc4d44 4553 obj = i915_gem_alloc_object(dev, 4096);
e552eb70
JB		 4554 if (obj == NULL) {
4555 DRM_ERROR("Failed to allocate seqno page\n");
4556 ret = -ENOMEM;
4557 goto err;
4558 }
4559 obj_priv = to_intel_bo(obj);
4560 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4561
4562 ret = i915_gem_object_pin(obj, 4096);
4563 if (ret)
4564 goto err_unref;
4565
4566 dev_priv->seqno_gfx_addr = obj_priv->gtt_offset;
4567 dev_priv->seqno_page = kmap(obj_priv->pages[0]);
4568 if (dev_priv->seqno_page == NULL)
4569 goto err_unpin;
4570
4571 dev_priv->seqno_obj = obj;
4572 memset(dev_priv->seqno_page, 0, PAGE_SIZE);
4573
4574 return 0;
4575
4576err_unpin:
4577 i915_gem_object_unpin(obj);
4578err_unref:
4579 drm_gem_object_unreference(obj);
4580err:
4581 return ret;
4582}
4583
8187a2b7
ZN		 4584
4585static void
e552eb70
JB		 4586i915_gem_cleanup_pipe_control(struct drm_device *dev)
4587{
4588 drm_i915_private_t *dev_priv = dev->dev_private;
4589 struct drm_gem_object *obj;
4590 struct drm_i915_gem_object *obj_priv;
4591
4592 obj = dev_priv->seqno_obj;
4593 obj_priv = to_intel_bo(obj);
4594 kunmap(obj_priv->pages[0]);
4595 i915_gem_object_unpin(obj);
4596 drm_gem_object_unreference(obj);
4597 dev_priv->seqno_obj = NULL;
4598
4599 dev_priv->seqno_page = NULL;
673a394b
EA		 4600}
4601
8187a2b7
ZN		 4602int
4603i915_gem_init_ringbuffer(struct drm_device *dev)
4604{
4605 drm_i915_private_t *dev_priv = dev->dev_private;
4606 int ret;
68f95ba9 4607
8187a2b7 4608 dev_priv->render_ring = render_ring;
68f95ba9 4609
8187a2b7
ZN		 4610 if (!I915_NEED_GFX_HWS(dev)) {
4611 dev_priv->render_ring.status_page.page_addr
4612 = dev_priv->status_page_dmah->vaddr;
4613 memset(dev_priv->render_ring.status_page.page_addr,
4614 0, PAGE_SIZE);
4615 }
68f95ba9 4616
8187a2b7
ZN		 4617 if (HAS_PIPE_CONTROL(dev)) {
4618 ret = i915_gem_init_pipe_control(dev);
4619 if (ret)
4620 return ret;
4621 }
68f95ba9 4622
8187a2b7 4623 ret = intel_init_ring_buffer(dev, &dev_priv->render_ring);
68f95ba9
CW		 4624 if (ret)
4625 goto cleanup_pipe_control;
4626
4627 if (HAS_BSD(dev)) {
d1b851fc
ZN		 4628 dev_priv->bsd_ring = bsd_ring;
4629 ret = intel_init_ring_buffer(dev, &dev_priv->bsd_ring);
68f95ba9
CW		 4630 if (ret)
4631 goto cleanup_render_ring;
d1b851fc 4632 }
68f95ba9
CW		 4633
4634 return 0;
4635
4636cleanup_render_ring:
4637 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4638cleanup_pipe_control:
4639 if (HAS_PIPE_CONTROL(dev))
4640 i915_gem_cleanup_pipe_control(dev);
8187a2b7
ZN		 4641 return ret;
4642}
4643
4644void
4645i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4646{
4647 drm_i915_private_t *dev_priv = dev->dev_private;
4648
4649 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
d1b851fc
ZN		 4650 if (HAS_BSD(dev))
4651 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
8187a2b7
ZN		 4652 if (HAS_PIPE_CONTROL(dev))
4653 i915_gem_cleanup_pipe_control(dev);
4654}
4655
673a394b
EA		 4656int
4657i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4658 struct drm_file *file_priv)
4659{
4660 drm_i915_private_t *dev_priv = dev->dev_private;
4661 int ret;
4662
79e53945
JB		 4663 if (drm_core_check_feature(dev, DRIVER_MODESET))
4664 return 0;
4665
ba1234d1 4666 if (atomic_read(&dev_priv->mm.wedged)) {
673a394b 4667 DRM_ERROR("Reenabling wedged hardware, good luck\n");
ba1234d1 4668 atomic_set(&dev_priv->mm.wedged, 0);
673a394b
EA		 4669 }
4670
673a394b 4671 mutex_lock(&dev->struct_mutex);
9bb2d6f9
EA		 4672 dev_priv->mm.suspended = 0;
4673
4674 ret = i915_gem_init_ringbuffer(dev);
d816f6ac
WF		 4675 if (ret != 0) {
4676 mutex_unlock(&dev->struct_mutex);
9bb2d6f9 4677 return ret;
d816f6ac 4678 }
9bb2d6f9 4679
5e118f41 4680 spin_lock(&dev_priv->mm.active_list_lock);
852835f3 4681 BUG_ON(!list_empty(&dev_priv->render_ring.active_list));
d1b851fc 4682 BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.active_list));
5e118f41
CW		 4683 spin_unlock(&dev_priv->mm.active_list_lock);
4684
673a394b
EA		 4685 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4686 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
852835f3 4687 BUG_ON(!list_empty(&dev_priv->render_ring.request_list));
d1b851fc 4688 BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.request_list));
673a394b 4689 mutex_unlock(&dev->struct_mutex);
dbb19d30
KH		 4690
4691 drm_irq_install(dev);
4692
673a394b
EA		 4693 return 0;
4694}
4695
4696int
4697i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4698 struct drm_file *file_priv)
4699{
79e53945
JB		 4700 if (drm_core_check_feature(dev, DRIVER_MODESET))
4701 return 0;
4702
dbb19d30 4703 drm_irq_uninstall(dev);
e6890f6f 4704 return i915_gem_idle(dev);
673a394b
EA		 4705}
4706
4707void
4708i915_gem_lastclose(struct drm_device *dev)
4709{
4710 int ret;
673a394b 4711
e806b495
EA		 4712 if (drm_core_check_feature(dev, DRIVER_MODESET))
4713 return;
4714
6dbe2772
KP		 4715 ret = i915_gem_idle(dev);
4716 if (ret)
4717 DRM_ERROR("failed to idle hardware: %d\n", ret);
673a394b
EA		 4718}
4719
4720void
4721i915_gem_load(struct drm_device *dev)
4722{
b5aa8a0f 4723 int i;
673a394b
EA		 4724 drm_i915_private_t *dev_priv = dev->dev_private;
4725
5e118f41 4726 spin_lock_init(&dev_priv->mm.active_list_lock);
673a394b 4727 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
99fcb766 4728 INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
673a394b 4729 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
a09ba7fa 4730 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
852835f3
ZN		 4731 INIT_LIST_HEAD(&dev_priv->render_ring.active_list);
4732 INIT_LIST_HEAD(&dev_priv->render_ring.request_list);
d1b851fc
ZN		 4733 if (HAS_BSD(dev)) {
4734 INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list);
4735 INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list);
4736 }
007cc8ac
DV		 4737 for (i = 0; i < 16; i++)
4738 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
673a394b
EA		 4739 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4740 i915_gem_retire_work_handler);
31169714
CW		 4741 spin_lock(&shrink_list_lock);
4742 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4743 spin_unlock(&shrink_list_lock);
4744
de151cf6 4745 /* Old X drivers will take 0-2 for front, back, depth buffers */
b397c836
EA		 4746 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4747 dev_priv->fence_reg_start = 3;
de151cf6 4748
0f973f27 4749 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
de151cf6
JB		 4750 dev_priv->num_fence_regs = 16;
4751 else
4752 dev_priv->num_fence_regs = 8;
4753
b5aa8a0f
GH		 4754 /* Initialize fence registers to zero */
4755 if (IS_I965G(dev)) {
4756 for (i = 0; i < 16; i++)
4757 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4758 } else {
4759 for (i = 0; i < 8; i++)
4760 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4761 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4762 for (i = 0; i < 8; i++)
4763 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4764 }
673a394b 4765 i915_gem_detect_bit_6_swizzle(dev);
6b95a207 4766 init_waitqueue_head(&dev_priv->pending_flip_queue);
673a394b 4767}
71acb5eb
DA		 4768
4769/*
4770 * Create a physically contiguous memory object for this object
4771 * e.g. for cursor + overlay regs
4772 */
4773int i915_gem_init_phys_object(struct drm_device *dev,
4774 int id, int size)
4775{
4776 drm_i915_private_t *dev_priv = dev->dev_private;
4777 struct drm_i915_gem_phys_object *phys_obj;
4778 int ret;
4779
4780 if (dev_priv->mm.phys_objs[id - 1] || !size)
4781 return 0;
4782
9a298b2a 4783 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
71acb5eb
DA		 4784 if (!phys_obj)
4785 return -ENOMEM;
4786
4787 phys_obj->id = id;
4788
e6be8d9d 4789 phys_obj->handle = drm_pci_alloc(dev, size, 0);
71acb5eb
DA		 4790 if (!phys_obj->handle) {
4791 ret = -ENOMEM;
4792 goto kfree_obj;
4793 }
4794#ifdef CONFIG_X86
4795 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4796#endif
4797
4798 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4799
4800 return 0;
4801kfree_obj:
9a298b2a 4802 kfree(phys_obj);
71acb5eb
DA		 4803 return ret;
4804}
4805
4806void i915_gem_free_phys_object(struct drm_device *dev, int id)
4807{
4808 drm_i915_private_t *dev_priv = dev->dev_private;
4809 struct drm_i915_gem_phys_object *phys_obj;
4810
4811 if (!dev_priv->mm.phys_objs[id - 1])
4812 return;
4813
4814 phys_obj = dev_priv->mm.phys_objs[id - 1];
4815 if (phys_obj->cur_obj) {
4816 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4817 }
4818
4819#ifdef CONFIG_X86
4820 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4821#endif
4822 drm_pci_free(dev, phys_obj->handle);
4823 kfree(phys_obj);
4824 dev_priv->mm.phys_objs[id - 1] = NULL;
4825}
4826
4827void i915_gem_free_all_phys_object(struct drm_device *dev)
4828{
4829 int i;
4830
260883c8 4831 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
71acb5eb
DA		 4832 i915_gem_free_phys_object(dev, i);
4833}
4834
4835void i915_gem_detach_phys_object(struct drm_device *dev,
4836 struct drm_gem_object *obj)
4837{
4838 struct drm_i915_gem_object *obj_priv;
4839 int i;
4840 int ret;
4841 int page_count;
4842
23010e43 4843 obj_priv = to_intel_bo(obj);
71acb5eb
DA		 4844 if (!obj_priv->phys_obj)
4845 return;
4846
4bdadb97 4847 ret = i915_gem_object_get_pages(obj, 0);
71acb5eb
DA		 4848 if (ret)
4849 goto out;
4850
4851 page_count = obj->size / PAGE_SIZE;
4852
4853 for (i = 0; i < page_count; i++) {
856fa198 4854 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
71acb5eb
DA		 4855 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4856
4857 memcpy(dst, src, PAGE_SIZE);
4858 kunmap_atomic(dst, KM_USER0);
4859 }
856fa198 4860 drm_clflush_pages(obj_priv->pages, page_count);
71acb5eb 4861 drm_agp_chipset_flush(dev);
d78b47b9
CW		 4862
4863 i915_gem_object_put_pages(obj);
71acb5eb
DA		 4864out:
4865 obj_priv->phys_obj->cur_obj = NULL;
4866 obj_priv->phys_obj = NULL;
4867}
4868
4869int
4870i915_gem_attach_phys_object(struct drm_device *dev,
4871 struct drm_gem_object *obj, int id)
4872{
4873 drm_i915_private_t *dev_priv = dev->dev_private;
4874 struct drm_i915_gem_object *obj_priv;
4875 int ret = 0;
4876 int page_count;
4877 int i;
4878
4879 if (id > I915_MAX_PHYS_OBJECT)
4880 return -EINVAL;
4881
23010e43 4882 obj_priv = to_intel_bo(obj);
71acb5eb
DA		 4883
4884 if (obj_priv->phys_obj) {
4885 if (obj_priv->phys_obj->id == id)
4886 return 0;
4887 i915_gem_detach_phys_object(dev, obj);
4888 }
4889
4890
4891 /* create a new object */
4892 if (!dev_priv->mm.phys_objs[id - 1]) {
4893 ret = i915_gem_init_phys_object(dev, id,
4894 obj->size);
4895 if (ret) {
aeb565df 4896 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
71acb5eb
DA		 4897 goto out;
4898 }
4899 }
4900
4901 /* bind to the object */
4902 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4903 obj_priv->phys_obj->cur_obj = obj;
4904
4bdadb97 4905 ret = i915_gem_object_get_pages(obj, 0);
71acb5eb
DA		 4906 if (ret) {
4907 DRM_ERROR("failed to get page list\n");
4908 goto out;
4909 }
4910
4911 page_count = obj->size / PAGE_SIZE;
4912
4913 for (i = 0; i < page_count; i++) {
856fa198 4914 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
71acb5eb
DA		 4915 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4916
4917 memcpy(dst, src, PAGE_SIZE);
4918 kunmap_atomic(src, KM_USER0);
4919 }
4920
d78b47b9
CW		 4921 i915_gem_object_put_pages(obj);
4922
71acb5eb
DA		 4923 return 0;
4924out:
4925 return ret;
4926}
4927
4928static int
4929i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4930 struct drm_i915_gem_pwrite *args,
4931 struct drm_file *file_priv)
4932{
23010e43 4933 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
71acb5eb
DA		 4934 void *obj_addr;
4935 int ret;
4936 char __user *user_data;
4937
4938 user_data = (char __user *) (uintptr_t) args->data_ptr;
4939 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4940
44d98a61 4941 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
71acb5eb
DA		 4942 ret = copy_from_user(obj_addr, user_data, args->size);
4943 if (ret)
4944 return -EFAULT;
4945
4946 drm_agp_chipset_flush(dev);
4947 return 0;
4948}
b962442e
EA		 4949
4950void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
4951{
4952 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
4953
4954 /* Clean up our request list when the client is going away, so that
4955 * later retire_requests won't dereference our soon-to-be-gone
4956 * file_priv.
4957 */
4958 mutex_lock(&dev->struct_mutex);
4959 while (!list_empty(&i915_file_priv->mm.request_list))
4960 list_del_init(i915_file_priv->mm.request_list.next);
4961 mutex_unlock(&dev->struct_mutex);
4962}
31169714 4963
1637ef41
CW		 4964static int
4965i915_gpu_is_active(struct drm_device *dev)
4966{
4967 drm_i915_private_t *dev_priv = dev->dev_private;
4968 int lists_empty;
4969
4970 spin_lock(&dev_priv->mm.active_list_lock);
4971 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
852835f3 4972 list_empty(&dev_priv->render_ring.active_list);
d1b851fc
ZN		 4973 if (HAS_BSD(dev))
4974 lists_empty &= list_empty(&dev_priv->bsd_ring.active_list);
1637ef41
CW		 4975 spin_unlock(&dev_priv->mm.active_list_lock);
4976
4977 return !lists_empty;
4978}
4979
31169714
CW		 4980static int
4981i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask)
4982{
4983 drm_i915_private_t *dev_priv, *next_dev;
4984 struct drm_i915_gem_object *obj_priv, *next_obj;
4985 int cnt = 0;
4986 int would_deadlock = 1;
4987
4988 /* "fast-path" to count number of available objects */
4989 if (nr_to_scan == 0) {
4990 spin_lock(&shrink_list_lock);
4991 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4992 struct drm_device *dev = dev_priv->dev;
4993
4994 if (mutex_trylock(&dev->struct_mutex)) {
4995 list_for_each_entry(obj_priv,
4996 &dev_priv->mm.inactive_list,
4997 list)
4998 cnt++;
4999 mutex_unlock(&dev->struct_mutex);
5000 }
5001 }
5002 spin_unlock(&shrink_list_lock);
5003
5004 return (cnt / 100) * sysctl_vfs_cache_pressure;
5005 }
5006
5007 spin_lock(&shrink_list_lock);
5008
1637ef41 5009rescan:
31169714
CW		 5010 /* first scan for clean buffers */
5011 list_for_each_entry_safe(dev_priv, next_dev,
5012 &shrink_list, mm.shrink_list) {
5013 struct drm_device *dev = dev_priv->dev;
5014
5015 if (! mutex_trylock(&dev->struct_mutex))
5016 continue;
5017
5018 spin_unlock(&shrink_list_lock);
852835f3 5019 i915_gem_retire_requests(dev, &dev_priv->render_ring);
d1b851fc
ZN		 5020
5021 if (HAS_BSD(dev))
5022 i915_gem_retire_requests(dev, &dev_priv->bsd_ring);
31169714
CW		 5023
5024 list_for_each_entry_safe(obj_priv, next_obj,
5025 &dev_priv->mm.inactive_list,
5026 list) {
5027 if (i915_gem_object_is_purgeable(obj_priv)) {
a8089e84 5028 i915_gem_object_unbind(&obj_priv->base);
31169714
CW		 5029 if (--nr_to_scan <= 0)
5030 break;
5031 }
5032 }
5033
5034 spin_lock(&shrink_list_lock);
5035 mutex_unlock(&dev->struct_mutex);
5036
963b4836
CW		 5037 would_deadlock = 0;
5038
31169714
CW		 5039 if (nr_to_scan <= 0)
5040 break;
5041 }
5042
5043 /* second pass, evict/count anything still on the inactive list */
5044 list_for_each_entry_safe(dev_priv, next_dev,
5045 &shrink_list, mm.shrink_list) {
5046 struct drm_device *dev = dev_priv->dev;
5047
5048 if (! mutex_trylock(&dev->struct_mutex))
5049 continue;
5050
5051 spin_unlock(&shrink_list_lock);
5052
5053 list_for_each_entry_safe(obj_priv, next_obj,
5054 &dev_priv->mm.inactive_list,
5055 list) {
5056 if (nr_to_scan > 0) {
a8089e84 5057 i915_gem_object_unbind(&obj_priv->base);
31169714
CW		 5058 nr_to_scan--;
5059 } else
5060 cnt++;
5061 }
5062
5063 spin_lock(&shrink_list_lock);
5064 mutex_unlock(&dev->struct_mutex);
5065
5066 would_deadlock = 0;
5067 }
5068
1637ef41
CW		 5069 if (nr_to_scan) {
5070 int active = 0;
5071
5072 /*
5073 * We are desperate for pages, so as a last resort, wait
5074 * for the GPU to finish and discard whatever we can.
5075 * This has a dramatic impact to reduce the number of
5076 * OOM-killer events whilst running the GPU aggressively.
5077 */
5078 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
5079 struct drm_device *dev = dev_priv->dev;
5080
5081 if (!mutex_trylock(&dev->struct_mutex))
5082 continue;
5083
5084 spin_unlock(&shrink_list_lock);
5085
5086 if (i915_gpu_is_active(dev)) {
5087 i915_gpu_idle(dev);
5088 active++;
5089 }
5090
5091 spin_lock(&shrink_list_lock);
5092 mutex_unlock(&dev->struct_mutex);
5093 }
5094
5095 if (active)
5096 goto rescan;
5097 }
5098
31169714
CW		 5099 spin_unlock(&shrink_list_lock);
5100
5101 if (would_deadlock)
5102 return -1;
5103 else if (cnt > 0)
5104 return (cnt / 100) * sysctl_vfs_cache_pressure;
5105 else
5106 return 0;
5107}
5108
5109static struct shrinker shrinker = {
5110 .shrink = i915_gem_shrink,
5111 .seeks = DEFAULT_SEEKS,
5112};
5113
5114__init void
5115i915_gem_shrinker_init(void)
5116{
5117 register_shrinker(&shrinker);
5118}
5119
5120__exit void
5121i915_gem_shrinker_exit(void)
5122{
5123 unregister_shrinker(&shrinker);
5124}
Clone of davem's net-next-2.6 tree