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drm/i915: Prevent module unload to avoid random memory corruption
[net-next-2.6.git] / drivers / gpu / drm / i915 / i915_dma.c
CommitLineData
1da177e4
LT		 1/* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4
LT		 28
29#include "drmP.h"
30#include "drm.h"
79e53945 31#include "drm_crtc_helper.h"
785b93ef 32#include "drm_fb_helper.h"
79e53945 33#include "intel_drv.h"
1da177e4
LT		 34#include "i915_drm.h"
35#include "i915_drv.h"
1c5d22f7 36#include "i915_trace.h"
dcdb1674 37#include <linux/pci.h>
28d52043 38#include <linux/vgaarb.h>
c4804411
ZW		 39#include <linux/acpi.h>
40#include <linux/pnp.h>
6a9ee8af 41#include <linux/vga_switcheroo.h>
5a0e3ad6 42#include <linux/slab.h>
1da177e4 43
d1d6ca73
JB		 44extern int intel_max_stolen; /* from AGP driver */
45
398c9cb2
KP		 46/**
47 * Sets up the hardware status page for devices that need a physical address
48 * in the register.
49 */
3043c60c 50static int i915_init_phys_hws(struct drm_device *dev)
398c9cb2
KP		 51{
52 drm_i915_private_t *dev_priv = dev->dev_private;
53 /* Program Hardware Status Page */
54 dev_priv->status_page_dmah =
e6be8d9d 55 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
398c9cb2
KP		 56
57 if (!dev_priv->status_page_dmah) {
58 DRM_ERROR("Can not allocate hardware status page\n");
59 return -ENOMEM;
60 }
8187a2b7
ZN		 61 dev_priv->render_ring.status_page.page_addr
62 = dev_priv->status_page_dmah->vaddr;
398c9cb2
KP		 63 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
64
8187a2b7 65 memset(dev_priv->render_ring.status_page.page_addr, 0, PAGE_SIZE);
398c9cb2 66
9b974cc1
ZW		 67 if (IS_I965G(dev))
68 dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
69 0xf0;
70
398c9cb2 71 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
8a4c47f3 72 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
398c9cb2
KP		 73 return 0;
74}
75
76/**
77 * Frees the hardware status page, whether it's a physical address or a virtual
78 * address set up by the X Server.
79 */
3043c60c 80static void i915_free_hws(struct drm_device *dev)
398c9cb2
KP		 81{
82 drm_i915_private_t *dev_priv = dev->dev_private;
83 if (dev_priv->status_page_dmah) {
84 drm_pci_free(dev, dev_priv->status_page_dmah);
85 dev_priv->status_page_dmah = NULL;
86 }
87
852835f3
ZN		 88 if (dev_priv->render_ring.status_page.gfx_addr) {
89 dev_priv->render_ring.status_page.gfx_addr = 0;
398c9cb2
KP		 90 drm_core_ioremapfree(&dev_priv->hws_map, dev);
91 }
92
93 /* Need to rewrite hardware status page */
94 I915_WRITE(HWS_PGA, 0x1ffff000);
95}
96
84b1fd10 97void i915_kernel_lost_context(struct drm_device * dev)
1da177e4
LT		 98{
99 drm_i915_private_t *dev_priv = dev->dev_private;
7c1c2871 100 struct drm_i915_master_private *master_priv;
8187a2b7 101 struct intel_ring_buffer *ring = &dev_priv->render_ring;
1da177e4 102
79e53945
JB		 103 /*
104 * We should never lose context on the ring with modesetting
105 * as we don't expose it to userspace
106 */
107 if (drm_core_check_feature(dev, DRIVER_MODESET))
108 return;
109
585fb111
JB		 110 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
111 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
1da177e4
LT		 112 ring->space = ring->head - (ring->tail + 8);
113 if (ring->space < 0)
8187a2b7 114 ring->space += ring->size;
1da177e4 115
7c1c2871
DA		 116 if (!dev->primary->master)
117 return;
118
119 master_priv = dev->primary->master->driver_priv;
120 if (ring->head == ring->tail && master_priv->sarea_priv)
121 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
1da177e4
LT		 122}
123
84b1fd10 124static int i915_dma_cleanup(struct drm_device * dev)
1da177e4 125{
ba8bbcf6 126 drm_i915_private_t *dev_priv = dev->dev_private;
1da177e4
LT		 127 /* Make sure interrupts are disabled here because the uninstall ioctl
128 * may not have been called from userspace and after dev_private
129 * is freed, it's too late.
130 */
ed4cb414 131 if (dev->irq_enabled)
b5e89ed5 132 drm_irq_uninstall(dev);
1da177e4 133
ee0c6bfb 134 mutex_lock(&dev->struct_mutex);
8187a2b7 135 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
d1b851fc
ZN		 136 if (HAS_BSD(dev))
137 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
ee0c6bfb 138 mutex_unlock(&dev->struct_mutex);
dc7a9319 139
398c9cb2
KP		 140 /* Clear the HWS virtual address at teardown */
141 if (I915_NEED_GFX_HWS(dev))
142 i915_free_hws(dev);
1da177e4
LT		 143
144 return 0;
145}
146
ba8bbcf6 147static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
1da177e4 148{
ba8bbcf6 149 drm_i915_private_t *dev_priv = dev->dev_private;
7c1c2871 150 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1da177e4 151
3a03ac1a
DA		 152 master_priv->sarea = drm_getsarea(dev);
153 if (master_priv->sarea) {
154 master_priv->sarea_priv = (drm_i915_sarea_t *)
155 ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
156 } else {
8a4c47f3 157 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
3a03ac1a
DA		 158 }
159
673a394b 160 if (init->ring_size != 0) {
8187a2b7 161 if (dev_priv->render_ring.gem_object != NULL) {
673a394b
EA		 162 i915_dma_cleanup(dev);
163 DRM_ERROR("Client tried to initialize ringbuffer in "
164 "GEM mode\n");
165 return -EINVAL;
166 }
1da177e4 167
8187a2b7 168 dev_priv->render_ring.size = init->ring_size;
1da177e4 169
d3301d86
EA		 170 dev_priv->render_ring.map.offset = init->ring_start;
171 dev_priv->render_ring.map.size = init->ring_size;
172 dev_priv->render_ring.map.type = 0;
173 dev_priv->render_ring.map.flags = 0;
174 dev_priv->render_ring.map.mtrr = 0;
1da177e4 175
d3301d86 176 drm_core_ioremap_wc(&dev_priv->render_ring.map, dev);
673a394b 177
d3301d86 178 if (dev_priv->render_ring.map.handle == NULL) {
673a394b
EA		 179 i915_dma_cleanup(dev);
180 DRM_ERROR("can not ioremap virtual address for"
181 " ring buffer\n");
182 return -ENOMEM;
183 }
1da177e4
LT		 184 }
185
d3301d86 186 dev_priv->render_ring.virtual_start = dev_priv->render_ring.map.handle;
1da177e4 187
a6b54f3f 188 dev_priv->cpp = init->cpp;
1da177e4
LT		 189 dev_priv->back_offset = init->back_offset;
190 dev_priv->front_offset = init->front_offset;
191 dev_priv->current_page = 0;
7c1c2871
DA		 192 if (master_priv->sarea_priv)
193 master_priv->sarea_priv->pf_current_page = 0;
1da177e4 194
1da177e4
LT		 195 /* Allow hardware batchbuffers unless told otherwise.
196 */
197 dev_priv->allow_batchbuffer = 1;
198
1da177e4
LT		 199 return 0;
200}
201
84b1fd10 202static int i915_dma_resume(struct drm_device * dev)
1da177e4
LT		 203{
204 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
205
8187a2b7 206 struct intel_ring_buffer *ring;
8a4c47f3 207 DRM_DEBUG_DRIVER("%s\n", __func__);
1da177e4 208
8187a2b7
ZN		 209 ring = &dev_priv->render_ring;
210
211 if (ring->map.handle == NULL) {
1da177e4
LT		 212 DRM_ERROR("can not ioremap virtual address for"
213 " ring buffer\n");
20caafa6 214 return -ENOMEM;
1da177e4
LT		 215 }
216
217 /* Program Hardware Status Page */
8187a2b7 218 if (!ring->status_page.page_addr) {
1da177e4 219 DRM_ERROR("Can not find hardware status page\n");
20caafa6 220 return -EINVAL;
1da177e4 221 }
8a4c47f3 222 DRM_DEBUG_DRIVER("hw status page @ %p\n",
8187a2b7
ZN		 223 ring->status_page.page_addr);
224 if (ring->status_page.gfx_addr != 0)
225 ring->setup_status_page(dev, ring);
dc7a9319 226 else
585fb111 227 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
8187a2b7 228
8a4c47f3 229 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
1da177e4
LT		 230
231 return 0;
232}
233
c153f45f
EA		 234static int i915_dma_init(struct drm_device *dev, void *data,
235 struct drm_file *file_priv)
1da177e4 236{
c153f45f 237 drm_i915_init_t *init = data;
1da177e4
LT		 238 int retcode = 0;
239
c153f45f 240 switch (init->func) {
1da177e4 241 case I915_INIT_DMA:
ba8bbcf6 242 retcode = i915_initialize(dev, init);
1da177e4
LT		 243 break;
244 case I915_CLEANUP_DMA:
245 retcode = i915_dma_cleanup(dev);
246 break;
247 case I915_RESUME_DMA:
0d6aa60b 248 retcode = i915_dma_resume(dev);
1da177e4
LT		 249 break;
250 default:
20caafa6 251 retcode = -EINVAL;
1da177e4
LT		 252 break;
253 }
254
255 return retcode;
256}
257
258/* Implement basically the same security restrictions as hardware does
259 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
260 *
261 * Most of the calculations below involve calculating the size of a
262 * particular instruction. It's important to get the size right as
263 * that tells us where the next instruction to check is. Any illegal
264 * instruction detected will be given a size of zero, which is a
265 * signal to abort the rest of the buffer.
266 */
267static int do_validate_cmd(int cmd)
268{
269 switch (((cmd >> 29) & 0x7)) {
270 case 0x0:
271 switch ((cmd >> 23) & 0x3f) {
272 case 0x0:
273 return 1; /* MI_NOOP */
274 case 0x4:
275 return 1; /* MI_FLUSH */
276 default:
277 return 0; /* disallow everything else */
278 }
279 break;
280 case 0x1:
281 return 0; /* reserved */
282 case 0x2:
283 return (cmd & 0xff) + 2; /* 2d commands */
284 case 0x3:
285 if (((cmd >> 24) & 0x1f) <= 0x18)
286 return 1;
287
288 switch ((cmd >> 24) & 0x1f) {
289 case 0x1c:
290 return 1;
291 case 0x1d:
b5e89ed5 292 switch ((cmd >> 16) & 0xff) {
1da177e4
LT		 293 case 0x3:
294 return (cmd & 0x1f) + 2;
295 case 0x4:
296 return (cmd & 0xf) + 2;
297 default:
298 return (cmd & 0xffff) + 2;
299 }
300 case 0x1e:
301 if (cmd & (1 << 23))
302 return (cmd & 0xffff) + 1;
303 else
304 return 1;
305 case 0x1f:
306 if ((cmd & (1 << 23)) == 0) /* inline vertices */
307 return (cmd & 0x1ffff) + 2;
308 else if (cmd & (1 << 17)) /* indirect random */
309 if ((cmd & 0xffff) == 0)
310 return 0; /* unknown length, too hard */
311 else
312 return (((cmd & 0xffff) + 1) / 2) + 1;
313 else
314 return 2; /* indirect sequential */
315 default:
316 return 0;
317 }
318 default:
319 return 0;
320 }
321
322 return 0;
323}
324
325static int validate_cmd(int cmd)
326{
327 int ret = do_validate_cmd(cmd);
328
bc5f4523 329/* printk("validate_cmd( %x ): %d\n", cmd, ret); */
1da177e4
LT		 330
331 return ret;
332}
333
201361a5 334static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
1da177e4
LT		 335{
336 drm_i915_private_t *dev_priv = dev->dev_private;
337 int i;
1da177e4 338
8187a2b7 339 if ((dwords+1) * sizeof(int) >= dev_priv->render_ring.size - 8)
20caafa6 340 return -EINVAL;
de227f5f 341
c29b669c 342 BEGIN_LP_RING((dwords+1)&~1);
de227f5f 343
1da177e4
LT		 344 for (i = 0; i < dwords;) {
345 int cmd, sz;
346
201361a5 347 cmd = buffer[i];
1da177e4 348
1da177e4 349 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
20caafa6 350 return -EINVAL;
1da177e4 351
1da177e4
LT		 352 OUT_RING(cmd);
353
354 while (++i, --sz) {
201361a5 355 OUT_RING(buffer[i]);
1da177e4 356 }
1da177e4
LT		 357 }
358
de227f5f
DA		 359 if (dwords & 1)
360 OUT_RING(0);
361
362 ADVANCE_LP_RING();
363
1da177e4
LT		 364 return 0;
365}
366
673a394b
EA		 367int
368i915_emit_box(struct drm_device *dev,
201361a5 369 struct drm_clip_rect *boxes,
673a394b 370 int i, int DR1, int DR4)
1da177e4 371{
201361a5 372 struct drm_clip_rect box = boxes[i];
1da177e4 373
1da177e4
LT		 374 if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
375 DRM_ERROR("Bad box %d,%d..%d,%d\n",
376 box.x1, box.y1, box.x2, box.y2);
20caafa6 377 return -EINVAL;
1da177e4
LT		 378 }
379
c29b669c
AH		 380 if (IS_I965G(dev)) {
381 BEGIN_LP_RING(4);
382 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
383 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
78eca43d 384 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
c29b669c
AH		 385 OUT_RING(DR4);
386 ADVANCE_LP_RING();
387 } else {
388 BEGIN_LP_RING(6);
389 OUT_RING(GFX_OP_DRAWRECT_INFO);
390 OUT_RING(DR1);
391 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
392 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
393 OUT_RING(DR4);
394 OUT_RING(0);
395 ADVANCE_LP_RING();
396 }
1da177e4
LT		 397
398 return 0;
399}
400
c29b669c
AH		 401/* XXX: Emitting the counter should really be moved to part of the IRQ
402 * emit. For now, do it in both places:
403 */
404
84b1fd10 405static void i915_emit_breadcrumb(struct drm_device *dev)
de227f5f
DA		 406{
407 drm_i915_private_t *dev_priv = dev->dev_private;
7c1c2871 408 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
de227f5f 409
c99b058f 410 dev_priv->counter++;
af6061af 411 if (dev_priv->counter > 0x7FFFFFFFUL)
c99b058f 412 dev_priv->counter = 0;
7c1c2871
DA		 413 if (master_priv->sarea_priv)
414 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
de227f5f
DA		 415
416 BEGIN_LP_RING(4);
585fb111 417 OUT_RING(MI_STORE_DWORD_INDEX);
0baf823a 418 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
de227f5f
DA		 419 OUT_RING(dev_priv->counter);
420 OUT_RING(0);
421 ADVANCE_LP_RING();
422}
423
84b1fd10 424static int i915_dispatch_cmdbuffer(struct drm_device * dev,
201361a5
EA		 425 drm_i915_cmdbuffer_t *cmd,
426 struct drm_clip_rect *cliprects,
427 void *cmdbuf)
1da177e4
LT		 428{
429 int nbox = cmd->num_cliprects;
430 int i = 0, count, ret;
431
432 if (cmd->sz & 0x3) {
433 DRM_ERROR("alignment");
20caafa6 434 return -EINVAL;
1da177e4
LT		 435 }
436
437 i915_kernel_lost_context(dev);
438
439 count = nbox ? nbox : 1;
440
441 for (i = 0; i < count; i++) {
442 if (i < nbox) {
201361a5 443 ret = i915_emit_box(dev, cliprects, i,
1da177e4
LT		 444 cmd->DR1, cmd->DR4);
445 if (ret)
446 return ret;
447 }
448
201361a5 449 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
1da177e4
LT		 450 if (ret)
451 return ret;
452 }
453
de227f5f 454 i915_emit_breadcrumb(dev);
1da177e4
LT		 455 return 0;
456}
457
84b1fd10 458static int i915_dispatch_batchbuffer(struct drm_device * dev,
201361a5
EA		 459 drm_i915_batchbuffer_t * batch,
460 struct drm_clip_rect *cliprects)
1da177e4 461{
1da177e4
LT		 462 int nbox = batch->num_cliprects;
463 int i = 0, count;
1da177e4
LT		 464
465 if ((batch->start | batch->used) & 0x7) {
466 DRM_ERROR("alignment");
20caafa6 467 return -EINVAL;
1da177e4
LT		 468 }
469
470 i915_kernel_lost_context(dev);
471
472 count = nbox ? nbox : 1;
473
474 for (i = 0; i < count; i++) {
475 if (i < nbox) {
201361a5 476 int ret = i915_emit_box(dev, cliprects, i,
1da177e4
LT		 477 batch->DR1, batch->DR4);
478 if (ret)
479 return ret;
480 }
481
0790d5e1 482 if (!IS_I830(dev) && !IS_845G(dev)) {
1da177e4 483 BEGIN_LP_RING(2);
21f16289
DA		 484 if (IS_I965G(dev)) {
485 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
486 OUT_RING(batch->start);
487 } else {
488 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
489 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
490 }
1da177e4
LT		 491 ADVANCE_LP_RING();
492 } else {
493 BEGIN_LP_RING(4);
494 OUT_RING(MI_BATCH_BUFFER);
495 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
496 OUT_RING(batch->start + batch->used - 4);
497 OUT_RING(0);
498 ADVANCE_LP_RING();
499 }
500 }
501
1cafd347
ZN		 502
503 if (IS_G4X(dev) || IS_IRONLAKE(dev)) {
504 BEGIN_LP_RING(2);
505 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
506 OUT_RING(MI_NOOP);
507 ADVANCE_LP_RING();
508 }
de227f5f 509 i915_emit_breadcrumb(dev);
1da177e4
LT		 510
511 return 0;
512}
513
af6061af 514static int i915_dispatch_flip(struct drm_device * dev)
1da177e4
LT		 515{
516 drm_i915_private_t *dev_priv = dev->dev_private;
7c1c2871
DA		 517 struct drm_i915_master_private *master_priv =
518 dev->primary->master->driver_priv;
1da177e4 519
7c1c2871 520 if (!master_priv->sarea_priv)
c99b058f
KH		 521 return -EINVAL;
522
8a4c47f3 523 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
be25ed9c 524 __func__,
525 dev_priv->current_page,
526 master_priv->sarea_priv->pf_current_page);
1da177e4 527
af6061af
DA		 528 i915_kernel_lost_context(dev);
529
530 BEGIN_LP_RING(2);
585fb111 531 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
af6061af
DA		 532 OUT_RING(0);
533 ADVANCE_LP_RING();
1da177e4 534
af6061af
DA		 535 BEGIN_LP_RING(6);
536 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
537 OUT_RING(0);
538 if (dev_priv->current_page == 0) {
539 OUT_RING(dev_priv->back_offset);
540 dev_priv->current_page = 1;
1da177e4 541 } else {
af6061af
DA		 542 OUT_RING(dev_priv->front_offset);
543 dev_priv->current_page = 0;
1da177e4 544 }
af6061af
DA		 545 OUT_RING(0);
546 ADVANCE_LP_RING();
1da177e4 547
af6061af
DA		 548 BEGIN_LP_RING(2);
549 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
550 OUT_RING(0);
551 ADVANCE_LP_RING();
1da177e4 552
7c1c2871 553 master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
1da177e4
LT		 554
555 BEGIN_LP_RING(4);
585fb111 556 OUT_RING(MI_STORE_DWORD_INDEX);
0baf823a 557 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
af6061af
DA		 558 OUT_RING(dev_priv->counter);
559 OUT_RING(0);
1da177e4
LT		 560 ADVANCE_LP_RING();
561
7c1c2871 562 master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
af6061af 563 return 0;
1da177e4
LT		 564}
565
84b1fd10 566static int i915_quiescent(struct drm_device * dev)
1da177e4
LT		 567{
568 drm_i915_private_t *dev_priv = dev->dev_private;
569
570 i915_kernel_lost_context(dev);
8187a2b7
ZN		 571 return intel_wait_ring_buffer(dev, &dev_priv->render_ring,
572 dev_priv->render_ring.size - 8);
1da177e4
LT		 573}
574
c153f45f
EA		 575static int i915_flush_ioctl(struct drm_device *dev, void *data,
576 struct drm_file *file_priv)
1da177e4 577{
546b0974
EA		 578 int ret;
579
580 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 581
546b0974
EA		 582 mutex_lock(&dev->struct_mutex);
583 ret = i915_quiescent(dev);
584 mutex_unlock(&dev->struct_mutex);
585
586 return ret;
1da177e4
LT		 587}
588
c153f45f
EA		 589static int i915_batchbuffer(struct drm_device *dev, void *data,
590 struct drm_file *file_priv)
1da177e4 591{
1da177e4 592 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7c1c2871 593 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1da177e4 594 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
7c1c2871 595 master_priv->sarea_priv;
c153f45f 596 drm_i915_batchbuffer_t *batch = data;
1da177e4 597 int ret;
201361a5 598 struct drm_clip_rect *cliprects = NULL;
1da177e4
LT		 599
600 if (!dev_priv->allow_batchbuffer) {
601 DRM_ERROR("Batchbuffer ioctl disabled\n");
20caafa6 602 return -EINVAL;
1da177e4
LT		 603 }
604
8a4c47f3 605 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
be25ed9c 606 batch->start, batch->used, batch->num_cliprects);
1da177e4 607
546b0974 608 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 609
201361a5
EA		 610 if (batch->num_cliprects < 0)
611 return -EINVAL;
612
613 if (batch->num_cliprects) {
9a298b2a
EA		 614 cliprects = kcalloc(batch->num_cliprects,
615 sizeof(struct drm_clip_rect),
616 GFP_KERNEL);
201361a5
EA		 617 if (cliprects == NULL)
618 return -ENOMEM;
619
620 ret = copy_from_user(cliprects, batch->cliprects,
621 batch->num_cliprects *
622 sizeof(struct drm_clip_rect));
9927a403
DC		 623 if (ret != 0) {
624 ret = -EFAULT;
201361a5 625 goto fail_free;
9927a403 626 }
201361a5 627 }
1da177e4 628
546b0974 629 mutex_lock(&dev->struct_mutex);
201361a5 630 ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
546b0974 631 mutex_unlock(&dev->struct_mutex);
1da177e4 632
c99b058f 633 if (sarea_priv)
0baf823a 634 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
201361a5
EA		 635
636fail_free:
9a298b2a 637 kfree(cliprects);
201361a5 638
1da177e4
LT		 639 return ret;
640}
641
c153f45f
EA		 642static int i915_cmdbuffer(struct drm_device *dev, void *data,
643 struct drm_file *file_priv)
1da177e4 644{
1da177e4 645 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7c1c2871 646 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1da177e4 647 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
7c1c2871 648 master_priv->sarea_priv;
c153f45f 649 drm_i915_cmdbuffer_t *cmdbuf = data;
201361a5
EA		 650 struct drm_clip_rect *cliprects = NULL;
651 void *batch_data;
1da177e4
LT		 652 int ret;
653
8a4c47f3 654 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
be25ed9c 655 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
1da177e4 656
546b0974 657 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 658
201361a5
EA		 659 if (cmdbuf->num_cliprects < 0)
660 return -EINVAL;
661
9a298b2a 662 batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
201361a5
EA		 663 if (batch_data == NULL)
664 return -ENOMEM;
665
666 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
9927a403
DC		 667 if (ret != 0) {
668 ret = -EFAULT;
201361a5 669 goto fail_batch_free;
9927a403 670 }
201361a5
EA		 671
672 if (cmdbuf->num_cliprects) {
9a298b2a
EA		 673 cliprects = kcalloc(cmdbuf->num_cliprects,
674 sizeof(struct drm_clip_rect), GFP_KERNEL);
a40e8d31
OA		 675 if (cliprects == NULL) {
676 ret = -ENOMEM;
201361a5 677 goto fail_batch_free;
a40e8d31 678 }
201361a5
EA		 679
680 ret = copy_from_user(cliprects, cmdbuf->cliprects,
681 cmdbuf->num_cliprects *
682 sizeof(struct drm_clip_rect));
9927a403
DC		 683 if (ret != 0) {
684 ret = -EFAULT;
201361a5 685 goto fail_clip_free;
9927a403 686 }
1da177e4
LT		 687 }
688
546b0974 689 mutex_lock(&dev->struct_mutex);
201361a5 690 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
546b0974 691 mutex_unlock(&dev->struct_mutex);
1da177e4
LT		 692 if (ret) {
693 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
355d7f37 694 goto fail_clip_free;
1da177e4
LT		 695 }
696
c99b058f 697 if (sarea_priv)
0baf823a 698 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
201361a5 699
201361a5 700fail_clip_free:
9a298b2a 701 kfree(cliprects);
355d7f37 702fail_batch_free:
9a298b2a 703 kfree(batch_data);
201361a5
EA		 704
705 return ret;
1da177e4
LT		 706}
707
c153f45f
EA		 708static int i915_flip_bufs(struct drm_device *dev, void *data,
709 struct drm_file *file_priv)
1da177e4 710{
546b0974
EA		 711 int ret;
712
8a4c47f3 713 DRM_DEBUG_DRIVER("%s\n", __func__);
1da177e4 714
546b0974 715 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 716
546b0974
EA		 717 mutex_lock(&dev->struct_mutex);
718 ret = i915_dispatch_flip(dev);
719 mutex_unlock(&dev->struct_mutex);
720
721 return ret;
1da177e4
LT		 722}
723
c153f45f
EA		 724static int i915_getparam(struct drm_device *dev, void *data,
725 struct drm_file *file_priv)
1da177e4 726{
1da177e4 727 drm_i915_private_t *dev_priv = dev->dev_private;
c153f45f 728 drm_i915_getparam_t *param = data;
1da177e4
LT		 729 int value;
730
731 if (!dev_priv) {
3e684eae 732 DRM_ERROR("called with no initialization\n");
20caafa6 733 return -EINVAL;
1da177e4
LT		 734 }
735
c153f45f 736 switch (param->param) {
1da177e4 737 case I915_PARAM_IRQ_ACTIVE:
0a3e67a4 738 value = dev->pdev->irq ? 1 : 0;
1da177e4
LT		 739 break;
740 case I915_PARAM_ALLOW_BATCHBUFFER:
741 value = dev_priv->allow_batchbuffer ? 1 : 0;
742 break;
0d6aa60b
DA		 743 case I915_PARAM_LAST_DISPATCH:
744 value = READ_BREADCRUMB(dev_priv);
745 break;
ed4c9c4a
KH		 746 case I915_PARAM_CHIPSET_ID:
747 value = dev->pci_device;
748 break;
673a394b 749 case I915_PARAM_HAS_GEM:
ac5c4e76 750 value = dev_priv->has_gem;
673a394b 751 break;
0f973f27
JB		 752 case I915_PARAM_NUM_FENCES_AVAIL:
753 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
754 break;
02e792fb
DV		 755 case I915_PARAM_HAS_OVERLAY:
756 value = dev_priv->overlay ? 1 : 0;
757 break;
e9560f7c
JB		 758 case I915_PARAM_HAS_PAGEFLIPPING:
759 value = 1;
760 break;
76446cac
JB		 761 case I915_PARAM_HAS_EXECBUF2:
762 /* depends on GEM */
763 value = dev_priv->has_gem;
764 break;
e3a815fc
ZN		 765 case I915_PARAM_HAS_BSD:
766 value = HAS_BSD(dev);
767 break;
1da177e4 768 default:
8a4c47f3 769 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
76446cac 770 param->param);
20caafa6 771 return -EINVAL;
1da177e4
LT		 772 }
773
c153f45f 774 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
1da177e4 775 DRM_ERROR("DRM_COPY_TO_USER failed\n");
20caafa6 776 return -EFAULT;
1da177e4
LT		 777 }
778
779 return 0;
780}
781
c153f45f
EA		 782static int i915_setparam(struct drm_device *dev, void *data,
783 struct drm_file *file_priv)
1da177e4 784{
1da177e4 785 drm_i915_private_t *dev_priv = dev->dev_private;
c153f45f 786 drm_i915_setparam_t *param = data;
1da177e4
LT		 787
788 if (!dev_priv) {
3e684eae 789 DRM_ERROR("called with no initialization\n");
20caafa6 790 return -EINVAL;
1da177e4
LT		 791 }
792
c153f45f 793 switch (param->param) {
1da177e4 794 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1da177e4
LT		 795 break;
796 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
c153f45f 797 dev_priv->tex_lru_log_granularity = param->value;
1da177e4
LT		 798 break;
799 case I915_SETPARAM_ALLOW_BATCHBUFFER:
c153f45f 800 dev_priv->allow_batchbuffer = param->value;
1da177e4 801 break;
0f973f27
JB		 802 case I915_SETPARAM_NUM_USED_FENCES:
803 if (param->value > dev_priv->num_fence_regs ||
804 param->value < 0)
805 return -EINVAL;
806 /* Userspace can use first N regs */
807 dev_priv->fence_reg_start = param->value;
808 break;
1da177e4 809 default:
8a4c47f3 810 DRM_DEBUG_DRIVER("unknown parameter %d\n",
be25ed9c 811 param->param);
20caafa6 812 return -EINVAL;
1da177e4
LT		 813 }
814
815 return 0;
816}
817
c153f45f
EA		 818static int i915_set_status_page(struct drm_device *dev, void *data,
819 struct drm_file *file_priv)
dc7a9319 820{
dc7a9319 821 drm_i915_private_t *dev_priv = dev->dev_private;
c153f45f 822 drm_i915_hws_addr_t *hws = data;
8187a2b7 823 struct intel_ring_buffer *ring = &dev_priv->render_ring;
b39d50e5
ZW		 824
825 if (!I915_NEED_GFX_HWS(dev))
826 return -EINVAL;
dc7a9319
WZ		 827
828 if (!dev_priv) {
3e684eae 829 DRM_ERROR("called with no initialization\n");
20caafa6 830 return -EINVAL;
dc7a9319 831 }
dc7a9319 832
79e53945
JB		 833 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
834 WARN(1, "tried to set status page when mode setting active\n");
835 return 0;
836 }
837
8a4c47f3 838 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
c153f45f 839
8187a2b7 840 ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
dc7a9319 841
8b409580 842 dev_priv->hws_map.offset = dev->agp->base + hws->addr;
dc7a9319
WZ		 843 dev_priv->hws_map.size = 4*1024;
844 dev_priv->hws_map.type = 0;
845 dev_priv->hws_map.flags = 0;
846 dev_priv->hws_map.mtrr = 0;
847
dd0910b3 848 drm_core_ioremap_wc(&dev_priv->hws_map, dev);
dc7a9319 849 if (dev_priv->hws_map.handle == NULL) {
dc7a9319 850 i915_dma_cleanup(dev);
e20f9c64 851 ring->status_page.gfx_addr = 0;
dc7a9319
WZ		 852 DRM_ERROR("can not ioremap virtual address for"
853 " G33 hw status page\n");
20caafa6 854 return -ENOMEM;
dc7a9319 855 }
8187a2b7
ZN		 856 ring->status_page.page_addr = dev_priv->hws_map.handle;
857 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
858 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
dc7a9319 859
8a4c47f3 860 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
e20f9c64 861 ring->status_page.gfx_addr);
8a4c47f3 862 DRM_DEBUG_DRIVER("load hws at %p\n",
e20f9c64 863 ring->status_page.page_addr);
dc7a9319
WZ		 864 return 0;
865}
866
ec2a4c3f
DA		 867static int i915_get_bridge_dev(struct drm_device *dev)
868{
869 struct drm_i915_private *dev_priv = dev->dev_private;
870
871 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
872 if (!dev_priv->bridge_dev) {
873 DRM_ERROR("bridge device not found\n");
874 return -1;
875 }
876 return 0;
877}
878
c4804411
ZW		 879#define MCHBAR_I915 0x44
880#define MCHBAR_I965 0x48
881#define MCHBAR_SIZE (4*4096)
882
883#define DEVEN_REG 0x54
884#define DEVEN_MCHBAR_EN (1 << 28)
885
886/* Allocate space for the MCH regs if needed, return nonzero on error */
887static int
888intel_alloc_mchbar_resource(struct drm_device *dev)
889{
890 drm_i915_private_t *dev_priv = dev->dev_private;
891 int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
892 u32 temp_lo, temp_hi = 0;
893 u64 mchbar_addr;
a25c25c2 894 int ret;
c4804411
ZW		 895
896 if (IS_I965G(dev))
897 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
898 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
899 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
900
901 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
902#ifdef CONFIG_PNP
903 if (mchbar_addr &&
a25c25c2
CW		 904 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
905 return 0;
c4804411
ZW		 906#endif
907
908 /* Get some space for it */
a25c25c2
CW		 909 dev_priv->mch_res.name = "i915 MCHBAR";
910 dev_priv->mch_res.flags = IORESOURCE_MEM;
911 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
912 &dev_priv->mch_res,
c4804411
ZW		 913 MCHBAR_SIZE, MCHBAR_SIZE,
914 PCIBIOS_MIN_MEM,
a25c25c2 915 0, pcibios_align_resource,
c4804411
ZW		 916 dev_priv->bridge_dev);
917 if (ret) {
918 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
919 dev_priv->mch_res.start = 0;
a25c25c2 920 return ret;
c4804411
ZW		 921 }
922
923 if (IS_I965G(dev))
924 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
925 upper_32_bits(dev_priv->mch_res.start));
926
927 pci_write_config_dword(dev_priv->bridge_dev, reg,
928 lower_32_bits(dev_priv->mch_res.start));
a25c25c2 929 return 0;
c4804411
ZW		 930}
931
932/* Setup MCHBAR if possible, return true if we should disable it again */
933static void
934intel_setup_mchbar(struct drm_device *dev)
935{
936 drm_i915_private_t *dev_priv = dev->dev_private;
937 int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
938 u32 temp;
939 bool enabled;
940
941 dev_priv->mchbar_need_disable = false;
942
943 if (IS_I915G(dev) || IS_I915GM(dev)) {
944 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
945 enabled = !!(temp & DEVEN_MCHBAR_EN);
946 } else {
947 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
948 enabled = temp & 1;
949 }
950
951 /* If it's already enabled, don't have to do anything */
952 if (enabled)
953 return;
954
955 if (intel_alloc_mchbar_resource(dev))
956 return;
957
958 dev_priv->mchbar_need_disable = true;
959
960 /* Space is allocated or reserved, so enable it. */
961 if (IS_I915G(dev) || IS_I915GM(dev)) {
962 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
963 temp | DEVEN_MCHBAR_EN);
964 } else {
965 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
966 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
967 }
968}
969
970static void
971intel_teardown_mchbar(struct drm_device *dev)
972{
973 drm_i915_private_t *dev_priv = dev->dev_private;
974 int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
975 u32 temp;
976
977 if (dev_priv->mchbar_need_disable) {
978 if (IS_I915G(dev) || IS_I915GM(dev)) {
979 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
980 temp &= ~DEVEN_MCHBAR_EN;
981 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
982 } else {
983 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
984 temp &= ~1;
985 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
986 }
987 }
988
989 if (dev_priv->mch_res.start)
990 release_resource(&dev_priv->mch_res);
991}
992
79e53945
JB		 993/**
994 * i915_probe_agp - get AGP bootup configuration
995 * @pdev: PCI device
996 * @aperture_size: returns AGP aperture configured size
997 * @preallocated_size: returns size of BIOS preallocated AGP space
998 *
999 * Since Intel integrated graphics are UMA, the BIOS has to set aside
1000 * some RAM for the framebuffer at early boot. This code figures out
1001 * how much was set aside so we can use it for our own purposes.
1002 */
2a34f5e6 1003static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size,
80824003
JB		 1004 uint32_t *preallocated_size,
1005 uint32_t *start)
79e53945 1006{
ec2a4c3f 1007 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 1008 u16 tmp = 0;
1009 unsigned long overhead;
241fa85b 1010 unsigned long stolen;
79e53945 1011
79e53945 1012 /* Get the fb aperture size and "stolen" memory amount. */
ec2a4c3f 1013 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &tmp);
79e53945
JB		 1014
1015 *aperture_size = 1024 * 1024;
1016 *preallocated_size = 1024 * 1024;
1017
60fd99e3 1018 switch (dev->pdev->device) {
79e53945
JB		 1019 case PCI_DEVICE_ID_INTEL_82830_CGC:
1020 case PCI_DEVICE_ID_INTEL_82845G_IG:
1021 case PCI_DEVICE_ID_INTEL_82855GM_IG:
1022 case PCI_DEVICE_ID_INTEL_82865_IG:
1023 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
1024 *aperture_size *= 64;
1025 else
1026 *aperture_size *= 128;
1027 break;
1028 default:
1029 /* 9xx supports large sizes, just look at the length */
60fd99e3 1030 *aperture_size = pci_resource_len(dev->pdev, 2);
79e53945
JB		 1031 break;
1032 }
1033
1034 /*
1035 * Some of the preallocated space is taken by the GTT
1036 * and popup. GTT is 1K per MB of aperture size, and popup is 4K.
1037 */
bad720ff 1038 if (IS_G4X(dev) || IS_PINEVIEW(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev))
60fd99e3
EA		 1039 overhead = 4096;
1040 else
1041 overhead = (*aperture_size / 1024) + 4096;
1042
14bc490b
ZW		 1043 if (IS_GEN6(dev)) {
1044 /* SNB has memory control reg at 0x50.w */
1045 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &tmp);
1046
1047 switch (tmp & SNB_GMCH_GMS_STOLEN_MASK) {
1048 case INTEL_855_GMCH_GMS_DISABLED:
1049 DRM_ERROR("video memory is disabled\n");
1050 return -1;
1051 case SNB_GMCH_GMS_STOLEN_32M:
1052 stolen = 32 * 1024 * 1024;
1053 break;
1054 case SNB_GMCH_GMS_STOLEN_64M:
bad720ff 1055 stolen = 64 * 1024 * 1024;
14bc490b
ZW		 1056 break;
1057 case SNB_GMCH_GMS_STOLEN_96M:
1058 stolen = 96 * 1024 * 1024;
1059 break;
1060 case SNB_GMCH_GMS_STOLEN_128M:
1061 stolen = 128 * 1024 * 1024;
1062 break;
1063 case SNB_GMCH_GMS_STOLEN_160M:
1064 stolen = 160 * 1024 * 1024;
1065 break;
1066 case SNB_GMCH_GMS_STOLEN_192M:
1067 stolen = 192 * 1024 * 1024;
1068 break;
1069 case SNB_GMCH_GMS_STOLEN_224M:
1070 stolen = 224 * 1024 * 1024;
1071 break;
1072 case SNB_GMCH_GMS_STOLEN_256M:
1073 stolen = 256 * 1024 * 1024;
1074 break;
1075 case SNB_GMCH_GMS_STOLEN_288M:
1076 stolen = 288 * 1024 * 1024;
1077 break;
1078 case SNB_GMCH_GMS_STOLEN_320M:
1079 stolen = 320 * 1024 * 1024;
1080 break;
1081 case SNB_GMCH_GMS_STOLEN_352M:
1082 stolen = 352 * 1024 * 1024;
1083 break;
1084 case SNB_GMCH_GMS_STOLEN_384M:
1085 stolen = 384 * 1024 * 1024;
1086 break;
1087 case SNB_GMCH_GMS_STOLEN_416M:
1088 stolen = 416 * 1024 * 1024;
1089 break;
1090 case SNB_GMCH_GMS_STOLEN_448M:
1091 stolen = 448 * 1024 * 1024;
1092 break;
1093 case SNB_GMCH_GMS_STOLEN_480M:
1094 stolen = 480 * 1024 * 1024;
1095 break;
1096 case SNB_GMCH_GMS_STOLEN_512M:
1097 stolen = 512 * 1024 * 1024;
1098 break;
1099 default:
1100 DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1101 tmp & SNB_GMCH_GMS_STOLEN_MASK);
1102 return -1;
1103 }
1104 } else {
1105 switch (tmp & INTEL_GMCH_GMS_MASK) {
1106 case INTEL_855_GMCH_GMS_DISABLED:
bad720ff
EA		 1107 DRM_ERROR("video memory is disabled\n");
1108 return -1;
14bc490b
ZW		 1109 case INTEL_855_GMCH_GMS_STOLEN_1M:
1110 stolen = 1 * 1024 * 1024;
1111 break;
1112 case INTEL_855_GMCH_GMS_STOLEN_4M:
1113 stolen = 4 * 1024 * 1024;
1114 break;
1115 case INTEL_855_GMCH_GMS_STOLEN_8M:
1116 stolen = 8 * 1024 * 1024;
1117 break;
1118 case INTEL_855_GMCH_GMS_STOLEN_16M:
1119 stolen = 16 * 1024 * 1024;
1120 break;
1121 case INTEL_855_GMCH_GMS_STOLEN_32M:
1122 stolen = 32 * 1024 * 1024;
1123 break;
1124 case INTEL_915G_GMCH_GMS_STOLEN_48M:
1125 stolen = 48 * 1024 * 1024;
1126 break;
1127 case INTEL_915G_GMCH_GMS_STOLEN_64M:
1128 stolen = 64 * 1024 * 1024;
1129 break;
1130 case INTEL_GMCH_GMS_STOLEN_128M:
1131 stolen = 128 * 1024 * 1024;
1132 break;
1133 case INTEL_GMCH_GMS_STOLEN_256M:
1134 stolen = 256 * 1024 * 1024;
1135 break;
1136 case INTEL_GMCH_GMS_STOLEN_96M:
1137 stolen = 96 * 1024 * 1024;
1138 break;
1139 case INTEL_GMCH_GMS_STOLEN_160M:
1140 stolen = 160 * 1024 * 1024;
1141 break;
1142 case INTEL_GMCH_GMS_STOLEN_224M:
1143 stolen = 224 * 1024 * 1024;
1144 break;
1145 case INTEL_GMCH_GMS_STOLEN_352M:
1146 stolen = 352 * 1024 * 1024;
1147 break;
1148 default:
1149 DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1150 tmp & INTEL_GMCH_GMS_MASK);
1151 return -1;
bad720ff 1152 }
79e53945 1153 }
14bc490b 1154
241fa85b 1155 *preallocated_size = stolen - overhead;
80824003 1156 *start = overhead;
79e53945
JB		 1157
1158 return 0;
1159}
1160
80824003
JB		 1161#define PTE_ADDRESS_MASK 0xfffff000
1162#define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */
1163#define PTE_MAPPING_TYPE_UNCACHED (0 << 1)
1164#define PTE_MAPPING_TYPE_DCACHE (1 << 1) /* i830 only */
1165#define PTE_MAPPING_TYPE_CACHED (3 << 1)
1166#define PTE_MAPPING_TYPE_MASK (3 << 1)
1167#define PTE_VALID (1 << 0)
1168
1169/**
1170 * i915_gtt_to_phys - take a GTT address and turn it into a physical one
1171 * @dev: drm device
1172 * @gtt_addr: address to translate
1173 *
1174 * Some chip functions require allocations from stolen space but need the
1175 * physical address of the memory in question. We use this routine
1176 * to get a physical address suitable for register programming from a given
1177 * GTT address.
1178 */
1179static unsigned long i915_gtt_to_phys(struct drm_device *dev,
1180 unsigned long gtt_addr)
1181{
1182 unsigned long *gtt;
1183 unsigned long entry, phys;
1184 int gtt_bar = IS_I9XX(dev) ? 0 : 1;
1185 int gtt_offset, gtt_size;
1186
1187 if (IS_I965G(dev)) {
bad720ff 1188 if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
80824003
JB		 1189 gtt_offset = 2*1024*1024;
1190 gtt_size = 2*1024*1024;
1191 } else {
1192 gtt_offset = 512*1024;
1193 gtt_size = 512*1024;
1194 }
1195 } else {
1196 gtt_bar = 3;
1197 gtt_offset = 0;
1198 gtt_size = pci_resource_len(dev->pdev, gtt_bar);
1199 }
1200
1201 gtt = ioremap_wc(pci_resource_start(dev->pdev, gtt_bar) + gtt_offset,
1202 gtt_size);
1203 if (!gtt) {
1204 DRM_ERROR("ioremap of GTT failed\n");
1205 return 0;
1206 }
1207
1208 entry = *(volatile u32 *)(gtt + (gtt_addr / 1024));
1209
44d98a61 1210 DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry);
80824003
JB		 1211
1212 /* Mask out these reserved bits on this hardware. */
1213 if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev) ||
1214 IS_I945G(dev) || IS_I945GM(dev)) {
1215 entry &= ~PTE_ADDRESS_MASK_HIGH;
1216 }
1217
1218 /* If it's not a mapping type we know, then bail. */
1219 if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED &&
1220 (entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_CACHED) {
1221 iounmap(gtt);
1222 return 0;
1223 }
1224
1225 if (!(entry & PTE_VALID)) {
1226 DRM_ERROR("bad GTT entry in stolen space\n");
1227 iounmap(gtt);
1228 return 0;
1229 }
1230
1231 iounmap(gtt);
1232
1233 phys =(entry & PTE_ADDRESS_MASK) |
1234 ((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4));
1235
44d98a61 1236 DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys);
80824003
JB		 1237
1238 return phys;
1239}
1240
1241static void i915_warn_stolen(struct drm_device *dev)
1242{
1243 DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1244 DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1245}
1246
1247static void i915_setup_compression(struct drm_device *dev, int size)
1248{
1249 struct drm_i915_private *dev_priv = dev->dev_private;
132b6aab 1250 struct drm_mm_node *compressed_fb, *uninitialized_var(compressed_llb);
29bd0ae2
AM		 1251 unsigned long cfb_base;
1252 unsigned long ll_base = 0;
80824003
JB		 1253
1254 /* Leave 1M for line length buffer & misc. */
1255 compressed_fb = drm_mm_search_free(&dev_priv->vram, size, 4096, 0);
1256 if (!compressed_fb) {
b5e50c3f 1257 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
80824003
JB		 1258 i915_warn_stolen(dev);
1259 return;
1260 }
1261
1262 compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
1263 if (!compressed_fb) {
1264 i915_warn_stolen(dev);
b5e50c3f 1265 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
80824003
JB		 1266 return;
1267 }
1268
74dff282
JB		 1269 cfb_base = i915_gtt_to_phys(dev, compressed_fb->start);
1270 if (!cfb_base) {
1271 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1272 drm_mm_put_block(compressed_fb);
80824003
JB		 1273 }
1274
b52eb4dc 1275 if (!(IS_GM45(dev) || IS_IRONLAKE_M(dev))) {
74dff282
JB		 1276 compressed_llb = drm_mm_search_free(&dev_priv->vram, 4096,
1277 4096, 0);
1278 if (!compressed_llb) {
1279 i915_warn_stolen(dev);
1280 return;
1281 }
1282
1283 compressed_llb = drm_mm_get_block(compressed_llb, 4096, 4096);
1284 if (!compressed_llb) {
1285 i915_warn_stolen(dev);
1286 return;
1287 }
1288
1289 ll_base = i915_gtt_to_phys(dev, compressed_llb->start);
1290 if (!ll_base) {
1291 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1292 drm_mm_put_block(compressed_fb);
1293 drm_mm_put_block(compressed_llb);
1294 }
80824003
JB		 1295 }
1296
1297 dev_priv->cfb_size = size;
1298
ee5382ae 1299 intel_disable_fbc(dev);
20bf377e 1300 dev_priv->compressed_fb = compressed_fb;
b52eb4dc
ZY		 1301 if (IS_IRONLAKE_M(dev))
1302 I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start);
1303 else if (IS_GM45(dev)) {
74dff282
JB		 1304 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
1305 } else {
74dff282
JB		 1306 I915_WRITE(FBC_CFB_BASE, cfb_base);
1307 I915_WRITE(FBC_LL_BASE, ll_base);
20bf377e 1308 dev_priv->compressed_llb = compressed_llb;
80824003
JB		 1309 }
1310
b52eb4dc 1311 DRM_DEBUG_KMS("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base,
80824003 1312 ll_base, size >> 20);
80824003
JB		 1313}
1314
20bf377e
JB		 1315static void i915_cleanup_compression(struct drm_device *dev)
1316{
1317 struct drm_i915_private *dev_priv = dev->dev_private;
1318
1319 drm_mm_put_block(dev_priv->compressed_fb);
aebf0daf 1320 if (dev_priv->compressed_llb)
20bf377e
JB		 1321 drm_mm_put_block(dev_priv->compressed_llb);
1322}
1323
28d52043
DA		 1324/* true = enable decode, false = disable decoder */
1325static unsigned int i915_vga_set_decode(void *cookie, bool state)
1326{
1327 struct drm_device *dev = cookie;
1328
1329 intel_modeset_vga_set_state(dev, state);
1330 if (state)
1331 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1332 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1333 else
1334 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1335}
1336
6a9ee8af
DA		 1337static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1338{
1339 struct drm_device *dev = pci_get_drvdata(pdev);
1340 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1341 if (state == VGA_SWITCHEROO_ON) {
fbf81762 1342 printk(KERN_INFO "i915: switched on\n");
6a9ee8af
DA		 1343 /* i915 resume handler doesn't set to D0 */
1344 pci_set_power_state(dev->pdev, PCI_D0);
1345 i915_resume(dev);
fbf81762 1346 drm_kms_helper_poll_enable(dev);
6a9ee8af
DA		 1347 } else {
1348 printk(KERN_ERR "i915: switched off\n");
fbf81762 1349 drm_kms_helper_poll_disable(dev);
6a9ee8af
DA		 1350 i915_suspend(dev, pmm);
1351 }
1352}
1353
1354static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1355{
1356 struct drm_device *dev = pci_get_drvdata(pdev);
1357 bool can_switch;
1358
1359 spin_lock(&dev->count_lock);
1360 can_switch = (dev->open_count == 0);
1361 spin_unlock(&dev->count_lock);
1362 return can_switch;
1363}
1364
2a34f5e6 1365static int i915_load_modeset_init(struct drm_device *dev,
80824003 1366 unsigned long prealloc_start,
2a34f5e6
EA		 1367 unsigned long prealloc_size,
1368 unsigned long agp_size)
79e53945
JB		 1369{
1370 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 1371 int fb_bar = IS_I9XX(dev) ? 2 : 0;
1372 int ret = 0;
1373
01d73a69 1374 dev->mode_config.fb_base = pci_resource_start(dev->pdev, fb_bar) &
79e53945
JB		 1375 0xff000000;
1376
79e53945
JB		 1377 /* Basic memrange allocator for stolen space (aka vram) */
1378 drm_mm_init(&dev_priv->vram, 0, prealloc_size);
80824003 1379 DRM_INFO("set up %ldM of stolen space\n", prealloc_size / (1024*1024));
79e53945 1380
11ed50ec
BG		 1381 /* We're off and running w/KMS */
1382 dev_priv->mm.suspended = 0;
79e53945 1383
13f4c435
EA		 1384 /* Let GEM Manage from end of prealloc space to end of aperture.
1385 *
1386 * However, leave one page at the end still bound to the scratch page.
1387 * There are a number of places where the hardware apparently
1388 * prefetches past the end of the object, and we've seen multiple
1389 * hangs with the GPU head pointer stuck in a batchbuffer bound
1390 * at the last page of the aperture. One page should be enough to
1391 * keep any prefetching inside of the aperture.
1392 */
1393 i915_gem_do_init(dev, prealloc_size, agp_size - 4096);
79e53945 1394
11ed50ec 1395 mutex_lock(&dev->struct_mutex);
79e53945 1396 ret = i915_gem_init_ringbuffer(dev);
11ed50ec 1397 mutex_unlock(&dev->struct_mutex);
79e53945 1398 if (ret)
b8da7de5 1399 goto out;
79e53945 1400
80824003 1401 /* Try to set up FBC with a reasonable compressed buffer size */
9216d44d 1402 if (I915_HAS_FBC(dev) && i915_powersave) {
80824003
JB		 1403 int cfb_size;
1404
1405 /* Try to get an 8M buffer... */
1406 if (prealloc_size > (9*1024*1024))
1407 cfb_size = 8*1024*1024;
1408 else /* fall back to 7/8 of the stolen space */
1409 cfb_size = prealloc_size * 7 / 8;
1410 i915_setup_compression(dev, cfb_size);
1411 }
1412
79e53945
JB		 1413 /* Allow hardware batchbuffers unless told otherwise.
1414 */
1415 dev_priv->allow_batchbuffer = 1;
1416
1417 ret = intel_init_bios(dev);
1418 if (ret)
1419 DRM_INFO("failed to find VBIOS tables\n");
1420
28d52043
DA		 1421 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1422 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1423 if (ret)
5a79395b 1424 goto cleanup_ringbuffer;
28d52043 1425
6a9ee8af
DA		 1426 ret = vga_switcheroo_register_client(dev->pdev,
1427 i915_switcheroo_set_state,
1428 i915_switcheroo_can_switch);
1429 if (ret)
5a79395b 1430 goto cleanup_vga_client;
6a9ee8af 1431
1afe3e9d
JB		 1432 /* IIR "flip pending" bit means done if this bit is set */
1433 if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
1434 dev_priv->flip_pending_is_done = true;
1435
b01f2c3a
JB		 1436 intel_modeset_init(dev);
1437
79e53945
JB		 1438 ret = drm_irq_install(dev);
1439 if (ret)
5a79395b 1440 goto cleanup_vga_switcheroo;
79e53945 1441
79e53945
JB		 1442 /* Always safe in the mode setting case. */
1443 /* FIXME: do pre/post-mode set stuff in core KMS code */
1444 dev->vblank_disable_allowed = 1;
1445
1446 /*
1447 * Initialize the hardware status page IRQ location.
1448 */
1449
1450 I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
1451
5a79395b
CW		 1452 ret = intel_fbdev_init(dev);
1453 if (ret)
1454 goto cleanup_irq;
1455
eb1f8e4f 1456 drm_kms_helper_poll_init(dev);
79e53945
JB		 1457 return 0;
1458
5a79395b
CW		 1459cleanup_irq:
1460 drm_irq_uninstall(dev);
1461cleanup_vga_switcheroo:
1462 vga_switcheroo_unregister_client(dev->pdev);
1463cleanup_vga_client:
1464 vga_client_register(dev->pdev, NULL, NULL, NULL);
1465cleanup_ringbuffer:
21099537 1466 mutex_lock(&dev->struct_mutex);
79e53945 1467 i915_gem_cleanup_ringbuffer(dev);
21099537 1468 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 1469out:
1470 return ret;
1471}
1472
7c1c2871
DA		 1473int i915_master_create(struct drm_device *dev, struct drm_master *master)
1474{
1475 struct drm_i915_master_private *master_priv;
1476
9a298b2a 1477 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
7c1c2871
DA		 1478 if (!master_priv)
1479 return -ENOMEM;
1480
1481 master->driver_priv = master_priv;
1482 return 0;
1483}
1484
1485void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1486{
1487 struct drm_i915_master_private *master_priv = master->driver_priv;
1488
1489 if (!master_priv)
1490 return;
1491
9a298b2a 1492 kfree(master_priv);
7c1c2871
DA		 1493
1494 master->driver_priv = NULL;
1495}
1496
7648fa99 1497static void i915_pineview_get_mem_freq(struct drm_device *dev)
7662c8bd
SL		 1498{
1499 drm_i915_private_t *dev_priv = dev->dev_private;
1500 u32 tmp;
1501
7662c8bd
SL		 1502 tmp = I915_READ(CLKCFG);
1503
1504 switch (tmp & CLKCFG_FSB_MASK) {
1505 case CLKCFG_FSB_533:
1506 dev_priv->fsb_freq = 533; /* 133*4 */
1507 break;
1508 case CLKCFG_FSB_800:
1509 dev_priv->fsb_freq = 800; /* 200*4 */
1510 break;
1511 case CLKCFG_FSB_667:
1512 dev_priv->fsb_freq = 667; /* 167*4 */
1513 break;
1514 case CLKCFG_FSB_400:
1515 dev_priv->fsb_freq = 400; /* 100*4 */
1516 break;
1517 }
1518
1519 switch (tmp & CLKCFG_MEM_MASK) {
1520 case CLKCFG_MEM_533:
1521 dev_priv->mem_freq = 533;
1522 break;
1523 case CLKCFG_MEM_667:
1524 dev_priv->mem_freq = 667;
1525 break;
1526 case CLKCFG_MEM_800:
1527 dev_priv->mem_freq = 800;
1528 break;
1529 }
95534263
LP		 1530
1531 /* detect pineview DDR3 setting */
1532 tmp = I915_READ(CSHRDDR3CTL);
1533 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
7662c8bd
SL		 1534}
1535
7648fa99
JB		 1536static void i915_ironlake_get_mem_freq(struct drm_device *dev)
1537{
1538 drm_i915_private_t *dev_priv = dev->dev_private;
1539 u16 ddrpll, csipll;
1540
1541 ddrpll = I915_READ16(DDRMPLL1);
1542 csipll = I915_READ16(CSIPLL0);
1543
1544 switch (ddrpll & 0xff) {
1545 case 0xc:
1546 dev_priv->mem_freq = 800;
1547 break;
1548 case 0x10:
1549 dev_priv->mem_freq = 1066;
1550 break;
1551 case 0x14:
1552 dev_priv->mem_freq = 1333;
1553 break;
1554 case 0x18:
1555 dev_priv->mem_freq = 1600;
1556 break;
1557 default:
1558 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
1559 ddrpll & 0xff);
1560 dev_priv->mem_freq = 0;
1561 break;
1562 }
1563
1564 dev_priv->r_t = dev_priv->mem_freq;
1565
1566 switch (csipll & 0x3ff) {
1567 case 0x00c:
1568 dev_priv->fsb_freq = 3200;
1569 break;
1570 case 0x00e:
1571 dev_priv->fsb_freq = 3733;
1572 break;
1573 case 0x010:
1574 dev_priv->fsb_freq = 4266;
1575 break;
1576 case 0x012:
1577 dev_priv->fsb_freq = 4800;
1578 break;
1579 case 0x014:
1580 dev_priv->fsb_freq = 5333;
1581 break;
1582 case 0x016:
1583 dev_priv->fsb_freq = 5866;
1584 break;
1585 case 0x018:
1586 dev_priv->fsb_freq = 6400;
1587 break;
1588 default:
1589 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
1590 csipll & 0x3ff);
1591 dev_priv->fsb_freq = 0;
1592 break;
1593 }
1594
1595 if (dev_priv->fsb_freq == 3200) {
1596 dev_priv->c_m = 0;
1597 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
1598 dev_priv->c_m = 1;
1599 } else {
1600 dev_priv->c_m = 2;
1601 }
1602}
1603
1604struct v_table {
1605 u8 vid;
1606 unsigned long vd; /* in .1 mil */
1607 unsigned long vm; /* in .1 mil */
1608 u8 pvid;
1609};
1610
1611static struct v_table v_table[] = {
1612 { 0, 16125, 15000, 0x7f, },
1613 { 1, 16000, 14875, 0x7e, },
1614 { 2, 15875, 14750, 0x7d, },
1615 { 3, 15750, 14625, 0x7c, },
1616 { 4, 15625, 14500, 0x7b, },
1617 { 5, 15500, 14375, 0x7a, },
1618 { 6, 15375, 14250, 0x79, },
1619 { 7, 15250, 14125, 0x78, },
1620 { 8, 15125, 14000, 0x77, },
1621 { 9, 15000, 13875, 0x76, },
1622 { 10, 14875, 13750, 0x75, },
1623 { 11, 14750, 13625, 0x74, },
1624 { 12, 14625, 13500, 0x73, },
1625 { 13, 14500, 13375, 0x72, },
1626 { 14, 14375, 13250, 0x71, },
1627 { 15, 14250, 13125, 0x70, },
1628 { 16, 14125, 13000, 0x6f, },
1629 { 17, 14000, 12875, 0x6e, },
1630 { 18, 13875, 12750, 0x6d, },
1631 { 19, 13750, 12625, 0x6c, },
1632 { 20, 13625, 12500, 0x6b, },
1633 { 21, 13500, 12375, 0x6a, },
1634 { 22, 13375, 12250, 0x69, },
1635 { 23, 13250, 12125, 0x68, },
1636 { 24, 13125, 12000, 0x67, },
1637 { 25, 13000, 11875, 0x66, },
1638 { 26, 12875, 11750, 0x65, },
1639 { 27, 12750, 11625, 0x64, },
1640 { 28, 12625, 11500, 0x63, },
1641 { 29, 12500, 11375, 0x62, },
1642 { 30, 12375, 11250, 0x61, },
1643 { 31, 12250, 11125, 0x60, },
1644 { 32, 12125, 11000, 0x5f, },
1645 { 33, 12000, 10875, 0x5e, },
1646 { 34, 11875, 10750, 0x5d, },
1647 { 35, 11750, 10625, 0x5c, },
1648 { 36, 11625, 10500, 0x5b, },
1649 { 37, 11500, 10375, 0x5a, },
1650 { 38, 11375, 10250, 0x59, },
1651 { 39, 11250, 10125, 0x58, },
1652 { 40, 11125, 10000, 0x57, },
1653 { 41, 11000, 9875, 0x56, },
1654 { 42, 10875, 9750, 0x55, },
1655 { 43, 10750, 9625, 0x54, },
1656 { 44, 10625, 9500, 0x53, },
1657 { 45, 10500, 9375, 0x52, },
1658 { 46, 10375, 9250, 0x51, },
1659 { 47, 10250, 9125, 0x50, },
1660 { 48, 10125, 9000, 0x4f, },
1661 { 49, 10000, 8875, 0x4e, },
1662 { 50, 9875, 8750, 0x4d, },
1663 { 51, 9750, 8625, 0x4c, },
1664 { 52, 9625, 8500, 0x4b, },
1665 { 53, 9500, 8375, 0x4a, },
1666 { 54, 9375, 8250, 0x49, },
1667 { 55, 9250, 8125, 0x48, },
1668 { 56, 9125, 8000, 0x47, },
1669 { 57, 9000, 7875, 0x46, },
1670 { 58, 8875, 7750, 0x45, },
1671 { 59, 8750, 7625, 0x44, },
1672 { 60, 8625, 7500, 0x43, },
1673 { 61, 8500, 7375, 0x42, },
1674 { 62, 8375, 7250, 0x41, },
1675 { 63, 8250, 7125, 0x40, },
1676 { 64, 8125, 7000, 0x3f, },
1677 { 65, 8000, 6875, 0x3e, },
1678 { 66, 7875, 6750, 0x3d, },
1679 { 67, 7750, 6625, 0x3c, },
1680 { 68, 7625, 6500, 0x3b, },
1681 { 69, 7500, 6375, 0x3a, },
1682 { 70, 7375, 6250, 0x39, },
1683 { 71, 7250, 6125, 0x38, },
1684 { 72, 7125, 6000, 0x37, },
1685 { 73, 7000, 5875, 0x36, },
1686 { 74, 6875, 5750, 0x35, },
1687 { 75, 6750, 5625, 0x34, },
1688 { 76, 6625, 5500, 0x33, },
1689 { 77, 6500, 5375, 0x32, },
1690 { 78, 6375, 5250, 0x31, },
1691 { 79, 6250, 5125, 0x30, },
1692 { 80, 6125, 5000, 0x2f, },
1693 { 81, 6000, 4875, 0x2e, },
1694 { 82, 5875, 4750, 0x2d, },
1695 { 83, 5750, 4625, 0x2c, },
1696 { 84, 5625, 4500, 0x2b, },
1697 { 85, 5500, 4375, 0x2a, },
1698 { 86, 5375, 4250, 0x29, },
1699 { 87, 5250, 4125, 0x28, },
1700 { 88, 5125, 4000, 0x27, },
1701 { 89, 5000, 3875, 0x26, },
1702 { 90, 4875, 3750, 0x25, },
1703 { 91, 4750, 3625, 0x24, },
1704 { 92, 4625, 3500, 0x23, },
1705 { 93, 4500, 3375, 0x22, },
1706 { 94, 4375, 3250, 0x21, },
1707 { 95, 4250, 3125, 0x20, },
1708 { 96, 4125, 3000, 0x1f, },
1709 { 97, 4125, 3000, 0x1e, },
1710 { 98, 4125, 3000, 0x1d, },
1711 { 99, 4125, 3000, 0x1c, },
1712 { 100, 4125, 3000, 0x1b, },
1713 { 101, 4125, 3000, 0x1a, },
1714 { 102, 4125, 3000, 0x19, },
1715 { 103, 4125, 3000, 0x18, },
1716 { 104, 4125, 3000, 0x17, },
1717 { 105, 4125, 3000, 0x16, },
1718 { 106, 4125, 3000, 0x15, },
1719 { 107, 4125, 3000, 0x14, },
1720 { 108, 4125, 3000, 0x13, },
1721 { 109, 4125, 3000, 0x12, },
1722 { 110, 4125, 3000, 0x11, },
1723 { 111, 4125, 3000, 0x10, },
1724 { 112, 4125, 3000, 0x0f, },
1725 { 113, 4125, 3000, 0x0e, },
1726 { 114, 4125, 3000, 0x0d, },
1727 { 115, 4125, 3000, 0x0c, },
1728 { 116, 4125, 3000, 0x0b, },
1729 { 117, 4125, 3000, 0x0a, },
1730 { 118, 4125, 3000, 0x09, },
1731 { 119, 4125, 3000, 0x08, },
1732 { 120, 1125, 0, 0x07, },
1733 { 121, 1000, 0, 0x06, },
1734 { 122, 875, 0, 0x05, },
1735 { 123, 750, 0, 0x04, },
1736 { 124, 625, 0, 0x03, },
1737 { 125, 500, 0, 0x02, },
1738 { 126, 375, 0, 0x01, },
1739 { 127, 0, 0, 0x00, },
1740};
1741
1742struct cparams {
1743 int i;
1744 int t;
1745 int m;
1746 int c;
1747};
1748
1749static struct cparams cparams[] = {
1750 { 1, 1333, 301, 28664 },
1751 { 1, 1066, 294, 24460 },
1752 { 1, 800, 294, 25192 },
1753 { 0, 1333, 276, 27605 },
1754 { 0, 1066, 276, 27605 },
1755 { 0, 800, 231, 23784 },
1756};
1757
1758unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
1759{
1760 u64 total_count, diff, ret;
1761 u32 count1, count2, count3, m = 0, c = 0;
1762 unsigned long now = jiffies_to_msecs(jiffies), diff1;
1763 int i;
1764
1765 diff1 = now - dev_priv->last_time1;
1766
1767 count1 = I915_READ(DMIEC);
1768 count2 = I915_READ(DDREC);
1769 count3 = I915_READ(CSIEC);
1770
1771 total_count = count1 + count2 + count3;
1772
1773 /* FIXME: handle per-counter overflow */
1774 if (total_count < dev_priv->last_count1) {
1775 diff = ~0UL - dev_priv->last_count1;
1776 diff += total_count;
1777 } else {
1778 diff = total_count - dev_priv->last_count1;
1779 }
1780
1781 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
1782 if (cparams[i].i == dev_priv->c_m &&
1783 cparams[i].t == dev_priv->r_t) {
1784 m = cparams[i].m;
1785 c = cparams[i].c;
1786 break;
1787 }
1788 }
1789
d270ae34 1790 diff = div_u64(diff, diff1);
7648fa99 1791 ret = ((m * diff) + c);
d270ae34 1792 ret = div_u64(ret, 10);
7648fa99
JB		 1793
1794 dev_priv->last_count1 = total_count;
1795 dev_priv->last_time1 = now;
1796
1797 return ret;
1798}
1799
1800unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
1801{
1802 unsigned long m, x, b;
1803 u32 tsfs;
1804
1805 tsfs = I915_READ(TSFS);
1806
1807 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
1808 x = I915_READ8(TR1);
1809
1810 b = tsfs & TSFS_INTR_MASK;
1811
1812 return ((m * x) / 127) - b;
1813}
1814
1815static unsigned long pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
1816{
1817 unsigned long val = 0;
1818 int i;
1819
1820 for (i = 0; i < ARRAY_SIZE(v_table); i++) {
1821 if (v_table[i].pvid == pxvid) {
1822 if (IS_MOBILE(dev_priv->dev))
1823 val = v_table[i].vm;
1824 else
1825 val = v_table[i].vd;
1826 }
1827 }
1828
1829 return val;
1830}
1831
1832void i915_update_gfx_val(struct drm_i915_private *dev_priv)
1833{
1834 struct timespec now, diff1;
1835 u64 diff;
1836 unsigned long diffms;
1837 u32 count;
1838
1839 getrawmonotonic(&now);
1840 diff1 = timespec_sub(now, dev_priv->last_time2);
1841
1842 /* Don't divide by 0 */
1843 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
1844 if (!diffms)
1845 return;
1846
1847 count = I915_READ(GFXEC);
1848
1849 if (count < dev_priv->last_count2) {
1850 diff = ~0UL - dev_priv->last_count2;
1851 diff += count;
1852 } else {
1853 diff = count - dev_priv->last_count2;
1854 }
1855
1856 dev_priv->last_count2 = count;
1857 dev_priv->last_time2 = now;
1858
1859 /* More magic constants... */
1860 diff = diff * 1181;
d270ae34 1861 diff = div_u64(diff, diffms * 10);
7648fa99
JB		 1862 dev_priv->gfx_power = diff;
1863}
1864
1865unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
1866{
1867 unsigned long t, corr, state1, corr2, state2;
1868 u32 pxvid, ext_v;
1869
1870 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
1871 pxvid = (pxvid >> 24) & 0x7f;
1872 ext_v = pvid_to_extvid(dev_priv, pxvid);
1873
1874 state1 = ext_v;
1875
1876 t = i915_mch_val(dev_priv);
1877
1878 /* Revel in the empirically derived constants */
1879
1880 /* Correction factor in 1/100000 units */
1881 if (t > 80)
1882 corr = ((t * 2349) + 135940);
1883 else if (t >= 50)
1884 corr = ((t * 964) + 29317);
1885 else /* < 50 */
1886 corr = ((t * 301) + 1004);
1887
1888 corr = corr * ((150142 * state1) / 10000 - 78642);
1889 corr /= 100000;
1890 corr2 = (corr * dev_priv->corr);
1891
1892 state2 = (corr2 * state1) / 10000;
1893 state2 /= 100; /* convert to mW */
1894
1895 i915_update_gfx_val(dev_priv);
1896
1897 return dev_priv->gfx_power + state2;
1898}
1899
1900/* Global for IPS driver to get at the current i915 device */
1901static struct drm_i915_private *i915_mch_dev;
1902/*
1903 * Lock protecting IPS related data structures
1904 * - i915_mch_dev
1905 * - dev_priv->max_delay
1906 * - dev_priv->min_delay
1907 * - dev_priv->fmax
1908 * - dev_priv->gpu_busy
1909 */
1910DEFINE_SPINLOCK(mchdev_lock);
1911
1912/**
1913 * i915_read_mch_val - return value for IPS use
1914 *
1915 * Calculate and return a value for the IPS driver to use when deciding whether
1916 * we have thermal and power headroom to increase CPU or GPU power budget.
1917 */
1918unsigned long i915_read_mch_val(void)
1919{
1920 struct drm_i915_private *dev_priv;
1921 unsigned long chipset_val, graphics_val, ret = 0;
1922
1923 spin_lock(&mchdev_lock);
1924 if (!i915_mch_dev)
1925 goto out_unlock;
1926 dev_priv = i915_mch_dev;
1927
1928 chipset_val = i915_chipset_val(dev_priv);
1929 graphics_val = i915_gfx_val(dev_priv);
1930
1931 ret = chipset_val + graphics_val;
1932
1933out_unlock:
1934 spin_unlock(&mchdev_lock);
1935
1936 return ret;
1937}
1938EXPORT_SYMBOL_GPL(i915_read_mch_val);
1939
1940/**
1941 * i915_gpu_raise - raise GPU frequency limit
1942 *
1943 * Raise the limit; IPS indicates we have thermal headroom.
1944 */
1945bool i915_gpu_raise(void)
1946{
1947 struct drm_i915_private *dev_priv;
1948 bool ret = true;
1949
1950 spin_lock(&mchdev_lock);
1951 if (!i915_mch_dev) {
1952 ret = false;
1953 goto out_unlock;
1954 }
1955 dev_priv = i915_mch_dev;
1956
1957 if (dev_priv->max_delay > dev_priv->fmax)
1958 dev_priv->max_delay--;
1959
1960out_unlock:
1961 spin_unlock(&mchdev_lock);
1962
1963 return ret;
1964}
1965EXPORT_SYMBOL_GPL(i915_gpu_raise);
1966
1967/**
1968 * i915_gpu_lower - lower GPU frequency limit
1969 *
1970 * IPS indicates we're close to a thermal limit, so throttle back the GPU
1971 * frequency maximum.
1972 */
1973bool i915_gpu_lower(void)
1974{
1975 struct drm_i915_private *dev_priv;
1976 bool ret = true;
1977
1978 spin_lock(&mchdev_lock);
1979 if (!i915_mch_dev) {
1980 ret = false;
1981 goto out_unlock;
1982 }
1983 dev_priv = i915_mch_dev;
1984
1985 if (dev_priv->max_delay < dev_priv->min_delay)
1986 dev_priv->max_delay++;
1987
1988out_unlock:
1989 spin_unlock(&mchdev_lock);
1990
1991 return ret;
1992}
1993EXPORT_SYMBOL_GPL(i915_gpu_lower);
1994
1995/**
1996 * i915_gpu_busy - indicate GPU business to IPS
1997 *
1998 * Tell the IPS driver whether or not the GPU is busy.
1999 */
2000bool i915_gpu_busy(void)
2001{
2002 struct drm_i915_private *dev_priv;
2003 bool ret = false;
2004
2005 spin_lock(&mchdev_lock);
2006 if (!i915_mch_dev)
2007 goto out_unlock;
2008 dev_priv = i915_mch_dev;
2009
2010 ret = dev_priv->busy;
2011
2012out_unlock:
2013 spin_unlock(&mchdev_lock);
2014
2015 return ret;
2016}
2017EXPORT_SYMBOL_GPL(i915_gpu_busy);
2018
2019/**
2020 * i915_gpu_turbo_disable - disable graphics turbo
2021 *
2022 * Disable graphics turbo by resetting the max frequency and setting the
2023 * current frequency to the default.
2024 */
2025bool i915_gpu_turbo_disable(void)
2026{
2027 struct drm_i915_private *dev_priv;
2028 bool ret = true;
2029
2030 spin_lock(&mchdev_lock);
2031 if (!i915_mch_dev) {
2032 ret = false;
2033 goto out_unlock;
2034 }
2035 dev_priv = i915_mch_dev;
2036
2037 dev_priv->max_delay = dev_priv->fstart;
2038
2039 if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
2040 ret = false;
2041
2042out_unlock:
2043 spin_unlock(&mchdev_lock);
2044
2045 return ret;
2046}
2047EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
2048
79e53945
JB		 2049/**
2050 * i915_driver_load - setup chip and create an initial config
2051 * @dev: DRM device
2052 * @flags: startup flags
2053 *
2054 * The driver load routine has to do several things:
2055 * - drive output discovery via intel_modeset_init()
2056 * - initialize the memory manager
2057 * - allocate initial config memory
2058 * - setup the DRM framebuffer with the allocated memory
2059 */
84b1fd10 2060int i915_driver_load(struct drm_device *dev, unsigned long flags)
22eae947 2061{
ea059a1e 2062 struct drm_i915_private *dev_priv;
d883f7f1 2063 resource_size_t base, size;
cfdf1fa2 2064 int ret = 0, mmio_bar;
80824003 2065 uint32_t agp_size, prealloc_size, prealloc_start;
22eae947
DA		 2066 /* i915 has 4 more counters */
2067 dev->counters += 4;
2068 dev->types[6] = _DRM_STAT_IRQ;
2069 dev->types[7] = _DRM_STAT_PRIMARY;
2070 dev->types[8] = _DRM_STAT_SECONDARY;
2071 dev->types[9] = _DRM_STAT_DMA;
2072
9a298b2a 2073 dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
ba8bbcf6
JB		 2074 if (dev_priv == NULL)
2075 return -ENOMEM;
2076
ba8bbcf6 2077 dev->dev_private = (void *)dev_priv;
673a394b 2078 dev_priv->dev = dev;
cfdf1fa2 2079 dev_priv->info = (struct intel_device_info *) flags;
ba8bbcf6
JB		 2080
2081 /* Add register map (needed for suspend/resume) */
cfdf1fa2 2082 mmio_bar = IS_I9XX(dev) ? 0 : 1;
01d73a69
JC		 2083 base = pci_resource_start(dev->pdev, mmio_bar);
2084 size = pci_resource_len(dev->pdev, mmio_bar);
ba8bbcf6 2085
ec2a4c3f
DA		 2086 if (i915_get_bridge_dev(dev)) {
2087 ret = -EIO;
2088 goto free_priv;
2089 }
2090
9f82d238
DV		 2091 /* overlay on gen2 is broken and can't address above 1G */
2092 if (IS_GEN2(dev))
2093 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
2094
3043c60c 2095 dev_priv->regs = ioremap(base, size);
79e53945
JB		 2096 if (!dev_priv->regs) {
2097 DRM_ERROR("failed to map registers\n");
2098 ret = -EIO;
ec2a4c3f 2099 goto put_bridge;
79e53945 2100 }
ed4cb414 2101
ab657db1
EA		 2102 dev_priv->mm.gtt_mapping =
2103 io_mapping_create_wc(dev->agp->base,
2104 dev->agp->agp_info.aper_size * 1024*1024);
6644107d
VP		 2105 if (dev_priv->mm.gtt_mapping == NULL) {
2106 ret = -EIO;
2107 goto out_rmmap;
2108 }
2109
ab657db1
EA		 2110 /* Set up a WC MTRR for non-PAT systems. This is more common than
2111 * one would think, because the kernel disables PAT on first
2112 * generation Core chips because WC PAT gets overridden by a UC
2113 * MTRR if present. Even if a UC MTRR isn't present.
2114 */
2115 dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
2116 dev->agp->agp_info.aper_size *
2117 1024 * 1024,
2118 MTRR_TYPE_WRCOMB, 1);
2119 if (dev_priv->mm.gtt_mtrr < 0) {
040aefa2 2120 DRM_INFO("MTRR allocation failed. Graphics "
ab657db1
EA		 2121 "performance may suffer.\n");
2122 }
2123
80824003 2124 ret = i915_probe_agp(dev, &agp_size, &prealloc_size, &prealloc_start);
2a34f5e6
EA		 2125 if (ret)
2126 goto out_iomapfree;
2127
d1d6ca73
JB		 2128 if (prealloc_size > intel_max_stolen) {
2129 DRM_INFO("detected %dM stolen memory, trimming to %dM\n",
2130 prealloc_size >> 20, intel_max_stolen >> 20);
2131 prealloc_size = intel_max_stolen;
2132 }
2133
aed5f1dc 2134 dev_priv->wq = create_singlethread_workqueue("i915");
9c9fe1f8
EA		 2135 if (dev_priv->wq == NULL) {
2136 DRM_ERROR("Failed to create our workqueue.\n");
2137 ret = -ENOMEM;
2138 goto out_iomapfree;
2139 }
2140
ac5c4e76
DA		 2141 /* enable GEM by default */
2142 dev_priv->has_gem = 1;
ac5c4e76 2143
2a34f5e6
EA		 2144 if (prealloc_size > agp_size * 3 / 4) {
2145 DRM_ERROR("Detected broken video BIOS with %d/%dkB of video "
2146 "memory stolen.\n",
2147 prealloc_size / 1024, agp_size / 1024);
2148 DRM_ERROR("Disabling GEM. (try reducing stolen memory or "
2149 "updating the BIOS to fix).\n");
2150 dev_priv->has_gem = 0;
2151 }
2152
79a78dd6
CW		 2153 if (dev_priv->has_gem == 0 &&
2154 drm_core_check_feature(dev, DRIVER_MODESET)) {
2155 DRM_ERROR("kernel modesetting requires GEM, disabling driver.\n");
2156 ret = -ENODEV;
2157 goto out_iomapfree;
2158 }
2159
9880b7a5 2160 dev->driver->get_vblank_counter = i915_get_vblank_counter;
42c2798b 2161 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
bad720ff 2162 if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
42c2798b 2163 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
9880b7a5 2164 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
42c2798b 2165 }
9880b7a5 2166
c4804411
ZW		 2167 /* Try to make sure MCHBAR is enabled before poking at it */
2168 intel_setup_mchbar(dev);
2169
673a394b
EA		 2170 i915_gem_load(dev);
2171
398c9cb2
KP		 2172 /* Init HWS */
2173 if (!I915_NEED_GFX_HWS(dev)) {
2174 ret = i915_init_phys_hws(dev);
2175 if (ret != 0)
9c9fe1f8 2176 goto out_workqueue_free;
398c9cb2 2177 }
ed4cb414 2178
7648fa99
JB		 2179 if (IS_PINEVIEW(dev))
2180 i915_pineview_get_mem_freq(dev);
2181 else if (IS_IRONLAKE(dev))
2182 i915_ironlake_get_mem_freq(dev);
7662c8bd 2183
ed4cb414
EA		 2184 /* On the 945G/GM, the chipset reports the MSI capability on the
2185 * integrated graphics even though the support isn't actually there
2186 * according to the published specs. It doesn't appear to function
2187 * correctly in testing on 945G.
2188 * This may be a side effect of MSI having been made available for PEG
2189 * and the registers being closely associated.
d1ed629f
KP		 2190 *
2191 * According to chipset errata, on the 965GM, MSI interrupts may
b60678a7
KP		 2192 * be lost or delayed, but we use them anyways to avoid
2193 * stuck interrupts on some machines.
ed4cb414 2194 */
b60678a7 2195 if (!IS_I945G(dev) && !IS_I945GM(dev))
d3e74d02 2196 pci_enable_msi(dev->pdev);
ed4cb414
EA		 2197
2198 spin_lock_init(&dev_priv->user_irq_lock);
63eeaf38 2199 spin_lock_init(&dev_priv->error_lock);
9d34e5db 2200 dev_priv->trace_irq_seqno = 0;
ed4cb414 2201
52440211
KP		 2202 ret = drm_vblank_init(dev, I915_NUM_PIPE);
2203
2204 if (ret) {
2205 (void) i915_driver_unload(dev);
2206 return ret;
2207 }
2208
11ed50ec
BG		 2209 /* Start out suspended */
2210 dev_priv->mm.suspended = 1;
2211
3bad0781
ZW		 2212 intel_detect_pch(dev);
2213
79e53945 2214 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
80824003
JB		 2215 ret = i915_load_modeset_init(dev, prealloc_start,
2216 prealloc_size, agp_size);
79e53945
JB		 2217 if (ret < 0) {
2218 DRM_ERROR("failed to init modeset\n");
9c9fe1f8 2219 goto out_workqueue_free;
79e53945
JB		 2220 }
2221 }
2222
74a365b3 2223 /* Must be done after probing outputs */
01c66889 2224 intel_opregion_init(dev, 0);
74a365b3 2225
f65d9421
BG		 2226 setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
2227 (unsigned long) dev);
7648fa99
JB		 2228
2229 spin_lock(&mchdev_lock);
2230 i915_mch_dev = dev_priv;
2231 dev_priv->mchdev_lock = &mchdev_lock;
2232 spin_unlock(&mchdev_lock);
2233
6939a5ac
CW		 2234 /* XXX Prevent module unload due to memory corruption bugs. */
2235 __module_get(THIS_MODULE);
2236
79e53945
JB		 2237 return 0;
2238
9c9fe1f8
EA		 2239out_workqueue_free:
2240 destroy_workqueue(dev_priv->wq);
6644107d
VP		 2241out_iomapfree:
2242 io_mapping_free(dev_priv->mm.gtt_mapping);
79e53945
JB		 2243out_rmmap:
2244 iounmap(dev_priv->regs);
ec2a4c3f
DA		 2245put_bridge:
2246 pci_dev_put(dev_priv->bridge_dev);
79e53945 2247free_priv:
9a298b2a 2248 kfree(dev_priv);
ba8bbcf6
JB		 2249 return ret;
2250}
2251
2252int i915_driver_unload(struct drm_device *dev)
2253{
2254 struct drm_i915_private *dev_priv = dev->dev_private;
2255
9df30794
CW		 2256 i915_destroy_error_state(dev);
2257
7648fa99
JB		 2258 spin_lock(&mchdev_lock);
2259 i915_mch_dev = NULL;
2260 spin_unlock(&mchdev_lock);
2261
9c9fe1f8 2262 destroy_workqueue(dev_priv->wq);
f65d9421 2263 del_timer_sync(&dev_priv->hangcheck_timer);
9c9fe1f8 2264
ab657db1
EA		 2265 io_mapping_free(dev_priv->mm.gtt_mapping);
2266 if (dev_priv->mm.gtt_mtrr >= 0) {
2267 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2268 dev->agp->agp_info.aper_size * 1024 * 1024);
2269 dev_priv->mm.gtt_mtrr = -1;
2270 }
2271
79e53945 2272 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
3d8620cc
JB		 2273 intel_modeset_cleanup(dev);
2274
6363ee6f
ZY		 2275 /*
2276 * free the memory space allocated for the child device
2277 * config parsed from VBT
2278 */
2279 if (dev_priv->child_dev && dev_priv->child_dev_num) {
2280 kfree(dev_priv->child_dev);
2281 dev_priv->child_dev = NULL;
2282 dev_priv->child_dev_num = 0;
2283 }
79e53945 2284 drm_irq_uninstall(dev);
6a9ee8af 2285 vga_switcheroo_unregister_client(dev->pdev);
28d52043 2286 vga_client_register(dev->pdev, NULL, NULL, NULL);
79e53945
JB		 2287 }
2288
ed4cb414
EA		 2289 if (dev->pdev->msi_enabled)
2290 pci_disable_msi(dev->pdev);
2291
3043c60c
EA		 2292 if (dev_priv->regs != NULL)
2293 iounmap(dev_priv->regs);
ba8bbcf6 2294
01c66889 2295 intel_opregion_free(dev, 0);
8ee1c3db 2296
79e53945 2297 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
71acb5eb
DA		 2298 i915_gem_free_all_phys_object(dev);
2299
79e53945
JB		 2300 mutex_lock(&dev->struct_mutex);
2301 i915_gem_cleanup_ringbuffer(dev);
2302 mutex_unlock(&dev->struct_mutex);
20bf377e
JB		 2303 if (I915_HAS_FBC(dev) && i915_powersave)
2304 i915_cleanup_compression(dev);
79e53945
JB		 2305 drm_mm_takedown(&dev_priv->vram);
2306 i915_gem_lastclose(dev);
02e792fb
DV		 2307
2308 intel_cleanup_overlay(dev);
79e53945
JB		 2309 }
2310
c4804411
ZW		 2311 intel_teardown_mchbar(dev);
2312
ec2a4c3f 2313 pci_dev_put(dev_priv->bridge_dev);
9a298b2a 2314 kfree(dev->dev_private);
ba8bbcf6 2315
22eae947
DA		 2316 return 0;
2317}
2318
673a394b
EA		 2319int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
2320{
2321 struct drm_i915_file_private *i915_file_priv;
2322
8a4c47f3 2323 DRM_DEBUG_DRIVER("\n");
673a394b 2324 i915_file_priv = (struct drm_i915_file_private *)
9a298b2a 2325 kmalloc(sizeof(*i915_file_priv), GFP_KERNEL);
673a394b
EA		 2326
2327 if (!i915_file_priv)
2328 return -ENOMEM;
2329
2330 file_priv->driver_priv = i915_file_priv;
2331
b962442e 2332 INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
673a394b
EA		 2333
2334 return 0;
2335}
2336
79e53945
JB		 2337/**
2338 * i915_driver_lastclose - clean up after all DRM clients have exited
2339 * @dev: DRM device
2340 *
2341 * Take care of cleaning up after all DRM clients have exited. In the
2342 * mode setting case, we want to restore the kernel's initial mode (just
2343 * in case the last client left us in a bad state).
2344 *
2345 * Additionally, in the non-mode setting case, we'll tear down the AGP
2346 * and DMA structures, since the kernel won't be using them, and clea
2347 * up any GEM state.
2348 */
84b1fd10 2349void i915_driver_lastclose(struct drm_device * dev)
1da177e4 2350{
ba8bbcf6
JB		 2351 drm_i915_private_t *dev_priv = dev->dev_private;
2352
79e53945 2353 if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
785b93ef 2354 drm_fb_helper_restore();
6a9ee8af 2355 vga_switcheroo_process_delayed_switch();
144a75fa 2356 return;
79e53945 2357 }
144a75fa 2358
673a394b
EA		 2359 i915_gem_lastclose(dev);
2360
ba8bbcf6 2361 if (dev_priv->agp_heap)
b5e89ed5 2362 i915_mem_takedown(&(dev_priv->agp_heap));
ba8bbcf6 2363
b5e89ed5 2364 i915_dma_cleanup(dev);
1da177e4
LT		 2365}
2366
6c340eac 2367void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1da177e4 2368{
ba8bbcf6 2369 drm_i915_private_t *dev_priv = dev->dev_private;
b962442e 2370 i915_gem_release(dev, file_priv);
79e53945
JB		 2371 if (!drm_core_check_feature(dev, DRIVER_MODESET))
2372 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
1da177e4
LT		 2373}
2374
673a394b
EA		 2375void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
2376{
2377 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
2378
9a298b2a 2379 kfree(i915_file_priv);
673a394b
EA		 2380}
2381
c153f45f 2382struct drm_ioctl_desc i915_ioctls[] = {
1b2f1489
DA		 2383 DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2384 DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2385 DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
2386 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2387 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2388 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2389 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
2390 DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2391 DRM_IOCTL_DEF_DRV(I915_ALLOC, i915_mem_alloc, DRM_AUTH),
2392 DRM_IOCTL_DEF_DRV(I915_FREE, i915_mem_free, DRM_AUTH),
2393 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2394 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
2395 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2396 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2397 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH),
2398 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
2399 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2400 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2401 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2402 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
2403 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2404 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2405 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
2406 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
2407 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2408 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2409 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
2410 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
2411 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
2412 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
2413 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
2414 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
2415 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
2416 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
2417 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
2418 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
2419 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2420 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
2421 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2422 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
c94f7029
DA		 2423};
2424
2425int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
cda17380
DA		 2426
2427/**
2428 * Determine if the device really is AGP or not.
2429 *
2430 * All Intel graphics chipsets are treated as AGP, even if they are really
2431 * PCI-e.
2432 *
2433 * \param dev The device to be tested.
2434 *
2435 * \returns
2436 * A value of 1 is always retured to indictate every i9x5 is AGP.
2437 */
84b1fd10 2438int i915_driver_device_is_agp(struct drm_device * dev)
cda17380
DA		 2439{
2440 return 1;
2441}
Clone of davem's net-next-2.6 tree