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drm/edid: Fix the HDTV hack sync adjustment
[net-next-2.6.git] / drivers / gpu / drm / drm_edid.c
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f453ba04
DA		 1/*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
61e57a8d 5 * Copyright 2010 Red Hat, Inc.
f453ba04
DA		 6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30#include <linux/kernel.h>
5a0e3ad6 31#include <linux/slab.h>
f453ba04
DA		 32#include <linux/i2c.h>
33#include <linux/i2c-algo-bit.h>
34#include "drmP.h"
35#include "drm_edid.h"
36
d1ff6409
AJ		 37#define EDID_EST_TIMINGS 16
38#define EDID_STD_TIMINGS 8
39#define EDID_DETAILED_TIMINGS 4
f453ba04
DA		 40
41/*
42 * EDID blocks out in the wild have a variety of bugs, try to collect
43 * them here (note that userspace may work around broken monitors first,
44 * but fixes should make their way here so that the kernel "just works"
45 * on as many displays as possible).
46 */
47
48/* First detailed mode wrong, use largest 60Hz mode */
49#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
50/* Reported 135MHz pixel clock is too high, needs adjustment */
51#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
52/* Prefer the largest mode at 75 Hz */
53#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
54/* Detail timing is in cm not mm */
55#define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
56/* Detailed timing descriptors have bogus size values, so just take the
57 * maximum size and use that.
58 */
59#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
60/* Monitor forgot to set the first detailed is preferred bit. */
61#define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
62/* use +hsync +vsync for detailed mode */
63#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
3c537889 64
f453ba04 65
5c61259e
ZY		 66#define LEVEL_DMT 0
67#define LEVEL_GTF 1
7a374350
AJ		 68#define LEVEL_GTF2 2
69#define LEVEL_CVT 3
5c61259e 70
f453ba04
DA		 71static struct edid_quirk {
72 char *vendor;
73 int product_id;
74 u32 quirks;
75} edid_quirk_list[] = {
76 /* Acer AL1706 */
77 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
78 /* Acer F51 */
79 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
80 /* Unknown Acer */
81 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
82
83 /* Belinea 10 15 55 */
84 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
85 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
86
87 /* Envision Peripherals, Inc. EN-7100e */
88 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
ba1163de
AJ		 89 /* Envision EN2028 */
90 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
f453ba04
DA		 91
92 /* Funai Electronics PM36B */
93 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
94 EDID_QUIRK_DETAILED_IN_CM },
95
96 /* LG Philips LCD LP154W01-A5 */
97 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
98 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
99
100 /* Philips 107p5 CRT */
101 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
102
103 /* Proview AY765C */
104 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
105
106 /* Samsung SyncMaster 205BW. Note: irony */
107 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
108 /* Samsung SyncMaster 22[5-6]BW */
109 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
110 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
111};
112
61e57a8d 113/*** DDC fetch and block validation ***/
f453ba04 114
083ae056
AJ		 115static const u8 edid_header[] = {
116 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
117};
f453ba04 118
61e57a8d
AJ		 119/*
120 * Sanity check the EDID block (base or extension). Return 0 if the block
121 * doesn't check out, or 1 if it's valid.
f453ba04 122 */
61e57a8d
AJ		 123static bool
124drm_edid_block_valid(u8 *raw_edid)
f453ba04 125{
61e57a8d 126 int i;
f453ba04 127 u8 csum = 0;
61e57a8d 128 struct edid *edid = (struct edid *)raw_edid;
f453ba04 129
61e57a8d
AJ		 130 if (raw_edid[0] == 0x00) {
131 int score = 0;
862b89c0 132
61e57a8d
AJ		 133 for (i = 0; i < sizeof(edid_header); i++)
134 if (raw_edid[i] == edid_header[i])
135 score++;
136
137 if (score == 8) ;
138 else if (score >= 6) {
139 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
140 memcpy(raw_edid, edid_header, sizeof(edid_header));
141 } else {
142 goto bad;
143 }
144 }
f453ba04
DA		 145
146 for (i = 0; i < EDID_LENGTH; i++)
147 csum += raw_edid[i];
148 if (csum) {
149 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum);
4a638b4e
AJ		 150
151 /* allow CEA to slide through, switches mangle this */
152 if (raw_edid[0] != 0x02)
153 goto bad;
f453ba04
DA		 154 }
155
61e57a8d
AJ		 156 /* per-block-type checks */
157 switch (raw_edid[0]) {
158 case 0: /* base */
159 if (edid->version != 1) {
160 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version);
161 goto bad;
162 }
862b89c0 163
61e57a8d
AJ		 164 if (edid->revision > 4)
165 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
166 break;
862b89c0 167
61e57a8d
AJ		 168 default:
169 break;
170 }
47ee4ccf 171
f453ba04
DA		 172 return 1;
173
174bad:
175 if (raw_edid) {
176 DRM_ERROR("Raw EDID:\n");
177 print_hex_dump_bytes(KERN_ERR, DUMP_PREFIX_NONE, raw_edid, EDID_LENGTH);
178 printk("\n");
179 }
180 return 0;
181}
61e57a8d
AJ		 182
183/**
184 * drm_edid_is_valid - sanity check EDID data
185 * @edid: EDID data
186 *
187 * Sanity-check an entire EDID record (including extensions)
188 */
189bool drm_edid_is_valid(struct edid *edid)
190{
191 int i;
192 u8 *raw = (u8 *)edid;
193
194 if (!edid)
195 return false;
196
197 for (i = 0; i <= edid->extensions; i++)
198 if (!drm_edid_block_valid(raw + i * EDID_LENGTH))
199 return false;
200
201 return true;
202}
3c537889 203EXPORT_SYMBOL(drm_edid_is_valid);
f453ba04 204
61e57a8d
AJ		 205#define DDC_ADDR 0x50
206#define DDC_SEGMENT_ADDR 0x30
207/**
208 * Get EDID information via I2C.
209 *
210 * \param adapter : i2c device adaptor
211 * \param buf : EDID data buffer to be filled
212 * \param len : EDID data buffer length
213 * \return 0 on success or -1 on failure.
214 *
215 * Try to fetch EDID information by calling i2c driver function.
216 */
217static int
218drm_do_probe_ddc_edid(struct i2c_adapter *adapter, unsigned char *buf,
219 int block, int len)
220{
221 unsigned char start = block * EDID_LENGTH;
222 struct i2c_msg msgs[] = {
223 {
224 .addr = DDC_ADDR,
225 .flags = 0,
226 .len = 1,
227 .buf = &start,
228 }, {
229 .addr = DDC_ADDR,
230 .flags = I2C_M_RD,
231 .len = len,
232 .buf = buf + start,
233 }
234 };
235
236 if (i2c_transfer(adapter, msgs, 2) == 2)
237 return 0;
238
239 return -1;
240}
241
242static u8 *
243drm_do_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
244{
245 int i, j = 0;
246 u8 *block, *new;
247
248 if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
249 return NULL;
250
251 /* base block fetch */
252 for (i = 0; i < 4; i++) {
253 if (drm_do_probe_ddc_edid(adapter, block, 0, EDID_LENGTH))
254 goto out;
255 if (drm_edid_block_valid(block))
256 break;
257 }
258 if (i == 4)
259 goto carp;
260
261 /* if there's no extensions, we're done */
262 if (block[0x7e] == 0)
263 return block;
264
265 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL);
266 if (!new)
267 goto out;
268 block = new;
269
270 for (j = 1; j <= block[0x7e]; j++) {
271 for (i = 0; i < 4; i++) {
272 if (drm_do_probe_ddc_edid(adapter, block, j,
273 EDID_LENGTH))
274 goto out;
275 if (drm_edid_block_valid(block + j * EDID_LENGTH))
276 break;
277 }
278 if (i == 4)
279 goto carp;
280 }
281
282 return block;
283
284carp:
285 dev_warn(&connector->dev->pdev->dev, "%s: EDID block %d invalid.\n",
286 drm_get_connector_name(connector), j);
287
288out:
289 kfree(block);
290 return NULL;
291}
292
293/**
294 * Probe DDC presence.
295 *
296 * \param adapter : i2c device adaptor
297 * \return 1 on success
298 */
299static bool
300drm_probe_ddc(struct i2c_adapter *adapter)
301{
302 unsigned char out;
303
304 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
305}
306
307/**
308 * drm_get_edid - get EDID data, if available
309 * @connector: connector we're probing
310 * @adapter: i2c adapter to use for DDC
311 *
312 * Poke the given i2c channel to grab EDID data if possible. If found,
313 * attach it to the connector.
314 *
315 * Return edid data or NULL if we couldn't find any.
316 */
317struct edid *drm_get_edid(struct drm_connector *connector,
318 struct i2c_adapter *adapter)
319{
320 struct edid *edid = NULL;
321
322 if (drm_probe_ddc(adapter))
323 edid = (struct edid *)drm_do_get_edid(connector, adapter);
324
325 connector->display_info.raw_edid = (char *)edid;
326
327 return edid;
328
329}
330EXPORT_SYMBOL(drm_get_edid);
331
332/*** EDID parsing ***/
333
f453ba04
DA		 334/**
335 * edid_vendor - match a string against EDID's obfuscated vendor field
336 * @edid: EDID to match
337 * @vendor: vendor string
338 *
339 * Returns true if @vendor is in @edid, false otherwise
340 */
341static bool edid_vendor(struct edid *edid, char *vendor)
342{
343 char edid_vendor[3];
344
345 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
346 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
347 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
16456c87 348 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
f453ba04
DA		 349
350 return !strncmp(edid_vendor, vendor, 3);
351}
352
353/**
354 * edid_get_quirks - return quirk flags for a given EDID
355 * @edid: EDID to process
356 *
357 * This tells subsequent routines what fixes they need to apply.
358 */
359static u32 edid_get_quirks(struct edid *edid)
360{
361 struct edid_quirk *quirk;
362 int i;
363
364 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
365 quirk = &edid_quirk_list[i];
366
367 if (edid_vendor(edid, quirk->vendor) &&
368 (EDID_PRODUCT_ID(edid) == quirk->product_id))
369 return quirk->quirks;
370 }
371
372 return 0;
373}
374
375#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
376#define MODE_REFRESH_DIFF(m,r) (abs((m)->vrefresh - target_refresh))
377
378
379/**
380 * edid_fixup_preferred - set preferred modes based on quirk list
381 * @connector: has mode list to fix up
382 * @quirks: quirks list
383 *
384 * Walk the mode list for @connector, clearing the preferred status
385 * on existing modes and setting it anew for the right mode ala @quirks.
386 */
387static void edid_fixup_preferred(struct drm_connector *connector,
388 u32 quirks)
389{
390 struct drm_display_mode *t, *cur_mode, *preferred_mode;
f890607b 391 int target_refresh = 0;
f453ba04
DA		 392
393 if (list_empty(&connector->probed_modes))
394 return;
395
396 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
397 target_refresh = 60;
398 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
399 target_refresh = 75;
400
401 preferred_mode = list_first_entry(&connector->probed_modes,
402 struct drm_display_mode, head);
403
404 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
405 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
406
407 if (cur_mode == preferred_mode)
408 continue;
409
410 /* Largest mode is preferred */
411 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
412 preferred_mode = cur_mode;
413
414 /* At a given size, try to get closest to target refresh */
415 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
416 MODE_REFRESH_DIFF(cur_mode, target_refresh) <
417 MODE_REFRESH_DIFF(preferred_mode, target_refresh)) {
418 preferred_mode = cur_mode;
419 }
420 }
421
422 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
423}
424
aa9eaa1f
ZY		 425/*
426 * Add the Autogenerated from the DMT spec.
427 * This table is copied from xfree86/modes/xf86EdidModes.c.
428 * But the mode with Reduced blank feature is deleted.
429 */
430static struct drm_display_mode drm_dmt_modes[] = {
431 /* 640x350@85Hz */
432 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
433 736, 832, 0, 350, 382, 385, 445, 0,
434 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
435 /* 640x400@85Hz */
436 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
437 736, 832, 0, 400, 401, 404, 445, 0,
438 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
439 /* 720x400@85Hz */
440 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
441 828, 936, 0, 400, 401, 404, 446, 0,
442 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
443 /* 640x480@60Hz */
444 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
445 752, 800, 0, 480, 489, 492, 525, 0,
446 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
447 /* 640x480@72Hz */
448 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
449 704, 832, 0, 480, 489, 492, 520, 0,
450 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
451 /* 640x480@75Hz */
452 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
453 720, 840, 0, 480, 481, 484, 500, 0,
454 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
455 /* 640x480@85Hz */
456 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
457 752, 832, 0, 480, 481, 484, 509, 0,
458 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
459 /* 800x600@56Hz */
460 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
461 896, 1024, 0, 600, 601, 603, 625, 0,
462 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
463 /* 800x600@60Hz */
464 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
465 968, 1056, 0, 600, 601, 605, 628, 0,
466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
467 /* 800x600@72Hz */
468 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
469 976, 1040, 0, 600, 637, 643, 666, 0,
470 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
471 /* 800x600@75Hz */
472 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
473 896, 1056, 0, 600, 601, 604, 625, 0,
474 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
475 /* 800x600@85Hz */
476 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
477 896, 1048, 0, 600, 601, 604, 631, 0,
478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
479 /* 848x480@60Hz */
480 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
481 976, 1088, 0, 480, 486, 494, 517, 0,
482 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
483 /* 1024x768@43Hz, interlace */
484 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
485 1208, 1264, 0, 768, 768, 772, 817, 0,
486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
487 DRM_MODE_FLAG_INTERLACE) },
488 /* 1024x768@60Hz */
489 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
490 1184, 1344, 0, 768, 771, 777, 806, 0,
491 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
492 /* 1024x768@70Hz */
493 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
494 1184, 1328, 0, 768, 771, 777, 806, 0,
495 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
496 /* 1024x768@75Hz */
497 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
498 1136, 1312, 0, 768, 769, 772, 800, 0,
499 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
500 /* 1024x768@85Hz */
501 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
61dd98fa 502 1168, 1376, 0, 768, 769, 772, 808, 0,
aa9eaa1f
ZY		 503 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
504 /* 1152x864@75Hz */
505 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
506 1344, 1600, 0, 864, 865, 868, 900, 0,
507 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
508 /* 1280x768@60Hz */
509 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
510 1472, 1664, 0, 768, 771, 778, 798, 0,
511 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
512 /* 1280x768@75Hz */
513 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
514 1488, 1696, 0, 768, 771, 778, 805, 0,
515 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
516 /* 1280x768@85Hz */
517 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
518 1496, 1712, 0, 768, 771, 778, 809, 0,
519 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
520 /* 1280x800@60Hz */
521 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
522 1480, 1680, 0, 800, 803, 809, 831, 0,
523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
524 /* 1280x800@75Hz */
525 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
526 1488, 1696, 0, 800, 803, 809, 838, 0,
527 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
528 /* 1280x800@85Hz */
529 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
530 1496, 1712, 0, 800, 803, 809, 843, 0,
531 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
532 /* 1280x960@60Hz */
533 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
534 1488, 1800, 0, 960, 961, 964, 1000, 0,
535 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
536 /* 1280x960@85Hz */
537 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
538 1504, 1728, 0, 960, 961, 964, 1011, 0,
539 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
540 /* 1280x1024@60Hz */
541 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
542 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
543 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
544 /* 1280x1024@75Hz */
545 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
546 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
547 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
548 /* 1280x1024@85Hz */
549 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
550 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
551 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
552 /* 1360x768@60Hz */
553 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
554 1536, 1792, 0, 768, 771, 777, 795, 0,
555 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
556 /* 1440x1050@60Hz */
557 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
558 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
559 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
560 /* 1440x1050@75Hz */
561 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
562 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
563 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
564 /* 1440x1050@85Hz */
565 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
566 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
567 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
568 /* 1440x900@60Hz */
569 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
570 1672, 1904, 0, 900, 903, 909, 934, 0,
571 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
572 /* 1440x900@75Hz */
573 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
574 1688, 1936, 0, 900, 903, 909, 942, 0,
575 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
576 /* 1440x900@85Hz */
577 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
578 1696, 1952, 0, 900, 903, 909, 948, 0,
579 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
580 /* 1600x1200@60Hz */
581 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
582 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
583 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
584 /* 1600x1200@65Hz */
585 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
586 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
587 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
588 /* 1600x1200@70Hz */
589 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
590 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
591 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
592 /* 1600x1200@75Hz */
c43ae476 593 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
aa9eaa1f
ZY		 594 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
595 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
596 /* 1600x1200@85Hz */
597 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
598 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
599 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
600 /* 1680x1050@60Hz */
601 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
602 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
603 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
604 /* 1680x1050@75Hz */
605 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
606 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
607 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
608 /* 1680x1050@85Hz */
609 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
610 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
611 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
612 /* 1792x1344@60Hz */
613 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
614 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
615 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
616 /* 1729x1344@75Hz */
617 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
618 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
619 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
620 /* 1853x1392@60Hz */
621 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
622 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
623 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
624 /* 1856x1392@75Hz */
625 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
626 2208, 2560, 0, 1392, 1395, 1399, 1500, 0,
627 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
628 /* 1920x1200@60Hz */
629 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
630 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
631 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
632 /* 1920x1200@75Hz */
633 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
634 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
635 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
636 /* 1920x1200@85Hz */
637 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
638 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
639 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
640 /* 1920x1440@60Hz */
641 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
642 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
643 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
644 /* 1920x1440@75Hz */
645 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
646 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
647 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
648 /* 2560x1600@60Hz */
649 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
650 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
651 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
652 /* 2560x1600@75HZ */
653 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
654 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
655 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
656 /* 2560x1600@85HZ */
657 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
658 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
659 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
660};
07a5e632
AJ		 661static const int drm_num_dmt_modes =
662 sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode);
aa9eaa1f 663
1d42bbc8
DA		 664struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
665 int hsize, int vsize, int fresh)
559ee21d 666{
07a5e632 667 int i;
559ee21d
ZY		 668 struct drm_display_mode *ptr, *mode;
669
559ee21d 670 mode = NULL;
07a5e632 671 for (i = 0; i < drm_num_dmt_modes; i++) {
559ee21d
ZY		 672 ptr = &drm_dmt_modes[i];
673 if (hsize == ptr->hdisplay &&
674 vsize == ptr->vdisplay &&
675 fresh == drm_mode_vrefresh(ptr)) {
676 /* get the expected default mode */
677 mode = drm_mode_duplicate(dev, ptr);
678 break;
679 }
680 }
681 return mode;
682}
1d42bbc8 683EXPORT_SYMBOL(drm_mode_find_dmt);
23425cae 684
d1ff6409
AJ		 685typedef void detailed_cb(struct detailed_timing *timing, void *closure);
686
687static void
688drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
689{
690 int i;
691 struct edid *edid = (struct edid *)raw_edid;
692
693 if (edid == NULL)
694 return;
695
696 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
697 cb(&(edid->detailed_timings[i]), closure);
698
699 /* XXX extension block walk */
700}
701
702static void
703is_rb(struct detailed_timing *t, void *data)
704{
705 u8 *r = (u8 *)t;
706 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
707 if (r[15] & 0x10)
708 *(bool *)data = true;
709}
710
711/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
712static bool
713drm_monitor_supports_rb(struct edid *edid)
714{
715 if (edid->revision >= 4) {
716 bool ret;
717 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
718 return ret;
719 }
720
721 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
722}
723
7a374350
AJ		 724static void
725find_gtf2(struct detailed_timing *t, void *data)
726{
727 u8 *r = (u8 *)t;
728 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
729 *(u8 **)data = r;
730}
731
732/* Secondary GTF curve kicks in above some break frequency */
733static int
734drm_gtf2_hbreak(struct edid *edid)
735{
736 u8 *r = NULL;
737 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
738 return r ? (r[12] * 2) : 0;
739}
740
741static int
742drm_gtf2_2c(struct edid *edid)
743{
744 u8 *r = NULL;
745 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
746 return r ? r[13] : 0;
747}
748
749static int
750drm_gtf2_m(struct edid *edid)
751{
752 u8 *r = NULL;
753 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
754 return r ? (r[15] << 8) + r[14] : 0;
755}
756
757static int
758drm_gtf2_k(struct edid *edid)
759{
760 u8 *r = NULL;
761 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
762 return r ? r[16] : 0;
763}
764
765static int
766drm_gtf2_2j(struct edid *edid)
767{
768 u8 *r = NULL;
769 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
770 return r ? r[17] : 0;
771}
772
773/**
774 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
775 * @edid: EDID block to scan
776 */
777static int standard_timing_level(struct edid *edid)
778{
779 if (edid->revision >= 2) {
780 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
781 return LEVEL_CVT;
782 if (drm_gtf2_hbreak(edid))
783 return LEVEL_GTF2;
784 return LEVEL_GTF;
785 }
786 return LEVEL_DMT;
787}
788
23425cae
AJ		 789/*
790 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
791 * monitors fill with ascii space (0x20) instead.
792 */
793static int
794bad_std_timing(u8 a, u8 b)
795{
796 return (a == 0x00 && b == 0x00) ||
797 (a == 0x01 && b == 0x01) ||
798 (a == 0x20 && b == 0x20);
799}
800
f453ba04
DA		 801/**
802 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
803 * @t: standard timing params
5c61259e 804 * @timing_level: standard timing level
f453ba04
DA		 805 *
806 * Take the standard timing params (in this case width, aspect, and refresh)
5c61259e 807 * and convert them into a real mode using CVT/GTF/DMT.
f453ba04 808 */
7ca6adb3 809static struct drm_display_mode *
7a374350
AJ		 810drm_mode_std(struct drm_connector *connector, struct edid *edid,
811 struct std_timing *t, int revision)
f453ba04 812{
7ca6adb3
AJ		 813 struct drm_device *dev = connector->dev;
814 struct drm_display_mode *m, *mode = NULL;
5c61259e
ZY		 815 int hsize, vsize;
816 int vrefresh_rate;
0454beab
MD		 817 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
818 >> EDID_TIMING_ASPECT_SHIFT;
5c61259e
ZY		 819 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
820 >> EDID_TIMING_VFREQ_SHIFT;
7a374350 821 int timing_level = standard_timing_level(edid);
5c61259e 822
23425cae
AJ		 823 if (bad_std_timing(t->hsize, t->vfreq_aspect))
824 return NULL;
825
5c61259e
ZY		 826 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
827 hsize = t->hsize * 8 + 248;
828 /* vrefresh_rate = vfreq + 60 */
829 vrefresh_rate = vfreq + 60;
830 /* the vdisplay is calculated based on the aspect ratio */
f066a17d
AJ		 831 if (aspect_ratio == 0) {
832 if (revision < 3)
833 vsize = hsize;
834 else
835 vsize = (hsize * 10) / 16;
836 } else if (aspect_ratio == 1)
f453ba04 837 vsize = (hsize * 3) / 4;
0454beab 838 else if (aspect_ratio == 2)
f453ba04
DA		 839 vsize = (hsize * 4) / 5;
840 else
841 vsize = (hsize * 9) / 16;
a0910c8e
AJ		 842
843 /* HDTV hack, part 1 */
844 if (vrefresh_rate == 60 &&
845 ((hsize == 1360 && vsize == 765) ||
846 (hsize == 1368 && vsize == 769))) {
847 hsize = 1366;
848 vsize = 768;
849 }
850
7ca6adb3
AJ		 851 /*
852 * If this connector already has a mode for this size and refresh
853 * rate (because it came from detailed or CVT info), use that
854 * instead. This way we don't have to guess at interlace or
855 * reduced blanking.
856 */
522032da 857 list_for_each_entry(m, &connector->probed_modes, head)
7ca6adb3
AJ		 858 if (m->hdisplay == hsize && m->vdisplay == vsize &&
859 drm_mode_vrefresh(m) == vrefresh_rate)
860 return NULL;
861
a0910c8e
AJ		 862 /* HDTV hack, part 2 */
863 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
864 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
d50ba256 865 false);
559ee21d 866 mode->hdisplay = 1366;
a4967de6
AJ		 867 mode->hsync_start = mode->hsync_start - 1;
868 mode->hsync_end = mode->hsync_end - 1;
559ee21d
ZY		 869 return mode;
870 }
a0910c8e 871
559ee21d 872 /* check whether it can be found in default mode table */
1d42bbc8 873 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate);
559ee21d
ZY		 874 if (mode)
875 return mode;
876
5c61259e
ZY		 877 switch (timing_level) {
878 case LEVEL_DMT:
5c61259e
ZY		 879 break;
880 case LEVEL_GTF:
881 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
882 break;
7a374350
AJ		 883 case LEVEL_GTF2:
884 /*
885 * This is potentially wrong if there's ever a monitor with
886 * more than one ranges section, each claiming a different
887 * secondary GTF curve. Please don't do that.
888 */
889 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
890 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
891 kfree(mode);
892 mode = drm_gtf_mode_complex(dev, hsize, vsize,
893 vrefresh_rate, 0, 0,
894 drm_gtf2_m(edid),
895 drm_gtf2_2c(edid),
896 drm_gtf2_k(edid),
897 drm_gtf2_2j(edid));
898 }
899 break;
5c61259e 900 case LEVEL_CVT:
d50ba256
DA		 901 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
902 false);
5c61259e
ZY		 903 break;
904 }
f453ba04
DA		 905 return mode;
906}
907
b58db2c6
AJ		 908/*
909 * EDID is delightfully ambiguous about how interlaced modes are to be
910 * encoded. Our internal representation is of frame height, but some
911 * HDTV detailed timings are encoded as field height.
912 *
913 * The format list here is from CEA, in frame size. Technically we
914 * should be checking refresh rate too. Whatever.
915 */
916static void
917drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
918 struct detailed_pixel_timing *pt)
919{
920 int i;
921 static const struct {
922 int w, h;
923 } cea_interlaced[] = {
924 { 1920, 1080 },
925 { 720, 480 },
926 { 1440, 480 },
927 { 2880, 480 },
928 { 720, 576 },
929 { 1440, 576 },
930 { 2880, 576 },
931 };
932 static const int n_sizes =
933 sizeof(cea_interlaced)/sizeof(cea_interlaced[0]);
934
935 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
936 return;
937
938 for (i = 0; i < n_sizes; i++) {
939 if ((mode->hdisplay == cea_interlaced[i].w) &&
940 (mode->vdisplay == cea_interlaced[i].h / 2)) {
941 mode->vdisplay *= 2;
942 mode->vsync_start *= 2;
943 mode->vsync_end *= 2;
944 mode->vtotal *= 2;
945 mode->vtotal |= 1;
946 }
947 }
948
949 mode->flags |= DRM_MODE_FLAG_INTERLACE;
950}
951
f453ba04
DA		 952/**
953 * drm_mode_detailed - create a new mode from an EDID detailed timing section
954 * @dev: DRM device (needed to create new mode)
955 * @edid: EDID block
956 * @timing: EDID detailed timing info
957 * @quirks: quirks to apply
958 *
959 * An EDID detailed timing block contains enough info for us to create and
960 * return a new struct drm_display_mode.
961 */
962static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
963 struct edid *edid,
964 struct detailed_timing *timing,
965 u32 quirks)
966{
967 struct drm_display_mode *mode;
968 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
0454beab
MD		 969 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
970 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
971 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
972 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
e14cbee4
MD		 973 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
974 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
975 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) >> 2 | pt->vsync_offset_pulse_width_lo >> 4;
976 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
f453ba04 977
fc438966 978 /* ignore tiny modes */
0454beab 979 if (hactive < 64 || vactive < 64)
fc438966
AJ		 980 return NULL;
981
0454beab 982 if (pt->misc & DRM_EDID_PT_STEREO) {
f453ba04
DA		 983 printk(KERN_WARNING "stereo mode not supported\n");
984 return NULL;
985 }
0454beab 986 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
79b7dcb2 987 printk(KERN_WARNING "composite sync not supported\n");
f453ba04
DA		 988 }
989
fcb45611
ZY		 990 /* it is incorrect if hsync/vsync width is zero */
991 if (!hsync_pulse_width || !vsync_pulse_width) {
992 DRM_DEBUG_KMS("Incorrect Detailed timing. "
993 "Wrong Hsync/Vsync pulse width\n");
994 return NULL;
995 }
f453ba04
DA		 996 mode = drm_mode_create(dev);
997 if (!mode)
998 return NULL;
999
1000 mode->type = DRM_MODE_TYPE_DRIVER;
1001
1002 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
0454beab
MD		 1003 timing->pixel_clock = cpu_to_le16(1088);
1004
1005 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
1006
1007 mode->hdisplay = hactive;
1008 mode->hsync_start = mode->hdisplay + hsync_offset;
1009 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
1010 mode->htotal = mode->hdisplay + hblank;
1011
1012 mode->vdisplay = vactive;
1013 mode->vsync_start = mode->vdisplay + vsync_offset;
1014 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
1015 mode->vtotal = mode->vdisplay + vblank;
f453ba04 1016
7064fef5
JB		 1017 /* Some EDIDs have bogus h/vtotal values */
1018 if (mode->hsync_end > mode->htotal)
1019 mode->htotal = mode->hsync_end + 1;
1020 if (mode->vsync_end > mode->vtotal)
1021 mode->vtotal = mode->vsync_end + 1;
1022
b58db2c6 1023 drm_mode_do_interlace_quirk(mode, pt);
f453ba04 1024
171fdd89
AJ		 1025 drm_mode_set_name(mode);
1026
f453ba04 1027 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
0454beab 1028 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
f453ba04
DA		 1029 }
1030
0454beab
MD		 1031 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
1032 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
1033 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
1034 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
f453ba04 1035
e14cbee4
MD		 1036 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
1037 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
f453ba04
DA		 1038
1039 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
1040 mode->width_mm *= 10;
1041 mode->height_mm *= 10;
1042 }
1043
1044 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
1045 mode->width_mm = edid->width_cm * 10;
1046 mode->height_mm = edid->height_cm * 10;
1047 }
1048
1049 return mode;
1050}
1051
1052/*
1053 * Detailed mode info for the EDID "established modes" data to use.
1054 */
1055static struct drm_display_mode edid_est_modes[] = {
1056 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
1057 968, 1056, 0, 600, 601, 605, 628, 0,
1058 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
1059 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
1060 896, 1024, 0, 600, 601, 603, 625, 0,
1061 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
1062 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
1063 720, 840, 0, 480, 481, 484, 500, 0,
1064 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
1065 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
1066 704, 832, 0, 480, 489, 491, 520, 0,
1067 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
1068 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
1069 768, 864, 0, 480, 483, 486, 525, 0,
1070 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
1071 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656,
1072 752, 800, 0, 480, 490, 492, 525, 0,
1073 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
1074 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
1075 846, 900, 0, 400, 421, 423, 449, 0,
1076 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
1077 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
1078 846, 900, 0, 400, 412, 414, 449, 0,
1079 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
1080 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
1081 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
1082 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
1083 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040,
1084 1136, 1312, 0, 768, 769, 772, 800, 0,
1085 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
1086 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
1087 1184, 1328, 0, 768, 771, 777, 806, 0,
1088 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
1089 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
1090 1184, 1344, 0, 768, 771, 777, 806, 0,
1091 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
1092 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
1093 1208, 1264, 0, 768, 768, 776, 817, 0,
1094 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
1095 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
1096 928, 1152, 0, 624, 625, 628, 667, 0,
1097 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
1098 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
1099 896, 1056, 0, 600, 601, 604, 625, 0,
1100 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
1101 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
1102 976, 1040, 0, 600, 637, 643, 666, 0,
1103 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
1104 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
1105 1344, 1600, 0, 864, 865, 868, 900, 0,
1106 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
1107};
1108
f453ba04
DA		 1109/**
1110 * add_established_modes - get est. modes from EDID and add them
1111 * @edid: EDID block to scan
1112 *
1113 * Each EDID block contains a bitmap of the supported "established modes" list
1114 * (defined above). Tease them out and add them to the global modes list.
1115 */
1116static int add_established_modes(struct drm_connector *connector, struct edid *edid)
1117{
1118 struct drm_device *dev = connector->dev;
1119 unsigned long est_bits = edid->established_timings.t1 |
1120 (edid->established_timings.t2 << 8) |
1121 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
1122 int i, modes = 0;
1123
1124 for (i = 0; i <= EDID_EST_TIMINGS; i++)
1125 if (est_bits & (1<<i)) {
1126 struct drm_display_mode *newmode;
1127 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
1128 if (newmode) {
1129 drm_mode_probed_add(connector, newmode);
1130 modes++;
1131 }
1132 }
1133
1134 return modes;
1135}
1136
1137/**
1138 * add_standard_modes - get std. modes from EDID and add them
1139 * @edid: EDID block to scan
1140 *
1141 * Standard modes can be calculated using the CVT standard. Grab them from
1142 * @edid, calculate them, and add them to the list.
1143 */
1144static int add_standard_modes(struct drm_connector *connector, struct edid *edid)
1145{
f453ba04
DA		 1146 int i, modes = 0;
1147
1148 for (i = 0; i < EDID_STD_TIMINGS; i++) {
f453ba04
DA		 1149 struct drm_display_mode *newmode;
1150
7a374350
AJ		 1151 newmode = drm_mode_std(connector, edid,
1152 &edid->standard_timings[i],
1153 edid->revision);
f453ba04
DA		 1154 if (newmode) {
1155 drm_mode_probed_add(connector, newmode);
1156 modes++;
1157 }
1158 }
1159
1160 return modes;
1161}
1162
07a5e632 1163static bool
b17e52ef 1164mode_is_rb(struct drm_display_mode *mode)
07a5e632 1165{
b17e52ef
AJ		 1166 return (mode->htotal - mode->hdisplay == 160) &&
1167 (mode->hsync_end - mode->hdisplay == 80) &&
1168 (mode->hsync_end - mode->hsync_start == 32) &&
1169 (mode->vsync_start - mode->vdisplay == 3);
1170}
07a5e632 1171
b17e52ef
AJ		 1172static bool
1173mode_in_hsync_range(struct drm_display_mode *mode, struct edid *edid, u8 *t)
1174{
1175 int hsync, hmin, hmax;
1176
1177 hmin = t[7];
1178 if (edid->revision >= 4)
1179 hmin += ((t[4] & 0x04) ? 255 : 0);
1180 hmax = t[8];
1181 if (edid->revision >= 4)
1182 hmax += ((t[4] & 0x08) ? 255 : 0);
07a5e632 1183 hsync = drm_mode_hsync(mode);
07a5e632 1184
b17e52ef
AJ		 1185 return (hsync <= hmax && hsync >= hmin);
1186}
1187
1188static bool
1189mode_in_vsync_range(struct drm_display_mode *mode, struct edid *edid, u8 *t)
1190{
1191 int vsync, vmin, vmax;
1192
1193 vmin = t[5];
1194 if (edid->revision >= 4)
1195 vmin += ((t[4] & 0x01) ? 255 : 0);
1196 vmax = t[6];
1197 if (edid->revision >= 4)
1198 vmax += ((t[4] & 0x02) ? 255 : 0);
1199 vsync = drm_mode_vrefresh(mode);
1200
1201 return (vsync <= vmax && vsync >= vmin);
1202}
1203
1204static u32
1205range_pixel_clock(struct edid *edid, u8 *t)
1206{
1207 /* unspecified */
1208 if (t[9] == 0 || t[9] == 255)
1209 return 0;
1210
1211 /* 1.4 with CVT support gives us real precision, yay */
1212 if (edid->revision >= 4 && t[10] == 0x04)
1213 return (t[9] * 10000) - ((t[12] >> 2) * 250);
1214
1215 /* 1.3 is pathetic, so fuzz up a bit */
1216 return t[9] * 10000 + 5001;
1217}
1218
b17e52ef
AJ		 1219static bool
1220mode_in_range(struct drm_display_mode *mode, struct edid *edid,
1221 struct detailed_timing *timing)
1222{
1223 u32 max_clock;
1224 u8 *t = (u8 *)timing;
1225
1226 if (!mode_in_hsync_range(mode, edid, t))
07a5e632
AJ		 1227 return false;
1228
b17e52ef 1229 if (!mode_in_vsync_range(mode, edid, t))
07a5e632
AJ		 1230 return false;
1231
b17e52ef 1232 if ((max_clock = range_pixel_clock(edid, t)))
07a5e632
AJ		 1233 if (mode->clock > max_clock)
1234 return false;
b17e52ef
AJ		 1235
1236 /* 1.4 max horizontal check */
1237 if (edid->revision >= 4 && t[10] == 0x04)
1238 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
1239 return false;
1240
1241 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
1242 return false;
07a5e632
AJ		 1243
1244 return true;
1245}
1246
1247/*
1248 * XXX If drm_dmt_modes ever regrows the CVT-R modes (and it will) this will
1249 * need to account for them.
1250 */
b17e52ef
AJ		 1251static int
1252drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
1253 struct detailed_timing *timing)
07a5e632
AJ		 1254{
1255 int i, modes = 0;
1256 struct drm_display_mode *newmode;
1257 struct drm_device *dev = connector->dev;
1258
1259 for (i = 0; i < drm_num_dmt_modes; i++) {
b17e52ef 1260 if (mode_in_range(drm_dmt_modes + i, edid, timing)) {
07a5e632
AJ		 1261 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
1262 if (newmode) {
1263 drm_mode_probed_add(connector, newmode);
1264 modes++;
1265 }
1266 }
1267 }
1268
1269 return modes;
1270}
1271
9340d8cf
AJ		 1272static int drm_cvt_modes(struct drm_connector *connector,
1273 struct detailed_timing *timing)
1274{
1275 int i, j, modes = 0;
1276 struct drm_display_mode *newmode;
1277 struct drm_device *dev = connector->dev;
1278 struct cvt_timing *cvt;
1279 const int rates[] = { 60, 85, 75, 60, 50 };
69da3015 1280 const u8 empty[3] = { 0, 0, 0 };
9340d8cf
AJ		 1281
1282 for (i = 0; i < 4; i++) {
29ebdf92 1283 int uninitialized_var(width), height;
9340d8cf
AJ		 1284 cvt = &(timing->data.other_data.data.cvt[i]);
1285
69da3015
AJ		 1286 if (!memcmp(cvt->code, empty, 3))
1287 continue;
1288
8e10ee9a
AJ		 1289 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
1290 switch (cvt->code[1] & 0x0c) {
9340d8cf
AJ		 1291 case 0x00:
1292 width = height * 4 / 3;
1293 break;
8e10ee9a 1294 case 0x04:
9340d8cf
AJ		 1295 width = height * 16 / 9;
1296 break;
8e10ee9a 1297 case 0x08:
9340d8cf
AJ		 1298 width = height * 16 / 10;
1299 break;
8e10ee9a 1300 case 0x0c:
9340d8cf
AJ		 1301 width = height * 15 / 9;
1302 break;
1303 }
1304
1305 for (j = 1; j < 5; j++) {
1306 if (cvt->code[2] & (1 << j)) {
1307 newmode = drm_cvt_mode(dev, width, height,
1308 rates[j], j == 0,
1309 false, false);
1310 if (newmode) {
1311 drm_mode_probed_add(connector, newmode);
1312 modes++;
1313 }
1314 }
1315 }
1316 }
1317
1318 return modes;
1319}
1320
2255be14
AJ		 1321static const struct {
1322 short w;
1323 short h;
1324 short r;
1325 short rb;
1326} est3_modes[] = {
1327 /* byte 6 */
1328 { 640, 350, 85, 0 },
1329 { 640, 400, 85, 0 },
1330 { 720, 400, 85, 0 },
1331 { 640, 480, 85, 0 },
1332 { 848, 480, 60, 0 },
1333 { 800, 600, 85, 0 },
1334 { 1024, 768, 85, 0 },
1335 { 1152, 864, 75, 0 },
1336 /* byte 7 */
1337 { 1280, 768, 60, 1 },
1338 { 1280, 768, 60, 0 },
1339 { 1280, 768, 75, 0 },
1340 { 1280, 768, 85, 0 },
1341 { 1280, 960, 60, 0 },
1342 { 1280, 960, 85, 0 },
1343 { 1280, 1024, 60, 0 },
1344 { 1280, 1024, 85, 0 },
1345 /* byte 8 */
1346 { 1360, 768, 60, 0 },
1347 { 1440, 900, 60, 1 },
1348 { 1440, 900, 60, 0 },
1349 { 1440, 900, 75, 0 },
1350 { 1440, 900, 85, 0 },
1351 { 1400, 1050, 60, 1 },
1352 { 1400, 1050, 60, 0 },
1353 { 1400, 1050, 75, 0 },
1354 /* byte 9 */
1355 { 1400, 1050, 85, 0 },
1356 { 1680, 1050, 60, 1 },
1357 { 1680, 1050, 60, 0 },
1358 { 1680, 1050, 75, 0 },
1359 { 1680, 1050, 85, 0 },
1360 { 1600, 1200, 60, 0 },
1361 { 1600, 1200, 65, 0 },
1362 { 1600, 1200, 70, 0 },
1363 /* byte 10 */
1364 { 1600, 1200, 75, 0 },
1365 { 1600, 1200, 85, 0 },
1366 { 1792, 1344, 60, 0 },
1367 { 1792, 1344, 85, 0 },
1368 { 1856, 1392, 60, 0 },
1369 { 1856, 1392, 75, 0 },
1370 { 1920, 1200, 60, 1 },
1371 { 1920, 1200, 60, 0 },
1372 /* byte 11 */
1373 { 1920, 1200, 75, 0 },
1374 { 1920, 1200, 85, 0 },
1375 { 1920, 1440, 60, 0 },
1376 { 1920, 1440, 75, 0 },
1377};
1378static const int num_est3_modes = sizeof(est3_modes) / sizeof(est3_modes[0]);
1379
1380static int
1381drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
1382{
1383 int i, j, m, modes = 0;
1384 struct drm_display_mode *mode;
1385 u8 *est = ((u8 *)timing) + 5;
1386
1387 for (i = 0; i < 6; i++) {
1388 for (j = 7; j > 0; j--) {
1389 m = (i * 8) + (7 - j);
0ddfa7d5 1390 if (m >= num_est3_modes)
2255be14
AJ		 1391 break;
1392 if (est[i] & (1 << j)) {
1d42bbc8
DA		 1393 mode = drm_mode_find_dmt(connector->dev,
1394 est3_modes[m].w,
1395 est3_modes[m].h,
1396 est3_modes[m].r
1397 /*, est3_modes[m].rb */);
2255be14
AJ		 1398 if (mode) {
1399 drm_mode_probed_add(connector, mode);
1400 modes++;
1401 }
1402 }
1403 }
1404 }
1405
1406 return modes;
1407}
1408
9cf00977
AJ		 1409static int add_detailed_modes(struct drm_connector *connector,
1410 struct detailed_timing *timing,
1411 struct edid *edid, u32 quirks, int preferred)
1412{
1413 int i, modes = 0;
1414 struct detailed_non_pixel *data = &timing->data.other_data;
07a5e632 1415 int gtf = (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF);
9cf00977
AJ		 1416 struct drm_display_mode *newmode;
1417 struct drm_device *dev = connector->dev;
1418
1419 if (timing->pixel_clock) {
1420 newmode = drm_mode_detailed(dev, edid, timing, quirks);
1421 if (!newmode)
1422 return 0;
1423
1424 if (preferred)
1425 newmode->type |= DRM_MODE_TYPE_PREFERRED;
1426
1427 drm_mode_probed_add(connector, newmode);
1428 return 1;
1429 }
1430
1431 /* other timing types */
1432 switch (data->type) {
1433 case EDID_DETAIL_MONITOR_RANGE:
07a5e632 1434 if (gtf)
b17e52ef
AJ		 1435 modes += drm_gtf_modes_for_range(connector, edid,
1436 timing);
9cf00977
AJ		 1437 break;
1438 case EDID_DETAIL_STD_MODES:
1439 /* Six modes per detailed section */
1440 for (i = 0; i < 6; i++) {
1441 struct std_timing *std;
1442 struct drm_display_mode *newmode;
1443
1444 std = &data->data.timings[i];
7a374350
AJ		 1445 newmode = drm_mode_std(connector, edid, std,
1446 edid->revision);
9cf00977
AJ		 1447 if (newmode) {
1448 drm_mode_probed_add(connector, newmode);
1449 modes++;
1450 }
1451 }
1452 break;
9340d8cf
AJ		 1453 case EDID_DETAIL_CVT_3BYTE:
1454 modes += drm_cvt_modes(connector, timing);
1455 break;
2255be14
AJ		 1456 case EDID_DETAIL_EST_TIMINGS:
1457 modes += drm_est3_modes(connector, timing);
1458 break;
9cf00977
AJ		 1459 default:
1460 break;
1461 }
1462
1463 return modes;
1464}
1465
f453ba04 1466/**
9cf00977 1467 * add_detailed_info - get detailed mode info from EDID data
f453ba04
DA		 1468 * @connector: attached connector
1469 * @edid: EDID block to scan
1470 * @quirks: quirks to apply
1471 *
1472 * Some of the detailed timing sections may contain mode information. Grab
1473 * it and add it to the list.
1474 */
1475static int add_detailed_info(struct drm_connector *connector,
1476 struct edid *edid, u32 quirks)
1477{
9cf00977 1478 int i, modes = 0;
f453ba04
DA		 1479
1480 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) {
1481 struct detailed_timing *timing = &edid->detailed_timings[i];
a327f6b8
AJ		 1482 int preferred = (i == 0);
1483
1484 if (preferred && edid->version == 1 && edid->revision < 4)
1485 preferred = (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
f453ba04 1486
9cf00977
AJ		 1487 /* In 1.0, only timings are allowed */
1488 if (!timing->pixel_clock && edid->version == 1 &&
1489 edid->revision == 0)
1490 continue;
f453ba04 1491
9cf00977
AJ		 1492 modes += add_detailed_modes(connector, timing, edid, quirks,
1493 preferred);
f453ba04
DA		 1494 }
1495
1496 return modes;
1497}
9cf00977 1498
882f0219
ZY		 1499/**
1500 * add_detailed_mode_eedid - get detailed mode info from addtional timing
1501 * EDID block
1502 * @connector: attached connector
1503 * @edid: EDID block to scan(It is only to get addtional timing EDID block)
1504 * @quirks: quirks to apply
1505 *
1506 * Some of the detailed timing sections may contain mode information. Grab
1507 * it and add it to the list.
1508 */
1509static int add_detailed_info_eedid(struct drm_connector *connector,
1510 struct edid *edid, u32 quirks)
1511{
9cf00977 1512 int i, modes = 0;
882f0219
ZY		 1513 char *edid_ext = NULL;
1514 struct detailed_timing *timing;
882f0219 1515 int start_offset, end_offset;
882f0219 1516
59d8aff6 1517 if (edid->version == 1 && edid->revision < 3)
882f0219 1518 return 0;
59d8aff6 1519 if (!edid->extensions)
882f0219 1520 return 0;
882f0219
ZY		 1521
1522 /* Find CEA extension */
7466f4cc 1523 for (i = 0; i < edid->extensions; i++) {
882f0219 1524 edid_ext = (char *)edid + EDID_LENGTH * (i + 1);
882f0219
ZY		 1525 if (edid_ext[0] == 0x02)
1526 break;
1527 }
1528
59d8aff6 1529 if (i == edid->extensions)
882f0219 1530 return 0;
882f0219
ZY		 1531
1532 /* Get the start offset of detailed timing block */
1533 start_offset = edid_ext[2];
1534 if (start_offset == 0) {
1535 /* If the start_offset is zero, it means that neither detailed
1536 * info nor data block exist. In such case it is also
1537 * unnecessary to parse the detailed timing info.
1538 */
1539 return 0;
1540 }
1541
882f0219
ZY		 1542 end_offset = EDID_LENGTH;
1543 end_offset -= sizeof(struct detailed_timing);
1544 for (i = start_offset; i < end_offset;
1545 i += sizeof(struct detailed_timing)) {
1546 timing = (struct detailed_timing *)(edid_ext + i);
9cf00977 1547 modes += add_detailed_modes(connector, timing, edid, quirks, 0);
882f0219
ZY		 1548 }
1549
1550 return modes;
1551}
f453ba04 1552
f23c20c8
ML		 1553#define HDMI_IDENTIFIER 0x000C03
1554#define VENDOR_BLOCK 0x03
1555/**
1556 * drm_detect_hdmi_monitor - detect whether monitor is hdmi.
1557 * @edid: monitor EDID information
1558 *
1559 * Parse the CEA extension according to CEA-861-B.
1560 * Return true if HDMI, false if not or unknown.
1561 */
1562bool drm_detect_hdmi_monitor(struct edid *edid)
1563{
1564 char *edid_ext = NULL;
7466f4cc 1565 int i, hdmi_id;
f23c20c8
ML		 1566 int start_offset, end_offset;
1567 bool is_hdmi = false;
1568
1569 /* No EDID or EDID extensions */
1570 if (edid == NULL || edid->extensions == 0)
1571 goto end;
1572
f23c20c8 1573 /* Find CEA extension */
7466f4cc 1574 for (i = 0; i < edid->extensions; i++) {
f23c20c8
ML		 1575 edid_ext = (char *)edid + EDID_LENGTH * (i + 1);
1576 /* This block is CEA extension */
1577 if (edid_ext[0] == 0x02)
1578 break;
1579 }
1580
7466f4cc 1581 if (i == edid->extensions)
f23c20c8
ML		 1582 goto end;
1583
1584 /* Data block offset in CEA extension block */
1585 start_offset = 4;
1586 end_offset = edid_ext[2];
1587
1588 /*
1589 * Because HDMI identifier is in Vendor Specific Block,
1590 * search it from all data blocks of CEA extension.
1591 */
1592 for (i = start_offset; i < end_offset;
1593 /* Increased by data block len */
1594 i += ((edid_ext[i] & 0x1f) + 1)) {
1595 /* Find vendor specific block */
1596 if ((edid_ext[i] >> 5) == VENDOR_BLOCK) {
1597 hdmi_id = edid_ext[i + 1] | (edid_ext[i + 2] << 8) |
1598 edid_ext[i + 3] << 16;
1599 /* Find HDMI identifier */
1600 if (hdmi_id == HDMI_IDENTIFIER)
1601 is_hdmi = true;
1602 break;
1603 }
1604 }
1605
1606end:
1607 return is_hdmi;
1608}
1609EXPORT_SYMBOL(drm_detect_hdmi_monitor);
1610
f453ba04
DA		 1611/**
1612 * drm_add_edid_modes - add modes from EDID data, if available
1613 * @connector: connector we're probing
1614 * @edid: edid data
1615 *
1616 * Add the specified modes to the connector's mode list.
1617 *
1618 * Return number of modes added or 0 if we couldn't find any.
1619 */
1620int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
1621{
1622 int num_modes = 0;
1623 u32 quirks;
1624
1625 if (edid == NULL) {
1626 return 0;
1627 }
3c537889 1628 if (!drm_edid_is_valid(edid)) {
f453ba04
DA		 1629 dev_warn(&connector->dev->pdev->dev, "%s: EDID invalid.\n",
1630 drm_get_connector_name(connector));
1631 return 0;
1632 }
1633
1634 quirks = edid_get_quirks(edid);
1635
c867df70
AJ		 1636 /*
1637 * EDID spec says modes should be preferred in this order:
1638 * - preferred detailed mode
1639 * - other detailed modes from base block
1640 * - detailed modes from extension blocks
1641 * - CVT 3-byte code modes
1642 * - standard timing codes
1643 * - established timing codes
1644 * - modes inferred from GTF or CVT range information
1645 *
1646 * We don't quite implement this yet, but we're close.
1647 *
1648 * XXX order for additional mode types in extension blocks?
1649 */
f453ba04 1650 num_modes += add_detailed_info(connector, edid, quirks);
882f0219 1651 num_modes += add_detailed_info_eedid(connector, edid, quirks);
c867df70
AJ		 1652 num_modes += add_standard_modes(connector, edid);
1653 num_modes += add_established_modes(connector, edid);
f453ba04
DA		 1654
1655 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
1656 edid_fixup_preferred(connector, quirks);
1657
0454beab
MD		 1658 connector->display_info.serration_vsync = (edid->input & DRM_EDID_INPUT_SERRATION_VSYNC) ? 1 : 0;
1659 connector->display_info.sync_on_green = (edid->input & DRM_EDID_INPUT_SYNC_ON_GREEN) ? 1 : 0;
1660 connector->display_info.composite_sync = (edid->input & DRM_EDID_INPUT_COMPOSITE_SYNC) ? 1 : 0;
1661 connector->display_info.separate_syncs = (edid->input & DRM_EDID_INPUT_SEPARATE_SYNCS) ? 1 : 0;
1662 connector->display_info.blank_to_black = (edid->input & DRM_EDID_INPUT_BLANK_TO_BLACK) ? 1 : 0;
1663 connector->display_info.video_level = (edid->input & DRM_EDID_INPUT_VIDEO_LEVEL) >> 5;
1664 connector->display_info.digital = (edid->input & DRM_EDID_INPUT_DIGITAL) ? 1 : 0;
f453ba04
DA		 1665 connector->display_info.width_mm = edid->width_cm * 10;
1666 connector->display_info.height_mm = edid->height_cm * 10;
1667 connector->display_info.gamma = edid->gamma;
0454beab
MD		 1668 connector->display_info.gtf_supported = (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) ? 1 : 0;
1669 connector->display_info.standard_color = (edid->features & DRM_EDID_FEATURE_STANDARD_COLOR) ? 1 : 0;
1670 connector->display_info.display_type = (edid->features & DRM_EDID_FEATURE_DISPLAY_TYPE) >> 3;
1671 connector->display_info.active_off_supported = (edid->features & DRM_EDID_FEATURE_PM_ACTIVE_OFF) ? 1 : 0;
1672 connector->display_info.suspend_supported = (edid->features & DRM_EDID_FEATURE_PM_SUSPEND) ? 1 : 0;
1673 connector->display_info.standby_supported = (edid->features & DRM_EDID_FEATURE_PM_STANDBY) ? 1 : 0;
f453ba04
DA		 1674 connector->display_info.gamma = edid->gamma;
1675
1676 return num_modes;
1677}
1678EXPORT_SYMBOL(drm_add_edid_modes);
f0fda0a4
ZY		 1679
1680/**
1681 * drm_add_modes_noedid - add modes for the connectors without EDID
1682 * @connector: connector we're probing
1683 * @hdisplay: the horizontal display limit
1684 * @vdisplay: the vertical display limit
1685 *
1686 * Add the specified modes to the connector's mode list. Only when the
1687 * hdisplay/vdisplay is not beyond the given limit, it will be added.
1688 *
1689 * Return number of modes added or 0 if we couldn't find any.
1690 */
1691int drm_add_modes_noedid(struct drm_connector *connector,
1692 int hdisplay, int vdisplay)
1693{
1694 int i, count, num_modes = 0;
1695 struct drm_display_mode *mode, *ptr;
1696 struct drm_device *dev = connector->dev;
1697
1698 count = sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode);
1699 if (hdisplay < 0)
1700 hdisplay = 0;
1701 if (vdisplay < 0)
1702 vdisplay = 0;
1703
1704 for (i = 0; i < count; i++) {
1705 ptr = &drm_dmt_modes[i];
1706 if (hdisplay && vdisplay) {
1707 /*
1708 * Only when two are valid, they will be used to check
1709 * whether the mode should be added to the mode list of
1710 * the connector.
1711 */
1712 if (ptr->hdisplay > hdisplay ||
1713 ptr->vdisplay > vdisplay)
1714 continue;
1715 }
f985dedb
AJ		 1716 if (drm_mode_vrefresh(ptr) > 61)
1717 continue;
f0fda0a4
ZY		 1718 mode = drm_mode_duplicate(dev, ptr);
1719 if (mode) {
1720 drm_mode_probed_add(connector, mode);
1721 num_modes++;
1722 }
1723 }
1724 return num_modes;
1725}
1726EXPORT_SYMBOL(drm_add_modes_noedid);
Clone of davem's net-next-2.6 tree