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ahci: fix module refcount breakage introduced by libahci split
[net-next-2.6.git] / drivers / ata / libahci.c
CommitLineData
365cfa1e
AV		 1/*
2 * libahci.c - Common AHCI SATA low-level routines
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35#include <linux/kernel.h>
fbaf666b 36#include <linux/gfp.h>
365cfa1e
AV		 37#include <linux/module.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
42#include <linux/dma-mapping.h>
43#include <linux/device.h>
44#include <scsi/scsi_host.h>
45#include <scsi/scsi_cmnd.h>
46#include <linux/libata.h>
47#include "ahci.h"
48
49static int ahci_skip_host_reset;
50int ahci_ignore_sss;
51EXPORT_SYMBOL_GPL(ahci_ignore_sss);
52
53module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
54MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
55
56module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
57MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
58
59static int ahci_enable_alpm(struct ata_port *ap,
60 enum link_pm policy);
61static void ahci_disable_alpm(struct ata_port *ap);
62static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
63static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
64 size_t size);
65static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
66 ssize_t size);
67
68
69
70static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
71static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
72static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
73static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
74static int ahci_port_start(struct ata_port *ap);
75static void ahci_port_stop(struct ata_port *ap);
76static void ahci_qc_prep(struct ata_queued_cmd *qc);
77static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
78static void ahci_freeze(struct ata_port *ap);
79static void ahci_thaw(struct ata_port *ap);
80static void ahci_enable_fbs(struct ata_port *ap);
81static void ahci_disable_fbs(struct ata_port *ap);
82static void ahci_pmp_attach(struct ata_port *ap);
83static void ahci_pmp_detach(struct ata_port *ap);
84static int ahci_softreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86static int ahci_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
88static void ahci_postreset(struct ata_link *link, unsigned int *class);
89static void ahci_error_handler(struct ata_port *ap);
90static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
91static int ahci_port_resume(struct ata_port *ap);
92static void ahci_dev_config(struct ata_device *dev);
93static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
94 u32 opts);
95#ifdef CONFIG_PM
96static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
97#endif
98static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
99static ssize_t ahci_activity_store(struct ata_device *dev,
100 enum sw_activity val);
101static void ahci_init_sw_activity(struct ata_link *link);
102
103static ssize_t ahci_show_host_caps(struct device *dev,
104 struct device_attribute *attr, char *buf);
105static ssize_t ahci_show_host_cap2(struct device *dev,
106 struct device_attribute *attr, char *buf);
107static ssize_t ahci_show_host_version(struct device *dev,
108 struct device_attribute *attr, char *buf);
109static ssize_t ahci_show_port_cmd(struct device *dev,
110 struct device_attribute *attr, char *buf);
c0623166
HZ		 111static ssize_t ahci_read_em_buffer(struct device *dev,
112 struct device_attribute *attr, char *buf);
113static ssize_t ahci_store_em_buffer(struct device *dev,
114 struct device_attribute *attr,
115 const char *buf, size_t size);
365cfa1e
AV		 116
117static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
118static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
119static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
120static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
c0623166
HZ		 121static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
122 ahci_read_em_buffer, ahci_store_em_buffer);
365cfa1e 123
fad16e7a 124struct device_attribute *ahci_shost_attrs[] = {
365cfa1e
AV		 125 &dev_attr_link_power_management_policy,
126 &dev_attr_em_message_type,
127 &dev_attr_em_message,
128 &dev_attr_ahci_host_caps,
129 &dev_attr_ahci_host_cap2,
130 &dev_attr_ahci_host_version,
131 &dev_attr_ahci_port_cmd,
c0623166 132 &dev_attr_em_buffer,
365cfa1e
AV		 133 NULL
134};
fad16e7a 135EXPORT_SYMBOL_GPL(ahci_shost_attrs);
365cfa1e 136
fad16e7a 137struct device_attribute *ahci_sdev_attrs[] = {
365cfa1e
AV		 138 &dev_attr_sw_activity,
139 &dev_attr_unload_heads,
140 NULL
141};
fad16e7a 142EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
365cfa1e
AV		 143
144struct ata_port_operations ahci_ops = {
145 .inherits = &sata_pmp_port_ops,
146
147 .qc_defer = ahci_pmp_qc_defer,
148 .qc_prep = ahci_qc_prep,
149 .qc_issue = ahci_qc_issue,
150 .qc_fill_rtf = ahci_qc_fill_rtf,
151
152 .freeze = ahci_freeze,
153 .thaw = ahci_thaw,
154 .softreset = ahci_softreset,
155 .hardreset = ahci_hardreset,
156 .postreset = ahci_postreset,
157 .pmp_softreset = ahci_softreset,
158 .error_handler = ahci_error_handler,
159 .post_internal_cmd = ahci_post_internal_cmd,
160 .dev_config = ahci_dev_config,
161
162 .scr_read = ahci_scr_read,
163 .scr_write = ahci_scr_write,
164 .pmp_attach = ahci_pmp_attach,
165 .pmp_detach = ahci_pmp_detach,
166
167 .enable_pm = ahci_enable_alpm,
168 .disable_pm = ahci_disable_alpm,
169 .em_show = ahci_led_show,
170 .em_store = ahci_led_store,
171 .sw_activity_show = ahci_activity_show,
172 .sw_activity_store = ahci_activity_store,
173#ifdef CONFIG_PM
174 .port_suspend = ahci_port_suspend,
175 .port_resume = ahci_port_resume,
176#endif
177 .port_start = ahci_port_start,
178 .port_stop = ahci_port_stop,
179};
180EXPORT_SYMBOL_GPL(ahci_ops);
181
182int ahci_em_messages = 1;
183EXPORT_SYMBOL_GPL(ahci_em_messages);
184module_param(ahci_em_messages, int, 0444);
185/* add other LED protocol types when they become supported */
186MODULE_PARM_DESC(ahci_em_messages,
008dbd61 187 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
365cfa1e
AV		 188
189static void ahci_enable_ahci(void __iomem *mmio)
190{
191 int i;
192 u32 tmp;
193
194 /* turn on AHCI_EN */
195 tmp = readl(mmio + HOST_CTL);
196 if (tmp & HOST_AHCI_EN)
197 return;
198
199 /* Some controllers need AHCI_EN to be written multiple times.
200 * Try a few times before giving up.
201 */
202 for (i = 0; i < 5; i++) {
203 tmp |= HOST_AHCI_EN;
204 writel(tmp, mmio + HOST_CTL);
205 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
206 if (tmp & HOST_AHCI_EN)
207 return;
208 msleep(10);
209 }
210
211 WARN_ON(1);
212}
213
214static ssize_t ahci_show_host_caps(struct device *dev,
215 struct device_attribute *attr, char *buf)
216{
217 struct Scsi_Host *shost = class_to_shost(dev);
218 struct ata_port *ap = ata_shost_to_port(shost);
219 struct ahci_host_priv *hpriv = ap->host->private_data;
220
221 return sprintf(buf, "%x\n", hpriv->cap);
222}
223
224static ssize_t ahci_show_host_cap2(struct device *dev,
225 struct device_attribute *attr, char *buf)
226{
227 struct Scsi_Host *shost = class_to_shost(dev);
228 struct ata_port *ap = ata_shost_to_port(shost);
229 struct ahci_host_priv *hpriv = ap->host->private_data;
230
231 return sprintf(buf, "%x\n", hpriv->cap2);
232}
233
234static ssize_t ahci_show_host_version(struct device *dev,
235 struct device_attribute *attr, char *buf)
236{
237 struct Scsi_Host *shost = class_to_shost(dev);
238 struct ata_port *ap = ata_shost_to_port(shost);
239 struct ahci_host_priv *hpriv = ap->host->private_data;
240 void __iomem *mmio = hpriv->mmio;
241
242 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
243}
244
245static ssize_t ahci_show_port_cmd(struct device *dev,
246 struct device_attribute *attr, char *buf)
247{
248 struct Scsi_Host *shost = class_to_shost(dev);
249 struct ata_port *ap = ata_shost_to_port(shost);
250 void __iomem *port_mmio = ahci_port_base(ap);
251
252 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
253}
254
c0623166
HZ		 255static ssize_t ahci_read_em_buffer(struct device *dev,
256 struct device_attribute *attr, char *buf)
257{
258 struct Scsi_Host *shost = class_to_shost(dev);
259 struct ata_port *ap = ata_shost_to_port(shost);
260 struct ahci_host_priv *hpriv = ap->host->private_data;
261 void __iomem *mmio = hpriv->mmio;
262 void __iomem *em_mmio = mmio + hpriv->em_loc;
263 u32 em_ctl, msg;
264 unsigned long flags;
265 size_t count;
266 int i;
267
268 spin_lock_irqsave(ap->lock, flags);
269
270 em_ctl = readl(mmio + HOST_EM_CTL);
271 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
272 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
273 spin_unlock_irqrestore(ap->lock, flags);
274 return -EINVAL;
275 }
276
277 if (!(em_ctl & EM_CTL_MR)) {
278 spin_unlock_irqrestore(ap->lock, flags);
279 return -EAGAIN;
280 }
281
282 if (!(em_ctl & EM_CTL_SMB))
283 em_mmio += hpriv->em_buf_sz;
284
285 count = hpriv->em_buf_sz;
286
287 /* the count should not be larger than PAGE_SIZE */
288 if (count > PAGE_SIZE) {
289 if (printk_ratelimit())
290 ata_port_printk(ap, KERN_WARNING,
291 "EM read buffer size too large: "
292 "buffer size %u, page size %lu\n",
293 hpriv->em_buf_sz, PAGE_SIZE);
294 count = PAGE_SIZE;
295 }
296
297 for (i = 0; i < count; i += 4) {
298 msg = readl(em_mmio + i);
299 buf[i] = msg & 0xff;
300 buf[i + 1] = (msg >> 8) & 0xff;
301 buf[i + 2] = (msg >> 16) & 0xff;
302 buf[i + 3] = (msg >> 24) & 0xff;
303 }
304
305 spin_unlock_irqrestore(ap->lock, flags);
306
307 return i;
308}
309
310static ssize_t ahci_store_em_buffer(struct device *dev,
311 struct device_attribute *attr,
312 const char *buf, size_t size)
313{
314 struct Scsi_Host *shost = class_to_shost(dev);
315 struct ata_port *ap = ata_shost_to_port(shost);
316 struct ahci_host_priv *hpriv = ap->host->private_data;
317 void __iomem *mmio = hpriv->mmio;
318 void __iomem *em_mmio = mmio + hpriv->em_loc;
f9ce889b 319 const unsigned char *msg_buf = buf;
c0623166
HZ		 320 u32 em_ctl, msg;
321 unsigned long flags;
322 int i;
323
324 /* check size validity */
325 if (!(ap->flags & ATA_FLAG_EM) ||
326 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
327 size % 4 || size > hpriv->em_buf_sz)
328 return -EINVAL;
329
330 spin_lock_irqsave(ap->lock, flags);
331
332 em_ctl = readl(mmio + HOST_EM_CTL);
333 if (em_ctl & EM_CTL_TM) {
334 spin_unlock_irqrestore(ap->lock, flags);
335 return -EBUSY;
336 }
337
338 for (i = 0; i < size; i += 4) {
f9ce889b
HZ		 339 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
340 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
c0623166
HZ		 341 writel(msg, em_mmio + i);
342 }
343
344 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
345
346 spin_unlock_irqrestore(ap->lock, flags);
347
348 return size;
349}
350
365cfa1e
AV		 351/**
352 * ahci_save_initial_config - Save and fixup initial config values
353 * @dev: target AHCI device
354 * @hpriv: host private area to store config values
355 * @force_port_map: force port map to a specified value
356 * @mask_port_map: mask out particular bits from port map
357 *
358 * Some registers containing configuration info might be setup by
359 * BIOS and might be cleared on reset. This function saves the
360 * initial values of those registers into @hpriv such that they
361 * can be restored after controller reset.
362 *
363 * If inconsistent, config values are fixed up by this function.
364 *
365 * LOCKING:
366 * None.
367 */
368void ahci_save_initial_config(struct device *dev,
369 struct ahci_host_priv *hpriv,
370 unsigned int force_port_map,
371 unsigned int mask_port_map)
372{
373 void __iomem *mmio = hpriv->mmio;
374 u32 cap, cap2, vers, port_map;
375 int i;
376
377 /* make sure AHCI mode is enabled before accessing CAP */
378 ahci_enable_ahci(mmio);
379
380 /* Values prefixed with saved_ are written back to host after
381 * reset. Values without are used for driver operation.
382 */
383 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
384 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
385
386 /* CAP2 register is only defined for AHCI 1.2 and later */
387 vers = readl(mmio + HOST_VERSION);
388 if ((vers >> 16) > 1 ||
389 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
390 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
391 else
392 hpriv->saved_cap2 = cap2 = 0;
393
394 /* some chips have errata preventing 64bit use */
395 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
396 dev_printk(KERN_INFO, dev,
397 "controller can't do 64bit DMA, forcing 32bit\n");
398 cap &= ~HOST_CAP_64;
399 }
400
401 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
402 dev_printk(KERN_INFO, dev,
403 "controller can't do NCQ, turning off CAP_NCQ\n");
404 cap &= ~HOST_CAP_NCQ;
405 }
406
407 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
408 dev_printk(KERN_INFO, dev,
409 "controller can do NCQ, turning on CAP_NCQ\n");
410 cap |= HOST_CAP_NCQ;
411 }
412
413 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
414 dev_printk(KERN_INFO, dev,
415 "controller can't do PMP, turning off CAP_PMP\n");
416 cap &= ~HOST_CAP_PMP;
417 }
418
419 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
420 dev_printk(KERN_INFO, dev,
421 "controller can't do SNTF, turning off CAP_SNTF\n");
422 cap &= ~HOST_CAP_SNTF;
423 }
424
5f173107
TH		 425 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
426 dev_printk(KERN_INFO, dev,
427 "controller can do FBS, turning on CAP_FBS\n");
428 cap |= HOST_CAP_FBS;
429 }
430
365cfa1e
AV		 431 if (force_port_map && port_map != force_port_map) {
432 dev_printk(KERN_INFO, dev, "forcing port_map 0x%x -> 0x%x\n",
433 port_map, force_port_map);
434 port_map = force_port_map;
435 }
436
437 if (mask_port_map) {
438 dev_printk(KERN_ERR, dev, "masking port_map 0x%x -> 0x%x\n",
439 port_map,
440 port_map & mask_port_map);
441 port_map &= mask_port_map;
442 }
443
444 /* cross check port_map and cap.n_ports */
445 if (port_map) {
446 int map_ports = 0;
447
448 for (i = 0; i < AHCI_MAX_PORTS; i++)
449 if (port_map & (1 << i))
450 map_ports++;
451
452 /* If PI has more ports than n_ports, whine, clear
453 * port_map and let it be generated from n_ports.
454 */
455 if (map_ports > ahci_nr_ports(cap)) {
456 dev_printk(KERN_WARNING, dev,
457 "implemented port map (0x%x) contains more "
458 "ports than nr_ports (%u), using nr_ports\n",
459 port_map, ahci_nr_ports(cap));
460 port_map = 0;
461 }
462 }
463
464 /* fabricate port_map from cap.nr_ports */
465 if (!port_map) {
466 port_map = (1 << ahci_nr_ports(cap)) - 1;
467 dev_printk(KERN_WARNING, dev,
468 "forcing PORTS_IMPL to 0x%x\n", port_map);
469
470 /* write the fixed up value to the PI register */
471 hpriv->saved_port_map = port_map;
472 }
473
474 /* record values to use during operation */
475 hpriv->cap = cap;
476 hpriv->cap2 = cap2;
477 hpriv->port_map = port_map;
478}
479EXPORT_SYMBOL_GPL(ahci_save_initial_config);
480
481/**
482 * ahci_restore_initial_config - Restore initial config
483 * @host: target ATA host
484 *
485 * Restore initial config stored by ahci_save_initial_config().
486 *
487 * LOCKING:
488 * None.
489 */
490static void ahci_restore_initial_config(struct ata_host *host)
491{
492 struct ahci_host_priv *hpriv = host->private_data;
493 void __iomem *mmio = hpriv->mmio;
494
495 writel(hpriv->saved_cap, mmio + HOST_CAP);
496 if (hpriv->saved_cap2)
497 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
498 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
499 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
500}
501
502static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
503{
504 static const int offset[] = {
505 [SCR_STATUS] = PORT_SCR_STAT,
506 [SCR_CONTROL] = PORT_SCR_CTL,
507 [SCR_ERROR] = PORT_SCR_ERR,
508 [SCR_ACTIVE] = PORT_SCR_ACT,
509 [SCR_NOTIFICATION] = PORT_SCR_NTF,
510 };
511 struct ahci_host_priv *hpriv = ap->host->private_data;
512
513 if (sc_reg < ARRAY_SIZE(offset) &&
514 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
515 return offset[sc_reg];
516 return 0;
517}
518
519static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
520{
521 void __iomem *port_mmio = ahci_port_base(link->ap);
522 int offset = ahci_scr_offset(link->ap, sc_reg);
523
524 if (offset) {
525 *val = readl(port_mmio + offset);
526 return 0;
527 }
528 return -EINVAL;
529}
530
531static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
532{
533 void __iomem *port_mmio = ahci_port_base(link->ap);
534 int offset = ahci_scr_offset(link->ap, sc_reg);
535
536 if (offset) {
537 writel(val, port_mmio + offset);
538 return 0;
539 }
540 return -EINVAL;
541}
542
543void ahci_start_engine(struct ata_port *ap)
544{
545 void __iomem *port_mmio = ahci_port_base(ap);
546 u32 tmp;
547
548 /* start DMA */
549 tmp = readl(port_mmio + PORT_CMD);
550 tmp |= PORT_CMD_START;
551 writel(tmp, port_mmio + PORT_CMD);
552 readl(port_mmio + PORT_CMD); /* flush */
553}
554EXPORT_SYMBOL_GPL(ahci_start_engine);
555
556int ahci_stop_engine(struct ata_port *ap)
557{
558 void __iomem *port_mmio = ahci_port_base(ap);
559 u32 tmp;
560
561 tmp = readl(port_mmio + PORT_CMD);
562
563 /* check if the HBA is idle */
564 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
565 return 0;
566
567 /* setting HBA to idle */
568 tmp &= ~PORT_CMD_START;
569 writel(tmp, port_mmio + PORT_CMD);
570
571 /* wait for engine to stop. This could be as long as 500 msec */
572 tmp = ata_wait_register(port_mmio + PORT_CMD,
573 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
574 if (tmp & PORT_CMD_LIST_ON)
575 return -EIO;
576
577 return 0;
578}
579EXPORT_SYMBOL_GPL(ahci_stop_engine);
580
581static void ahci_start_fis_rx(struct ata_port *ap)
582{
583 void __iomem *port_mmio = ahci_port_base(ap);
584 struct ahci_host_priv *hpriv = ap->host->private_data;
585 struct ahci_port_priv *pp = ap->private_data;
586 u32 tmp;
587
588 /* set FIS registers */
589 if (hpriv->cap & HOST_CAP_64)
590 writel((pp->cmd_slot_dma >> 16) >> 16,
591 port_mmio + PORT_LST_ADDR_HI);
592 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
593
594 if (hpriv->cap & HOST_CAP_64)
595 writel((pp->rx_fis_dma >> 16) >> 16,
596 port_mmio + PORT_FIS_ADDR_HI);
597 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
598
599 /* enable FIS reception */
600 tmp = readl(port_mmio + PORT_CMD);
601 tmp |= PORT_CMD_FIS_RX;
602 writel(tmp, port_mmio + PORT_CMD);
603
604 /* flush */
605 readl(port_mmio + PORT_CMD);
606}
607
608static int ahci_stop_fis_rx(struct ata_port *ap)
609{
610 void __iomem *port_mmio = ahci_port_base(ap);
611 u32 tmp;
612
613 /* disable FIS reception */
614 tmp = readl(port_mmio + PORT_CMD);
615 tmp &= ~PORT_CMD_FIS_RX;
616 writel(tmp, port_mmio + PORT_CMD);
617
618 /* wait for completion, spec says 500ms, give it 1000 */
619 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
620 PORT_CMD_FIS_ON, 10, 1000);
621 if (tmp & PORT_CMD_FIS_ON)
622 return -EBUSY;
623
624 return 0;
625}
626
627static void ahci_power_up(struct ata_port *ap)
628{
629 struct ahci_host_priv *hpriv = ap->host->private_data;
630 void __iomem *port_mmio = ahci_port_base(ap);
631 u32 cmd;
632
633 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
634
635 /* spin up device */
636 if (hpriv->cap & HOST_CAP_SSS) {
637 cmd |= PORT_CMD_SPIN_UP;
638 writel(cmd, port_mmio + PORT_CMD);
639 }
640
641 /* wake up link */
642 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
643}
644
645static void ahci_disable_alpm(struct ata_port *ap)
646{
647 struct ahci_host_priv *hpriv = ap->host->private_data;
648 void __iomem *port_mmio = ahci_port_base(ap);
649 u32 cmd;
650 struct ahci_port_priv *pp = ap->private_data;
651
652 /* IPM bits should be disabled by libata-core */
653 /* get the existing command bits */
654 cmd = readl(port_mmio + PORT_CMD);
655
656 /* disable ALPM and ASP */
657 cmd &= ~PORT_CMD_ASP;
658 cmd &= ~PORT_CMD_ALPE;
659
660 /* force the interface back to active */
661 cmd |= PORT_CMD_ICC_ACTIVE;
662
663 /* write out new cmd value */
664 writel(cmd, port_mmio + PORT_CMD);
665 cmd = readl(port_mmio + PORT_CMD);
666
667 /* wait 10ms to be sure we've come out of any low power state */
668 msleep(10);
669
670 /* clear out any PhyRdy stuff from interrupt status */
671 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
672
673 /* go ahead and clean out PhyRdy Change from Serror too */
674 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
675
676 /*
677 * Clear flag to indicate that we should ignore all PhyRdy
678 * state changes
679 */
680 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
681
682 /*
683 * Enable interrupts on Phy Ready.
684 */
685 pp->intr_mask |= PORT_IRQ_PHYRDY;
686 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
687
688 /*
689 * don't change the link pm policy - we can be called
690 * just to turn of link pm temporarily
691 */
692}
693
694static int ahci_enable_alpm(struct ata_port *ap,
695 enum link_pm policy)
696{
697 struct ahci_host_priv *hpriv = ap->host->private_data;
698 void __iomem *port_mmio = ahci_port_base(ap);
699 u32 cmd;
700 struct ahci_port_priv *pp = ap->private_data;
701 u32 asp;
702
703 /* Make sure the host is capable of link power management */
704 if (!(hpriv->cap & HOST_CAP_ALPM))
705 return -EINVAL;
706
707 switch (policy) {
708 case MAX_PERFORMANCE:
709 case NOT_AVAILABLE:
710 /*
711 * if we came here with NOT_AVAILABLE,
712 * it just means this is the first time we
713 * have tried to enable - default to max performance,
714 * and let the user go to lower power modes on request.
715 */
716 ahci_disable_alpm(ap);
717 return 0;
718 case MIN_POWER:
719 /* configure HBA to enter SLUMBER */
720 asp = PORT_CMD_ASP;
721 break;
722 case MEDIUM_POWER:
723 /* configure HBA to enter PARTIAL */
724 asp = 0;
725 break;
726 default:
727 return -EINVAL;
728 }
729
730 /*
731 * Disable interrupts on Phy Ready. This keeps us from
732 * getting woken up due to spurious phy ready interrupts
733 * TBD - Hot plug should be done via polling now, is
734 * that even supported?
735 */
736 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
737 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
738
739 /*
740 * Set a flag to indicate that we should ignore all PhyRdy
741 * state changes since these can happen now whenever we
742 * change link state
743 */
744 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
745
746 /* get the existing command bits */
747 cmd = readl(port_mmio + PORT_CMD);
748
749 /*
750 * Set ASP based on Policy
751 */
752 cmd |= asp;
753
754 /*
755 * Setting this bit will instruct the HBA to aggressively
756 * enter a lower power link state when it's appropriate and
757 * based on the value set above for ASP
758 */
759 cmd |= PORT_CMD_ALPE;
760
761 /* write out new cmd value */
762 writel(cmd, port_mmio + PORT_CMD);
763 cmd = readl(port_mmio + PORT_CMD);
764
765 /* IPM bits should be set by libata-core */
766 return 0;
767}
768
769#ifdef CONFIG_PM
770static void ahci_power_down(struct ata_port *ap)
771{
772 struct ahci_host_priv *hpriv = ap->host->private_data;
773 void __iomem *port_mmio = ahci_port_base(ap);
774 u32 cmd, scontrol;
775
776 if (!(hpriv->cap & HOST_CAP_SSS))
777 return;
778
779 /* put device into listen mode, first set PxSCTL.DET to 0 */
780 scontrol = readl(port_mmio + PORT_SCR_CTL);
781 scontrol &= ~0xf;
782 writel(scontrol, port_mmio + PORT_SCR_CTL);
783
784 /* then set PxCMD.SUD to 0 */
785 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
786 cmd &= ~PORT_CMD_SPIN_UP;
787 writel(cmd, port_mmio + PORT_CMD);
788}
789#endif
790
791static void ahci_start_port(struct ata_port *ap)
792{
793 struct ahci_port_priv *pp = ap->private_data;
794 struct ata_link *link;
795 struct ahci_em_priv *emp;
796 ssize_t rc;
797 int i;
798
799 /* enable FIS reception */
800 ahci_start_fis_rx(ap);
801
802 /* enable DMA */
803 ahci_start_engine(ap);
804
805 /* turn on LEDs */
806 if (ap->flags & ATA_FLAG_EM) {
807 ata_for_each_link(link, ap, EDGE) {
808 emp = &pp->em_priv[link->pmp];
809
810 /* EM Transmit bit maybe busy during init */
811 for (i = 0; i < EM_MAX_RETRY; i++) {
812 rc = ahci_transmit_led_message(ap,
813 emp->led_state,
814 4);
815 if (rc == -EBUSY)
816 msleep(1);
817 else
818 break;
819 }
820 }
821 }
822
823 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
824 ata_for_each_link(link, ap, EDGE)
825 ahci_init_sw_activity(link);
826
827}
828
829static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
830{
831 int rc;
832
833 /* disable DMA */
834 rc = ahci_stop_engine(ap);
835 if (rc) {
836 *emsg = "failed to stop engine";
837 return rc;
838 }
839
840 /* disable FIS reception */
841 rc = ahci_stop_fis_rx(ap);
842 if (rc) {
843 *emsg = "failed stop FIS RX";
844 return rc;
845 }
846
847 return 0;
848}
849
850int ahci_reset_controller(struct ata_host *host)
851{
852 struct ahci_host_priv *hpriv = host->private_data;
853 void __iomem *mmio = hpriv->mmio;
854 u32 tmp;
855
856 /* we must be in AHCI mode, before using anything
857 * AHCI-specific, such as HOST_RESET.
858 */
859 ahci_enable_ahci(mmio);
860
861 /* global controller reset */
862 if (!ahci_skip_host_reset) {
863 tmp = readl(mmio + HOST_CTL);
864 if ((tmp & HOST_RESET) == 0) {
865 writel(tmp | HOST_RESET, mmio + HOST_CTL);
866 readl(mmio + HOST_CTL); /* flush */
867 }
868
869 /*
870 * to perform host reset, OS should set HOST_RESET
871 * and poll until this bit is read to be "0".
872 * reset must complete within 1 second, or
873 * the hardware should be considered fried.
874 */
875 tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
876 HOST_RESET, 10, 1000);
877
878 if (tmp & HOST_RESET) {
879 dev_printk(KERN_ERR, host->dev,
880 "controller reset failed (0x%x)\n", tmp);
881 return -EIO;
882 }
883
884 /* turn on AHCI mode */
885 ahci_enable_ahci(mmio);
886
887 /* Some registers might be cleared on reset. Restore
888 * initial values.
889 */
890 ahci_restore_initial_config(host);
891 } else
892 dev_printk(KERN_INFO, host->dev,
893 "skipping global host reset\n");
894
895 return 0;
896}
897EXPORT_SYMBOL_GPL(ahci_reset_controller);
898
899static void ahci_sw_activity(struct ata_link *link)
900{
901 struct ata_port *ap = link->ap;
902 struct ahci_port_priv *pp = ap->private_data;
903 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
904
905 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
906 return;
907
908 emp->activity++;
909 if (!timer_pending(&emp->timer))
910 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
911}
912
913static void ahci_sw_activity_blink(unsigned long arg)
914{
915 struct ata_link *link = (struct ata_link *)arg;
916 struct ata_port *ap = link->ap;
917 struct ahci_port_priv *pp = ap->private_data;
918 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
919 unsigned long led_message = emp->led_state;
920 u32 activity_led_state;
921 unsigned long flags;
922
923 led_message &= EM_MSG_LED_VALUE;
924 led_message |= ap->port_no | (link->pmp << 8);
925
926 /* check to see if we've had activity. If so,
927 * toggle state of LED and reset timer. If not,
928 * turn LED to desired idle state.
929 */
930 spin_lock_irqsave(ap->lock, flags);
931 if (emp->saved_activity != emp->activity) {
932 emp->saved_activity = emp->activity;
933 /* get the current LED state */
934 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
935
936 if (activity_led_state)
937 activity_led_state = 0;
938 else
939 activity_led_state = 1;
940
941 /* clear old state */
942 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
943
944 /* toggle state */
945 led_message |= (activity_led_state << 16);
946 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
947 } else {
948 /* switch to idle */
949 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
950 if (emp->blink_policy == BLINK_OFF)
951 led_message |= (1 << 16);
952 }
953 spin_unlock_irqrestore(ap->lock, flags);
954 ahci_transmit_led_message(ap, led_message, 4);
955}
956
957static void ahci_init_sw_activity(struct ata_link *link)
958{
959 struct ata_port *ap = link->ap;
960 struct ahci_port_priv *pp = ap->private_data;
961 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
962
963 /* init activity stats, setup timer */
964 emp->saved_activity = emp->activity = 0;
965 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
966
967 /* check our blink policy and set flag for link if it's enabled */
968 if (emp->blink_policy)
969 link->flags |= ATA_LFLAG_SW_ACTIVITY;
970}
971
972int ahci_reset_em(struct ata_host *host)
973{
974 struct ahci_host_priv *hpriv = host->private_data;
975 void __iomem *mmio = hpriv->mmio;
976 u32 em_ctl;
977
978 em_ctl = readl(mmio + HOST_EM_CTL);
979 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
980 return -EINVAL;
981
982 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
983 return 0;
984}
985EXPORT_SYMBOL_GPL(ahci_reset_em);
986
987static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
988 ssize_t size)
989{
990 struct ahci_host_priv *hpriv = ap->host->private_data;
991 struct ahci_port_priv *pp = ap->private_data;
992 void __iomem *mmio = hpriv->mmio;
993 u32 em_ctl;
994 u32 message[] = {0, 0};
995 unsigned long flags;
996 int pmp;
997 struct ahci_em_priv *emp;
998
999 /* get the slot number from the message */
1000 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1001 if (pmp < EM_MAX_SLOTS)
1002 emp = &pp->em_priv[pmp];
1003 else
1004 return -EINVAL;
1005
1006 spin_lock_irqsave(ap->lock, flags);
1007
1008 /*
1009 * if we are still busy transmitting a previous message,
1010 * do not allow
1011 */
1012 em_ctl = readl(mmio + HOST_EM_CTL);
1013 if (em_ctl & EM_CTL_TM) {
1014 spin_unlock_irqrestore(ap->lock, flags);
1015 return -EBUSY;
1016 }
1017
008dbd61
HZ		 1018 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1019 /*
1020 * create message header - this is all zero except for
1021 * the message size, which is 4 bytes.
1022 */
1023 message[0] |= (4 << 8);
365cfa1e 1024
008dbd61
HZ		 1025 /* ignore 0:4 of byte zero, fill in port info yourself */
1026 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
365cfa1e 1027
008dbd61
HZ		 1028 /* write message to EM_LOC */
1029 writel(message[0], mmio + hpriv->em_loc);
1030 writel(message[1], mmio + hpriv->em_loc+4);
1031
1032 /*
1033 * tell hardware to transmit the message
1034 */
1035 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1036 }
365cfa1e
AV		 1037
1038 /* save off new led state for port/slot */
1039 emp->led_state = state;
1040
365cfa1e
AV		 1041 spin_unlock_irqrestore(ap->lock, flags);
1042 return size;
1043}
1044
1045static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1046{
1047 struct ahci_port_priv *pp = ap->private_data;
1048 struct ata_link *link;
1049 struct ahci_em_priv *emp;
1050 int rc = 0;
1051
1052 ata_for_each_link(link, ap, EDGE) {
1053 emp = &pp->em_priv[link->pmp];
1054 rc += sprintf(buf, "%lx\n", emp->led_state);
1055 }
1056 return rc;
1057}
1058
1059static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1060 size_t size)
1061{
1062 int state;
1063 int pmp;
1064 struct ahci_port_priv *pp = ap->private_data;
1065 struct ahci_em_priv *emp;
1066
1067 state = simple_strtoul(buf, NULL, 0);
1068
1069 /* get the slot number from the message */
1070 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1071 if (pmp < EM_MAX_SLOTS)
1072 emp = &pp->em_priv[pmp];
1073 else
1074 return -EINVAL;
1075
1076 /* mask off the activity bits if we are in sw_activity
1077 * mode, user should turn off sw_activity before setting
1078 * activity led through em_message
1079 */
1080 if (emp->blink_policy)
1081 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1082
1083 return ahci_transmit_led_message(ap, state, size);
1084}
1085
1086static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1087{
1088 struct ata_link *link = dev->link;
1089 struct ata_port *ap = link->ap;
1090 struct ahci_port_priv *pp = ap->private_data;
1091 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1092 u32 port_led_state = emp->led_state;
1093
1094 /* save the desired Activity LED behavior */
1095 if (val == OFF) {
1096 /* clear LFLAG */
1097 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1098
1099 /* set the LED to OFF */
1100 port_led_state &= EM_MSG_LED_VALUE_OFF;
1101 port_led_state |= (ap->port_no | (link->pmp << 8));
1102 ahci_transmit_led_message(ap, port_led_state, 4);
1103 } else {
1104 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1105 if (val == BLINK_OFF) {
1106 /* set LED to ON for idle */
1107 port_led_state &= EM_MSG_LED_VALUE_OFF;
1108 port_led_state |= (ap->port_no | (link->pmp << 8));
1109 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1110 ahci_transmit_led_message(ap, port_led_state, 4);
1111 }
1112 }
1113 emp->blink_policy = val;
1114 return 0;
1115}
1116
1117static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1118{
1119 struct ata_link *link = dev->link;
1120 struct ata_port *ap = link->ap;
1121 struct ahci_port_priv *pp = ap->private_data;
1122 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1123
1124 /* display the saved value of activity behavior for this
1125 * disk.
1126 */
1127 return sprintf(buf, "%d\n", emp->blink_policy);
1128}
1129
1130static void ahci_port_init(struct device *dev, struct ata_port *ap,
1131 int port_no, void __iomem *mmio,
1132 void __iomem *port_mmio)
1133{
1134 const char *emsg = NULL;
1135 int rc;
1136 u32 tmp;
1137
1138 /* make sure port is not active */
1139 rc = ahci_deinit_port(ap, &emsg);
1140 if (rc)
1141 dev_warn(dev, "%s (%d)\n", emsg, rc);
1142
1143 /* clear SError */
1144 tmp = readl(port_mmio + PORT_SCR_ERR);
1145 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1146 writel(tmp, port_mmio + PORT_SCR_ERR);
1147
1148 /* clear port IRQ */
1149 tmp = readl(port_mmio + PORT_IRQ_STAT);
1150 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1151 if (tmp)
1152 writel(tmp, port_mmio + PORT_IRQ_STAT);
1153
1154 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1155}
1156
1157void ahci_init_controller(struct ata_host *host)
1158{
1159 struct ahci_host_priv *hpriv = host->private_data;
1160 void __iomem *mmio = hpriv->mmio;
1161 int i;
1162 void __iomem *port_mmio;
1163 u32 tmp;
1164
1165 for (i = 0; i < host->n_ports; i++) {
1166 struct ata_port *ap = host->ports[i];
1167
1168 port_mmio = ahci_port_base(ap);
1169 if (ata_port_is_dummy(ap))
1170 continue;
1171
1172 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1173 }
1174
1175 tmp = readl(mmio + HOST_CTL);
1176 VPRINTK("HOST_CTL 0x%x\n", tmp);
1177 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1178 tmp = readl(mmio + HOST_CTL);
1179 VPRINTK("HOST_CTL 0x%x\n", tmp);
1180}
1181EXPORT_SYMBOL_GPL(ahci_init_controller);
1182
1183static void ahci_dev_config(struct ata_device *dev)
1184{
1185 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1186
1187 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1188 dev->max_sectors = 255;
1189 ata_dev_printk(dev, KERN_INFO,
1190 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1191 }
1192}
1193
1194static unsigned int ahci_dev_classify(struct ata_port *ap)
1195{
1196 void __iomem *port_mmio = ahci_port_base(ap);
1197 struct ata_taskfile tf;
1198 u32 tmp;
1199
1200 tmp = readl(port_mmio + PORT_SIG);
1201 tf.lbah = (tmp >> 24) & 0xff;
1202 tf.lbam = (tmp >> 16) & 0xff;
1203 tf.lbal = (tmp >> 8) & 0xff;
1204 tf.nsect = (tmp) & 0xff;
1205
1206 return ata_dev_classify(&tf);
1207}
1208
1209static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1210 u32 opts)
1211{
1212 dma_addr_t cmd_tbl_dma;
1213
1214 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1215
1216 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1217 pp->cmd_slot[tag].status = 0;
1218 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1219 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1220}
1221
1222int ahci_kick_engine(struct ata_port *ap)
1223{
1224 void __iomem *port_mmio = ahci_port_base(ap);
1225 struct ahci_host_priv *hpriv = ap->host->private_data;
1226 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1227 u32 tmp;
1228 int busy, rc;
1229
1230 /* stop engine */
1231 rc = ahci_stop_engine(ap);
1232 if (rc)
1233 goto out_restart;
1234
1235 /* need to do CLO?
1236 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1237 */
1238 busy = status & (ATA_BUSY | ATA_DRQ);
1239 if (!busy && !sata_pmp_attached(ap)) {
1240 rc = 0;
1241 goto out_restart;
1242 }
1243
1244 if (!(hpriv->cap & HOST_CAP_CLO)) {
1245 rc = -EOPNOTSUPP;
1246 goto out_restart;
1247 }
1248
1249 /* perform CLO */
1250 tmp = readl(port_mmio + PORT_CMD);
1251 tmp |= PORT_CMD_CLO;
1252 writel(tmp, port_mmio + PORT_CMD);
1253
1254 rc = 0;
1255 tmp = ata_wait_register(port_mmio + PORT_CMD,
1256 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1257 if (tmp & PORT_CMD_CLO)
1258 rc = -EIO;
1259
1260 /* restart engine */
1261 out_restart:
1262 ahci_start_engine(ap);
1263 return rc;
1264}
1265EXPORT_SYMBOL_GPL(ahci_kick_engine);
1266
1267static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1268 struct ata_taskfile *tf, int is_cmd, u16 flags,
1269 unsigned long timeout_msec)
1270{
1271 const u32 cmd_fis_len = 5; /* five dwords */
1272 struct ahci_port_priv *pp = ap->private_data;
1273 void __iomem *port_mmio = ahci_port_base(ap);
1274 u8 *fis = pp->cmd_tbl;
1275 u32 tmp;
1276
1277 /* prep the command */
1278 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1279 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1280
1281 /* issue & wait */
1282 writel(1, port_mmio + PORT_CMD_ISSUE);
1283
1284 if (timeout_msec) {
1285 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1286 1, timeout_msec);
1287 if (tmp & 0x1) {
1288 ahci_kick_engine(ap);
1289 return -EBUSY;
1290 }
1291 } else
1292 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1293
1294 return 0;
1295}
1296
1297int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1298 int pmp, unsigned long deadline,
1299 int (*check_ready)(struct ata_link *link))
1300{
1301 struct ata_port *ap = link->ap;
1302 struct ahci_host_priv *hpriv = ap->host->private_data;
1303 const char *reason = NULL;
1304 unsigned long now, msecs;
1305 struct ata_taskfile tf;
1306 int rc;
1307
1308 DPRINTK("ENTER\n");
1309
1310 /* prepare for SRST (AHCI-1.1 10.4.1) */
1311 rc = ahci_kick_engine(ap);
1312 if (rc && rc != -EOPNOTSUPP)
1313 ata_link_printk(link, KERN_WARNING,
1314 "failed to reset engine (errno=%d)\n", rc);
1315
1316 ata_tf_init(link->device, &tf);
1317
1318 /* issue the first D2H Register FIS */
1319 msecs = 0;
1320 now = jiffies;
f1f5a807 1321 if (time_after(deadline, now))
365cfa1e
AV		 1322 msecs = jiffies_to_msecs(deadline - now);
1323
1324 tf.ctl |= ATA_SRST;
1325 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1326 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1327 rc = -EIO;
1328 reason = "1st FIS failed";
1329 goto fail;
1330 }
1331
1332 /* spec says at least 5us, but be generous and sleep for 1ms */
1333 msleep(1);
1334
1335 /* issue the second D2H Register FIS */
1336 tf.ctl &= ~ATA_SRST;
1337 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1338
1339 /* wait for link to become ready */
1340 rc = ata_wait_after_reset(link, deadline, check_ready);
1341 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1342 /*
1343 * Workaround for cases where link online status can't
1344 * be trusted. Treat device readiness timeout as link
1345 * offline.
1346 */
1347 ata_link_printk(link, KERN_INFO,
1348 "device not ready, treating as offline\n");
1349 *class = ATA_DEV_NONE;
1350 } else if (rc) {
1351 /* link occupied, -ENODEV too is an error */
1352 reason = "device not ready";
1353 goto fail;
1354 } else
1355 *class = ahci_dev_classify(ap);
1356
1357 DPRINTK("EXIT, class=%u\n", *class);
1358 return 0;
1359
1360 fail:
1361 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1362 return rc;
1363}
1364
1365int ahci_check_ready(struct ata_link *link)
1366{
1367 void __iomem *port_mmio = ahci_port_base(link->ap);
1368 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1369
1370 return ata_check_ready(status);
1371}
1372EXPORT_SYMBOL_GPL(ahci_check_ready);
1373
1374static int ahci_softreset(struct ata_link *link, unsigned int *class,
1375 unsigned long deadline)
1376{
1377 int pmp = sata_srst_pmp(link);
1378
1379 DPRINTK("ENTER\n");
1380
1381 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1382}
1383EXPORT_SYMBOL_GPL(ahci_do_softreset);
1384
1385static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1386 unsigned long deadline)
1387{
1388 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1389 struct ata_port *ap = link->ap;
1390 struct ahci_port_priv *pp = ap->private_data;
1391 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1392 struct ata_taskfile tf;
1393 bool online;
1394 int rc;
1395
1396 DPRINTK("ENTER\n");
1397
1398 ahci_stop_engine(ap);
1399
1400 /* clear D2H reception area to properly wait for D2H FIS */
1401 ata_tf_init(link->device, &tf);
1402 tf.command = 0x80;
1403 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1404
1405 rc = sata_link_hardreset(link, timing, deadline, &online,
1406 ahci_check_ready);
1407
1408 ahci_start_engine(ap);
1409
1410 if (online)
1411 *class = ahci_dev_classify(ap);
1412
1413 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1414 return rc;
1415}
1416
1417static void ahci_postreset(struct ata_link *link, unsigned int *class)
1418{
1419 struct ata_port *ap = link->ap;
1420 void __iomem *port_mmio = ahci_port_base(ap);
1421 u32 new_tmp, tmp;
1422
1423 ata_std_postreset(link, class);
1424
1425 /* Make sure port's ATAPI bit is set appropriately */
1426 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1427 if (*class == ATA_DEV_ATAPI)
1428 new_tmp |= PORT_CMD_ATAPI;
1429 else
1430 new_tmp &= ~PORT_CMD_ATAPI;
1431 if (new_tmp != tmp) {
1432 writel(new_tmp, port_mmio + PORT_CMD);
1433 readl(port_mmio + PORT_CMD); /* flush */
1434 }
1435}
1436
1437static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1438{
1439 struct scatterlist *sg;
1440 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1441 unsigned int si;
1442
1443 VPRINTK("ENTER\n");
1444
1445 /*
1446 * Next, the S/G list.
1447 */
1448 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1449 dma_addr_t addr = sg_dma_address(sg);
1450 u32 sg_len = sg_dma_len(sg);
1451
1452 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1453 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1454 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1455 }
1456
1457 return si;
1458}
1459
1460static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1461{
1462 struct ata_port *ap = qc->ap;
1463 struct ahci_port_priv *pp = ap->private_data;
1464
1465 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1466 return ata_std_qc_defer(qc);
1467 else
1468 return sata_pmp_qc_defer_cmd_switch(qc);
1469}
1470
1471static void ahci_qc_prep(struct ata_queued_cmd *qc)
1472{
1473 struct ata_port *ap = qc->ap;
1474 struct ahci_port_priv *pp = ap->private_data;
1475 int is_atapi = ata_is_atapi(qc->tf.protocol);
1476 void *cmd_tbl;
1477 u32 opts;
1478 const u32 cmd_fis_len = 5; /* five dwords */
1479 unsigned int n_elem;
1480
1481 /*
1482 * Fill in command table information. First, the header,
1483 * a SATA Register - Host to Device command FIS.
1484 */
1485 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1486
1487 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1488 if (is_atapi) {
1489 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1490 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1491 }
1492
1493 n_elem = 0;
1494 if (qc->flags & ATA_QCFLAG_DMAMAP)
1495 n_elem = ahci_fill_sg(qc, cmd_tbl);
1496
1497 /*
1498 * Fill in command slot information.
1499 */
1500 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1501 if (qc->tf.flags & ATA_TFLAG_WRITE)
1502 opts |= AHCI_CMD_WRITE;
1503 if (is_atapi)
1504 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1505
1506 ahci_fill_cmd_slot(pp, qc->tag, opts);
1507}
1508
1509static void ahci_fbs_dec_intr(struct ata_port *ap)
1510{
1511 struct ahci_port_priv *pp = ap->private_data;
1512 void __iomem *port_mmio = ahci_port_base(ap);
1513 u32 fbs = readl(port_mmio + PORT_FBS);
1514 int retries = 3;
1515
1516 DPRINTK("ENTER\n");
1517 BUG_ON(!pp->fbs_enabled);
1518
1519 /* time to wait for DEC is not specified by AHCI spec,
1520 * add a retry loop for safety.
1521 */
1522 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1523 fbs = readl(port_mmio + PORT_FBS);
1524 while ((fbs & PORT_FBS_DEC) && retries--) {
1525 udelay(1);
1526 fbs = readl(port_mmio + PORT_FBS);
1527 }
1528
1529 if (fbs & PORT_FBS_DEC)
1530 dev_printk(KERN_ERR, ap->host->dev,
1531 "failed to clear device error\n");
1532}
1533
1534static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1535{
1536 struct ahci_host_priv *hpriv = ap->host->private_data;
1537 struct ahci_port_priv *pp = ap->private_data;
1538 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1539 struct ata_link *link = NULL;
1540 struct ata_queued_cmd *active_qc;
1541 struct ata_eh_info *active_ehi;
1542 bool fbs_need_dec = false;
1543 u32 serror;
1544
1545 /* determine active link with error */
1546 if (pp->fbs_enabled) {
1547 void __iomem *port_mmio = ahci_port_base(ap);
1548 u32 fbs = readl(port_mmio + PORT_FBS);
1549 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1550
1551 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links) &&
1552 ata_link_online(&ap->pmp_link[pmp])) {
1553 link = &ap->pmp_link[pmp];
1554 fbs_need_dec = true;
1555 }
1556
1557 } else
1558 ata_for_each_link(link, ap, EDGE)
1559 if (ata_link_active(link))
1560 break;
1561
1562 if (!link)
1563 link = &ap->link;
1564
1565 active_qc = ata_qc_from_tag(ap, link->active_tag);
1566 active_ehi = &link->eh_info;
1567
1568 /* record irq stat */
1569 ata_ehi_clear_desc(host_ehi);
1570 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1571
1572 /* AHCI needs SError cleared; otherwise, it might lock up */
1573 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1574 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1575 host_ehi->serror |= serror;
1576
1577 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1578 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1579 irq_stat &= ~PORT_IRQ_IF_ERR;
1580
1581 if (irq_stat & PORT_IRQ_TF_ERR) {
1582 /* If qc is active, charge it; otherwise, the active
1583 * link. There's no active qc on NCQ errors. It will
1584 * be determined by EH by reading log page 10h.
1585 */
1586 if (active_qc)
1587 active_qc->err_mask |= AC_ERR_DEV;
1588 else
1589 active_ehi->err_mask |= AC_ERR_DEV;
1590
1591 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1592 host_ehi->serror &= ~SERR_INTERNAL;
1593 }
1594
1595 if (irq_stat & PORT_IRQ_UNK_FIS) {
1596 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1597
1598 active_ehi->err_mask |= AC_ERR_HSM;
1599 active_ehi->action |= ATA_EH_RESET;
1600 ata_ehi_push_desc(active_ehi,
1601 "unknown FIS %08x %08x %08x %08x" ,
1602 unk[0], unk[1], unk[2], unk[3]);
1603 }
1604
1605 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1606 active_ehi->err_mask |= AC_ERR_HSM;
1607 active_ehi->action |= ATA_EH_RESET;
1608 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1609 }
1610
1611 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1612 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1613 host_ehi->action |= ATA_EH_RESET;
1614 ata_ehi_push_desc(host_ehi, "host bus error");
1615 }
1616
1617 if (irq_stat & PORT_IRQ_IF_ERR) {
1618 if (fbs_need_dec)
1619 active_ehi->err_mask |= AC_ERR_DEV;
1620 else {
1621 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1622 host_ehi->action |= ATA_EH_RESET;
1623 }
1624
1625 ata_ehi_push_desc(host_ehi, "interface fatal error");
1626 }
1627
1628 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1629 ata_ehi_hotplugged(host_ehi);
1630 ata_ehi_push_desc(host_ehi, "%s",
1631 irq_stat & PORT_IRQ_CONNECT ?
1632 "connection status changed" : "PHY RDY changed");
1633 }
1634
1635 /* okay, let's hand over to EH */
1636
1637 if (irq_stat & PORT_IRQ_FREEZE)
1638 ata_port_freeze(ap);
1639 else if (fbs_need_dec) {
1640 ata_link_abort(link);
1641 ahci_fbs_dec_intr(ap);
1642 } else
1643 ata_port_abort(ap);
1644}
1645
1646static void ahci_port_intr(struct ata_port *ap)
1647{
1648 void __iomem *port_mmio = ahci_port_base(ap);
1649 struct ata_eh_info *ehi = &ap->link.eh_info;
1650 struct ahci_port_priv *pp = ap->private_data;
1651 struct ahci_host_priv *hpriv = ap->host->private_data;
1652 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1653 u32 status, qc_active = 0;
1654 int rc;
1655
1656 status = readl(port_mmio + PORT_IRQ_STAT);
1657 writel(status, port_mmio + PORT_IRQ_STAT);
1658
1659 /* ignore BAD_PMP while resetting */
1660 if (unlikely(resetting))
1661 status &= ~PORT_IRQ_BAD_PMP;
1662
1663 /* If we are getting PhyRdy, this is
1664 * just a power state change, we should
1665 * clear out this, plus the PhyRdy/Comm
1666 * Wake bits from Serror
1667 */
1668 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
1669 (status & PORT_IRQ_PHYRDY)) {
1670 status &= ~PORT_IRQ_PHYRDY;
1671 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
1672 }
1673
1674 if (unlikely(status & PORT_IRQ_ERROR)) {
1675 ahci_error_intr(ap, status);
1676 return;
1677 }
1678
1679 if (status & PORT_IRQ_SDB_FIS) {
1680 /* If SNotification is available, leave notification
1681 * handling to sata_async_notification(). If not,
1682 * emulate it by snooping SDB FIS RX area.
1683 *
1684 * Snooping FIS RX area is probably cheaper than
1685 * poking SNotification but some constrollers which
1686 * implement SNotification, ICH9 for example, don't
1687 * store AN SDB FIS into receive area.
1688 */
1689 if (hpriv->cap & HOST_CAP_SNTF)
1690 sata_async_notification(ap);
1691 else {
1692 /* If the 'N' bit in word 0 of the FIS is set,
1693 * we just received asynchronous notification.
1694 * Tell libata about it.
1695 *
1696 * Lack of SNotification should not appear in
1697 * ahci 1.2, so the workaround is unnecessary
1698 * when FBS is enabled.
1699 */
1700 if (pp->fbs_enabled)
1701 WARN_ON_ONCE(1);
1702 else {
1703 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1704 u32 f0 = le32_to_cpu(f[0]);
1705 if (f0 & (1 << 15))
1706 sata_async_notification(ap);
1707 }
1708 }
1709 }
1710
1711 /* pp->active_link is not reliable once FBS is enabled, both
1712 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1713 * NCQ and non-NCQ commands may be in flight at the same time.
1714 */
1715 if (pp->fbs_enabled) {
1716 if (ap->qc_active) {
1717 qc_active = readl(port_mmio + PORT_SCR_ACT);
1718 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1719 }
1720 } else {
1721 /* pp->active_link is valid iff any command is in flight */
1722 if (ap->qc_active && pp->active_link->sactive)
1723 qc_active = readl(port_mmio + PORT_SCR_ACT);
1724 else
1725 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1726 }
1727
1728
1729 rc = ata_qc_complete_multiple(ap, qc_active);
1730
1731 /* while resetting, invalid completions are expected */
1732 if (unlikely(rc < 0 && !resetting)) {
1733 ehi->err_mask |= AC_ERR_HSM;
1734 ehi->action |= ATA_EH_RESET;
1735 ata_port_freeze(ap);
1736 }
1737}
1738
1739irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1740{
1741 struct ata_host *host = dev_instance;
1742 struct ahci_host_priv *hpriv;
1743 unsigned int i, handled = 0;
1744 void __iomem *mmio;
1745 u32 irq_stat, irq_masked;
1746
1747 VPRINTK("ENTER\n");
1748
1749 hpriv = host->private_data;
1750 mmio = hpriv->mmio;
1751
1752 /* sigh. 0xffffffff is a valid return from h/w */
1753 irq_stat = readl(mmio + HOST_IRQ_STAT);
1754 if (!irq_stat)
1755 return IRQ_NONE;
1756
1757 irq_masked = irq_stat & hpriv->port_map;
1758
1759 spin_lock(&host->lock);
1760
1761 for (i = 0; i < host->n_ports; i++) {
1762 struct ata_port *ap;
1763
1764 if (!(irq_masked & (1 << i)))
1765 continue;
1766
1767 ap = host->ports[i];
1768 if (ap) {
1769 ahci_port_intr(ap);
1770 VPRINTK("port %u\n", i);
1771 } else {
1772 VPRINTK("port %u (no irq)\n", i);
1773 if (ata_ratelimit())
1774 dev_printk(KERN_WARNING, host->dev,
1775 "interrupt on disabled port %u\n", i);
1776 }
1777
1778 handled = 1;
1779 }
1780
1781 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1782 * it should be cleared after all the port events are cleared;
1783 * otherwise, it will raise a spurious interrupt after each
1784 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1785 * information.
1786 *
1787 * Also, use the unmasked value to clear interrupt as spurious
1788 * pending event on a dummy port might cause screaming IRQ.
1789 */
1790 writel(irq_stat, mmio + HOST_IRQ_STAT);
1791
1792 spin_unlock(&host->lock);
1793
1794 VPRINTK("EXIT\n");
1795
1796 return IRQ_RETVAL(handled);
1797}
1798EXPORT_SYMBOL_GPL(ahci_interrupt);
1799
1800static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1801{
1802 struct ata_port *ap = qc->ap;
1803 void __iomem *port_mmio = ahci_port_base(ap);
1804 struct ahci_port_priv *pp = ap->private_data;
1805
1806 /* Keep track of the currently active link. It will be used
1807 * in completion path to determine whether NCQ phase is in
1808 * progress.
1809 */
1810 pp->active_link = qc->dev->link;
1811
1812 if (qc->tf.protocol == ATA_PROT_NCQ)
1813 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1814
1815 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
1816 u32 fbs = readl(port_mmio + PORT_FBS);
1817 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1818 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
1819 writel(fbs, port_mmio + PORT_FBS);
1820 pp->fbs_last_dev = qc->dev->link->pmp;
1821 }
1822
1823 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1824
1825 ahci_sw_activity(qc->dev->link);
1826
1827 return 0;
1828}
1829
1830static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
1831{
1832 struct ahci_port_priv *pp = qc->ap->private_data;
1833 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1834
1835 if (pp->fbs_enabled)
1836 d2h_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
1837
1838 ata_tf_from_fis(d2h_fis, &qc->result_tf);
1839 return true;
1840}
1841
1842static void ahci_freeze(struct ata_port *ap)
1843{
1844 void __iomem *port_mmio = ahci_port_base(ap);
1845
1846 /* turn IRQ off */
1847 writel(0, port_mmio + PORT_IRQ_MASK);
1848}
1849
1850static void ahci_thaw(struct ata_port *ap)
1851{
1852 struct ahci_host_priv *hpriv = ap->host->private_data;
1853 void __iomem *mmio = hpriv->mmio;
1854 void __iomem *port_mmio = ahci_port_base(ap);
1855 u32 tmp;
1856 struct ahci_port_priv *pp = ap->private_data;
1857
1858 /* clear IRQ */
1859 tmp = readl(port_mmio + PORT_IRQ_STAT);
1860 writel(tmp, port_mmio + PORT_IRQ_STAT);
1861 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1862
1863 /* turn IRQ back on */
1864 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1865}
1866
1867static void ahci_error_handler(struct ata_port *ap)
1868{
1869 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1870 /* restart engine */
1871 ahci_stop_engine(ap);
1872 ahci_start_engine(ap);
1873 }
1874
1875 sata_pmp_error_handler(ap);
0ee71952
TH		 1876
1877 if (!ata_dev_enabled(ap->link.device))
1878 ahci_stop_engine(ap);
365cfa1e
AV		 1879}
1880
1881static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1882{
1883 struct ata_port *ap = qc->ap;
1884
1885 /* make DMA engine forget about the failed command */
1886 if (qc->flags & ATA_QCFLAG_FAILED)
1887 ahci_kick_engine(ap);
1888}
1889
1890static void ahci_enable_fbs(struct ata_port *ap)
1891{
1892 struct ahci_port_priv *pp = ap->private_data;
1893 void __iomem *port_mmio = ahci_port_base(ap);
1894 u32 fbs;
1895 int rc;
1896
1897 if (!pp->fbs_supported)
1898 return;
1899
1900 fbs = readl(port_mmio + PORT_FBS);
1901 if (fbs & PORT_FBS_EN) {
1902 pp->fbs_enabled = true;
1903 pp->fbs_last_dev = -1; /* initialization */
1904 return;
1905 }
1906
1907 rc = ahci_stop_engine(ap);
1908 if (rc)
1909 return;
1910
1911 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
1912 fbs = readl(port_mmio + PORT_FBS);
1913 if (fbs & PORT_FBS_EN) {
1914 dev_printk(KERN_INFO, ap->host->dev, "FBS is enabled.\n");
1915 pp->fbs_enabled = true;
1916 pp->fbs_last_dev = -1; /* initialization */
1917 } else
1918 dev_printk(KERN_ERR, ap->host->dev, "Failed to enable FBS\n");
1919
1920 ahci_start_engine(ap);
1921}
1922
1923static void ahci_disable_fbs(struct ata_port *ap)
1924{
1925 struct ahci_port_priv *pp = ap->private_data;
1926 void __iomem *port_mmio = ahci_port_base(ap);
1927 u32 fbs;
1928 int rc;
1929
1930 if (!pp->fbs_supported)
1931 return;
1932
1933 fbs = readl(port_mmio + PORT_FBS);
1934 if ((fbs & PORT_FBS_EN) == 0) {
1935 pp->fbs_enabled = false;
1936 return;
1937 }
1938
1939 rc = ahci_stop_engine(ap);
1940 if (rc)
1941 return;
1942
1943 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
1944 fbs = readl(port_mmio + PORT_FBS);
1945 if (fbs & PORT_FBS_EN)
1946 dev_printk(KERN_ERR, ap->host->dev, "Failed to disable FBS\n");
1947 else {
1948 dev_printk(KERN_INFO, ap->host->dev, "FBS is disabled.\n");
1949 pp->fbs_enabled = false;
1950 }
1951
1952 ahci_start_engine(ap);
1953}
1954
1955static void ahci_pmp_attach(struct ata_port *ap)
1956{
1957 void __iomem *port_mmio = ahci_port_base(ap);
1958 struct ahci_port_priv *pp = ap->private_data;
1959 u32 cmd;
1960
1961 cmd = readl(port_mmio + PORT_CMD);
1962 cmd |= PORT_CMD_PMP;
1963 writel(cmd, port_mmio + PORT_CMD);
1964
1965 ahci_enable_fbs(ap);
1966
1967 pp->intr_mask |= PORT_IRQ_BAD_PMP;
1968 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1969}
1970
1971static void ahci_pmp_detach(struct ata_port *ap)
1972{
1973 void __iomem *port_mmio = ahci_port_base(ap);
1974 struct ahci_port_priv *pp = ap->private_data;
1975 u32 cmd;
1976
1977 ahci_disable_fbs(ap);
1978
1979 cmd = readl(port_mmio + PORT_CMD);
1980 cmd &= ~PORT_CMD_PMP;
1981 writel(cmd, port_mmio + PORT_CMD);
1982
1983 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
1984 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1985}
1986
1987static int ahci_port_resume(struct ata_port *ap)
1988{
1989 ahci_power_up(ap);
1990 ahci_start_port(ap);
1991
1992 if (sata_pmp_attached(ap))
1993 ahci_pmp_attach(ap);
1994 else
1995 ahci_pmp_detach(ap);
1996
1997 return 0;
1998}
1999
2000#ifdef CONFIG_PM
2001static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2002{
2003 const char *emsg = NULL;
2004 int rc;
2005
2006 rc = ahci_deinit_port(ap, &emsg);
2007 if (rc == 0)
2008 ahci_power_down(ap);
2009 else {
2010 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
2011 ahci_start_port(ap);
2012 }
2013
2014 return rc;
2015}
2016#endif
2017
2018static int ahci_port_start(struct ata_port *ap)
2019{
2020 struct ahci_host_priv *hpriv = ap->host->private_data;
2021 struct device *dev = ap->host->dev;
2022 struct ahci_port_priv *pp;
2023 void *mem;
2024 dma_addr_t mem_dma;
2025 size_t dma_sz, rx_fis_sz;
2026
2027 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2028 if (!pp)
2029 return -ENOMEM;
2030
2031 /* check FBS capability */
2032 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2033 void __iomem *port_mmio = ahci_port_base(ap);
2034 u32 cmd = readl(port_mmio + PORT_CMD);
2035 if (cmd & PORT_CMD_FBSCP)
2036 pp->fbs_supported = true;
5f173107
TH		 2037 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
2038 dev_printk(KERN_INFO, dev,
2039 "port %d can do FBS, forcing FBSCP\n",
2040 ap->port_no);
2041 pp->fbs_supported = true;
2042 } else
365cfa1e 2043 dev_printk(KERN_WARNING, dev,
5f173107
TH		 2044 "port %d is not capable of FBS\n",
2045 ap->port_no);
365cfa1e
AV		 2046 }
2047
2048 if (pp->fbs_supported) {
2049 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2050 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2051 } else {
2052 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2053 rx_fis_sz = AHCI_RX_FIS_SZ;
2054 }
2055
2056 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2057 if (!mem)
2058 return -ENOMEM;
2059 memset(mem, 0, dma_sz);
2060
2061 /*
2062 * First item in chunk of DMA memory: 32-slot command table,
2063 * 32 bytes each in size
2064 */
2065 pp->cmd_slot = mem;
2066 pp->cmd_slot_dma = mem_dma;
2067
2068 mem += AHCI_CMD_SLOT_SZ;
2069 mem_dma += AHCI_CMD_SLOT_SZ;
2070
2071 /*
2072 * Second item: Received-FIS area
2073 */
2074 pp->rx_fis = mem;
2075 pp->rx_fis_dma = mem_dma;
2076
2077 mem += rx_fis_sz;
2078 mem_dma += rx_fis_sz;
2079
2080 /*
2081 * Third item: data area for storing a single command
2082 * and its scatter-gather table
2083 */
2084 pp->cmd_tbl = mem;
2085 pp->cmd_tbl_dma = mem_dma;
2086
2087 /*
2088 * Save off initial list of interrupts to be enabled.
2089 * This could be changed later
2090 */
2091 pp->intr_mask = DEF_PORT_IRQ;
2092
2093 ap->private_data = pp;
2094
2095 /* engage engines, captain */
2096 return ahci_port_resume(ap);
2097}
2098
2099static void ahci_port_stop(struct ata_port *ap)
2100{
2101 const char *emsg = NULL;
2102 int rc;
2103
2104 /* de-initialize port */
2105 rc = ahci_deinit_port(ap, &emsg);
2106 if (rc)
2107 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
2108}
2109
2110void ahci_print_info(struct ata_host *host, const char *scc_s)
2111{
2112 struct ahci_host_priv *hpriv = host->private_data;
2113 void __iomem *mmio = hpriv->mmio;
2114 u32 vers, cap, cap2, impl, speed;
2115 const char *speed_s;
2116
2117 vers = readl(mmio + HOST_VERSION);
2118 cap = hpriv->cap;
2119 cap2 = hpriv->cap2;
2120 impl = hpriv->port_map;
2121
2122 speed = (cap >> 20) & 0xf;
2123 if (speed == 1)
2124 speed_s = "1.5";
2125 else if (speed == 2)
2126 speed_s = "3";
2127 else if (speed == 3)
2128 speed_s = "6";
2129 else
2130 speed_s = "?";
2131
2132 dev_info(host->dev,
2133 "AHCI %02x%02x.%02x%02x "
2134 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2135 ,
2136
2137 (vers >> 24) & 0xff,
2138 (vers >> 16) & 0xff,
2139 (vers >> 8) & 0xff,
2140 vers & 0xff,
2141
2142 ((cap >> 8) & 0x1f) + 1,
2143 (cap & 0x1f) + 1,
2144 speed_s,
2145 impl,
2146 scc_s);
2147
2148 dev_info(host->dev,
2149 "flags: "
2150 "%s%s%s%s%s%s%s"
2151 "%s%s%s%s%s%s%s"
2152 "%s%s%s%s%s%s\n"
2153 ,
2154
2155 cap & HOST_CAP_64 ? "64bit " : "",
2156 cap & HOST_CAP_NCQ ? "ncq " : "",
2157 cap & HOST_CAP_SNTF ? "sntf " : "",
2158 cap & HOST_CAP_MPS ? "ilck " : "",
2159 cap & HOST_CAP_SSS ? "stag " : "",
2160 cap & HOST_CAP_ALPM ? "pm " : "",
2161 cap & HOST_CAP_LED ? "led " : "",
2162 cap & HOST_CAP_CLO ? "clo " : "",
2163 cap & HOST_CAP_ONLY ? "only " : "",
2164 cap & HOST_CAP_PMP ? "pmp " : "",
2165 cap & HOST_CAP_FBS ? "fbs " : "",
2166 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2167 cap & HOST_CAP_SSC ? "slum " : "",
2168 cap & HOST_CAP_PART ? "part " : "",
2169 cap & HOST_CAP_CCC ? "ccc " : "",
2170 cap & HOST_CAP_EMS ? "ems " : "",
2171 cap & HOST_CAP_SXS ? "sxs " : "",
2172 cap2 & HOST_CAP2_APST ? "apst " : "",
2173 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2174 cap2 & HOST_CAP2_BOH ? "boh " : ""
2175 );
2176}
2177EXPORT_SYMBOL_GPL(ahci_print_info);
2178
2179void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2180 struct ata_port_info *pi)
2181{
2182 u8 messages;
2183 void __iomem *mmio = hpriv->mmio;
2184 u32 em_loc = readl(mmio + HOST_EM_LOC);
2185 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2186
2187 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2188 return;
2189
2190 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2191
008dbd61 2192 if (messages) {
365cfa1e
AV		 2193 /* store em_loc */
2194 hpriv->em_loc = ((em_loc >> 16) * 4);
c0623166 2195 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
008dbd61 2196 hpriv->em_msg_type = messages;
365cfa1e
AV		 2197 pi->flags |= ATA_FLAG_EM;
2198 if (!(em_ctl & EM_CTL_ALHD))
2199 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2200 }
2201}
2202EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2203
2204MODULE_AUTHOR("Jeff Garzik");
2205MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2206MODULE_LICENSE("GPL");
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