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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
8f47e163 | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
1da177e4 LT |
5 | * |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
1da177e4 | 33 | #include <linux/sysdev.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
5a0e3ad6 | 39 | #include <linux/slab.h> |
d4057bdb YL |
40 | #ifdef CONFIG_ACPI |
41 | #include <acpi/acpi_bus.h> | |
42 | #endif | |
43 | #include <linux/bootmem.h> | |
44 | #include <linux/dmar.h> | |
58ac1e76 | 45 | #include <linux/hpet.h> |
54d5d424 | 46 | |
d4057bdb | 47 | #include <asm/idle.h> |
1da177e4 LT |
48 | #include <asm/io.h> |
49 | #include <asm/smp.h> | |
6d652ea1 | 50 | #include <asm/cpu.h> |
1da177e4 | 51 | #include <asm/desc.h> |
d4057bdb YL |
52 | #include <asm/proto.h> |
53 | #include <asm/acpi.h> | |
54 | #include <asm/dma.h> | |
1da177e4 | 55 | #include <asm/timer.h> |
306e440d | 56 | #include <asm/i8259.h> |
3e4ff115 | 57 | #include <asm/nmi.h> |
2d3fcc1c | 58 | #include <asm/msidef.h> |
8b955b0d | 59 | #include <asm/hypertransport.h> |
a4dbc34d | 60 | #include <asm/setup.h> |
d4057bdb | 61 | #include <asm/irq_remapping.h> |
58ac1e76 | 62 | #include <asm/hpet.h> |
2c1b284e | 63 | #include <asm/hw_irq.h> |
1da177e4 | 64 | |
7b6aa335 | 65 | #include <asm/apic.h> |
1da177e4 | 66 | |
32f71aff | 67 | #define __apicdebuginit(type) static type __init |
2977fb3f CG |
68 | #define for_each_irq_pin(entry, head) \ |
69 | for (entry = head; entry; entry = entry->next) | |
32f71aff | 70 | |
1da177e4 | 71 | /* |
54168ed7 IM |
72 | * Is the SiS APIC rmw bug present ? |
73 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
74 | */ |
75 | int sis_apic_bug = -1; | |
76 | ||
dade7716 TG |
77 | static DEFINE_RAW_SPINLOCK(ioapic_lock); |
78 | static DEFINE_RAW_SPINLOCK(vector_lock); | |
efa2559f | 79 | |
1da177e4 LT |
80 | /* |
81 | * # of IRQ routing registers | |
82 | */ | |
83 | int nr_ioapic_registers[MAX_IO_APICS]; | |
84 | ||
9f640ccb | 85 | /* I/O APIC entries */ |
b5ba7e6d | 86 | struct mpc_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
87 | int nr_ioapics; |
88 | ||
2a4ab640 FT |
89 | /* IO APIC gsi routing info */ |
90 | struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS]; | |
91 | ||
a4384df3 EB |
92 | /* The one past the highest gsi number used */ |
93 | u32 gsi_top; | |
5777372a | 94 | |
584f734d | 95 | /* MP IRQ source entries */ |
c2c21745 | 96 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
97 | |
98 | /* # of MP IRQ source entries */ | |
99 | int mp_irq_entries; | |
100 | ||
bc07844a TG |
101 | /* GSI interrupts */ |
102 | static int nr_irqs_gsi = NR_IRQS_LEGACY; | |
103 | ||
8732fc4b AS |
104 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
105 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
106 | #endif | |
107 | ||
108 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
109 | ||
efa2559f YL |
110 | int skip_ioapic_setup; |
111 | ||
65a4e574 IM |
112 | void arch_disable_smp_support(void) |
113 | { | |
114 | #ifdef CONFIG_PCI | |
115 | noioapicquirk = 1; | |
116 | noioapicreroute = -1; | |
117 | #endif | |
118 | skip_ioapic_setup = 1; | |
119 | } | |
120 | ||
54168ed7 | 121 | static int __init parse_noapic(char *str) |
efa2559f YL |
122 | { |
123 | /* disable IO-APIC */ | |
65a4e574 | 124 | arch_disable_smp_support(); |
efa2559f YL |
125 | return 0; |
126 | } | |
127 | early_param("noapic", parse_noapic); | |
66759a01 | 128 | |
0b8f1efa YL |
129 | struct irq_pin_list { |
130 | int apic, pin; | |
131 | struct irq_pin_list *next; | |
132 | }; | |
133 | ||
85ac16d0 | 134 | static struct irq_pin_list *get_one_free_irq_2_pin(int node) |
0b8f1efa YL |
135 | { |
136 | struct irq_pin_list *pin; | |
0b8f1efa YL |
137 | |
138 | pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node); | |
0b8f1efa YL |
139 | |
140 | return pin; | |
141 | } | |
142 | ||
a1420f39 | 143 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
0b8f1efa | 144 | #ifdef CONFIG_SPARSE_IRQ |
97943390 | 145 | static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY]; |
0b8f1efa | 146 | #else |
97943390 | 147 | static struct irq_cfg irq_cfgx[NR_IRQS]; |
0b8f1efa | 148 | #endif |
a1420f39 | 149 | |
13a0c3c2 | 150 | int __init arch_early_irq_init(void) |
8f09cd20 | 151 | { |
0b8f1efa YL |
152 | struct irq_cfg *cfg; |
153 | struct irq_desc *desc; | |
154 | int count; | |
dad213ae | 155 | int node; |
0b8f1efa | 156 | int i; |
d6c88a50 | 157 | |
1f91233c JP |
158 | if (!legacy_pic->nr_legacy_irqs) { |
159 | nr_irqs_gsi = 0; | |
160 | io_apic_irqs = ~0UL; | |
161 | } | |
162 | ||
0b8f1efa YL |
163 | cfg = irq_cfgx; |
164 | count = ARRAY_SIZE(irq_cfgx); | |
f6e9456c | 165 | node = cpu_to_node(0); |
8f09cd20 | 166 | |
0b8f1efa YL |
167 | for (i = 0; i < count; i++) { |
168 | desc = irq_to_desc(i); | |
169 | desc->chip_data = &cfg[i]; | |
12274e96 YL |
170 | zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node); |
171 | zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node); | |
97943390 SS |
172 | /* |
173 | * For legacy IRQ's, start with assigning irq0 to irq15 to | |
174 | * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0. | |
175 | */ | |
54b56170 | 176 | if (i < legacy_pic->nr_legacy_irqs) { |
97943390 SS |
177 | cfg[i].vector = IRQ0_VECTOR + i; |
178 | cpumask_set_cpu(0, cfg[i].domain); | |
179 | } | |
0b8f1efa | 180 | } |
13a0c3c2 YL |
181 | |
182 | return 0; | |
0b8f1efa | 183 | } |
8f09cd20 | 184 | |
0b8f1efa | 185 | #ifdef CONFIG_SPARSE_IRQ |
9338ad6f | 186 | struct irq_cfg *irq_cfg(unsigned int irq) |
8f09cd20 | 187 | { |
0b8f1efa YL |
188 | struct irq_cfg *cfg = NULL; |
189 | struct irq_desc *desc; | |
1da177e4 | 190 | |
0b8f1efa YL |
191 | desc = irq_to_desc(irq); |
192 | if (desc) | |
d4eba297 | 193 | cfg = get_irq_desc_chip_data(desc); |
0f978f45 | 194 | |
0b8f1efa | 195 | return cfg; |
8f09cd20 | 196 | } |
d6c88a50 | 197 | |
85ac16d0 | 198 | static struct irq_cfg *get_one_free_irq_cfg(int node) |
8f09cd20 | 199 | { |
0b8f1efa | 200 | struct irq_cfg *cfg; |
0f978f45 | 201 | |
0b8f1efa | 202 | cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node); |
22f65d31 | 203 | if (cfg) { |
79f55997 | 204 | if (!zalloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) { |
22f65d31 MT |
205 | kfree(cfg); |
206 | cfg = NULL; | |
79f55997 | 207 | } else if (!zalloc_cpumask_var_node(&cfg->old_domain, |
80855f73 | 208 | GFP_ATOMIC, node)) { |
22f65d31 MT |
209 | free_cpumask_var(cfg->domain); |
210 | kfree(cfg); | |
211 | cfg = NULL; | |
22f65d31 MT |
212 | } |
213 | } | |
0f978f45 | 214 | |
0b8f1efa | 215 | return cfg; |
8f09cd20 YL |
216 | } |
217 | ||
85ac16d0 | 218 | int arch_init_chip_data(struct irq_desc *desc, int node) |
0f978f45 | 219 | { |
0b8f1efa | 220 | struct irq_cfg *cfg; |
d6c88a50 | 221 | |
d4eba297 | 222 | cfg = get_irq_desc_chip_data(desc); |
0b8f1efa | 223 | if (!cfg) { |
d4eba297 TG |
224 | cfg = get_one_free_irq_cfg(node); |
225 | desc->chip_data = cfg; | |
226 | if (!cfg) { | |
0b8f1efa YL |
227 | printk(KERN_ERR "can not alloc irq_cfg\n"); |
228 | BUG_ON(1); | |
229 | } | |
230 | } | |
1da177e4 | 231 | |
13a0c3c2 | 232 | return 0; |
0b8f1efa | 233 | } |
0f978f45 | 234 | |
fcef5911 | 235 | /* for move_irq_desc */ |
48a1b10a | 236 | static void |
85ac16d0 | 237 | init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node) |
0f978f45 | 238 | { |
48a1b10a YL |
239 | struct irq_pin_list *old_entry, *head, *tail, *entry; |
240 | ||
241 | cfg->irq_2_pin = NULL; | |
242 | old_entry = old_cfg->irq_2_pin; | |
243 | if (!old_entry) | |
244 | return; | |
0f978f45 | 245 | |
85ac16d0 | 246 | entry = get_one_free_irq_2_pin(node); |
48a1b10a YL |
247 | if (!entry) |
248 | return; | |
0f978f45 | 249 | |
48a1b10a YL |
250 | entry->apic = old_entry->apic; |
251 | entry->pin = old_entry->pin; | |
252 | head = entry; | |
253 | tail = entry; | |
254 | old_entry = old_entry->next; | |
255 | while (old_entry) { | |
85ac16d0 | 256 | entry = get_one_free_irq_2_pin(node); |
48a1b10a YL |
257 | if (!entry) { |
258 | entry = head; | |
259 | while (entry) { | |
260 | head = entry->next; | |
261 | kfree(entry); | |
262 | entry = head; | |
263 | } | |
264 | /* still use the old one */ | |
265 | return; | |
266 | } | |
267 | entry->apic = old_entry->apic; | |
268 | entry->pin = old_entry->pin; | |
269 | tail->next = entry; | |
270 | tail = entry; | |
271 | old_entry = old_entry->next; | |
272 | } | |
0f978f45 | 273 | |
48a1b10a YL |
274 | tail->next = NULL; |
275 | cfg->irq_2_pin = head; | |
0f978f45 | 276 | } |
0f978f45 | 277 | |
48a1b10a | 278 | static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg) |
0f978f45 | 279 | { |
48a1b10a | 280 | struct irq_pin_list *entry, *next; |
0f978f45 | 281 | |
48a1b10a YL |
282 | if (old_cfg->irq_2_pin == cfg->irq_2_pin) |
283 | return; | |
301e6190 | 284 | |
48a1b10a | 285 | entry = old_cfg->irq_2_pin; |
0f978f45 | 286 | |
48a1b10a YL |
287 | while (entry) { |
288 | next = entry->next; | |
289 | kfree(entry); | |
290 | entry = next; | |
291 | } | |
292 | old_cfg->irq_2_pin = NULL; | |
0f978f45 | 293 | } |
0f978f45 | 294 | |
48a1b10a | 295 | void arch_init_copy_chip_data(struct irq_desc *old_desc, |
85ac16d0 | 296 | struct irq_desc *desc, int node) |
0f978f45 | 297 | { |
48a1b10a YL |
298 | struct irq_cfg *cfg; |
299 | struct irq_cfg *old_cfg; | |
0f978f45 | 300 | |
85ac16d0 | 301 | cfg = get_one_free_irq_cfg(node); |
301e6190 | 302 | |
48a1b10a YL |
303 | if (!cfg) |
304 | return; | |
305 | ||
306 | desc->chip_data = cfg; | |
307 | ||
308 | old_cfg = old_desc->chip_data; | |
309 | ||
1cf180c9 TG |
310 | cfg->vector = old_cfg->vector; |
311 | cfg->move_in_progress = old_cfg->move_in_progress; | |
312 | cpumask_copy(cfg->domain, old_cfg->domain); | |
313 | cpumask_copy(cfg->old_domain, old_cfg->old_domain); | |
48a1b10a | 314 | |
85ac16d0 | 315 | init_copy_irq_2_pin(old_cfg, cfg, node); |
0f978f45 | 316 | } |
1da177e4 | 317 | |
1cf180c9 | 318 | static void free_irq_cfg(struct irq_cfg *cfg) |
48a1b10a | 319 | { |
1cf180c9 TG |
320 | free_cpumask_var(cfg->domain); |
321 | free_cpumask_var(cfg->old_domain); | |
322 | kfree(cfg); | |
48a1b10a YL |
323 | } |
324 | ||
325 | void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc) | |
326 | { | |
327 | struct irq_cfg *old_cfg, *cfg; | |
328 | ||
d4eba297 TG |
329 | old_cfg = get_irq_desc_chip_data(old_desc); |
330 | cfg = get_irq_desc_chip_data(desc); | |
48a1b10a YL |
331 | |
332 | if (old_cfg == cfg) | |
333 | return; | |
334 | ||
335 | if (old_cfg) { | |
336 | free_irq_2_pin(old_cfg, cfg); | |
337 | free_irq_cfg(old_cfg); | |
338 | old_desc->chip_data = NULL; | |
339 | } | |
340 | } | |
fcef5911 | 341 | /* end for move_irq_desc */ |
48a1b10a | 342 | |
0b8f1efa | 343 | #else |
9338ad6f | 344 | struct irq_cfg *irq_cfg(unsigned int irq) |
0b8f1efa YL |
345 | { |
346 | return irq < nr_irqs ? irq_cfgx + irq : NULL; | |
0f978f45 | 347 | } |
1da177e4 | 348 | |
0b8f1efa YL |
349 | #endif |
350 | ||
130fe05d LT |
351 | struct io_apic { |
352 | unsigned int index; | |
353 | unsigned int unused[3]; | |
354 | unsigned int data; | |
0280f7c4 SS |
355 | unsigned int unused2[11]; |
356 | unsigned int eoi; | |
130fe05d LT |
357 | }; |
358 | ||
359 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
360 | { | |
361 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
b5ba7e6d | 362 | + (mp_ioapics[idx].apicaddr & ~PAGE_MASK); |
130fe05d LT |
363 | } |
364 | ||
0280f7c4 SS |
365 | static inline void io_apic_eoi(unsigned int apic, unsigned int vector) |
366 | { | |
367 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
368 | writel(vector, &io_apic->eoi); | |
369 | } | |
370 | ||
130fe05d LT |
371 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) |
372 | { | |
373 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
374 | writel(reg, &io_apic->index); | |
375 | return readl(&io_apic->data); | |
376 | } | |
377 | ||
378 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
379 | { | |
380 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
381 | writel(reg, &io_apic->index); | |
382 | writel(value, &io_apic->data); | |
383 | } | |
384 | ||
385 | /* | |
386 | * Re-write a value: to be used for read-modify-write | |
387 | * cycles where the read already set up the index register. | |
388 | * | |
389 | * Older SiS APIC requires we rewrite the index register | |
390 | */ | |
391 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
392 | { | |
54168ed7 | 393 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
394 | |
395 | if (sis_apic_bug) | |
396 | writel(reg, &io_apic->index); | |
130fe05d LT |
397 | writel(value, &io_apic->data); |
398 | } | |
399 | ||
3145e941 | 400 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
047c8fdb YL |
401 | { |
402 | struct irq_pin_list *entry; | |
403 | unsigned long flags; | |
047c8fdb | 404 | |
dade7716 | 405 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
2977fb3f | 406 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
047c8fdb YL |
407 | unsigned int reg; |
408 | int pin; | |
409 | ||
047c8fdb YL |
410 | pin = entry->pin; |
411 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
412 | /* Is the remote IRR bit set? */ | |
413 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
dade7716 | 414 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
047c8fdb YL |
415 | return true; |
416 | } | |
047c8fdb | 417 | } |
dade7716 | 418 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
047c8fdb YL |
419 | |
420 | return false; | |
421 | } | |
047c8fdb | 422 | |
cf4c6a2f AK |
423 | union entry_union { |
424 | struct { u32 w1, w2; }; | |
425 | struct IO_APIC_route_entry entry; | |
426 | }; | |
427 | ||
428 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
429 | { | |
430 | union entry_union eu; | |
431 | unsigned long flags; | |
dade7716 | 432 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
cf4c6a2f AK |
433 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); |
434 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
dade7716 | 435 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
436 | return eu.entry; |
437 | } | |
438 | ||
f9dadfa7 LT |
439 | /* |
440 | * When we write a new IO APIC routing entry, we need to write the high | |
441 | * word first! If the mask bit in the low word is clear, we will enable | |
442 | * the interrupt, and we need to make sure the entry is fully populated | |
443 | * before that happens. | |
444 | */ | |
d15512f4 AK |
445 | static void |
446 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 447 | { |
50a8d4d2 F |
448 | union entry_union eu = {{0, 0}}; |
449 | ||
cf4c6a2f | 450 | eu.entry = e; |
f9dadfa7 LT |
451 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
452 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
453 | } |
454 | ||
ca97ab90 | 455 | void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
d15512f4 AK |
456 | { |
457 | unsigned long flags; | |
dade7716 | 458 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
d15512f4 | 459 | __ioapic_write_entry(apic, pin, e); |
dade7716 | 460 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f9dadfa7 LT |
461 | } |
462 | ||
463 | /* | |
464 | * When we mask an IO APIC routing entry, we need to write the low | |
465 | * word first, in order to set the mask bit before we change the | |
466 | * high bits! | |
467 | */ | |
468 | static void ioapic_mask_entry(int apic, int pin) | |
469 | { | |
470 | unsigned long flags; | |
471 | union entry_union eu = { .entry.mask = 1 }; | |
472 | ||
dade7716 | 473 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
cf4c6a2f AK |
474 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); |
475 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
dade7716 | 476 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
477 | } |
478 | ||
1da177e4 LT |
479 | /* |
480 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
481 | * shared ISA-space IRQs, so we have to support them. We are super | |
482 | * fast in the common case, and fast for shared ISA-space IRQs. | |
483 | */ | |
f3d1915a CG |
484 | static int |
485 | add_pin_to_irq_node_nopanic(struct irq_cfg *cfg, int node, int apic, int pin) | |
1da177e4 | 486 | { |
2977fb3f | 487 | struct irq_pin_list **last, *entry; |
0f978f45 | 488 | |
2977fb3f CG |
489 | /* don't allow duplicates */ |
490 | last = &cfg->irq_2_pin; | |
491 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
0f978f45 | 492 | if (entry->apic == apic && entry->pin == pin) |
f3d1915a | 493 | return 0; |
2977fb3f | 494 | last = &entry->next; |
1da177e4 | 495 | } |
0f978f45 | 496 | |
875e68ec | 497 | entry = get_one_free_irq_2_pin(node); |
a7428cd2 | 498 | if (!entry) { |
f3d1915a CG |
499 | printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n", |
500 | node, apic, pin); | |
501 | return -ENOMEM; | |
a7428cd2 | 502 | } |
1da177e4 LT |
503 | entry->apic = apic; |
504 | entry->pin = pin; | |
875e68ec | 505 | |
2977fb3f | 506 | *last = entry; |
f3d1915a CG |
507 | return 0; |
508 | } | |
509 | ||
510 | static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) | |
511 | { | |
512 | if (add_pin_to_irq_node_nopanic(cfg, node, apic, pin)) | |
513 | panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); | |
1da177e4 LT |
514 | } |
515 | ||
516 | /* | |
517 | * Reroute an IRQ to a different pin. | |
518 | */ | |
85ac16d0 | 519 | static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node, |
4eea6fff JF |
520 | int oldapic, int oldpin, |
521 | int newapic, int newpin) | |
1da177e4 | 522 | { |
535b6429 | 523 | struct irq_pin_list *entry; |
1da177e4 | 524 | |
2977fb3f | 525 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
1da177e4 LT |
526 | if (entry->apic == oldapic && entry->pin == oldpin) { |
527 | entry->apic = newapic; | |
528 | entry->pin = newpin; | |
0f978f45 | 529 | /* every one is different, right? */ |
4eea6fff | 530 | return; |
0f978f45 | 531 | } |
1da177e4 | 532 | } |
0f978f45 | 533 | |
4eea6fff JF |
534 | /* old apic/pin didn't exist, so just add new ones */ |
535 | add_pin_to_irq_node(cfg, node, newapic, newpin); | |
1da177e4 LT |
536 | } |
537 | ||
c29d9db3 SS |
538 | static void __io_apic_modify_irq(struct irq_pin_list *entry, |
539 | int mask_and, int mask_or, | |
540 | void (*final)(struct irq_pin_list *entry)) | |
541 | { | |
542 | unsigned int reg, pin; | |
543 | ||
544 | pin = entry->pin; | |
545 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
546 | reg &= mask_and; | |
547 | reg |= mask_or; | |
548 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
549 | if (final) | |
550 | final(entry); | |
551 | } | |
552 | ||
2f210deb JF |
553 | static void io_apic_modify_irq(struct irq_cfg *cfg, |
554 | int mask_and, int mask_or, | |
555 | void (*final)(struct irq_pin_list *entry)) | |
87783be4 | 556 | { |
87783be4 | 557 | struct irq_pin_list *entry; |
047c8fdb | 558 | |
c29d9db3 SS |
559 | for_each_irq_pin(entry, cfg->irq_2_pin) |
560 | __io_apic_modify_irq(entry, mask_and, mask_or, final); | |
561 | } | |
562 | ||
563 | static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list *entry) | |
564 | { | |
565 | __io_apic_modify_irq(entry, ~IO_APIC_REDIR_LEVEL_TRIGGER, | |
566 | IO_APIC_REDIR_MASKED, NULL); | |
567 | } | |
568 | ||
569 | static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list *entry) | |
570 | { | |
571 | __io_apic_modify_irq(entry, ~IO_APIC_REDIR_MASKED, | |
572 | IO_APIC_REDIR_LEVEL_TRIGGER, NULL); | |
87783be4 | 573 | } |
047c8fdb | 574 | |
7f3e632f | 575 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 576 | { |
87783be4 CG |
577 | /* |
578 | * Synchronize the IO-APIC and the CPU by doing | |
579 | * a dummy read from the IO-APIC | |
580 | */ | |
581 | struct io_apic __iomem *io_apic; | |
582 | io_apic = io_apic_base(entry->apic); | |
4e738e2f | 583 | readl(&io_apic->data); |
1da177e4 LT |
584 | } |
585 | ||
dd5f15e5 | 586 | static void mask_ioapic(struct irq_cfg *cfg) |
87783be4 | 587 | { |
dd5f15e5 TG |
588 | unsigned long flags; |
589 | ||
590 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 591 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
dd5f15e5 | 592 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
87783be4 | 593 | } |
1da177e4 | 594 | |
dd5f15e5 | 595 | static void mask_ioapic_irq(unsigned int irq) |
1da177e4 | 596 | { |
dd5f15e5 | 597 | struct irq_cfg *cfg = get_irq_chip_data(irq); |
1da177e4 | 598 | |
dd5f15e5 TG |
599 | mask_ioapic(cfg); |
600 | } | |
3145e941 | 601 | |
dd5f15e5 TG |
602 | static void __unmask_ioapic(struct irq_cfg *cfg) |
603 | { | |
604 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); | |
1da177e4 LT |
605 | } |
606 | ||
dd5f15e5 | 607 | static void unmask_ioapic(struct irq_cfg *cfg) |
1da177e4 LT |
608 | { |
609 | unsigned long flags; | |
610 | ||
dade7716 | 611 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
dd5f15e5 | 612 | __unmask_ioapic(cfg); |
dade7716 | 613 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
614 | } |
615 | ||
dd5f15e5 | 616 | static void unmask_ioapic_irq(unsigned int irq) |
3145e941 | 617 | { |
dd5f15e5 | 618 | struct irq_cfg *cfg = get_irq_chip_data(irq); |
3145e941 | 619 | |
dd5f15e5 | 620 | unmask_ioapic(cfg); |
3145e941 YL |
621 | } |
622 | ||
1da177e4 LT |
623 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
624 | { | |
625 | struct IO_APIC_route_entry entry; | |
36062448 | 626 | |
1da177e4 | 627 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 628 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
629 | if (entry.delivery_mode == dest_SMI) |
630 | return; | |
1da177e4 LT |
631 | /* |
632 | * Disable it in the IO-APIC irq-routing table: | |
633 | */ | |
f9dadfa7 | 634 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
635 | } |
636 | ||
54168ed7 | 637 | static void clear_IO_APIC (void) |
1da177e4 LT |
638 | { |
639 | int apic, pin; | |
640 | ||
641 | for (apic = 0; apic < nr_ioapics; apic++) | |
642 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
643 | clear_IO_APIC_pin(apic, pin); | |
644 | } | |
645 | ||
54168ed7 | 646 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
647 | /* |
648 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
649 | * specific CPU-side IRQs. | |
650 | */ | |
651 | ||
652 | #define MAX_PIRQS 8 | |
3bd25d0f YL |
653 | static int pirq_entries[MAX_PIRQS] = { |
654 | [0 ... MAX_PIRQS - 1] = -1 | |
655 | }; | |
1da177e4 | 656 | |
1da177e4 LT |
657 | static int __init ioapic_pirq_setup(char *str) |
658 | { | |
659 | int i, max; | |
660 | int ints[MAX_PIRQS+1]; | |
661 | ||
662 | get_options(str, ARRAY_SIZE(ints), ints); | |
663 | ||
1da177e4 LT |
664 | apic_printk(APIC_VERBOSE, KERN_INFO |
665 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
666 | max = MAX_PIRQS; | |
667 | if (ints[0] < MAX_PIRQS) | |
668 | max = ints[0]; | |
669 | ||
670 | for (i = 0; i < max; i++) { | |
671 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
672 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
673 | /* | |
674 | * PIRQs are mapped upside down, usually. | |
675 | */ | |
676 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
677 | } | |
678 | return 1; | |
679 | } | |
680 | ||
681 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
682 | #endif /* CONFIG_X86_32 */ |
683 | ||
b24696bc FY |
684 | struct IO_APIC_route_entry **alloc_ioapic_entries(void) |
685 | { | |
686 | int apic; | |
687 | struct IO_APIC_route_entry **ioapic_entries; | |
688 | ||
689 | ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics, | |
690 | GFP_ATOMIC); | |
691 | if (!ioapic_entries) | |
692 | return 0; | |
693 | ||
694 | for (apic = 0; apic < nr_ioapics; apic++) { | |
695 | ioapic_entries[apic] = | |
696 | kzalloc(sizeof(struct IO_APIC_route_entry) * | |
697 | nr_ioapic_registers[apic], GFP_ATOMIC); | |
698 | if (!ioapic_entries[apic]) | |
699 | goto nomem; | |
700 | } | |
701 | ||
702 | return ioapic_entries; | |
703 | ||
704 | nomem: | |
705 | while (--apic >= 0) | |
706 | kfree(ioapic_entries[apic]); | |
707 | kfree(ioapic_entries); | |
708 | ||
709 | return 0; | |
710 | } | |
54168ed7 IM |
711 | |
712 | /* | |
05c3dc2c | 713 | * Saves all the IO-APIC RTE's |
54168ed7 | 714 | */ |
b24696bc | 715 | int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) |
54168ed7 | 716 | { |
54168ed7 IM |
717 | int apic, pin; |
718 | ||
b24696bc FY |
719 | if (!ioapic_entries) |
720 | return -ENOMEM; | |
54168ed7 IM |
721 | |
722 | for (apic = 0; apic < nr_ioapics; apic++) { | |
b24696bc FY |
723 | if (!ioapic_entries[apic]) |
724 | return -ENOMEM; | |
54168ed7 | 725 | |
05c3dc2c | 726 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
b24696bc | 727 | ioapic_entries[apic][pin] = |
54168ed7 | 728 | ioapic_read_entry(apic, pin); |
b24696bc | 729 | } |
5ffa4eb2 | 730 | |
54168ed7 IM |
731 | return 0; |
732 | } | |
733 | ||
b24696bc FY |
734 | /* |
735 | * Mask all IO APIC entries. | |
736 | */ | |
737 | void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
05c3dc2c SS |
738 | { |
739 | int apic, pin; | |
740 | ||
b24696bc FY |
741 | if (!ioapic_entries) |
742 | return; | |
743 | ||
05c3dc2c | 744 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc | 745 | if (!ioapic_entries[apic]) |
05c3dc2c | 746 | break; |
b24696bc | 747 | |
05c3dc2c SS |
748 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
749 | struct IO_APIC_route_entry entry; | |
750 | ||
b24696bc | 751 | entry = ioapic_entries[apic][pin]; |
05c3dc2c SS |
752 | if (!entry.mask) { |
753 | entry.mask = 1; | |
754 | ioapic_write_entry(apic, pin, entry); | |
755 | } | |
756 | } | |
757 | } | |
758 | } | |
759 | ||
b24696bc FY |
760 | /* |
761 | * Restore IO APIC entries which was saved in ioapic_entries. | |
762 | */ | |
763 | int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
54168ed7 IM |
764 | { |
765 | int apic, pin; | |
766 | ||
b24696bc FY |
767 | if (!ioapic_entries) |
768 | return -ENOMEM; | |
769 | ||
5ffa4eb2 | 770 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc FY |
771 | if (!ioapic_entries[apic]) |
772 | return -ENOMEM; | |
773 | ||
54168ed7 IM |
774 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
775 | ioapic_write_entry(apic, pin, | |
b24696bc | 776 | ioapic_entries[apic][pin]); |
5ffa4eb2 | 777 | } |
b24696bc | 778 | return 0; |
54168ed7 IM |
779 | } |
780 | ||
b24696bc FY |
781 | void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries) |
782 | { | |
783 | int apic; | |
784 | ||
785 | for (apic = 0; apic < nr_ioapics; apic++) | |
786 | kfree(ioapic_entries[apic]); | |
787 | ||
788 | kfree(ioapic_entries); | |
54168ed7 | 789 | } |
1da177e4 LT |
790 | |
791 | /* | |
792 | * Find the IRQ entry number of a certain pin. | |
793 | */ | |
794 | static int find_irq_entry(int apic, int pin, int type) | |
795 | { | |
796 | int i; | |
797 | ||
798 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
799 | if (mp_irqs[i].irqtype == type && |
800 | (mp_irqs[i].dstapic == mp_ioapics[apic].apicid || | |
801 | mp_irqs[i].dstapic == MP_APIC_ALL) && | |
802 | mp_irqs[i].dstirq == pin) | |
1da177e4 LT |
803 | return i; |
804 | ||
805 | return -1; | |
806 | } | |
807 | ||
808 | /* | |
809 | * Find the pin to which IRQ[irq] (ISA) is connected | |
810 | */ | |
fcfd636a | 811 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
812 | { |
813 | int i; | |
814 | ||
815 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 816 | int lbus = mp_irqs[i].srcbus; |
1da177e4 | 817 | |
d27e2b8e | 818 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
819 | (mp_irqs[i].irqtype == type) && |
820 | (mp_irqs[i].srcbusirq == irq)) | |
1da177e4 | 821 | |
c2c21745 | 822 | return mp_irqs[i].dstirq; |
1da177e4 LT |
823 | } |
824 | return -1; | |
825 | } | |
826 | ||
fcfd636a EB |
827 | static int __init find_isa_irq_apic(int irq, int type) |
828 | { | |
829 | int i; | |
830 | ||
831 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 832 | int lbus = mp_irqs[i].srcbus; |
fcfd636a | 833 | |
73b2961b | 834 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
835 | (mp_irqs[i].irqtype == type) && |
836 | (mp_irqs[i].srcbusirq == irq)) | |
fcfd636a EB |
837 | break; |
838 | } | |
839 | if (i < mp_irq_entries) { | |
840 | int apic; | |
54168ed7 | 841 | for(apic = 0; apic < nr_ioapics; apic++) { |
c2c21745 | 842 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic) |
fcfd636a EB |
843 | return apic; |
844 | } | |
845 | } | |
846 | ||
847 | return -1; | |
848 | } | |
849 | ||
c0a282c2 | 850 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
851 | /* |
852 | * EISA Edge/Level control register, ELCR | |
853 | */ | |
854 | static int EISA_ELCR(unsigned int irq) | |
855 | { | |
b81bb373 | 856 | if (irq < legacy_pic->nr_legacy_irqs) { |
1da177e4 LT |
857 | unsigned int port = 0x4d0 + (irq >> 3); |
858 | return (inb(port) >> (irq & 7)) & 1; | |
859 | } | |
860 | apic_printk(APIC_VERBOSE, KERN_INFO | |
861 | "Broken MPtable reports ISA irq %d\n", irq); | |
862 | return 0; | |
863 | } | |
54168ed7 | 864 | |
c0a282c2 | 865 | #endif |
1da177e4 | 866 | |
6728801d AS |
867 | /* ISA interrupts are always polarity zero edge triggered, |
868 | * when listed as conforming in the MP table. */ | |
869 | ||
870 | #define default_ISA_trigger(idx) (0) | |
871 | #define default_ISA_polarity(idx) (0) | |
872 | ||
1da177e4 LT |
873 | /* EISA interrupts are always polarity zero and can be edge or level |
874 | * trigger depending on the ELCR value. If an interrupt is listed as | |
875 | * EISA conforming in the MP table, that means its trigger type must | |
876 | * be read in from the ELCR */ | |
877 | ||
c2c21745 | 878 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
6728801d | 879 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
880 | |
881 | /* PCI interrupts are always polarity one level triggered, | |
882 | * when listed as conforming in the MP table. */ | |
883 | ||
884 | #define default_PCI_trigger(idx) (1) | |
885 | #define default_PCI_polarity(idx) (1) | |
886 | ||
887 | /* MCA interrupts are always polarity zero level triggered, | |
888 | * when listed as conforming in the MP table. */ | |
889 | ||
890 | #define default_MCA_trigger(idx) (1) | |
6728801d | 891 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 892 | |
61fd47e0 | 893 | static int MPBIOS_polarity(int idx) |
1da177e4 | 894 | { |
c2c21745 | 895 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
896 | int polarity; |
897 | ||
898 | /* | |
899 | * Determine IRQ line polarity (high active or low active): | |
900 | */ | |
c2c21745 | 901 | switch (mp_irqs[idx].irqflag & 3) |
36062448 | 902 | { |
54168ed7 IM |
903 | case 0: /* conforms, ie. bus-type dependent polarity */ |
904 | if (test_bit(bus, mp_bus_not_pci)) | |
905 | polarity = default_ISA_polarity(idx); | |
906 | else | |
907 | polarity = default_PCI_polarity(idx); | |
908 | break; | |
909 | case 1: /* high active */ | |
910 | { | |
911 | polarity = 0; | |
912 | break; | |
913 | } | |
914 | case 2: /* reserved */ | |
915 | { | |
916 | printk(KERN_WARNING "broken BIOS!!\n"); | |
917 | polarity = 1; | |
918 | break; | |
919 | } | |
920 | case 3: /* low active */ | |
921 | { | |
922 | polarity = 1; | |
923 | break; | |
924 | } | |
925 | default: /* invalid */ | |
926 | { | |
927 | printk(KERN_WARNING "broken BIOS!!\n"); | |
928 | polarity = 1; | |
929 | break; | |
930 | } | |
1da177e4 LT |
931 | } |
932 | return polarity; | |
933 | } | |
934 | ||
935 | static int MPBIOS_trigger(int idx) | |
936 | { | |
c2c21745 | 937 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
938 | int trigger; |
939 | ||
940 | /* | |
941 | * Determine IRQ trigger mode (edge or level sensitive): | |
942 | */ | |
c2c21745 | 943 | switch ((mp_irqs[idx].irqflag>>2) & 3) |
1da177e4 | 944 | { |
54168ed7 IM |
945 | case 0: /* conforms, ie. bus-type dependent */ |
946 | if (test_bit(bus, mp_bus_not_pci)) | |
947 | trigger = default_ISA_trigger(idx); | |
948 | else | |
949 | trigger = default_PCI_trigger(idx); | |
c0a282c2 | 950 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
54168ed7 IM |
951 | switch (mp_bus_id_to_type[bus]) { |
952 | case MP_BUS_ISA: /* ISA pin */ | |
953 | { | |
954 | /* set before the switch */ | |
955 | break; | |
956 | } | |
957 | case MP_BUS_EISA: /* EISA pin */ | |
958 | { | |
959 | trigger = default_EISA_trigger(idx); | |
960 | break; | |
961 | } | |
962 | case MP_BUS_PCI: /* PCI pin */ | |
963 | { | |
964 | /* set before the switch */ | |
965 | break; | |
966 | } | |
967 | case MP_BUS_MCA: /* MCA pin */ | |
968 | { | |
969 | trigger = default_MCA_trigger(idx); | |
970 | break; | |
971 | } | |
972 | default: | |
973 | { | |
974 | printk(KERN_WARNING "broken BIOS!!\n"); | |
975 | trigger = 1; | |
976 | break; | |
977 | } | |
978 | } | |
979 | #endif | |
1da177e4 | 980 | break; |
54168ed7 | 981 | case 1: /* edge */ |
1da177e4 | 982 | { |
54168ed7 | 983 | trigger = 0; |
1da177e4 LT |
984 | break; |
985 | } | |
54168ed7 | 986 | case 2: /* reserved */ |
1da177e4 | 987 | { |
54168ed7 IM |
988 | printk(KERN_WARNING "broken BIOS!!\n"); |
989 | trigger = 1; | |
1da177e4 LT |
990 | break; |
991 | } | |
54168ed7 | 992 | case 3: /* level */ |
1da177e4 | 993 | { |
54168ed7 | 994 | trigger = 1; |
1da177e4 LT |
995 | break; |
996 | } | |
54168ed7 | 997 | default: /* invalid */ |
1da177e4 LT |
998 | { |
999 | printk(KERN_WARNING "broken BIOS!!\n"); | |
54168ed7 | 1000 | trigger = 0; |
1da177e4 LT |
1001 | break; |
1002 | } | |
1003 | } | |
1004 | return trigger; | |
1005 | } | |
1006 | ||
1007 | static inline int irq_polarity(int idx) | |
1008 | { | |
1009 | return MPBIOS_polarity(idx); | |
1010 | } | |
1011 | ||
1012 | static inline int irq_trigger(int idx) | |
1013 | { | |
1014 | return MPBIOS_trigger(idx); | |
1015 | } | |
1016 | ||
1017 | static int pin_2_irq(int idx, int apic, int pin) | |
1018 | { | |
d464207c | 1019 | int irq; |
c2c21745 | 1020 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
1021 | |
1022 | /* | |
1023 | * Debugging check, we are in big trouble if this message pops up! | |
1024 | */ | |
c2c21745 | 1025 | if (mp_irqs[idx].dstirq != pin) |
1da177e4 LT |
1026 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
1027 | ||
54168ed7 | 1028 | if (test_bit(bus, mp_bus_not_pci)) { |
c2c21745 | 1029 | irq = mp_irqs[idx].srcbusirq; |
54168ed7 | 1030 | } else { |
d464207c | 1031 | u32 gsi = mp_gsi_routing[apic].gsi_base + pin; |
988856ee EB |
1032 | |
1033 | if (gsi >= NR_IRQS_LEGACY) | |
1034 | irq = gsi; | |
1035 | else | |
a4384df3 | 1036 | irq = gsi_top + gsi; |
1da177e4 LT |
1037 | } |
1038 | ||
54168ed7 | 1039 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1040 | /* |
1041 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1042 | */ | |
1043 | if ((pin >= 16) && (pin <= 23)) { | |
1044 | if (pirq_entries[pin-16] != -1) { | |
1045 | if (!pirq_entries[pin-16]) { | |
1046 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1047 | "disabling PIRQ%d\n", pin-16); | |
1048 | } else { | |
1049 | irq = pirq_entries[pin-16]; | |
1050 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1051 | "using PIRQ%d -> IRQ %d\n", | |
1052 | pin-16, irq); | |
1053 | } | |
1054 | } | |
1055 | } | |
54168ed7 IM |
1056 | #endif |
1057 | ||
1da177e4 LT |
1058 | return irq; |
1059 | } | |
1060 | ||
e20c06fd YL |
1061 | /* |
1062 | * Find a specific PCI IRQ entry. | |
1063 | * Not an __init, possibly needed by modules | |
1064 | */ | |
1065 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin, | |
e5198075 | 1066 | struct io_apic_irq_attr *irq_attr) |
e20c06fd YL |
1067 | { |
1068 | int apic, i, best_guess = -1; | |
1069 | ||
1070 | apic_printk(APIC_DEBUG, | |
1071 | "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", | |
1072 | bus, slot, pin); | |
1073 | if (test_bit(bus, mp_bus_not_pci)) { | |
1074 | apic_printk(APIC_VERBOSE, | |
1075 | "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
1076 | return -1; | |
1077 | } | |
1078 | for (i = 0; i < mp_irq_entries; i++) { | |
1079 | int lbus = mp_irqs[i].srcbus; | |
1080 | ||
1081 | for (apic = 0; apic < nr_ioapics; apic++) | |
1082 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic || | |
1083 | mp_irqs[i].dstapic == MP_APIC_ALL) | |
1084 | break; | |
1085 | ||
1086 | if (!test_bit(lbus, mp_bus_not_pci) && | |
1087 | !mp_irqs[i].irqtype && | |
1088 | (bus == lbus) && | |
1089 | (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) { | |
1090 | int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq); | |
1091 | ||
1092 | if (!(apic || IO_APIC_IRQ(irq))) | |
1093 | continue; | |
1094 | ||
1095 | if (pin == (mp_irqs[i].srcbusirq & 3)) { | |
e5198075 YL |
1096 | set_io_apic_irq_attr(irq_attr, apic, |
1097 | mp_irqs[i].dstirq, | |
1098 | irq_trigger(i), | |
1099 | irq_polarity(i)); | |
e20c06fd YL |
1100 | return irq; |
1101 | } | |
1102 | /* | |
1103 | * Use the first all-but-pin matching entry as a | |
1104 | * best-guess fuzzy result for broken mptables. | |
1105 | */ | |
1106 | if (best_guess < 0) { | |
e5198075 YL |
1107 | set_io_apic_irq_attr(irq_attr, apic, |
1108 | mp_irqs[i].dstirq, | |
1109 | irq_trigger(i), | |
1110 | irq_polarity(i)); | |
e20c06fd YL |
1111 | best_guess = irq; |
1112 | } | |
1113 | } | |
1114 | } | |
1115 | return best_guess; | |
1116 | } | |
1117 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); | |
1118 | ||
497c9a19 YL |
1119 | void lock_vector_lock(void) |
1120 | { | |
1121 | /* Used to the online set of cpus does not change | |
1122 | * during assign_irq_vector. | |
1123 | */ | |
dade7716 | 1124 | raw_spin_lock(&vector_lock); |
497c9a19 | 1125 | } |
1da177e4 | 1126 | |
497c9a19 | 1127 | void unlock_vector_lock(void) |
1da177e4 | 1128 | { |
dade7716 | 1129 | raw_spin_unlock(&vector_lock); |
497c9a19 | 1130 | } |
1da177e4 | 1131 | |
e7986739 MT |
1132 | static int |
1133 | __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 | 1134 | { |
047c8fdb YL |
1135 | /* |
1136 | * NOTE! The local APIC isn't very good at handling | |
1137 | * multiple interrupts at the same interrupt level. | |
1138 | * As the interrupt level is determined by taking the | |
1139 | * vector number and shifting that right by 4, we | |
1140 | * want to spread these out a bit so that they don't | |
1141 | * all fall in the same interrupt level. | |
1142 | * | |
1143 | * Also, we've got to be careful not to trash gate | |
1144 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1145 | */ | |
6579b474 | 1146 | static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; |
ea943966 | 1147 | static int current_offset = VECTOR_OFFSET_START % 8; |
54168ed7 | 1148 | unsigned int old_vector; |
22f65d31 MT |
1149 | int cpu, err; |
1150 | cpumask_var_t tmp_mask; | |
ace80ab7 | 1151 | |
23359a88 | 1152 | if (cfg->move_in_progress) |
54168ed7 | 1153 | return -EBUSY; |
0a1ad60d | 1154 | |
22f65d31 MT |
1155 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) |
1156 | return -ENOMEM; | |
ace80ab7 | 1157 | |
54168ed7 IM |
1158 | old_vector = cfg->vector; |
1159 | if (old_vector) { | |
22f65d31 MT |
1160 | cpumask_and(tmp_mask, mask, cpu_online_mask); |
1161 | cpumask_and(tmp_mask, cfg->domain, tmp_mask); | |
1162 | if (!cpumask_empty(tmp_mask)) { | |
1163 | free_cpumask_var(tmp_mask); | |
54168ed7 | 1164 | return 0; |
22f65d31 | 1165 | } |
54168ed7 | 1166 | } |
497c9a19 | 1167 | |
e7986739 | 1168 | /* Only try and allocate irqs on cpus that are present */ |
22f65d31 MT |
1169 | err = -ENOSPC; |
1170 | for_each_cpu_and(cpu, mask, cpu_online_mask) { | |
54168ed7 IM |
1171 | int new_cpu; |
1172 | int vector, offset; | |
497c9a19 | 1173 | |
e2d40b18 | 1174 | apic->vector_allocation_domain(cpu, tmp_mask); |
497c9a19 | 1175 | |
54168ed7 IM |
1176 | vector = current_vector; |
1177 | offset = current_offset; | |
497c9a19 | 1178 | next: |
54168ed7 IM |
1179 | vector += 8; |
1180 | if (vector >= first_system_vector) { | |
e7986739 | 1181 | /* If out of vectors on large boxen, must share them. */ |
54168ed7 | 1182 | offset = (offset + 1) % 8; |
6579b474 | 1183 | vector = FIRST_EXTERNAL_VECTOR + offset; |
54168ed7 IM |
1184 | } |
1185 | if (unlikely(current_vector == vector)) | |
1186 | continue; | |
b77b881f YL |
1187 | |
1188 | if (test_bit(vector, used_vectors)) | |
54168ed7 | 1189 | goto next; |
b77b881f | 1190 | |
22f65d31 | 1191 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1192 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) |
1193 | goto next; | |
1194 | /* Found one! */ | |
1195 | current_vector = vector; | |
1196 | current_offset = offset; | |
1197 | if (old_vector) { | |
1198 | cfg->move_in_progress = 1; | |
22f65d31 | 1199 | cpumask_copy(cfg->old_domain, cfg->domain); |
7a959cff | 1200 | } |
22f65d31 | 1201 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1202 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
1203 | cfg->vector = vector; | |
22f65d31 MT |
1204 | cpumask_copy(cfg->domain, tmp_mask); |
1205 | err = 0; | |
1206 | break; | |
54168ed7 | 1207 | } |
22f65d31 MT |
1208 | free_cpumask_var(tmp_mask); |
1209 | return err; | |
497c9a19 YL |
1210 | } |
1211 | ||
9338ad6f | 1212 | int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) |
497c9a19 YL |
1213 | { |
1214 | int err; | |
ace80ab7 | 1215 | unsigned long flags; |
ace80ab7 | 1216 | |
dade7716 | 1217 | raw_spin_lock_irqsave(&vector_lock, flags); |
3145e941 | 1218 | err = __assign_irq_vector(irq, cfg, mask); |
dade7716 | 1219 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1220 | return err; |
1221 | } | |
1222 | ||
3145e941 | 1223 | static void __clear_irq_vector(int irq, struct irq_cfg *cfg) |
497c9a19 | 1224 | { |
497c9a19 YL |
1225 | int cpu, vector; |
1226 | ||
497c9a19 YL |
1227 | BUG_ON(!cfg->vector); |
1228 | ||
1229 | vector = cfg->vector; | |
22f65d31 | 1230 | for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) |
497c9a19 YL |
1231 | per_cpu(vector_irq, cpu)[vector] = -1; |
1232 | ||
1233 | cfg->vector = 0; | |
22f65d31 | 1234 | cpumask_clear(cfg->domain); |
0ca4b6b0 MW |
1235 | |
1236 | if (likely(!cfg->move_in_progress)) | |
1237 | return; | |
22f65d31 | 1238 | for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { |
0ca4b6b0 MW |
1239 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
1240 | vector++) { | |
1241 | if (per_cpu(vector_irq, cpu)[vector] != irq) | |
1242 | continue; | |
1243 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1244 | break; | |
1245 | } | |
1246 | } | |
1247 | cfg->move_in_progress = 0; | |
497c9a19 YL |
1248 | } |
1249 | ||
1250 | void __setup_vector_irq(int cpu) | |
1251 | { | |
1252 | /* Initialize vector_irq on a new cpu */ | |
497c9a19 YL |
1253 | int irq, vector; |
1254 | struct irq_cfg *cfg; | |
0b8f1efa | 1255 | struct irq_desc *desc; |
497c9a19 | 1256 | |
9d133e5d SS |
1257 | /* |
1258 | * vector_lock will make sure that we don't run into irq vector | |
1259 | * assignments that might be happening on another cpu in parallel, | |
1260 | * while we setup our initial vector to irq mappings. | |
1261 | */ | |
dade7716 | 1262 | raw_spin_lock(&vector_lock); |
497c9a19 | 1263 | /* Mark the inuse vectors */ |
0b8f1efa | 1264 | for_each_irq_desc(irq, desc) { |
d4eba297 | 1265 | cfg = get_irq_desc_chip_data(desc); |
36e9e1ea SS |
1266 | |
1267 | /* | |
1268 | * If it is a legacy IRQ handled by the legacy PIC, this cpu | |
1269 | * will be part of the irq_cfg's domain. | |
1270 | */ | |
1271 | if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq)) | |
1272 | cpumask_set_cpu(cpu, cfg->domain); | |
1273 | ||
22f65d31 | 1274 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 YL |
1275 | continue; |
1276 | vector = cfg->vector; | |
497c9a19 YL |
1277 | per_cpu(vector_irq, cpu)[vector] = irq; |
1278 | } | |
1279 | /* Mark the free vectors */ | |
1280 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1281 | irq = per_cpu(vector_irq, cpu)[vector]; | |
1282 | if (irq < 0) | |
1283 | continue; | |
1284 | ||
1285 | cfg = irq_cfg(irq); | |
22f65d31 | 1286 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 | 1287 | per_cpu(vector_irq, cpu)[vector] = -1; |
54168ed7 | 1288 | } |
dade7716 | 1289 | raw_spin_unlock(&vector_lock); |
1da177e4 | 1290 | } |
3fde6900 | 1291 | |
f5b9ed7a | 1292 | static struct irq_chip ioapic_chip; |
54168ed7 | 1293 | static struct irq_chip ir_ioapic_chip; |
1da177e4 | 1294 | |
54168ed7 IM |
1295 | #define IOAPIC_AUTO -1 |
1296 | #define IOAPIC_EDGE 0 | |
1297 | #define IOAPIC_LEVEL 1 | |
1da177e4 | 1298 | |
047c8fdb | 1299 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1300 | static inline int IO_APIC_irq_trigger(int irq) |
1301 | { | |
d6c88a50 | 1302 | int apic, idx, pin; |
1d025192 | 1303 | |
d6c88a50 TG |
1304 | for (apic = 0; apic < nr_ioapics; apic++) { |
1305 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1306 | idx = find_irq_entry(apic, pin, mp_INT); | |
1307 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1308 | return irq_trigger(idx); | |
1309 | } | |
1310 | } | |
1311 | /* | |
54168ed7 IM |
1312 | * nonexistent IRQs are edge default |
1313 | */ | |
d6c88a50 | 1314 | return 0; |
1d025192 | 1315 | } |
047c8fdb YL |
1316 | #else |
1317 | static inline int IO_APIC_irq_trigger(int irq) | |
1318 | { | |
54168ed7 | 1319 | return 1; |
047c8fdb YL |
1320 | } |
1321 | #endif | |
1d025192 | 1322 | |
3145e941 | 1323 | static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger) |
1da177e4 | 1324 | { |
199751d7 | 1325 | |
6ebcc00e | 1326 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
047c8fdb | 1327 | trigger == IOAPIC_LEVEL) |
08678b08 | 1328 | desc->status |= IRQ_LEVEL; |
047c8fdb YL |
1329 | else |
1330 | desc->status &= ~IRQ_LEVEL; | |
1331 | ||
54168ed7 IM |
1332 | if (irq_remapped(irq)) { |
1333 | desc->status |= IRQ_MOVE_PCNTXT; | |
1334 | if (trigger) | |
1335 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1336 | handle_fasteoi_irq, | |
1337 | "fasteoi"); | |
1338 | else | |
1339 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1340 | handle_edge_irq, "edge"); | |
1341 | return; | |
1342 | } | |
29b61be6 | 1343 | |
047c8fdb YL |
1344 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
1345 | trigger == IOAPIC_LEVEL) | |
a460e745 | 1346 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 IM |
1347 | handle_fasteoi_irq, |
1348 | "fasteoi"); | |
047c8fdb | 1349 | else |
a460e745 | 1350 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 | 1351 | handle_edge_irq, "edge"); |
1da177e4 LT |
1352 | } |
1353 | ||
ca97ab90 JF |
1354 | int setup_ioapic_entry(int apic_id, int irq, |
1355 | struct IO_APIC_route_entry *entry, | |
1356 | unsigned int destination, int trigger, | |
0280f7c4 | 1357 | int polarity, int vector, int pin) |
1da177e4 | 1358 | { |
497c9a19 YL |
1359 | /* |
1360 | * add it to the IO-APIC irq-routing table: | |
1361 | */ | |
1362 | memset(entry,0,sizeof(*entry)); | |
1363 | ||
54168ed7 | 1364 | if (intr_remapping_enabled) { |
c8d46cf0 | 1365 | struct intel_iommu *iommu = map_ioapic_to_ir(apic_id); |
54168ed7 IM |
1366 | struct irte irte; |
1367 | struct IR_IO_APIC_route_entry *ir_entry = | |
1368 | (struct IR_IO_APIC_route_entry *) entry; | |
1369 | int index; | |
1370 | ||
1371 | if (!iommu) | |
c8d46cf0 | 1372 | panic("No mapping iommu for ioapic %d\n", apic_id); |
54168ed7 IM |
1373 | |
1374 | index = alloc_irte(iommu, irq, 1); | |
1375 | if (index < 0) | |
c8d46cf0 | 1376 | panic("Failed to allocate IRTE for ioapic %d\n", apic_id); |
54168ed7 | 1377 | |
62a92f4c | 1378 | prepare_irte(&irte, vector, destination); |
54168ed7 | 1379 | |
f007e99c WH |
1380 | /* Set source-id of interrupt request */ |
1381 | set_ioapic_sid(&irte, apic_id); | |
1382 | ||
54168ed7 IM |
1383 | modify_irte(irq, &irte); |
1384 | ||
1385 | ir_entry->index2 = (index >> 15) & 0x1; | |
1386 | ir_entry->zero = 0; | |
1387 | ir_entry->format = 1; | |
1388 | ir_entry->index = (index & 0x7fff); | |
0280f7c4 SS |
1389 | /* |
1390 | * IO-APIC RTE will be configured with virtual vector. | |
1391 | * irq handler will do the explicit EOI to the io-apic. | |
1392 | */ | |
1393 | ir_entry->vector = pin; | |
29b61be6 | 1394 | } else { |
9b5bc8dc IM |
1395 | entry->delivery_mode = apic->irq_delivery_mode; |
1396 | entry->dest_mode = apic->irq_dest_mode; | |
54168ed7 | 1397 | entry->dest = destination; |
0280f7c4 | 1398 | entry->vector = vector; |
54168ed7 | 1399 | } |
497c9a19 | 1400 | |
54168ed7 | 1401 | entry->mask = 0; /* enable IRQ */ |
497c9a19 YL |
1402 | entry->trigger = trigger; |
1403 | entry->polarity = polarity; | |
497c9a19 YL |
1404 | |
1405 | /* Mask level triggered irqs. | |
1406 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
1407 | */ | |
1408 | if (trigger) | |
1409 | entry->mask = 1; | |
497c9a19 YL |
1410 | return 0; |
1411 | } | |
1412 | ||
c8d46cf0 | 1413 | static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc, |
54168ed7 | 1414 | int trigger, int polarity) |
497c9a19 YL |
1415 | { |
1416 | struct irq_cfg *cfg; | |
1da177e4 | 1417 | struct IO_APIC_route_entry entry; |
22f65d31 | 1418 | unsigned int dest; |
497c9a19 YL |
1419 | |
1420 | if (!IO_APIC_IRQ(irq)) | |
1421 | return; | |
1422 | ||
d4eba297 | 1423 | cfg = get_irq_desc_chip_data(desc); |
497c9a19 | 1424 | |
69c89efb SS |
1425 | /* |
1426 | * For legacy irqs, cfg->domain starts with cpu 0 for legacy | |
1427 | * controllers like 8259. Now that IO-APIC can handle this irq, update | |
1428 | * the cfg->domain. | |
1429 | */ | |
28c6a0ba | 1430 | if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain)) |
69c89efb SS |
1431 | apic->vector_allocation_domain(0, cfg->domain); |
1432 | ||
fe402e1f | 1433 | if (assign_irq_vector(irq, cfg, apic->target_cpus())) |
497c9a19 YL |
1434 | return; |
1435 | ||
debccb3e | 1436 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 YL |
1437 | |
1438 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1439 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
1440 | "IRQ %d Mode:%i Active:%i)\n", | |
c8d46cf0 | 1441 | apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector, |
497c9a19 YL |
1442 | irq, trigger, polarity); |
1443 | ||
1444 | ||
c8d46cf0 | 1445 | if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry, |
0280f7c4 | 1446 | dest, trigger, polarity, cfg->vector, pin)) { |
497c9a19 | 1447 | printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", |
c8d46cf0 | 1448 | mp_ioapics[apic_id].apicid, pin); |
3145e941 | 1449 | __clear_irq_vector(irq, cfg); |
497c9a19 YL |
1450 | return; |
1451 | } | |
1452 | ||
3145e941 | 1453 | ioapic_register_intr(irq, desc, trigger); |
b81bb373 | 1454 | if (irq < legacy_pic->nr_legacy_irqs) |
4305df94 | 1455 | legacy_pic->mask(irq); |
497c9a19 | 1456 | |
c8d46cf0 | 1457 | ioapic_write_entry(apic_id, pin, entry); |
497c9a19 YL |
1458 | } |
1459 | ||
b9c61b70 YL |
1460 | static struct { |
1461 | DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1); | |
1462 | } mp_ioapic_routing[MAX_IO_APICS]; | |
1463 | ||
497c9a19 YL |
1464 | static void __init setup_IO_APIC_irqs(void) |
1465 | { | |
fad53995 | 1466 | int apic_id, pin, idx, irq; |
3c2cbd24 | 1467 | int notcon = 0; |
0b8f1efa | 1468 | struct irq_desc *desc; |
3145e941 | 1469 | struct irq_cfg *cfg; |
f6e9456c | 1470 | int node = cpu_to_node(0); |
1da177e4 LT |
1471 | |
1472 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1473 | ||
fad53995 | 1474 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) |
b9c61b70 YL |
1475 | for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) { |
1476 | idx = find_irq_entry(apic_id, pin, mp_INT); | |
1477 | if (idx == -1) { | |
1478 | if (!notcon) { | |
1479 | notcon = 1; | |
1480 | apic_printk(APIC_VERBOSE, | |
1481 | KERN_DEBUG " %d-%d", | |
1482 | mp_ioapics[apic_id].apicid, pin); | |
1483 | } else | |
1484 | apic_printk(APIC_VERBOSE, " %d-%d", | |
1485 | mp_ioapics[apic_id].apicid, pin); | |
1486 | continue; | |
1487 | } | |
1488 | if (notcon) { | |
1489 | apic_printk(APIC_VERBOSE, | |
1490 | " (apicid-pin) not connected\n"); | |
1491 | notcon = 0; | |
1492 | } | |
33a201fa | 1493 | |
b9c61b70 | 1494 | irq = pin_2_irq(idx, apic_id, pin); |
33a201fa | 1495 | |
fad53995 EB |
1496 | if ((apic_id > 0) && (irq > 16)) |
1497 | continue; | |
1498 | ||
b9c61b70 YL |
1499 | /* |
1500 | * Skip the timer IRQ if there's a quirk handler | |
1501 | * installed and if it returns 1: | |
1502 | */ | |
1503 | if (apic->multi_timer_check && | |
1504 | apic->multi_timer_check(apic_id, irq)) | |
1505 | continue; | |
36062448 | 1506 | |
b9c61b70 YL |
1507 | desc = irq_to_desc_alloc_node(irq, node); |
1508 | if (!desc) { | |
1509 | printk(KERN_INFO "can not get irq_desc for %d\n", irq); | |
1510 | continue; | |
3c2cbd24 | 1511 | } |
d4eba297 | 1512 | cfg = get_irq_desc_chip_data(desc); |
b9c61b70 | 1513 | add_pin_to_irq_node(cfg, node, apic_id, pin); |
4c6f18fc YL |
1514 | /* |
1515 | * don't mark it in pin_programmed, so later acpi could | |
1516 | * set it correctly when irq < 16 | |
1517 | */ | |
b9c61b70 YL |
1518 | setup_IO_APIC_irq(apic_id, pin, irq, desc, |
1519 | irq_trigger(idx), irq_polarity(idx)); | |
1da177e4 LT |
1520 | } |
1521 | ||
3c2cbd24 CG |
1522 | if (notcon) |
1523 | apic_printk(APIC_VERBOSE, | |
2a554fb1 | 1524 | " (apicid-pin) not connected\n"); |
1da177e4 LT |
1525 | } |
1526 | ||
18dce6ba YL |
1527 | /* |
1528 | * for the gsit that is not in first ioapic | |
1529 | * but could not use acpi_register_gsi() | |
1530 | * like some special sci in IBM x3330 | |
1531 | */ | |
1532 | void setup_IO_APIC_irq_extra(u32 gsi) | |
1533 | { | |
1534 | int apic_id = 0, pin, idx, irq; | |
f6e9456c | 1535 | int node = cpu_to_node(0); |
18dce6ba YL |
1536 | struct irq_desc *desc; |
1537 | struct irq_cfg *cfg; | |
1538 | ||
1539 | /* | |
1540 | * Convert 'gsi' to 'ioapic.pin'. | |
1541 | */ | |
1542 | apic_id = mp_find_ioapic(gsi); | |
1543 | if (apic_id < 0) | |
1544 | return; | |
1545 | ||
1546 | pin = mp_find_ioapic_pin(apic_id, gsi); | |
1547 | idx = find_irq_entry(apic_id, pin, mp_INT); | |
1548 | if (idx == -1) | |
1549 | return; | |
1550 | ||
1551 | irq = pin_2_irq(idx, apic_id, pin); | |
1552 | #ifdef CONFIG_SPARSE_IRQ | |
1553 | desc = irq_to_desc(irq); | |
1554 | if (desc) | |
1555 | return; | |
1556 | #endif | |
1557 | desc = irq_to_desc_alloc_node(irq, node); | |
1558 | if (!desc) { | |
1559 | printk(KERN_INFO "can not get irq_desc for %d\n", irq); | |
1560 | return; | |
1561 | } | |
1562 | ||
d4eba297 | 1563 | cfg = get_irq_desc_chip_data(desc); |
18dce6ba YL |
1564 | add_pin_to_irq_node(cfg, node, apic_id, pin); |
1565 | ||
1566 | if (test_bit(pin, mp_ioapic_routing[apic_id].pin_programmed)) { | |
1567 | pr_debug("Pin %d-%d already programmed\n", | |
1568 | mp_ioapics[apic_id].apicid, pin); | |
1569 | return; | |
1570 | } | |
1571 | set_bit(pin, mp_ioapic_routing[apic_id].pin_programmed); | |
1572 | ||
1573 | setup_IO_APIC_irq(apic_id, pin, irq, desc, | |
1574 | irq_trigger(idx), irq_polarity(idx)); | |
1575 | } | |
1576 | ||
1da177e4 | 1577 | /* |
f7633ce5 | 1578 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1579 | */ |
c8d46cf0 | 1580 | static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin, |
f7633ce5 | 1581 | int vector) |
1da177e4 LT |
1582 | { |
1583 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1584 | |
54168ed7 IM |
1585 | if (intr_remapping_enabled) |
1586 | return; | |
54168ed7 | 1587 | |
36062448 | 1588 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1589 | |
1590 | /* | |
1591 | * We use logical delivery to get the timer IRQ | |
1592 | * to the first CPU. | |
1593 | */ | |
9b5bc8dc | 1594 | entry.dest_mode = apic->irq_dest_mode; |
f72dccac | 1595 | entry.mask = 0; /* don't mask IRQ for edge */ |
debccb3e | 1596 | entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus()); |
9b5bc8dc | 1597 | entry.delivery_mode = apic->irq_delivery_mode; |
1da177e4 LT |
1598 | entry.polarity = 0; |
1599 | entry.trigger = 0; | |
1600 | entry.vector = vector; | |
1601 | ||
1602 | /* | |
1603 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1604 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1605 | */ |
54168ed7 | 1606 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); |
1da177e4 LT |
1607 | |
1608 | /* | |
1609 | * Add it to the IO-APIC irq-routing table: | |
1610 | */ | |
c8d46cf0 | 1611 | ioapic_write_entry(apic_id, pin, entry); |
1da177e4 LT |
1612 | } |
1613 | ||
32f71aff MR |
1614 | |
1615 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
1616 | { |
1617 | int apic, i; | |
1618 | union IO_APIC_reg_00 reg_00; | |
1619 | union IO_APIC_reg_01 reg_01; | |
1620 | union IO_APIC_reg_02 reg_02; | |
1621 | union IO_APIC_reg_03 reg_03; | |
1622 | unsigned long flags; | |
0f978f45 | 1623 | struct irq_cfg *cfg; |
0b8f1efa | 1624 | struct irq_desc *desc; |
8f09cd20 | 1625 | unsigned int irq; |
1da177e4 | 1626 | |
36062448 | 1627 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1628 | for (i = 0; i < nr_ioapics; i++) |
1629 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
b5ba7e6d | 1630 | mp_ioapics[i].apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1631 | |
1632 | /* | |
1633 | * We are a bit conservative about what we expect. We have to | |
1634 | * know about every hardware change ASAP. | |
1635 | */ | |
1636 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1637 | ||
1638 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1639 | ||
dade7716 | 1640 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 LT |
1641 | reg_00.raw = io_apic_read(apic, 0); |
1642 | reg_01.raw = io_apic_read(apic, 1); | |
1643 | if (reg_01.bits.version >= 0x10) | |
1644 | reg_02.raw = io_apic_read(apic, 2); | |
d6c88a50 TG |
1645 | if (reg_01.bits.version >= 0x20) |
1646 | reg_03.raw = io_apic_read(apic, 3); | |
dade7716 | 1647 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 | 1648 | |
54168ed7 | 1649 | printk("\n"); |
b5ba7e6d | 1650 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid); |
1da177e4 LT |
1651 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1652 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1653 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1654 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1655 | |
54168ed7 | 1656 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
1da177e4 | 1657 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); |
1da177e4 LT |
1658 | |
1659 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1660 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1661 | |
1662 | /* | |
1663 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1664 | * but the value of reg_02 is read as the previous read register | |
1665 | * value, so ignore it if reg_02 == reg_01. | |
1666 | */ | |
1667 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1668 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1669 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1670 | } |
1671 | ||
1672 | /* | |
1673 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1674 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1675 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1676 | */ | |
1677 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1678 | reg_03.raw != reg_01.raw) { | |
1679 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1680 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1681 | } |
1682 | ||
1683 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1684 | ||
d83e94ac | 1685 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
3235dc3f | 1686 | " Stat Dmod Deli Vect:\n"); |
1da177e4 LT |
1687 | |
1688 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1689 | struct IO_APIC_route_entry entry; | |
1690 | ||
cf4c6a2f | 1691 | entry = ioapic_read_entry(apic, i); |
1da177e4 | 1692 | |
54168ed7 IM |
1693 | printk(KERN_DEBUG " %02x %03X ", |
1694 | i, | |
1695 | entry.dest | |
1696 | ); | |
1da177e4 LT |
1697 | |
1698 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1699 | entry.mask, | |
1700 | entry.trigger, | |
1701 | entry.irr, | |
1702 | entry.polarity, | |
1703 | entry.delivery_status, | |
1704 | entry.dest_mode, | |
1705 | entry.delivery_mode, | |
1706 | entry.vector | |
1707 | ); | |
1708 | } | |
1709 | } | |
1da177e4 | 1710 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
0b8f1efa YL |
1711 | for_each_irq_desc(irq, desc) { |
1712 | struct irq_pin_list *entry; | |
1713 | ||
d4eba297 | 1714 | cfg = get_irq_desc_chip_data(desc); |
05e40760 DK |
1715 | if (!cfg) |
1716 | continue; | |
0b8f1efa | 1717 | entry = cfg->irq_2_pin; |
0f978f45 | 1718 | if (!entry) |
1da177e4 | 1719 | continue; |
8f09cd20 | 1720 | printk(KERN_DEBUG "IRQ%d ", irq); |
2977fb3f | 1721 | for_each_irq_pin(entry, cfg->irq_2_pin) |
1da177e4 | 1722 | printk("-> %d:%d", entry->apic, entry->pin); |
1da177e4 LT |
1723 | printk("\n"); |
1724 | } | |
1725 | ||
1726 | printk(KERN_INFO ".................................... done.\n"); | |
1727 | ||
1728 | return; | |
1729 | } | |
1730 | ||
251e1e44 | 1731 | __apicdebuginit(void) print_APIC_field(int base) |
1da177e4 | 1732 | { |
251e1e44 | 1733 | int i; |
1da177e4 | 1734 | |
251e1e44 IM |
1735 | printk(KERN_DEBUG); |
1736 | ||
1737 | for (i = 0; i < 8; i++) | |
1738 | printk(KERN_CONT "%08x", apic_read(base + i*0x10)); | |
1739 | ||
1740 | printk(KERN_CONT "\n"); | |
1da177e4 LT |
1741 | } |
1742 | ||
32f71aff | 1743 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 | 1744 | { |
97a52714 | 1745 | unsigned int i, v, ver, maxlvt; |
7ab6af7a | 1746 | u64 icr; |
1da177e4 | 1747 | |
251e1e44 | 1748 | printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", |
1da177e4 | 1749 | smp_processor_id(), hard_smp_processor_id()); |
66823114 | 1750 | v = apic_read(APIC_ID); |
54168ed7 | 1751 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1752 | v = apic_read(APIC_LVR); |
1753 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1754 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1755 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1756 | |
1757 | v = apic_read(APIC_TASKPRI); | |
1758 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1759 | ||
54168ed7 | 1760 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1761 | if (!APIC_XAPIC(ver)) { |
1762 | v = apic_read(APIC_ARBPRI); | |
1763 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1764 | v & APIC_ARBPRI_MASK); | |
1765 | } | |
1da177e4 LT |
1766 | v = apic_read(APIC_PROCPRI); |
1767 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1768 | } | |
1769 | ||
a11b5abe YL |
1770 | /* |
1771 | * Remote read supported only in the 82489DX and local APIC for | |
1772 | * Pentium processors. | |
1773 | */ | |
1774 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1775 | v = apic_read(APIC_RRR); | |
1776 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1777 | } | |
1778 | ||
1da177e4 LT |
1779 | v = apic_read(APIC_LDR); |
1780 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1781 | if (!x2apic_enabled()) { |
1782 | v = apic_read(APIC_DFR); | |
1783 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1784 | } | |
1da177e4 LT |
1785 | v = apic_read(APIC_SPIV); |
1786 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1787 | ||
1788 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
251e1e44 | 1789 | print_APIC_field(APIC_ISR); |
1da177e4 | 1790 | printk(KERN_DEBUG "... APIC TMR field:\n"); |
251e1e44 | 1791 | print_APIC_field(APIC_TMR); |
1da177e4 | 1792 | printk(KERN_DEBUG "... APIC IRR field:\n"); |
251e1e44 | 1793 | print_APIC_field(APIC_IRR); |
1da177e4 | 1794 | |
54168ed7 IM |
1795 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1796 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1797 | apic_write(APIC_ESR, 0); |
54168ed7 | 1798 | |
1da177e4 LT |
1799 | v = apic_read(APIC_ESR); |
1800 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1801 | } | |
1802 | ||
7ab6af7a | 1803 | icr = apic_icr_read(); |
0c425cec IM |
1804 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1805 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1806 | |
1807 | v = apic_read(APIC_LVTT); | |
1808 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1809 | ||
1810 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1811 | v = apic_read(APIC_LVTPC); | |
1812 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1813 | } | |
1814 | v = apic_read(APIC_LVT0); | |
1815 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1816 | v = apic_read(APIC_LVT1); | |
1817 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1818 | ||
1819 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1820 | v = apic_read(APIC_LVTERR); | |
1821 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1822 | } | |
1823 | ||
1824 | v = apic_read(APIC_TMICT); | |
1825 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1826 | v = apic_read(APIC_TMCCT); | |
1827 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1828 | v = apic_read(APIC_TDCR); | |
1829 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
97a52714 AH |
1830 | |
1831 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
1832 | v = apic_read(APIC_EFEAT); | |
1833 | maxlvt = (v >> 16) & 0xff; | |
1834 | printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v); | |
1835 | v = apic_read(APIC_ECTRL); | |
1836 | printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v); | |
1837 | for (i = 0; i < maxlvt; i++) { | |
1838 | v = apic_read(APIC_EILVTn(i)); | |
1839 | printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v); | |
1840 | } | |
1841 | } | |
1da177e4 LT |
1842 | printk("\n"); |
1843 | } | |
1844 | ||
2626eb2b | 1845 | __apicdebuginit(void) print_local_APICs(int maxcpu) |
1da177e4 | 1846 | { |
ffd5aae7 YL |
1847 | int cpu; |
1848 | ||
2626eb2b CG |
1849 | if (!maxcpu) |
1850 | return; | |
1851 | ||
ffd5aae7 | 1852 | preempt_disable(); |
2626eb2b CG |
1853 | for_each_online_cpu(cpu) { |
1854 | if (cpu >= maxcpu) | |
1855 | break; | |
ffd5aae7 | 1856 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); |
2626eb2b | 1857 | } |
ffd5aae7 | 1858 | preempt_enable(); |
1da177e4 LT |
1859 | } |
1860 | ||
32f71aff | 1861 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1862 | { |
1da177e4 LT |
1863 | unsigned int v; |
1864 | unsigned long flags; | |
1865 | ||
b81bb373 | 1866 | if (!legacy_pic->nr_legacy_irqs) |
1da177e4 LT |
1867 | return; |
1868 | ||
1869 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1870 | ||
5619c280 | 1871 | raw_spin_lock_irqsave(&i8259A_lock, flags); |
1da177e4 LT |
1872 | |
1873 | v = inb(0xa1) << 8 | inb(0x21); | |
1874 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1875 | ||
1876 | v = inb(0xa0) << 8 | inb(0x20); | |
1877 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1878 | ||
54168ed7 IM |
1879 | outb(0x0b,0xa0); |
1880 | outb(0x0b,0x20); | |
1da177e4 | 1881 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1882 | outb(0x0a,0xa0); |
1883 | outb(0x0a,0x20); | |
1da177e4 | 1884 | |
5619c280 | 1885 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); |
1da177e4 LT |
1886 | |
1887 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1888 | ||
1889 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1890 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1891 | } | |
1892 | ||
2626eb2b CG |
1893 | static int __initdata show_lapic = 1; |
1894 | static __init int setup_show_lapic(char *arg) | |
1895 | { | |
1896 | int num = -1; | |
1897 | ||
1898 | if (strcmp(arg, "all") == 0) { | |
1899 | show_lapic = CONFIG_NR_CPUS; | |
1900 | } else { | |
1901 | get_option(&arg, &num); | |
1902 | if (num >= 0) | |
1903 | show_lapic = num; | |
1904 | } | |
1905 | ||
1906 | return 1; | |
1907 | } | |
1908 | __setup("show_lapic=", setup_show_lapic); | |
1909 | ||
1910 | __apicdebuginit(int) print_ICs(void) | |
32f71aff | 1911 | { |
2626eb2b CG |
1912 | if (apic_verbosity == APIC_QUIET) |
1913 | return 0; | |
1914 | ||
32f71aff | 1915 | print_PIC(); |
4797f6b0 YL |
1916 | |
1917 | /* don't print out if apic is not there */ | |
8312136f | 1918 | if (!cpu_has_apic && !apic_from_smp_config()) |
4797f6b0 YL |
1919 | return 0; |
1920 | ||
2626eb2b | 1921 | print_local_APICs(show_lapic); |
32f71aff MR |
1922 | print_IO_APIC(); |
1923 | ||
1924 | return 0; | |
1925 | } | |
1926 | ||
2626eb2b | 1927 | fs_initcall(print_ICs); |
32f71aff | 1928 | |
1da177e4 | 1929 | |
efa2559f YL |
1930 | /* Where if anywhere is the i8259 connect in external int mode */ |
1931 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1932 | ||
54168ed7 | 1933 | void __init enable_IO_APIC(void) |
1da177e4 | 1934 | { |
fcfd636a | 1935 | int i8259_apic, i8259_pin; |
54168ed7 | 1936 | int apic; |
bc07844a | 1937 | |
b81bb373 | 1938 | if (!legacy_pic->nr_legacy_irqs) |
bc07844a TG |
1939 | return; |
1940 | ||
54168ed7 | 1941 | for(apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
1942 | int pin; |
1943 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 1944 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 1945 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1946 | entry = ioapic_read_entry(apic, pin); |
fcfd636a | 1947 | |
fcfd636a EB |
1948 | /* If the interrupt line is enabled and in ExtInt mode |
1949 | * I have found the pin where the i8259 is connected. | |
1950 | */ | |
1951 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1952 | ioapic_i8259.apic = apic; | |
1953 | ioapic_i8259.pin = pin; | |
1954 | goto found_i8259; | |
1955 | } | |
1956 | } | |
1957 | } | |
1958 | found_i8259: | |
1959 | /* Look to see what if the MP table has reported the ExtINT */ | |
1960 | /* If we could not find the appropriate pin by looking at the ioapic | |
1961 | * the i8259 probably is not connected the ioapic but give the | |
1962 | * mptable a chance anyway. | |
1963 | */ | |
1964 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1965 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1966 | /* Trust the MP table if nothing is setup in the hardware */ | |
1967 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1968 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1969 | ioapic_i8259.pin = i8259_pin; | |
1970 | ioapic_i8259.apic = i8259_apic; | |
1971 | } | |
1972 | /* Complain if the MP table and the hardware disagree */ | |
1973 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1974 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1975 | { | |
1976 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1977 | } |
1978 | ||
1979 | /* | |
1980 | * Do not trust the IO-APIC being empty at bootup | |
1981 | */ | |
1982 | clear_IO_APIC(); | |
1983 | } | |
1984 | ||
1985 | /* | |
1986 | * Not an __init, needed by the reboot code | |
1987 | */ | |
1988 | void disable_IO_APIC(void) | |
1989 | { | |
1990 | /* | |
1991 | * Clear the IO-APIC before rebooting: | |
1992 | */ | |
1993 | clear_IO_APIC(); | |
1994 | ||
b81bb373 | 1995 | if (!legacy_pic->nr_legacy_irqs) |
bc07844a TG |
1996 | return; |
1997 | ||
650927ef | 1998 | /* |
0b968d23 | 1999 | * If the i8259 is routed through an IOAPIC |
650927ef | 2000 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 2001 | * so legacy interrupts can be delivered. |
7c6d9f97 SS |
2002 | * |
2003 | * With interrupt-remapping, for now we will use virtual wire A mode, | |
2004 | * as virtual wire B is little complex (need to configure both | |
2005 | * IOAPIC RTE aswell as interrupt-remapping table entry). | |
2006 | * As this gets called during crash dump, keep this simple for now. | |
650927ef | 2007 | */ |
7c6d9f97 | 2008 | if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) { |
650927ef | 2009 | struct IO_APIC_route_entry entry; |
650927ef EB |
2010 | |
2011 | memset(&entry, 0, sizeof(entry)); | |
2012 | entry.mask = 0; /* Enabled */ | |
2013 | entry.trigger = 0; /* Edge */ | |
2014 | entry.irr = 0; | |
2015 | entry.polarity = 0; /* High */ | |
2016 | entry.delivery_status = 0; | |
2017 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 2018 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 2019 | entry.vector = 0; |
54168ed7 | 2020 | entry.dest = read_apic_id(); |
650927ef EB |
2021 | |
2022 | /* | |
2023 | * Add it to the IO-APIC irq-routing table: | |
2024 | */ | |
cf4c6a2f | 2025 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 2026 | } |
54168ed7 | 2027 | |
7c6d9f97 SS |
2028 | /* |
2029 | * Use virtual wire A mode when interrupt remapping is enabled. | |
2030 | */ | |
8312136f | 2031 | if (cpu_has_apic || apic_from_smp_config()) |
3f4c3955 CG |
2032 | disconnect_bsp_APIC(!intr_remapping_enabled && |
2033 | ioapic_i8259.pin != -1); | |
1da177e4 LT |
2034 | } |
2035 | ||
54168ed7 | 2036 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
2037 | /* |
2038 | * function to set the IO-APIC physical IDs based on the | |
2039 | * values stored in the MPC table. | |
2040 | * | |
2041 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
2042 | */ | |
2043 | ||
de934103 | 2044 | void __init setup_ioapic_ids_from_mpc(void) |
1da177e4 LT |
2045 | { |
2046 | union IO_APIC_reg_00 reg_00; | |
2047 | physid_mask_t phys_id_present_map; | |
c8d46cf0 | 2048 | int apic_id; |
1da177e4 LT |
2049 | int i; |
2050 | unsigned char old_id; | |
2051 | unsigned long flags; | |
2052 | ||
de934103 | 2053 | if (acpi_ioapic) |
d49c4288 | 2054 | return; |
ca05fea6 NP |
2055 | /* |
2056 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
2057 | * no meaning without the serial APIC bus. | |
2058 | */ | |
7c5c1e42 SL |
2059 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
2060 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 2061 | return; |
1da177e4 LT |
2062 | /* |
2063 | * This is broken; anything with a real cpu count has to | |
2064 | * circumvent this idiocy regardless. | |
2065 | */ | |
7abc0753 | 2066 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map); |
1da177e4 LT |
2067 | |
2068 | /* | |
2069 | * Set the IOAPIC ID to the value stored in the MPC table. | |
2070 | */ | |
c8d46cf0 | 2071 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) { |
1da177e4 LT |
2072 | |
2073 | /* Read the register 0 value */ | |
dade7716 | 2074 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2075 | reg_00.raw = io_apic_read(apic_id, 0); |
dade7716 | 2076 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 2077 | |
c8d46cf0 | 2078 | old_id = mp_ioapics[apic_id].apicid; |
1da177e4 | 2079 | |
c8d46cf0 | 2080 | if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) { |
1da177e4 | 2081 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
c8d46cf0 | 2082 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2083 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
2084 | reg_00.bits.ID); | |
c8d46cf0 | 2085 | mp_ioapics[apic_id].apicid = reg_00.bits.ID; |
1da177e4 LT |
2086 | } |
2087 | ||
1da177e4 LT |
2088 | /* |
2089 | * Sanity check, is the ID really free? Every APIC in a | |
2090 | * system must have a unique ID or we get lots of nice | |
2091 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
2092 | */ | |
7abc0753 | 2093 | if (apic->check_apicid_used(&phys_id_present_map, |
c8d46cf0 | 2094 | mp_ioapics[apic_id].apicid)) { |
1da177e4 | 2095 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
c8d46cf0 | 2096 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2097 | for (i = 0; i < get_physical_broadcast(); i++) |
2098 | if (!physid_isset(i, phys_id_present_map)) | |
2099 | break; | |
2100 | if (i >= get_physical_broadcast()) | |
2101 | panic("Max APIC ID exceeded!\n"); | |
2102 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
2103 | i); | |
2104 | physid_set(i, phys_id_present_map); | |
c8d46cf0 | 2105 | mp_ioapics[apic_id].apicid = i; |
1da177e4 LT |
2106 | } else { |
2107 | physid_mask_t tmp; | |
7abc0753 | 2108 | apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid, &tmp); |
1da177e4 LT |
2109 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
2110 | "phys_id_present_map\n", | |
c8d46cf0 | 2111 | mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2112 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
2113 | } | |
2114 | ||
2115 | ||
2116 | /* | |
2117 | * We need to adjust the IRQ routing table | |
2118 | * if the ID changed. | |
2119 | */ | |
c8d46cf0 | 2120 | if (old_id != mp_ioapics[apic_id].apicid) |
1da177e4 | 2121 | for (i = 0; i < mp_irq_entries; i++) |
c2c21745 JSR |
2122 | if (mp_irqs[i].dstapic == old_id) |
2123 | mp_irqs[i].dstapic | |
c8d46cf0 | 2124 | = mp_ioapics[apic_id].apicid; |
1da177e4 LT |
2125 | |
2126 | /* | |
2127 | * Read the right value from the MPC table and | |
2128 | * write it into the ID register. | |
36062448 | 2129 | */ |
1da177e4 LT |
2130 | apic_printk(APIC_VERBOSE, KERN_INFO |
2131 | "...changing IO-APIC physical APIC ID to %d ...", | |
c8d46cf0 | 2132 | mp_ioapics[apic_id].apicid); |
1da177e4 | 2133 | |
c8d46cf0 | 2134 | reg_00.bits.ID = mp_ioapics[apic_id].apicid; |
dade7716 | 2135 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2136 | io_apic_write(apic_id, 0, reg_00.raw); |
dade7716 | 2137 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2138 | |
2139 | /* | |
2140 | * Sanity check | |
2141 | */ | |
dade7716 | 2142 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2143 | reg_00.raw = io_apic_read(apic_id, 0); |
dade7716 | 2144 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
c8d46cf0 | 2145 | if (reg_00.bits.ID != mp_ioapics[apic_id].apicid) |
1da177e4 LT |
2146 | printk("could not set ID!\n"); |
2147 | else | |
2148 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
2149 | } | |
2150 | } | |
54168ed7 | 2151 | #endif |
1da177e4 | 2152 | |
7ce0bcfd | 2153 | int no_timer_check __initdata; |
8542b200 ZA |
2154 | |
2155 | static int __init notimercheck(char *s) | |
2156 | { | |
2157 | no_timer_check = 1; | |
2158 | return 1; | |
2159 | } | |
2160 | __setup("no_timer_check", notimercheck); | |
2161 | ||
1da177e4 LT |
2162 | /* |
2163 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2164 | * about the timer IRQ. We do the following to work around the situation: | |
2165 | * | |
2166 | * - timer IRQ defaults to IO-APIC IRQ | |
2167 | * - if this function detects that timer IRQs are defunct, then we fall | |
2168 | * back to ISA timer IRQs | |
2169 | */ | |
f0a7a5c9 | 2170 | static int __init timer_irq_works(void) |
1da177e4 LT |
2171 | { |
2172 | unsigned long t1 = jiffies; | |
4aae0702 | 2173 | unsigned long flags; |
1da177e4 | 2174 | |
8542b200 ZA |
2175 | if (no_timer_check) |
2176 | return 1; | |
2177 | ||
4aae0702 | 2178 | local_save_flags(flags); |
1da177e4 LT |
2179 | local_irq_enable(); |
2180 | /* Let ten ticks pass... */ | |
2181 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2182 | local_irq_restore(flags); |
1da177e4 LT |
2183 | |
2184 | /* | |
2185 | * Expect a few ticks at least, to be sure some possible | |
2186 | * glue logic does not lock up after one or two first | |
2187 | * ticks in a non-ExtINT mode. Also the local APIC | |
2188 | * might have cached one ExtINT interrupt. Finally, at | |
2189 | * least one tick may be lost due to delays. | |
2190 | */ | |
54168ed7 IM |
2191 | |
2192 | /* jiffies wrap? */ | |
1d16b53e | 2193 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2194 | return 1; |
1da177e4 LT |
2195 | return 0; |
2196 | } | |
2197 | ||
2198 | /* | |
2199 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2200 | * number of pending IRQ events unhandled. These cases are very rare, | |
2201 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2202 | * better to do it this way as thus we do not have to be aware of | |
2203 | * 'pending' interrupts in the IRQ path, except at this point. | |
2204 | */ | |
2205 | /* | |
2206 | * Edge triggered needs to resend any interrupt | |
2207 | * that was delayed but this is now handled in the device | |
2208 | * independent code. | |
2209 | */ | |
2210 | ||
2211 | /* | |
2212 | * Starting up a edge-triggered IO-APIC interrupt is | |
2213 | * nasty - we need to make sure that we get the edge. | |
2214 | * If it is already asserted for some reason, we need | |
2215 | * return 1 to indicate that is was pending. | |
2216 | * | |
2217 | * This is not complete - we should be able to fake | |
2218 | * an edge even if it isn't on the 8259A... | |
2219 | */ | |
54168ed7 | 2220 | |
f5b9ed7a | 2221 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
2222 | { |
2223 | int was_pending = 0; | |
2224 | unsigned long flags; | |
0b8f1efa | 2225 | struct irq_cfg *cfg; |
1da177e4 | 2226 | |
dade7716 | 2227 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
b81bb373 | 2228 | if (irq < legacy_pic->nr_legacy_irqs) { |
4305df94 | 2229 | legacy_pic->mask(irq); |
b81bb373 | 2230 | if (legacy_pic->irq_pending(irq)) |
1da177e4 LT |
2231 | was_pending = 1; |
2232 | } | |
0b8f1efa | 2233 | cfg = irq_cfg(irq); |
dd5f15e5 | 2234 | __unmask_ioapic(cfg); |
dade7716 | 2235 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2236 | |
2237 | return was_pending; | |
2238 | } | |
2239 | ||
ace80ab7 | 2240 | static int ioapic_retrigger_irq(unsigned int irq) |
1da177e4 | 2241 | { |
54168ed7 IM |
2242 | |
2243 | struct irq_cfg *cfg = irq_cfg(irq); | |
2244 | unsigned long flags; | |
2245 | ||
dade7716 | 2246 | raw_spin_lock_irqsave(&vector_lock, flags); |
dac5f412 | 2247 | apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector); |
dade7716 | 2248 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
c0ad90a3 IM |
2249 | |
2250 | return 1; | |
2251 | } | |
497c9a19 | 2252 | |
54168ed7 IM |
2253 | /* |
2254 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2255 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2256 | * handled with the level-triggered descriptor, but that one has slightly | |
2257 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2258 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2259 | * races. | |
2260 | */ | |
497c9a19 | 2261 | |
54168ed7 | 2262 | #ifdef CONFIG_SMP |
9338ad6f | 2263 | void send_cleanup_vector(struct irq_cfg *cfg) |
e85abf8f GH |
2264 | { |
2265 | cpumask_var_t cleanup_mask; | |
2266 | ||
2267 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
2268 | unsigned int i; | |
e85abf8f GH |
2269 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) |
2270 | apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); | |
2271 | } else { | |
2272 | cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); | |
e85abf8f GH |
2273 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); |
2274 | free_cpumask_var(cleanup_mask); | |
2275 | } | |
2276 | cfg->move_in_progress = 0; | |
2277 | } | |
2278 | ||
4420471f | 2279 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
e85abf8f GH |
2280 | { |
2281 | int apic, pin; | |
2282 | struct irq_pin_list *entry; | |
2283 | u8 vector = cfg->vector; | |
2284 | ||
2977fb3f | 2285 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
e85abf8f GH |
2286 | unsigned int reg; |
2287 | ||
e85abf8f GH |
2288 | apic = entry->apic; |
2289 | pin = entry->pin; | |
2290 | /* | |
2291 | * With interrupt-remapping, destination information comes | |
2292 | * from interrupt-remapping table entry. | |
2293 | */ | |
2294 | if (!irq_remapped(irq)) | |
2295 | io_apic_write(apic, 0x11 + pin*2, dest); | |
2296 | reg = io_apic_read(apic, 0x10 + pin*2); | |
2297 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
2298 | reg |= vector; | |
2299 | io_apic_modify(apic, 0x10 + pin*2, reg); | |
e85abf8f GH |
2300 | } |
2301 | } | |
2302 | ||
2303 | /* | |
2304 | * Either sets desc->affinity to a valid value, and returns | |
18374d89 | 2305 | * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and |
e85abf8f GH |
2306 | * leaves desc->affinity untouched. |
2307 | */ | |
9338ad6f | 2308 | unsigned int |
18374d89 SS |
2309 | set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask, |
2310 | unsigned int *dest_id) | |
e85abf8f GH |
2311 | { |
2312 | struct irq_cfg *cfg; | |
2313 | unsigned int irq; | |
2314 | ||
2315 | if (!cpumask_intersects(mask, cpu_online_mask)) | |
18374d89 | 2316 | return -1; |
e85abf8f GH |
2317 | |
2318 | irq = desc->irq; | |
d4eba297 | 2319 | cfg = get_irq_desc_chip_data(desc); |
e85abf8f | 2320 | if (assign_irq_vector(irq, cfg, mask)) |
18374d89 | 2321 | return -1; |
e85abf8f | 2322 | |
e85abf8f GH |
2323 | cpumask_copy(desc->affinity, mask); |
2324 | ||
18374d89 SS |
2325 | *dest_id = apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain); |
2326 | return 0; | |
e85abf8f GH |
2327 | } |
2328 | ||
4420471f | 2329 | static int |
e85abf8f GH |
2330 | set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask) |
2331 | { | |
2332 | struct irq_cfg *cfg; | |
2333 | unsigned long flags; | |
2334 | unsigned int dest; | |
2335 | unsigned int irq; | |
4420471f | 2336 | int ret = -1; |
e85abf8f GH |
2337 | |
2338 | irq = desc->irq; | |
d4eba297 | 2339 | cfg = get_irq_desc_chip_data(desc); |
e85abf8f | 2340 | |
dade7716 | 2341 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
18374d89 SS |
2342 | ret = set_desc_affinity(desc, mask, &dest); |
2343 | if (!ret) { | |
e85abf8f GH |
2344 | /* Only the high 8 bits are valid. */ |
2345 | dest = SET_APIC_LOGICAL_ID(dest); | |
2346 | __target_IO_APIC_irq(irq, dest, cfg); | |
2347 | } | |
dade7716 | 2348 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
4420471f IM |
2349 | |
2350 | return ret; | |
e85abf8f GH |
2351 | } |
2352 | ||
4420471f | 2353 | static int |
e85abf8f GH |
2354 | set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask) |
2355 | { | |
2356 | struct irq_desc *desc; | |
2357 | ||
2358 | desc = irq_to_desc(irq); | |
2359 | ||
4420471f | 2360 | return set_ioapic_affinity_irq_desc(desc, mask); |
e85abf8f | 2361 | } |
497c9a19 | 2362 | |
54168ed7 | 2363 | #ifdef CONFIG_INTR_REMAP |
497c9a19 | 2364 | |
54168ed7 IM |
2365 | /* |
2366 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
2367 | * | |
0280f7c4 SS |
2368 | * For both level and edge triggered, irq migration is a simple atomic |
2369 | * update(of vector and cpu destination) of IRTE and flush the hardware cache. | |
54168ed7 | 2370 | * |
0280f7c4 SS |
2371 | * For level triggered, we eliminate the io-apic RTE modification (with the |
2372 | * updated vector information), by using a virtual vector (io-apic pin number). | |
2373 | * Real vector that is used for interrupting cpu will be coming from | |
2374 | * the interrupt-remapping table entry. | |
54168ed7 | 2375 | */ |
d5dedd45 | 2376 | static int |
e7986739 | 2377 | migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask) |
497c9a19 | 2378 | { |
54168ed7 | 2379 | struct irq_cfg *cfg; |
54168ed7 | 2380 | struct irte irte; |
54168ed7 | 2381 | unsigned int dest; |
3145e941 | 2382 | unsigned int irq; |
d5dedd45 | 2383 | int ret = -1; |
497c9a19 | 2384 | |
22f65d31 | 2385 | if (!cpumask_intersects(mask, cpu_online_mask)) |
d5dedd45 | 2386 | return ret; |
497c9a19 | 2387 | |
3145e941 | 2388 | irq = desc->irq; |
54168ed7 | 2389 | if (get_irte(irq, &irte)) |
d5dedd45 | 2390 | return ret; |
497c9a19 | 2391 | |
d4eba297 | 2392 | cfg = get_irq_desc_chip_data(desc); |
3145e941 | 2393 | if (assign_irq_vector(irq, cfg, mask)) |
d5dedd45 | 2394 | return ret; |
54168ed7 | 2395 | |
debccb3e | 2396 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask); |
54168ed7 | 2397 | |
54168ed7 IM |
2398 | irte.vector = cfg->vector; |
2399 | irte.dest_id = IRTE_DEST(dest); | |
2400 | ||
2401 | /* | |
2402 | * Modified the IRTE and flushes the Interrupt entry cache. | |
2403 | */ | |
2404 | modify_irte(irq, &irte); | |
2405 | ||
22f65d31 MT |
2406 | if (cfg->move_in_progress) |
2407 | send_cleanup_vector(cfg); | |
54168ed7 | 2408 | |
7f7ace0c | 2409 | cpumask_copy(desc->affinity, mask); |
d5dedd45 YL |
2410 | |
2411 | return 0; | |
54168ed7 IM |
2412 | } |
2413 | ||
54168ed7 IM |
2414 | /* |
2415 | * Migrates the IRQ destination in the process context. | |
2416 | */ | |
d5dedd45 | 2417 | static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
968ea6d8 | 2418 | const struct cpumask *mask) |
54168ed7 | 2419 | { |
d5dedd45 | 2420 | return migrate_ioapic_irq_desc(desc, mask); |
3145e941 | 2421 | } |
d5dedd45 | 2422 | static int set_ir_ioapic_affinity_irq(unsigned int irq, |
968ea6d8 | 2423 | const struct cpumask *mask) |
3145e941 YL |
2424 | { |
2425 | struct irq_desc *desc = irq_to_desc(irq); | |
2426 | ||
d5dedd45 | 2427 | return set_ir_ioapic_affinity_irq_desc(desc, mask); |
54168ed7 | 2428 | } |
29b61be6 | 2429 | #else |
d5dedd45 | 2430 | static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
29b61be6 SS |
2431 | const struct cpumask *mask) |
2432 | { | |
d5dedd45 | 2433 | return 0; |
29b61be6 | 2434 | } |
54168ed7 IM |
2435 | #endif |
2436 | ||
2437 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | |
2438 | { | |
2439 | unsigned vector, me; | |
8f2466f4 | 2440 | |
54168ed7 | 2441 | ack_APIC_irq(); |
54168ed7 | 2442 | exit_idle(); |
54168ed7 IM |
2443 | irq_enter(); |
2444 | ||
2445 | me = smp_processor_id(); | |
2446 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
2447 | unsigned int irq; | |
68a8ca59 | 2448 | unsigned int irr; |
54168ed7 IM |
2449 | struct irq_desc *desc; |
2450 | struct irq_cfg *cfg; | |
2451 | irq = __get_cpu_var(vector_irq)[vector]; | |
2452 | ||
0b8f1efa YL |
2453 | if (irq == -1) |
2454 | continue; | |
2455 | ||
54168ed7 IM |
2456 | desc = irq_to_desc(irq); |
2457 | if (!desc) | |
2458 | continue; | |
2459 | ||
2460 | cfg = irq_cfg(irq); | |
239007b8 | 2461 | raw_spin_lock(&desc->lock); |
54168ed7 | 2462 | |
7f41c2e1 SS |
2463 | /* |
2464 | * Check if the irq migration is in progress. If so, we | |
2465 | * haven't received the cleanup request yet for this irq. | |
2466 | */ | |
2467 | if (cfg->move_in_progress) | |
2468 | goto unlock; | |
2469 | ||
22f65d31 | 2470 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
54168ed7 IM |
2471 | goto unlock; |
2472 | ||
68a8ca59 SS |
2473 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
2474 | /* | |
2475 | * Check if the vector that needs to be cleanedup is | |
2476 | * registered at the cpu's IRR. If so, then this is not | |
2477 | * the best time to clean it up. Lets clean it up in the | |
2478 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
2479 | * to myself. | |
2480 | */ | |
2481 | if (irr & (1 << (vector % 32))) { | |
2482 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
2483 | goto unlock; | |
2484 | } | |
54168ed7 | 2485 | __get_cpu_var(vector_irq)[vector] = -1; |
54168ed7 | 2486 | unlock: |
239007b8 | 2487 | raw_spin_unlock(&desc->lock); |
54168ed7 IM |
2488 | } |
2489 | ||
2490 | irq_exit(); | |
2491 | } | |
2492 | ||
dd5f15e5 | 2493 | static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) |
54168ed7 | 2494 | { |
a5e74b84 | 2495 | unsigned me; |
54168ed7 | 2496 | |
fcef5911 | 2497 | if (likely(!cfg->move_in_progress)) |
54168ed7 IM |
2498 | return; |
2499 | ||
54168ed7 | 2500 | me = smp_processor_id(); |
10b888d6 | 2501 | |
fcef5911 | 2502 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
22f65d31 | 2503 | send_cleanup_vector(cfg); |
497c9a19 | 2504 | } |
a5e74b84 | 2505 | |
dd5f15e5 | 2506 | static void irq_complete_move(struct irq_cfg *cfg) |
a5e74b84 | 2507 | { |
dd5f15e5 | 2508 | __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); |
a5e74b84 SS |
2509 | } |
2510 | ||
2511 | void irq_force_complete_move(int irq) | |
2512 | { | |
dd5f15e5 | 2513 | struct irq_cfg *cfg = get_irq_chip_data(irq); |
a5e74b84 | 2514 | |
bbd391a1 PB |
2515 | if (!cfg) |
2516 | return; | |
2517 | ||
dd5f15e5 | 2518 | __irq_complete_move(cfg, cfg->vector); |
a5e74b84 | 2519 | } |
497c9a19 | 2520 | #else |
dd5f15e5 | 2521 | static inline void irq_complete_move(struct irq_cfg *cfg) { } |
497c9a19 | 2522 | #endif |
3145e941 | 2523 | |
1d025192 YL |
2524 | static void ack_apic_edge(unsigned int irq) |
2525 | { | |
dd5f15e5 | 2526 | struct irq_cfg *cfg = get_irq_chip_data(irq); |
3145e941 | 2527 | |
dd5f15e5 | 2528 | irq_complete_move(cfg); |
1d025192 YL |
2529 | move_native_irq(irq); |
2530 | ack_APIC_irq(); | |
2531 | } | |
2532 | ||
3eb2cce8 | 2533 | atomic_t irq_mis_count; |
3eb2cce8 | 2534 | |
c29d9db3 SS |
2535 | /* |
2536 | * IO-APIC versions below 0x20 don't support EOI register. | |
2537 | * For the record, here is the information about various versions: | |
2538 | * 0Xh 82489DX | |
2539 | * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant | |
2540 | * 2Xh I/O(x)APIC which is PCI 2.2 Compliant | |
2541 | * 30h-FFh Reserved | |
2542 | * | |
2543 | * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic | |
2544 | * version as 0x2. This is an error with documentation and these ICH chips | |
2545 | * use io-apic's of version 0x20. | |
2546 | * | |
2547 | * For IO-APIC's with EOI register, we use that to do an explicit EOI. | |
2548 | * Otherwise, we simulate the EOI message manually by changing the trigger | |
2549 | * mode to edge and then back to level, with RTE being masked during this. | |
2550 | */ | |
dd5f15e5 | 2551 | static void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg) |
b3ec0a37 SS |
2552 | { |
2553 | struct irq_pin_list *entry; | |
dd5f15e5 | 2554 | unsigned long flags; |
b3ec0a37 | 2555 | |
dd5f15e5 | 2556 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
b3ec0a37 | 2557 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
c29d9db3 SS |
2558 | if (mp_ioapics[entry->apic].apicver >= 0x20) { |
2559 | /* | |
2560 | * Intr-remapping uses pin number as the virtual vector | |
2561 | * in the RTE. Actual vector is programmed in | |
2562 | * intr-remapping table entry. Hence for the io-apic | |
2563 | * EOI we use the pin number. | |
2564 | */ | |
2565 | if (irq_remapped(irq)) | |
2566 | io_apic_eoi(entry->apic, entry->pin); | |
2567 | else | |
2568 | io_apic_eoi(entry->apic, cfg->vector); | |
2569 | } else { | |
2570 | __mask_and_edge_IO_APIC_irq(entry); | |
2571 | __unmask_and_level_IO_APIC_irq(entry); | |
2572 | } | |
b3ec0a37 | 2573 | } |
dade7716 | 2574 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
b3ec0a37 SS |
2575 | } |
2576 | ||
047c8fdb YL |
2577 | static void ack_apic_level(unsigned int irq) |
2578 | { | |
3145e941 | 2579 | struct irq_desc *desc = irq_to_desc(irq); |
dd5f15e5 TG |
2580 | struct irq_cfg *cfg = get_irq_desc_chip_data(desc); |
2581 | int i, do_unmask_irq = 0; | |
3eb2cce8 | 2582 | unsigned long v; |
047c8fdb | 2583 | |
dd5f15e5 | 2584 | irq_complete_move(cfg); |
047c8fdb | 2585 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
54168ed7 | 2586 | /* If we are moving the irq we need to mask it */ |
3145e941 | 2587 | if (unlikely(desc->status & IRQ_MOVE_PENDING)) { |
54168ed7 | 2588 | do_unmask_irq = 1; |
dd5f15e5 | 2589 | mask_ioapic(cfg); |
54168ed7 | 2590 | } |
047c8fdb YL |
2591 | #endif |
2592 | ||
3eb2cce8 | 2593 | /* |
916a0fe7 JF |
2594 | * It appears there is an erratum which affects at least version 0x11 |
2595 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2596 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2597 | * erroneously delivered as edge-triggered one but the respective IRR | |
2598 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2599 | * message but it will never arrive and further interrupts are blocked | |
2600 | * from the source. The exact reason is so far unknown, but the | |
2601 | * phenomenon was observed when two consecutive interrupt requests | |
2602 | * from a given source get delivered to the same CPU and the source is | |
2603 | * temporarily disabled in between. | |
2604 | * | |
2605 | * A workaround is to simulate an EOI message manually. We achieve it | |
2606 | * by setting the trigger mode to edge and then to level when the edge | |
2607 | * trigger mode gets detected in the TMR of a local APIC for a | |
2608 | * level-triggered interrupt. We mask the source for the time of the | |
2609 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2610 | * The idea is from Manfred Spraul. --macro | |
1c83995b SS |
2611 | * |
2612 | * Also in the case when cpu goes offline, fixup_irqs() will forward | |
2613 | * any unhandled interrupt on the offlined cpu to the new cpu | |
2614 | * destination that is handling the corresponding interrupt. This | |
2615 | * interrupt forwarding is done via IPI's. Hence, in this case also | |
2616 | * level-triggered io-apic interrupt will be seen as an edge | |
2617 | * interrupt in the IRR. And we can't rely on the cpu's EOI | |
2618 | * to be broadcasted to the IO-APIC's which will clear the remoteIRR | |
2619 | * corresponding to the level-triggered interrupt. Hence on IO-APIC's | |
2620 | * supporting EOI register, we do an explicit EOI to clear the | |
2621 | * remote IRR and on IO-APIC's which don't have an EOI register, | |
2622 | * we use the above logic (mask+edge followed by unmask+level) from | |
2623 | * Manfred Spraul to clear the remote IRR. | |
916a0fe7 | 2624 | */ |
3145e941 | 2625 | i = cfg->vector; |
3eb2cce8 | 2626 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); |
3eb2cce8 | 2627 | |
54168ed7 IM |
2628 | /* |
2629 | * We must acknowledge the irq before we move it or the acknowledge will | |
2630 | * not propagate properly. | |
2631 | */ | |
2632 | ack_APIC_irq(); | |
2633 | ||
1c83995b SS |
2634 | /* |
2635 | * Tail end of clearing remote IRR bit (either by delivering the EOI | |
2636 | * message via io-apic EOI register write or simulating it using | |
2637 | * mask+edge followed by unnask+level logic) manually when the | |
2638 | * level triggered interrupt is seen as the edge triggered interrupt | |
2639 | * at the cpu. | |
2640 | */ | |
ca64c47c MR |
2641 | if (!(v & (1 << (i & 0x1f)))) { |
2642 | atomic_inc(&irq_mis_count); | |
2643 | ||
dd5f15e5 | 2644 | eoi_ioapic_irq(irq, cfg); |
ca64c47c MR |
2645 | } |
2646 | ||
54168ed7 IM |
2647 | /* Now we can move and renable the irq */ |
2648 | if (unlikely(do_unmask_irq)) { | |
2649 | /* Only migrate the irq if the ack has been received. | |
2650 | * | |
2651 | * On rare occasions the broadcast level triggered ack gets | |
2652 | * delayed going to ioapics, and if we reprogram the | |
2653 | * vector while Remote IRR is still set the irq will never | |
2654 | * fire again. | |
2655 | * | |
2656 | * To prevent this scenario we read the Remote IRR bit | |
2657 | * of the ioapic. This has two effects. | |
2658 | * - On any sane system the read of the ioapic will | |
2659 | * flush writes (and acks) going to the ioapic from | |
2660 | * this cpu. | |
2661 | * - We get to see if the ACK has actually been delivered. | |
2662 | * | |
2663 | * Based on failed experiments of reprogramming the | |
2664 | * ioapic entry from outside of irq context starting | |
2665 | * with masking the ioapic entry and then polling until | |
2666 | * Remote IRR was clear before reprogramming the | |
2667 | * ioapic I don't trust the Remote IRR bit to be | |
2668 | * completey accurate. | |
2669 | * | |
2670 | * However there appears to be no other way to plug | |
2671 | * this race, so if the Remote IRR bit is not | |
2672 | * accurate and is causing problems then it is a hardware bug | |
2673 | * and you can go talk to the chipset vendor about it. | |
2674 | */ | |
3145e941 | 2675 | if (!io_apic_level_ack_pending(cfg)) |
54168ed7 | 2676 | move_masked_irq(irq); |
dd5f15e5 | 2677 | unmask_ioapic(cfg); |
54168ed7 | 2678 | } |
3eb2cce8 | 2679 | } |
1d025192 | 2680 | |
d0b03bd1 HW |
2681 | #ifdef CONFIG_INTR_REMAP |
2682 | static void ir_ack_apic_edge(unsigned int irq) | |
2683 | { | |
5d0ae2db | 2684 | ack_APIC_irq(); |
d0b03bd1 HW |
2685 | } |
2686 | ||
2687 | static void ir_ack_apic_level(unsigned int irq) | |
2688 | { | |
dd5f15e5 | 2689 | struct irq_cfg *cfg = get_irq_chip_data(irq); |
5d0ae2db WH |
2690 | |
2691 | ack_APIC_irq(); | |
dd5f15e5 | 2692 | eoi_ioapic_irq(irq, cfg); |
d0b03bd1 HW |
2693 | } |
2694 | #endif /* CONFIG_INTR_REMAP */ | |
2695 | ||
f5b9ed7a | 2696 | static struct irq_chip ioapic_chip __read_mostly = { |
d6c88a50 TG |
2697 | .name = "IO-APIC", |
2698 | .startup = startup_ioapic_irq, | |
dd5f15e5 TG |
2699 | .mask = mask_ioapic_irq, |
2700 | .unmask = unmask_ioapic_irq, | |
d6c88a50 TG |
2701 | .ack = ack_apic_edge, |
2702 | .eoi = ack_apic_level, | |
54d5d424 | 2703 | #ifdef CONFIG_SMP |
d6c88a50 | 2704 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 2705 | #endif |
ace80ab7 | 2706 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2707 | }; |
2708 | ||
54168ed7 | 2709 | static struct irq_chip ir_ioapic_chip __read_mostly = { |
d6c88a50 TG |
2710 | .name = "IR-IO-APIC", |
2711 | .startup = startup_ioapic_irq, | |
dd5f15e5 TG |
2712 | .mask = mask_ioapic_irq, |
2713 | .unmask = unmask_ioapic_irq, | |
a1e38ca5 | 2714 | #ifdef CONFIG_INTR_REMAP |
d0b03bd1 HW |
2715 | .ack = ir_ack_apic_edge, |
2716 | .eoi = ir_ack_apic_level, | |
54168ed7 | 2717 | #ifdef CONFIG_SMP |
d6c88a50 | 2718 | .set_affinity = set_ir_ioapic_affinity_irq, |
a1e38ca5 | 2719 | #endif |
54168ed7 IM |
2720 | #endif |
2721 | .retrigger = ioapic_retrigger_irq, | |
2722 | }; | |
1da177e4 LT |
2723 | |
2724 | static inline void init_IO_APIC_traps(void) | |
2725 | { | |
2726 | int irq; | |
08678b08 | 2727 | struct irq_desc *desc; |
da51a821 | 2728 | struct irq_cfg *cfg; |
1da177e4 LT |
2729 | |
2730 | /* | |
2731 | * NOTE! The local APIC isn't very good at handling | |
2732 | * multiple interrupts at the same interrupt level. | |
2733 | * As the interrupt level is determined by taking the | |
2734 | * vector number and shifting that right by 4, we | |
2735 | * want to spread these out a bit so that they don't | |
2736 | * all fall in the same interrupt level. | |
2737 | * | |
2738 | * Also, we've got to be careful not to trash gate | |
2739 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2740 | */ | |
0b8f1efa | 2741 | for_each_irq_desc(irq, desc) { |
d4eba297 | 2742 | cfg = get_irq_desc_chip_data(desc); |
0b8f1efa | 2743 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { |
1da177e4 LT |
2744 | /* |
2745 | * Hmm.. We don't have an entry for this, | |
2746 | * so default to an old-fashioned 8259 | |
2747 | * interrupt if we can.. | |
2748 | */ | |
b81bb373 JP |
2749 | if (irq < legacy_pic->nr_legacy_irqs) |
2750 | legacy_pic->make_irq(irq); | |
0b8f1efa | 2751 | else |
1da177e4 | 2752 | /* Strange. Oh, well.. */ |
08678b08 | 2753 | desc->chip = &no_irq_chip; |
1da177e4 LT |
2754 | } |
2755 | } | |
2756 | } | |
2757 | ||
f5b9ed7a IM |
2758 | /* |
2759 | * The local APIC irq-chip implementation: | |
2760 | */ | |
1da177e4 | 2761 | |
36062448 | 2762 | static void mask_lapic_irq(unsigned int irq) |
1da177e4 LT |
2763 | { |
2764 | unsigned long v; | |
2765 | ||
2766 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2767 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2768 | } |
2769 | ||
36062448 | 2770 | static void unmask_lapic_irq(unsigned int irq) |
1da177e4 | 2771 | { |
f5b9ed7a | 2772 | unsigned long v; |
1da177e4 | 2773 | |
f5b9ed7a | 2774 | v = apic_read(APIC_LVT0); |
593f4a78 | 2775 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2776 | } |
1da177e4 | 2777 | |
3145e941 | 2778 | static void ack_lapic_irq(unsigned int irq) |
1d025192 YL |
2779 | { |
2780 | ack_APIC_irq(); | |
2781 | } | |
2782 | ||
f5b9ed7a | 2783 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2784 | .name = "local-APIC", |
f5b9ed7a IM |
2785 | .mask = mask_lapic_irq, |
2786 | .unmask = unmask_lapic_irq, | |
c88ac1df | 2787 | .ack = ack_lapic_irq, |
1da177e4 LT |
2788 | }; |
2789 | ||
3145e941 | 2790 | static void lapic_register_intr(int irq, struct irq_desc *desc) |
c88ac1df | 2791 | { |
08678b08 | 2792 | desc->status &= ~IRQ_LEVEL; |
c88ac1df MR |
2793 | set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
2794 | "edge"); | |
c88ac1df MR |
2795 | } |
2796 | ||
e9427101 | 2797 | static void __init setup_nmi(void) |
1da177e4 LT |
2798 | { |
2799 | /* | |
36062448 | 2800 | * Dirty trick to enable the NMI watchdog ... |
1da177e4 LT |
2801 | * We put the 8259A master into AEOI mode and |
2802 | * unmask on all local APICs LVT0 as NMI. | |
2803 | * | |
2804 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2805 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2806 | * the NMI handler or the timer interrupt. | |
36062448 | 2807 | */ |
1da177e4 LT |
2808 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); |
2809 | ||
e9427101 | 2810 | enable_NMI_through_LVT0(); |
1da177e4 LT |
2811 | |
2812 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2813 | } | |
2814 | ||
2815 | /* | |
2816 | * This looks a bit hackish but it's about the only one way of sending | |
2817 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2818 | * not support the ExtINT mode, unfortunately. We need to send these | |
2819 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2820 | * 8259A interrupt line asserted until INTA. --macro | |
2821 | */ | |
28acf285 | 2822 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2823 | { |
fcfd636a | 2824 | int apic, pin, i; |
1da177e4 LT |
2825 | struct IO_APIC_route_entry entry0, entry1; |
2826 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2827 | |
fcfd636a | 2828 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2829 | if (pin == -1) { |
2830 | WARN_ON_ONCE(1); | |
2831 | return; | |
2832 | } | |
fcfd636a | 2833 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2834 | if (apic == -1) { |
2835 | WARN_ON_ONCE(1); | |
1da177e4 | 2836 | return; |
956fb531 | 2837 | } |
1da177e4 | 2838 | |
cf4c6a2f | 2839 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2840 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2841 | |
2842 | memset(&entry1, 0, sizeof(entry1)); | |
2843 | ||
2844 | entry1.dest_mode = 0; /* physical delivery */ | |
2845 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2846 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2847 | entry1.delivery_mode = dest_ExtINT; |
2848 | entry1.polarity = entry0.polarity; | |
2849 | entry1.trigger = 0; | |
2850 | entry1.vector = 0; | |
2851 | ||
cf4c6a2f | 2852 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2853 | |
2854 | save_control = CMOS_READ(RTC_CONTROL); | |
2855 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2856 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2857 | RTC_FREQ_SELECT); | |
2858 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2859 | ||
2860 | i = 100; | |
2861 | while (i-- > 0) { | |
2862 | mdelay(10); | |
2863 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2864 | i -= 10; | |
2865 | } | |
2866 | ||
2867 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2868 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2869 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2870 | |
cf4c6a2f | 2871 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2872 | } |
2873 | ||
efa2559f | 2874 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2875 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2876 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2877 | { |
2878 | disable_timer_pin_1 = 1; | |
2879 | return 0; | |
2880 | } | |
54168ed7 | 2881 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f YL |
2882 | |
2883 | int timer_through_8259 __initdata; | |
2884 | ||
1da177e4 LT |
2885 | /* |
2886 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2887 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2888 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2889 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2890 | * |
2891 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2892 | */ |
8542b200 | 2893 | static inline void __init check_timer(void) |
1da177e4 | 2894 | { |
3145e941 | 2895 | struct irq_desc *desc = irq_to_desc(0); |
d4eba297 | 2896 | struct irq_cfg *cfg = get_irq_desc_chip_data(desc); |
f6e9456c | 2897 | int node = cpu_to_node(0); |
fcfd636a | 2898 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2899 | unsigned long flags; |
047c8fdb | 2900 | int no_pin1 = 0; |
4aae0702 IM |
2901 | |
2902 | local_irq_save(flags); | |
d4d25dec | 2903 | |
1da177e4 LT |
2904 | /* |
2905 | * get/set the timer IRQ vector: | |
2906 | */ | |
4305df94 | 2907 | legacy_pic->mask(0); |
fe402e1f | 2908 | assign_irq_vector(0, cfg, apic->target_cpus()); |
1da177e4 LT |
2909 | |
2910 | /* | |
d11d5794 MR |
2911 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2912 | * wire has to be disabled in the local APIC. Also | |
2913 | * timer interrupts need to be acknowledged manually in | |
2914 | * the 8259A for the i82489DX when using the NMI | |
2915 | * watchdog as that APIC treats NMIs as level-triggered. | |
2916 | * The AEOI mode will finish them in the 8259A | |
2917 | * automatically. | |
1da177e4 | 2918 | */ |
593f4a78 | 2919 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
b81bb373 | 2920 | legacy_pic->init(1); |
54168ed7 | 2921 | #ifdef CONFIG_X86_32 |
f72dccac YL |
2922 | { |
2923 | unsigned int ver; | |
2924 | ||
2925 | ver = apic_read(APIC_LVR); | |
2926 | ver = GET_APIC_VERSION(ver); | |
2927 | timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); | |
2928 | } | |
54168ed7 | 2929 | #endif |
1da177e4 | 2930 | |
fcfd636a EB |
2931 | pin1 = find_isa_irq_pin(0, mp_INT); |
2932 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2933 | pin2 = ioapic_i8259.pin; | |
2934 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2935 | |
49a66a0b MR |
2936 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2937 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2938 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2939 | |
691874fa MR |
2940 | /* |
2941 | * Some BIOS writers are clueless and report the ExtINTA | |
2942 | * I/O APIC input from the cascaded 8259A as the timer | |
2943 | * interrupt input. So just in case, if only one pin | |
2944 | * was found above, try it both directly and through the | |
2945 | * 8259A. | |
2946 | */ | |
2947 | if (pin1 == -1) { | |
54168ed7 IM |
2948 | if (intr_remapping_enabled) |
2949 | panic("BIOS bug: timer not connected to IO-APIC"); | |
691874fa MR |
2950 | pin1 = pin2; |
2951 | apic1 = apic2; | |
2952 | no_pin1 = 1; | |
2953 | } else if (pin2 == -1) { | |
2954 | pin2 = pin1; | |
2955 | apic2 = apic1; | |
2956 | } | |
2957 | ||
1da177e4 LT |
2958 | if (pin1 != -1) { |
2959 | /* | |
2960 | * Ok, does IRQ0 through the IOAPIC work? | |
2961 | */ | |
691874fa | 2962 | if (no_pin1) { |
85ac16d0 | 2963 | add_pin_to_irq_node(cfg, node, apic1, pin1); |
497c9a19 | 2964 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
f72dccac YL |
2965 | } else { |
2966 | /* for edge trigger, setup_IO_APIC_irq already | |
2967 | * leave it unmasked. | |
2968 | * so only need to unmask if it is level-trigger | |
2969 | * do we really have level trigger timer? | |
2970 | */ | |
2971 | int idx; | |
2972 | idx = find_irq_entry(apic1, pin1, mp_INT); | |
2973 | if (idx != -1 && irq_trigger(idx)) | |
dd5f15e5 | 2974 | unmask_ioapic(cfg); |
691874fa | 2975 | } |
1da177e4 LT |
2976 | if (timer_irq_works()) { |
2977 | if (nmi_watchdog == NMI_IO_APIC) { | |
1da177e4 | 2978 | setup_nmi(); |
4305df94 | 2979 | legacy_pic->unmask(0); |
1da177e4 | 2980 | } |
66759a01 CE |
2981 | if (disable_timer_pin_1 > 0) |
2982 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2983 | goto out; |
1da177e4 | 2984 | } |
54168ed7 IM |
2985 | if (intr_remapping_enabled) |
2986 | panic("timer doesn't work through Interrupt-remapped IO-APIC"); | |
f72dccac | 2987 | local_irq_disable(); |
fcfd636a | 2988 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2989 | if (!no_pin1) |
49a66a0b MR |
2990 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2991 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2992 | |
49a66a0b MR |
2993 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2994 | "(IRQ0) through the 8259A ...\n"); | |
2995 | apic_printk(APIC_QUIET, KERN_INFO | |
2996 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2997 | /* |
2998 | * legacy devices should be connected to IO APIC #0 | |
2999 | */ | |
85ac16d0 | 3000 | replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2); |
497c9a19 | 3001 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
4305df94 | 3002 | legacy_pic->unmask(0); |
1da177e4 | 3003 | if (timer_irq_works()) { |
49a66a0b | 3004 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 3005 | timer_through_8259 = 1; |
1da177e4 | 3006 | if (nmi_watchdog == NMI_IO_APIC) { |
4305df94 | 3007 | legacy_pic->mask(0); |
1da177e4 | 3008 | setup_nmi(); |
4305df94 | 3009 | legacy_pic->unmask(0); |
1da177e4 | 3010 | } |
4aae0702 | 3011 | goto out; |
1da177e4 LT |
3012 | } |
3013 | /* | |
3014 | * Cleanup, just in case ... | |
3015 | */ | |
f72dccac | 3016 | local_irq_disable(); |
4305df94 | 3017 | legacy_pic->mask(0); |
fcfd636a | 3018 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 3019 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 3020 | } |
1da177e4 LT |
3021 | |
3022 | if (nmi_watchdog == NMI_IO_APIC) { | |
49a66a0b MR |
3023 | apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work " |
3024 | "through the IO-APIC - disabling NMI Watchdog!\n"); | |
067fa0ff | 3025 | nmi_watchdog = NMI_NONE; |
1da177e4 | 3026 | } |
54168ed7 | 3027 | #ifdef CONFIG_X86_32 |
d11d5794 | 3028 | timer_ack = 0; |
54168ed7 | 3029 | #endif |
1da177e4 | 3030 | |
49a66a0b MR |
3031 | apic_printk(APIC_QUIET, KERN_INFO |
3032 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 3033 | |
3145e941 | 3034 | lapic_register_intr(0, desc); |
497c9a19 | 3035 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
4305df94 | 3036 | legacy_pic->unmask(0); |
1da177e4 LT |
3037 | |
3038 | if (timer_irq_works()) { | |
49a66a0b | 3039 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 3040 | goto out; |
1da177e4 | 3041 | } |
f72dccac | 3042 | local_irq_disable(); |
4305df94 | 3043 | legacy_pic->mask(0); |
497c9a19 | 3044 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 3045 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 3046 | |
49a66a0b MR |
3047 | apic_printk(APIC_QUIET, KERN_INFO |
3048 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 3049 | |
b81bb373 JP |
3050 | legacy_pic->init(0); |
3051 | legacy_pic->make_irq(0); | |
593f4a78 | 3052 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
3053 | |
3054 | unlock_ExtINT_logic(); | |
3055 | ||
3056 | if (timer_irq_works()) { | |
49a66a0b | 3057 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 3058 | goto out; |
1da177e4 | 3059 | } |
f72dccac | 3060 | local_irq_disable(); |
49a66a0b | 3061 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
1da177e4 | 3062 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 3063 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
3064 | out: |
3065 | local_irq_restore(flags); | |
1da177e4 LT |
3066 | } |
3067 | ||
3068 | /* | |
af174783 MR |
3069 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
3070 | * to devices. However there may be an I/O APIC pin available for | |
3071 | * this interrupt regardless. The pin may be left unconnected, but | |
3072 | * typically it will be reused as an ExtINT cascade interrupt for | |
3073 | * the master 8259A. In the MPS case such a pin will normally be | |
3074 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
3075 | * there is no provision for ExtINT interrupts, and in the absence | |
3076 | * of an override it would be treated as an ordinary ISA I/O APIC | |
3077 | * interrupt, that is edge-triggered and unmasked by default. We | |
3078 | * used to do this, but it caused problems on some systems because | |
3079 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
3080 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
3081 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
3082 | * the I/O APIC in all cases now. No actual device should request | |
3083 | * it anyway. --macro | |
1da177e4 | 3084 | */ |
bc07844a | 3085 | #define PIC_IRQS (1UL << PIC_CASCADE_IR) |
1da177e4 LT |
3086 | |
3087 | void __init setup_IO_APIC(void) | |
3088 | { | |
54168ed7 | 3089 | |
54168ed7 IM |
3090 | /* |
3091 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
3092 | */ | |
b81bb373 | 3093 | io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL; |
1da177e4 | 3094 | |
54168ed7 | 3095 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
d6c88a50 | 3096 | /* |
54168ed7 IM |
3097 | * Set up IO-APIC IRQ routing. |
3098 | */ | |
de934103 TG |
3099 | x86_init.mpparse.setup_ioapic_ids(); |
3100 | ||
1da177e4 LT |
3101 | sync_Arb_IDs(); |
3102 | setup_IO_APIC_irqs(); | |
3103 | init_IO_APIC_traps(); | |
b81bb373 | 3104 | if (legacy_pic->nr_legacy_irqs) |
bc07844a | 3105 | check_timer(); |
1da177e4 LT |
3106 | } |
3107 | ||
3108 | /* | |
54168ed7 IM |
3109 | * Called after all the initialization is done. If we didnt find any |
3110 | * APIC bugs then we can allow the modify fast path | |
1da177e4 | 3111 | */ |
36062448 | 3112 | |
1da177e4 LT |
3113 | static int __init io_apic_bug_finalize(void) |
3114 | { | |
d6c88a50 TG |
3115 | if (sis_apic_bug == -1) |
3116 | sis_apic_bug = 0; | |
3117 | return 0; | |
1da177e4 LT |
3118 | } |
3119 | ||
3120 | late_initcall(io_apic_bug_finalize); | |
3121 | ||
3122 | struct sysfs_ioapic_data { | |
3123 | struct sys_device dev; | |
3124 | struct IO_APIC_route_entry entry[0]; | |
3125 | }; | |
54168ed7 | 3126 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; |
1da177e4 | 3127 | |
438510f6 | 3128 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
3129 | { |
3130 | struct IO_APIC_route_entry *entry; | |
3131 | struct sysfs_ioapic_data *data; | |
1da177e4 | 3132 | int i; |
36062448 | 3133 | |
1da177e4 LT |
3134 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3135 | entry = data->entry; | |
54168ed7 IM |
3136 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) |
3137 | *entry = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
3138 | |
3139 | return 0; | |
3140 | } | |
3141 | ||
3142 | static int ioapic_resume(struct sys_device *dev) | |
3143 | { | |
3144 | struct IO_APIC_route_entry *entry; | |
3145 | struct sysfs_ioapic_data *data; | |
3146 | unsigned long flags; | |
3147 | union IO_APIC_reg_00 reg_00; | |
3148 | int i; | |
36062448 | 3149 | |
1da177e4 LT |
3150 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3151 | entry = data->entry; | |
3152 | ||
dade7716 | 3153 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 3154 | reg_00.raw = io_apic_read(dev->id, 0); |
b5ba7e6d JSR |
3155 | if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) { |
3156 | reg_00.bits.ID = mp_ioapics[dev->id].apicid; | |
1da177e4 LT |
3157 | io_apic_write(dev->id, 0, reg_00.raw); |
3158 | } | |
dade7716 | 3159 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 3160 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 3161 | ioapic_write_entry(dev->id, i, entry[i]); |
1da177e4 LT |
3162 | |
3163 | return 0; | |
3164 | } | |
3165 | ||
3166 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 3167 | .name = "ioapic", |
1da177e4 LT |
3168 | .suspend = ioapic_suspend, |
3169 | .resume = ioapic_resume, | |
3170 | }; | |
3171 | ||
3172 | static int __init ioapic_init_sysfs(void) | |
3173 | { | |
54168ed7 IM |
3174 | struct sys_device * dev; |
3175 | int i, size, error; | |
1da177e4 LT |
3176 | |
3177 | error = sysdev_class_register(&ioapic_sysdev_class); | |
3178 | if (error) | |
3179 | return error; | |
3180 | ||
54168ed7 | 3181 | for (i = 0; i < nr_ioapics; i++ ) { |
36062448 | 3182 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] |
1da177e4 | 3183 | * sizeof(struct IO_APIC_route_entry); |
25556c16 | 3184 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
3185 | if (!mp_ioapic_data[i]) { |
3186 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3187 | continue; | |
3188 | } | |
1da177e4 | 3189 | dev = &mp_ioapic_data[i]->dev; |
36062448 | 3190 | dev->id = i; |
1da177e4 LT |
3191 | dev->cls = &ioapic_sysdev_class; |
3192 | error = sysdev_register(dev); | |
3193 | if (error) { | |
3194 | kfree(mp_ioapic_data[i]); | |
3195 | mp_ioapic_data[i] = NULL; | |
3196 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3197 | continue; | |
3198 | } | |
3199 | } | |
3200 | ||
3201 | return 0; | |
3202 | } | |
3203 | ||
3204 | device_initcall(ioapic_init_sysfs); | |
3205 | ||
3fc471ed | 3206 | /* |
95d77884 | 3207 | * Dynamic irq allocate and deallocation |
3fc471ed | 3208 | */ |
d047f53a | 3209 | unsigned int create_irq_nr(unsigned int irq_want, int node) |
3fc471ed | 3210 | { |
ace80ab7 | 3211 | /* Allocate an unused irq */ |
54168ed7 IM |
3212 | unsigned int irq; |
3213 | unsigned int new; | |
3fc471ed | 3214 | unsigned long flags; |
0b8f1efa | 3215 | struct irq_cfg *cfg_new = NULL; |
0b8f1efa | 3216 | struct irq_desc *desc_new = NULL; |
199751d7 YL |
3217 | |
3218 | irq = 0; | |
abcaa2b8 YL |
3219 | if (irq_want < nr_irqs_gsi) |
3220 | irq_want = nr_irqs_gsi; | |
3221 | ||
dade7716 | 3222 | raw_spin_lock_irqsave(&vector_lock, flags); |
9594949b | 3223 | for (new = irq_want; new < nr_irqs; new++) { |
85ac16d0 | 3224 | desc_new = irq_to_desc_alloc_node(new, node); |
0b8f1efa YL |
3225 | if (!desc_new) { |
3226 | printk(KERN_INFO "can not get irq_desc for %d\n", new); | |
ace80ab7 | 3227 | continue; |
0b8f1efa | 3228 | } |
d4eba297 | 3229 | cfg_new = get_irq_desc_chip_data(desc_new); |
0b8f1efa YL |
3230 | |
3231 | if (cfg_new->vector != 0) | |
ace80ab7 | 3232 | continue; |
d047f53a | 3233 | |
15e957d0 | 3234 | desc_new = move_irq_desc(desc_new, node); |
d4eba297 | 3235 | cfg_new = get_irq_desc_chip_data(desc_new); |
d047f53a | 3236 | |
fe402e1f | 3237 | if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0) |
ace80ab7 EB |
3238 | irq = new; |
3239 | break; | |
3240 | } | |
dade7716 | 3241 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
3fc471ed | 3242 | |
ced5b697 BP |
3243 | if (irq > 0) |
3244 | dynamic_irq_init_keep_chip_data(irq); | |
3fc471ed | 3245 | |
3fc471ed EB |
3246 | return irq; |
3247 | } | |
3248 | ||
199751d7 YL |
3249 | int create_irq(void) |
3250 | { | |
f6e9456c | 3251 | int node = cpu_to_node(0); |
be5d5350 | 3252 | unsigned int irq_want; |
54168ed7 IM |
3253 | int irq; |
3254 | ||
be5d5350 | 3255 | irq_want = nr_irqs_gsi; |
d047f53a | 3256 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3257 | |
3258 | if (irq == 0) | |
3259 | irq = -1; | |
3260 | ||
3261 | return irq; | |
199751d7 YL |
3262 | } |
3263 | ||
3fc471ed EB |
3264 | void destroy_irq(unsigned int irq) |
3265 | { | |
3266 | unsigned long flags; | |
3fc471ed | 3267 | |
ced5b697 | 3268 | dynamic_irq_cleanup_keep_chip_data(irq); |
3fc471ed | 3269 | |
54168ed7 | 3270 | free_irte(irq); |
dade7716 | 3271 | raw_spin_lock_irqsave(&vector_lock, flags); |
eb5b3794 | 3272 | __clear_irq_vector(irq, get_irq_chip_data(irq)); |
dade7716 | 3273 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
3fc471ed | 3274 | } |
3fc471ed | 3275 | |
2d3fcc1c | 3276 | /* |
27b46d76 | 3277 | * MSI message composition |
2d3fcc1c EB |
3278 | */ |
3279 | #ifdef CONFIG_PCI_MSI | |
c8bc6f3c SS |
3280 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, |
3281 | struct msi_msg *msg, u8 hpet_id) | |
2d3fcc1c | 3282 | { |
497c9a19 YL |
3283 | struct irq_cfg *cfg; |
3284 | int err; | |
2d3fcc1c EB |
3285 | unsigned dest; |
3286 | ||
f1182638 JB |
3287 | if (disable_apic) |
3288 | return -ENXIO; | |
3289 | ||
3145e941 | 3290 | cfg = irq_cfg(irq); |
fe402e1f | 3291 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
497c9a19 YL |
3292 | if (err) |
3293 | return err; | |
2d3fcc1c | 3294 | |
debccb3e | 3295 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 | 3296 | |
54168ed7 IM |
3297 | if (irq_remapped(irq)) { |
3298 | struct irte irte; | |
3299 | int ir_index; | |
3300 | u16 sub_handle; | |
3301 | ||
3302 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
3303 | BUG_ON(ir_index == -1); | |
3304 | ||
62a92f4c | 3305 | prepare_irte(&irte, cfg->vector, dest); |
54168ed7 | 3306 | |
f007e99c | 3307 | /* Set source-id of interrupt request */ |
c8bc6f3c SS |
3308 | if (pdev) |
3309 | set_msi_sid(&irte, pdev); | |
3310 | else | |
3311 | set_hpet_sid(&irte, hpet_id); | |
f007e99c | 3312 | |
54168ed7 IM |
3313 | modify_irte(irq, &irte); |
3314 | ||
3315 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3316 | msg->data = sub_handle; | |
3317 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
3318 | MSI_ADDR_IR_SHV | | |
3319 | MSI_ADDR_IR_INDEX1(ir_index) | | |
3320 | MSI_ADDR_IR_INDEX2(ir_index); | |
29b61be6 | 3321 | } else { |
9d783ba0 SS |
3322 | if (x2apic_enabled()) |
3323 | msg->address_hi = MSI_ADDR_BASE_HI | | |
3324 | MSI_ADDR_EXT_DEST_ID(dest); | |
3325 | else | |
3326 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3327 | ||
54168ed7 IM |
3328 | msg->address_lo = |
3329 | MSI_ADDR_BASE_LO | | |
9b5bc8dc | 3330 | ((apic->irq_dest_mode == 0) ? |
54168ed7 IM |
3331 | MSI_ADDR_DEST_MODE_PHYSICAL: |
3332 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
9b5bc8dc | 3333 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3334 | MSI_ADDR_REDIRECTION_CPU: |
3335 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
3336 | MSI_ADDR_DEST_ID(dest); | |
497c9a19 | 3337 | |
54168ed7 IM |
3338 | msg->data = |
3339 | MSI_DATA_TRIGGER_EDGE | | |
3340 | MSI_DATA_LEVEL_ASSERT | | |
9b5bc8dc | 3341 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3342 | MSI_DATA_DELIVERY_FIXED: |
3343 | MSI_DATA_DELIVERY_LOWPRI) | | |
3344 | MSI_DATA_VECTOR(cfg->vector); | |
3345 | } | |
497c9a19 | 3346 | return err; |
2d3fcc1c EB |
3347 | } |
3348 | ||
3b7d1921 | 3349 | #ifdef CONFIG_SMP |
d5dedd45 | 3350 | static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
2d3fcc1c | 3351 | { |
3145e941 | 3352 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3353 | struct irq_cfg *cfg; |
3b7d1921 EB |
3354 | struct msi_msg msg; |
3355 | unsigned int dest; | |
3b7d1921 | 3356 | |
18374d89 | 3357 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3358 | return -1; |
2d3fcc1c | 3359 | |
d4eba297 | 3360 | cfg = get_irq_desc_chip_data(desc); |
2d3fcc1c | 3361 | |
39431acb | 3362 | __get_cached_msi_msg(desc->irq_data.msi_desc, &msg); |
3b7d1921 EB |
3363 | |
3364 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3365 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3366 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3367 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3368 | ||
39431acb | 3369 | __write_msi_msg(desc->irq_data.msi_desc, &msg); |
d5dedd45 YL |
3370 | |
3371 | return 0; | |
2d3fcc1c | 3372 | } |
54168ed7 IM |
3373 | #ifdef CONFIG_INTR_REMAP |
3374 | /* | |
3375 | * Migrate the MSI irq to another cpumask. This migration is | |
3376 | * done in the process context using interrupt-remapping hardware. | |
3377 | */ | |
d5dedd45 | 3378 | static int |
e7986739 | 3379 | ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3380 | { |
3145e941 | 3381 | struct irq_desc *desc = irq_to_desc(irq); |
d4eba297 | 3382 | struct irq_cfg *cfg = get_irq_desc_chip_data(desc); |
54168ed7 | 3383 | unsigned int dest; |
54168ed7 | 3384 | struct irte irte; |
54168ed7 IM |
3385 | |
3386 | if (get_irte(irq, &irte)) | |
d5dedd45 | 3387 | return -1; |
54168ed7 | 3388 | |
18374d89 | 3389 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3390 | return -1; |
54168ed7 | 3391 | |
54168ed7 IM |
3392 | irte.vector = cfg->vector; |
3393 | irte.dest_id = IRTE_DEST(dest); | |
3394 | ||
3395 | /* | |
3396 | * atomically update the IRTE with the new destination and vector. | |
3397 | */ | |
3398 | modify_irte(irq, &irte); | |
3399 | ||
3400 | /* | |
3401 | * After this point, all the interrupts will start arriving | |
3402 | * at the new destination. So, time to cleanup the previous | |
3403 | * vector allocation. | |
3404 | */ | |
22f65d31 MT |
3405 | if (cfg->move_in_progress) |
3406 | send_cleanup_vector(cfg); | |
d5dedd45 YL |
3407 | |
3408 | return 0; | |
54168ed7 | 3409 | } |
3145e941 | 3410 | |
54168ed7 | 3411 | #endif |
3b7d1921 | 3412 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 3413 | |
3b7d1921 EB |
3414 | /* |
3415 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3416 | * which implement the MSI or MSI-X Capability Structure. | |
3417 | */ | |
3418 | static struct irq_chip msi_chip = { | |
3419 | .name = "PCI-MSI", | |
1c9db525 TG |
3420 | .irq_unmask = unmask_msi_irq, |
3421 | .irq_mask = mask_msi_irq, | |
1d025192 | 3422 | .ack = ack_apic_edge, |
3b7d1921 EB |
3423 | #ifdef CONFIG_SMP |
3424 | .set_affinity = set_msi_irq_affinity, | |
3425 | #endif | |
3426 | .retrigger = ioapic_retrigger_irq, | |
2d3fcc1c EB |
3427 | }; |
3428 | ||
54168ed7 IM |
3429 | static struct irq_chip msi_ir_chip = { |
3430 | .name = "IR-PCI-MSI", | |
1c9db525 TG |
3431 | .irq_unmask = unmask_msi_irq, |
3432 | .irq_mask = mask_msi_irq, | |
a1e38ca5 | 3433 | #ifdef CONFIG_INTR_REMAP |
d0b03bd1 | 3434 | .ack = ir_ack_apic_edge, |
54168ed7 IM |
3435 | #ifdef CONFIG_SMP |
3436 | .set_affinity = ir_set_msi_irq_affinity, | |
a1e38ca5 | 3437 | #endif |
54168ed7 IM |
3438 | #endif |
3439 | .retrigger = ioapic_retrigger_irq, | |
3440 | }; | |
3441 | ||
3442 | /* | |
3443 | * Map the PCI dev to the corresponding remapping hardware unit | |
3444 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
3445 | * in it. | |
3446 | */ | |
3447 | static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) | |
3448 | { | |
3449 | struct intel_iommu *iommu; | |
3450 | int index; | |
3451 | ||
3452 | iommu = map_dev_to_ir(dev); | |
3453 | if (!iommu) { | |
3454 | printk(KERN_ERR | |
3455 | "Unable to map PCI %s to iommu\n", pci_name(dev)); | |
3456 | return -ENOENT; | |
3457 | } | |
3458 | ||
3459 | index = alloc_irte(iommu, irq, nvec); | |
3460 | if (index < 0) { | |
3461 | printk(KERN_ERR | |
3462 | "Unable to allocate %d IRTE for PCI %s\n", nvec, | |
d6c88a50 | 3463 | pci_name(dev)); |
54168ed7 IM |
3464 | return -ENOSPC; |
3465 | } | |
3466 | return index; | |
3467 | } | |
1d025192 | 3468 | |
3145e941 | 3469 | static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq) |
1d025192 YL |
3470 | { |
3471 | int ret; | |
3472 | struct msi_msg msg; | |
3473 | ||
c8bc6f3c | 3474 | ret = msi_compose_msg(dev, irq, &msg, -1); |
1d025192 YL |
3475 | if (ret < 0) |
3476 | return ret; | |
3477 | ||
3145e941 | 3478 | set_irq_msi(irq, msidesc); |
1d025192 YL |
3479 | write_msi_msg(irq, &msg); |
3480 | ||
54168ed7 IM |
3481 | if (irq_remapped(irq)) { |
3482 | struct irq_desc *desc = irq_to_desc(irq); | |
3483 | /* | |
3484 | * irq migration in process context | |
3485 | */ | |
3486 | desc->status |= IRQ_MOVE_PCNTXT; | |
3487 | set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge"); | |
3488 | } else | |
54168ed7 | 3489 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge"); |
1d025192 | 3490 | |
c81bba49 YL |
3491 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
3492 | ||
1d025192 YL |
3493 | return 0; |
3494 | } | |
3495 | ||
047c8fdb YL |
3496 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
3497 | { | |
54168ed7 IM |
3498 | unsigned int irq; |
3499 | int ret, sub_handle; | |
0b8f1efa | 3500 | struct msi_desc *msidesc; |
54168ed7 | 3501 | unsigned int irq_want; |
1cc18521 | 3502 | struct intel_iommu *iommu = NULL; |
54168ed7 | 3503 | int index = 0; |
d047f53a | 3504 | int node; |
54168ed7 | 3505 | |
1c8d7b0a MW |
3506 | /* x86 doesn't support multiple MSI yet */ |
3507 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
3508 | return 1; | |
3509 | ||
d047f53a | 3510 | node = dev_to_node(&dev->dev); |
be5d5350 | 3511 | irq_want = nr_irqs_gsi; |
54168ed7 | 3512 | sub_handle = 0; |
0b8f1efa | 3513 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
d047f53a | 3514 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3515 | if (irq == 0) |
3516 | return -1; | |
f1ee5548 | 3517 | irq_want = irq + 1; |
54168ed7 IM |
3518 | if (!intr_remapping_enabled) |
3519 | goto no_ir; | |
3520 | ||
3521 | if (!sub_handle) { | |
3522 | /* | |
3523 | * allocate the consecutive block of IRTE's | |
3524 | * for 'nvec' | |
3525 | */ | |
3526 | index = msi_alloc_irte(dev, irq, nvec); | |
3527 | if (index < 0) { | |
3528 | ret = index; | |
3529 | goto error; | |
3530 | } | |
3531 | } else { | |
3532 | iommu = map_dev_to_ir(dev); | |
3533 | if (!iommu) { | |
3534 | ret = -ENOENT; | |
3535 | goto error; | |
3536 | } | |
3537 | /* | |
3538 | * setup the mapping between the irq and the IRTE | |
3539 | * base index, the sub_handle pointing to the | |
3540 | * appropriate interrupt remap table entry. | |
3541 | */ | |
3542 | set_irte_irq(irq, iommu, index, sub_handle); | |
3543 | } | |
3544 | no_ir: | |
0b8f1efa | 3545 | ret = setup_msi_irq(dev, msidesc, irq); |
54168ed7 IM |
3546 | if (ret < 0) |
3547 | goto error; | |
3548 | sub_handle++; | |
3549 | } | |
3550 | return 0; | |
047c8fdb YL |
3551 | |
3552 | error: | |
54168ed7 IM |
3553 | destroy_irq(irq); |
3554 | return ret; | |
047c8fdb YL |
3555 | } |
3556 | ||
3b7d1921 EB |
3557 | void arch_teardown_msi_irq(unsigned int irq) |
3558 | { | |
f7feaca7 | 3559 | destroy_irq(irq); |
3b7d1921 EB |
3560 | } |
3561 | ||
9d783ba0 | 3562 | #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP) |
54168ed7 | 3563 | #ifdef CONFIG_SMP |
d5dedd45 | 3564 | static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3565 | { |
3145e941 | 3566 | struct irq_desc *desc = irq_to_desc(irq); |
54168ed7 IM |
3567 | struct irq_cfg *cfg; |
3568 | struct msi_msg msg; | |
3569 | unsigned int dest; | |
54168ed7 | 3570 | |
18374d89 | 3571 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3572 | return -1; |
54168ed7 | 3573 | |
d4eba297 | 3574 | cfg = get_irq_desc_chip_data(desc); |
54168ed7 IM |
3575 | |
3576 | dmar_msi_read(irq, &msg); | |
3577 | ||
3578 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3579 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3580 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3581 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3582 | ||
3583 | dmar_msi_write(irq, &msg); | |
d5dedd45 YL |
3584 | |
3585 | return 0; | |
54168ed7 | 3586 | } |
3145e941 | 3587 | |
54168ed7 IM |
3588 | #endif /* CONFIG_SMP */ |
3589 | ||
8f7007aa | 3590 | static struct irq_chip dmar_msi_type = { |
54168ed7 IM |
3591 | .name = "DMAR_MSI", |
3592 | .unmask = dmar_msi_unmask, | |
3593 | .mask = dmar_msi_mask, | |
3594 | .ack = ack_apic_edge, | |
3595 | #ifdef CONFIG_SMP | |
3596 | .set_affinity = dmar_msi_set_affinity, | |
3597 | #endif | |
3598 | .retrigger = ioapic_retrigger_irq, | |
3599 | }; | |
3600 | ||
3601 | int arch_setup_dmar_msi(unsigned int irq) | |
3602 | { | |
3603 | int ret; | |
3604 | struct msi_msg msg; | |
2d3fcc1c | 3605 | |
c8bc6f3c | 3606 | ret = msi_compose_msg(NULL, irq, &msg, -1); |
54168ed7 IM |
3607 | if (ret < 0) |
3608 | return ret; | |
3609 | dmar_msi_write(irq, &msg); | |
3610 | set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, | |
3611 | "edge"); | |
3612 | return 0; | |
3613 | } | |
3614 | #endif | |
3615 | ||
58ac1e76 | 3616 | #ifdef CONFIG_HPET_TIMER |
3617 | ||
3618 | #ifdef CONFIG_SMP | |
d5dedd45 | 3619 | static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
58ac1e76 | 3620 | { |
3145e941 | 3621 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3622 | struct irq_cfg *cfg; |
58ac1e76 | 3623 | struct msi_msg msg; |
3624 | unsigned int dest; | |
58ac1e76 | 3625 | |
18374d89 | 3626 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3627 | return -1; |
58ac1e76 | 3628 | |
d4eba297 | 3629 | cfg = get_irq_desc_chip_data(desc); |
58ac1e76 | 3630 | |
3631 | hpet_msi_read(irq, &msg); | |
3632 | ||
3633 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3634 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3635 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3636 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3637 | ||
3638 | hpet_msi_write(irq, &msg); | |
d5dedd45 YL |
3639 | |
3640 | return 0; | |
58ac1e76 | 3641 | } |
3145e941 | 3642 | |
58ac1e76 | 3643 | #endif /* CONFIG_SMP */ |
3644 | ||
c8bc6f3c SS |
3645 | static struct irq_chip ir_hpet_msi_type = { |
3646 | .name = "IR-HPET_MSI", | |
3647 | .unmask = hpet_msi_unmask, | |
3648 | .mask = hpet_msi_mask, | |
3649 | #ifdef CONFIG_INTR_REMAP | |
3650 | .ack = ir_ack_apic_edge, | |
3651 | #ifdef CONFIG_SMP | |
3652 | .set_affinity = ir_set_msi_irq_affinity, | |
3653 | #endif | |
3654 | #endif | |
3655 | .retrigger = ioapic_retrigger_irq, | |
3656 | }; | |
3657 | ||
1cc18521 | 3658 | static struct irq_chip hpet_msi_type = { |
58ac1e76 | 3659 | .name = "HPET_MSI", |
3660 | .unmask = hpet_msi_unmask, | |
3661 | .mask = hpet_msi_mask, | |
3662 | .ack = ack_apic_edge, | |
3663 | #ifdef CONFIG_SMP | |
3664 | .set_affinity = hpet_msi_set_affinity, | |
3665 | #endif | |
3666 | .retrigger = ioapic_retrigger_irq, | |
3667 | }; | |
3668 | ||
c8bc6f3c | 3669 | int arch_setup_hpet_msi(unsigned int irq, unsigned int id) |
58ac1e76 | 3670 | { |
3671 | int ret; | |
3672 | struct msi_msg msg; | |
6ec3cfec | 3673 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3674 | |
c8bc6f3c SS |
3675 | if (intr_remapping_enabled) { |
3676 | struct intel_iommu *iommu = map_hpet_to_ir(id); | |
3677 | int index; | |
3678 | ||
3679 | if (!iommu) | |
3680 | return -1; | |
3681 | ||
3682 | index = alloc_irte(iommu, irq, 1); | |
3683 | if (index < 0) | |
3684 | return -1; | |
3685 | } | |
3686 | ||
3687 | ret = msi_compose_msg(NULL, irq, &msg, id); | |
58ac1e76 | 3688 | if (ret < 0) |
3689 | return ret; | |
3690 | ||
3691 | hpet_msi_write(irq, &msg); | |
6ec3cfec | 3692 | desc->status |= IRQ_MOVE_PCNTXT; |
c8bc6f3c SS |
3693 | if (irq_remapped(irq)) |
3694 | set_irq_chip_and_handler_name(irq, &ir_hpet_msi_type, | |
3695 | handle_edge_irq, "edge"); | |
3696 | else | |
3697 | set_irq_chip_and_handler_name(irq, &hpet_msi_type, | |
3698 | handle_edge_irq, "edge"); | |
c81bba49 | 3699 | |
58ac1e76 | 3700 | return 0; |
3701 | } | |
3702 | #endif | |
3703 | ||
54168ed7 | 3704 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
3705 | /* |
3706 | * Hypertransport interrupt support | |
3707 | */ | |
3708 | #ifdef CONFIG_HT_IRQ | |
3709 | ||
3710 | #ifdef CONFIG_SMP | |
3711 | ||
497c9a19 | 3712 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3713 | { |
ec68307c EB |
3714 | struct ht_irq_msg msg; |
3715 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3716 | |
497c9a19 | 3717 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3718 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3719 | |
497c9a19 | 3720 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3721 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3722 | |
ec68307c | 3723 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3724 | } |
3725 | ||
d5dedd45 | 3726 | static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask) |
8b955b0d | 3727 | { |
3145e941 | 3728 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3729 | struct irq_cfg *cfg; |
8b955b0d | 3730 | unsigned int dest; |
8b955b0d | 3731 | |
18374d89 | 3732 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3733 | return -1; |
8b955b0d | 3734 | |
d4eba297 | 3735 | cfg = get_irq_desc_chip_data(desc); |
8b955b0d | 3736 | |
497c9a19 | 3737 | target_ht_irq(irq, dest, cfg->vector); |
d5dedd45 YL |
3738 | |
3739 | return 0; | |
8b955b0d | 3740 | } |
3145e941 | 3741 | |
8b955b0d EB |
3742 | #endif |
3743 | ||
c37e108d | 3744 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
3745 | .name = "PCI-HT", |
3746 | .mask = mask_ht_irq, | |
3747 | .unmask = unmask_ht_irq, | |
1d025192 | 3748 | .ack = ack_apic_edge, |
8b955b0d EB |
3749 | #ifdef CONFIG_SMP |
3750 | .set_affinity = set_ht_irq_affinity, | |
3751 | #endif | |
3752 | .retrigger = ioapic_retrigger_irq, | |
3753 | }; | |
3754 | ||
3755 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3756 | { | |
497c9a19 YL |
3757 | struct irq_cfg *cfg; |
3758 | int err; | |
8b955b0d | 3759 | |
f1182638 JB |
3760 | if (disable_apic) |
3761 | return -ENXIO; | |
3762 | ||
3145e941 | 3763 | cfg = irq_cfg(irq); |
fe402e1f | 3764 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
54168ed7 | 3765 | if (!err) { |
ec68307c | 3766 | struct ht_irq_msg msg; |
8b955b0d | 3767 | unsigned dest; |
8b955b0d | 3768 | |
debccb3e IM |
3769 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, |
3770 | apic->target_cpus()); | |
8b955b0d | 3771 | |
ec68307c | 3772 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3773 | |
ec68307c EB |
3774 | msg.address_lo = |
3775 | HT_IRQ_LOW_BASE | | |
8b955b0d | 3776 | HT_IRQ_LOW_DEST_ID(dest) | |
497c9a19 | 3777 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
9b5bc8dc | 3778 | ((apic->irq_dest_mode == 0) ? |
8b955b0d EB |
3779 | HT_IRQ_LOW_DM_PHYSICAL : |
3780 | HT_IRQ_LOW_DM_LOGICAL) | | |
3781 | HT_IRQ_LOW_RQEOI_EDGE | | |
9b5bc8dc | 3782 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
8b955b0d EB |
3783 | HT_IRQ_LOW_MT_FIXED : |
3784 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3785 | HT_IRQ_LOW_IRQ_MASKED; | |
3786 | ||
ec68307c | 3787 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3788 | |
a460e745 IM |
3789 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
3790 | handle_edge_irq, "edge"); | |
c81bba49 YL |
3791 | |
3792 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); | |
8b955b0d | 3793 | } |
497c9a19 | 3794 | return err; |
8b955b0d EB |
3795 | } |
3796 | #endif /* CONFIG_HT_IRQ */ | |
3797 | ||
9d6a4d08 YL |
3798 | int __init io_apic_get_redir_entries (int ioapic) |
3799 | { | |
3800 | union IO_APIC_reg_01 reg_01; | |
3801 | unsigned long flags; | |
3802 | ||
dade7716 | 3803 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
9d6a4d08 | 3804 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 3805 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
9d6a4d08 | 3806 | |
4b6b19a1 EB |
3807 | /* The register returns the maximum index redir index |
3808 | * supported, which is one less than the total number of redir | |
3809 | * entries. | |
3810 | */ | |
3811 | return reg_01.bits.entries + 1; | |
9d6a4d08 YL |
3812 | } |
3813 | ||
be5d5350 | 3814 | void __init probe_nr_irqs_gsi(void) |
9d6a4d08 | 3815 | { |
4afc51a8 | 3816 | int nr; |
be5d5350 | 3817 | |
a4384df3 | 3818 | nr = gsi_top + NR_IRQS_LEGACY; |
4afc51a8 | 3819 | if (nr > nr_irqs_gsi) |
be5d5350 | 3820 | nr_irqs_gsi = nr; |
cc6c5006 YL |
3821 | |
3822 | printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi); | |
9d6a4d08 YL |
3823 | } |
3824 | ||
4a046d17 YL |
3825 | #ifdef CONFIG_SPARSE_IRQ |
3826 | int __init arch_probe_nr_irqs(void) | |
3827 | { | |
3828 | int nr; | |
3829 | ||
f1ee5548 YL |
3830 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) |
3831 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
4a046d17 | 3832 | |
f1ee5548 YL |
3833 | nr = nr_irqs_gsi + 8 * nr_cpu_ids; |
3834 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
3835 | /* | |
3836 | * for MSI and HT dyn irq | |
3837 | */ | |
3838 | nr += nr_irqs_gsi * 16; | |
3839 | #endif | |
3840 | if (nr < nr_irqs) | |
4a046d17 YL |
3841 | nr_irqs = nr; |
3842 | ||
b683de2b | 3843 | return NR_IRQS_LEGACY; |
4a046d17 YL |
3844 | } |
3845 | #endif | |
3846 | ||
e5198075 YL |
3847 | static int __io_apic_set_pci_routing(struct device *dev, int irq, |
3848 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 YL |
3849 | { |
3850 | struct irq_desc *desc; | |
3851 | struct irq_cfg *cfg; | |
3852 | int node; | |
e5198075 YL |
3853 | int ioapic, pin; |
3854 | int trigger, polarity; | |
5ef21837 | 3855 | |
e5198075 | 3856 | ioapic = irq_attr->ioapic; |
5ef21837 YL |
3857 | if (!IO_APIC_IRQ(irq)) { |
3858 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
3859 | ioapic); | |
3860 | return -EINVAL; | |
3861 | } | |
3862 | ||
3863 | if (dev) | |
3864 | node = dev_to_node(dev); | |
3865 | else | |
f6e9456c | 3866 | node = cpu_to_node(0); |
5ef21837 YL |
3867 | |
3868 | desc = irq_to_desc_alloc_node(irq, node); | |
3869 | if (!desc) { | |
3870 | printk(KERN_INFO "can not get irq_desc %d\n", irq); | |
3871 | return 0; | |
3872 | } | |
3873 | ||
e5198075 YL |
3874 | pin = irq_attr->ioapic_pin; |
3875 | trigger = irq_attr->trigger; | |
3876 | polarity = irq_attr->polarity; | |
3877 | ||
5ef21837 YL |
3878 | /* |
3879 | * IRQs < 16 are already in the irq_2_pin[] map | |
3880 | */ | |
b81bb373 | 3881 | if (irq >= legacy_pic->nr_legacy_irqs) { |
d4eba297 | 3882 | cfg = get_irq_desc_chip_data(desc); |
f3d1915a CG |
3883 | if (add_pin_to_irq_node_nopanic(cfg, node, ioapic, pin)) { |
3884 | printk(KERN_INFO "can not add pin %d for irq %d\n", | |
3885 | pin, irq); | |
3886 | return 0; | |
3887 | } | |
5ef21837 YL |
3888 | } |
3889 | ||
e5198075 | 3890 | setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity); |
5ef21837 YL |
3891 | |
3892 | return 0; | |
3893 | } | |
3894 | ||
e5198075 YL |
3895 | int io_apic_set_pci_routing(struct device *dev, int irq, |
3896 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 | 3897 | { |
e5198075 | 3898 | int ioapic, pin; |
5ef21837 YL |
3899 | /* |
3900 | * Avoid pin reprogramming. PRTs typically include entries | |
3901 | * with redundant pin->gsi mappings (but unique PCI devices); | |
3902 | * we only program the IOAPIC on the first. | |
3903 | */ | |
e5198075 YL |
3904 | ioapic = irq_attr->ioapic; |
3905 | pin = irq_attr->ioapic_pin; | |
5ef21837 YL |
3906 | if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) { |
3907 | pr_debug("Pin %d-%d already programmed\n", | |
3908 | mp_ioapics[ioapic].apicid, pin); | |
3909 | return 0; | |
3910 | } | |
3911 | set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed); | |
3912 | ||
e5198075 | 3913 | return __io_apic_set_pci_routing(dev, irq, irq_attr); |
5ef21837 YL |
3914 | } |
3915 | ||
2a4ab640 FT |
3916 | u8 __init io_apic_unique_id(u8 id) |
3917 | { | |
3918 | #ifdef CONFIG_X86_32 | |
3919 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
3920 | !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
3921 | return io_apic_get_unique_id(nr_ioapics, id); | |
3922 | else | |
3923 | return id; | |
3924 | #else | |
3925 | int i; | |
3926 | DECLARE_BITMAP(used, 256); | |
1da177e4 | 3927 | |
2a4ab640 FT |
3928 | bitmap_zero(used, 256); |
3929 | for (i = 0; i < nr_ioapics; i++) { | |
3930 | struct mpc_ioapic *ia = &mp_ioapics[i]; | |
3931 | __set_bit(ia->apicid, used); | |
3932 | } | |
3933 | if (!test_bit(id, used)) | |
3934 | return id; | |
3935 | return find_first_zero_bit(used, 256); | |
3936 | #endif | |
3937 | } | |
1da177e4 | 3938 | |
54168ed7 | 3939 | #ifdef CONFIG_X86_32 |
36062448 | 3940 | int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3941 | { |
3942 | union IO_APIC_reg_00 reg_00; | |
3943 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3944 | physid_mask_t tmp; | |
3945 | unsigned long flags; | |
3946 | int i = 0; | |
3947 | ||
3948 | /* | |
36062448 PC |
3949 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3950 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3951 | * supports up to 16 on one shared APIC bus. |
36062448 | 3952 | * |
1da177e4 LT |
3953 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
3954 | * advantage of new APIC bus architecture. | |
3955 | */ | |
3956 | ||
3957 | if (physids_empty(apic_id_map)) | |
7abc0753 | 3958 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map); |
1da177e4 | 3959 | |
dade7716 | 3960 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 3961 | reg_00.raw = io_apic_read(ioapic, 0); |
dade7716 | 3962 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
3963 | |
3964 | if (apic_id >= get_physical_broadcast()) { | |
3965 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
3966 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
3967 | apic_id = reg_00.bits.ID; | |
3968 | } | |
3969 | ||
3970 | /* | |
36062448 | 3971 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
3972 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
3973 | */ | |
7abc0753 | 3974 | if (apic->check_apicid_used(&apic_id_map, apic_id)) { |
1da177e4 LT |
3975 | |
3976 | for (i = 0; i < get_physical_broadcast(); i++) { | |
7abc0753 | 3977 | if (!apic->check_apicid_used(&apic_id_map, i)) |
1da177e4 LT |
3978 | break; |
3979 | } | |
3980 | ||
3981 | if (i == get_physical_broadcast()) | |
3982 | panic("Max apic_id exceeded!\n"); | |
3983 | ||
3984 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
3985 | "trying %d\n", ioapic, apic_id, i); | |
3986 | ||
3987 | apic_id = i; | |
36062448 | 3988 | } |
1da177e4 | 3989 | |
7abc0753 | 3990 | apic->apicid_to_cpu_present(apic_id, &tmp); |
1da177e4 LT |
3991 | physids_or(apic_id_map, apic_id_map, tmp); |
3992 | ||
3993 | if (reg_00.bits.ID != apic_id) { | |
3994 | reg_00.bits.ID = apic_id; | |
3995 | ||
dade7716 | 3996 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 LT |
3997 | io_apic_write(ioapic, 0, reg_00.raw); |
3998 | reg_00.raw = io_apic_read(ioapic, 0); | |
dade7716 | 3999 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
4000 | |
4001 | /* Sanity check */ | |
6070f9ec AD |
4002 | if (reg_00.bits.ID != apic_id) { |
4003 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
4004 | return -1; | |
4005 | } | |
1da177e4 LT |
4006 | } |
4007 | ||
4008 | apic_printk(APIC_VERBOSE, KERN_INFO | |
4009 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
4010 | ||
4011 | return apic_id; | |
4012 | } | |
58f892e0 | 4013 | #endif |
1da177e4 | 4014 | |
36062448 | 4015 | int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
4016 | { |
4017 | union IO_APIC_reg_01 reg_01; | |
4018 | unsigned long flags; | |
4019 | ||
dade7716 | 4020 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 4021 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 4022 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
4023 | |
4024 | return reg_01.bits.version; | |
4025 | } | |
4026 | ||
9a0a91bb | 4027 | int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity) |
61fd47e0 | 4028 | { |
9a0a91bb | 4029 | int ioapic, pin, idx; |
61fd47e0 SL |
4030 | |
4031 | if (skip_ioapic_setup) | |
4032 | return -1; | |
4033 | ||
9a0a91bb EB |
4034 | ioapic = mp_find_ioapic(gsi); |
4035 | if (ioapic < 0) | |
61fd47e0 SL |
4036 | return -1; |
4037 | ||
9a0a91bb EB |
4038 | pin = mp_find_ioapic_pin(ioapic, gsi); |
4039 | if (pin < 0) | |
4040 | return -1; | |
4041 | ||
4042 | idx = find_irq_entry(ioapic, pin, mp_INT); | |
4043 | if (idx < 0) | |
61fd47e0 SL |
4044 | return -1; |
4045 | ||
9a0a91bb EB |
4046 | *trigger = irq_trigger(idx); |
4047 | *polarity = irq_polarity(idx); | |
61fd47e0 SL |
4048 | return 0; |
4049 | } | |
4050 | ||
497c9a19 YL |
4051 | /* |
4052 | * This function currently is only a helper for the i386 smp boot process where | |
4053 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
fe402e1f | 4054 | * so mask in all cases should simply be apic->target_cpus() |
497c9a19 YL |
4055 | */ |
4056 | #ifdef CONFIG_SMP | |
4057 | void __init setup_ioapic_dest(void) | |
4058 | { | |
fad53995 | 4059 | int pin, ioapic, irq, irq_entry; |
6c2e9403 | 4060 | struct irq_desc *desc; |
22f65d31 | 4061 | const struct cpumask *mask; |
497c9a19 YL |
4062 | |
4063 | if (skip_ioapic_setup == 1) | |
4064 | return; | |
4065 | ||
fad53995 | 4066 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) |
b9c61b70 YL |
4067 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { |
4068 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
4069 | if (irq_entry == -1) | |
4070 | continue; | |
4071 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
6c2e9403 | 4072 | |
fad53995 EB |
4073 | if ((ioapic > 0) && (irq > 16)) |
4074 | continue; | |
4075 | ||
b9c61b70 | 4076 | desc = irq_to_desc(irq); |
6c2e9403 | 4077 | |
b9c61b70 YL |
4078 | /* |
4079 | * Honour affinities which have been set in early boot | |
4080 | */ | |
4081 | if (desc->status & | |
4082 | (IRQ_NO_BALANCING | IRQ_AFFINITY_SET)) | |
4083 | mask = desc->affinity; | |
4084 | else | |
4085 | mask = apic->target_cpus(); | |
497c9a19 | 4086 | |
b9c61b70 YL |
4087 | if (intr_remapping_enabled) |
4088 | set_ir_ioapic_affinity_irq_desc(desc, mask); | |
4089 | else | |
4090 | set_ioapic_affinity_irq_desc(desc, mask); | |
497c9a19 | 4091 | } |
b9c61b70 | 4092 | |
497c9a19 YL |
4093 | } |
4094 | #endif | |
4095 | ||
54168ed7 IM |
4096 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
4097 | ||
4098 | static struct resource *ioapic_resources; | |
4099 | ||
ffc43836 | 4100 | static struct resource * __init ioapic_setup_resources(int nr_ioapics) |
54168ed7 IM |
4101 | { |
4102 | unsigned long n; | |
4103 | struct resource *res; | |
4104 | char *mem; | |
4105 | int i; | |
4106 | ||
4107 | if (nr_ioapics <= 0) | |
4108 | return NULL; | |
4109 | ||
4110 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
4111 | n *= nr_ioapics; | |
4112 | ||
4113 | mem = alloc_bootmem(n); | |
4114 | res = (void *)mem; | |
4115 | ||
ffc43836 | 4116 | mem += sizeof(struct resource) * nr_ioapics; |
54168ed7 | 4117 | |
ffc43836 CG |
4118 | for (i = 0; i < nr_ioapics; i++) { |
4119 | res[i].name = mem; | |
4120 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4343fe10 | 4121 | snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i); |
ffc43836 | 4122 | mem += IOAPIC_RESOURCE_NAME_SIZE; |
54168ed7 IM |
4123 | } |
4124 | ||
4125 | ioapic_resources = res; | |
4126 | ||
4127 | return res; | |
4128 | } | |
54168ed7 | 4129 | |
f3294a33 YL |
4130 | void __init ioapic_init_mappings(void) |
4131 | { | |
4132 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 4133 | struct resource *ioapic_res; |
d6c88a50 | 4134 | int i; |
f3294a33 | 4135 | |
ffc43836 | 4136 | ioapic_res = ioapic_setup_resources(nr_ioapics); |
f3294a33 YL |
4137 | for (i = 0; i < nr_ioapics; i++) { |
4138 | if (smp_found_config) { | |
b5ba7e6d | 4139 | ioapic_phys = mp_ioapics[i].apicaddr; |
54168ed7 | 4140 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
4141 | if (!ioapic_phys) { |
4142 | printk(KERN_ERR | |
4143 | "WARNING: bogus zero IO-APIC " | |
4144 | "address found in MPTABLE, " | |
4145 | "disabling IO/APIC support!\n"); | |
4146 | smp_found_config = 0; | |
4147 | skip_ioapic_setup = 1; | |
4148 | goto fake_ioapic_page; | |
4149 | } | |
54168ed7 | 4150 | #endif |
f3294a33 | 4151 | } else { |
54168ed7 | 4152 | #ifdef CONFIG_X86_32 |
f3294a33 | 4153 | fake_ioapic_page: |
54168ed7 | 4154 | #endif |
e79c65a9 | 4155 | ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
4156 | ioapic_phys = __pa(ioapic_phys); |
4157 | } | |
4158 | set_fixmap_nocache(idx, ioapic_phys); | |
e79c65a9 CG |
4159 | apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n", |
4160 | __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), | |
4161 | ioapic_phys); | |
f3294a33 | 4162 | idx++; |
54168ed7 | 4163 | |
ffc43836 | 4164 | ioapic_res->start = ioapic_phys; |
e79c65a9 | 4165 | ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1; |
ffc43836 | 4166 | ioapic_res++; |
f3294a33 YL |
4167 | } |
4168 | } | |
4169 | ||
857fdc53 | 4170 | void __init ioapic_insert_resources(void) |
54168ed7 IM |
4171 | { |
4172 | int i; | |
4173 | struct resource *r = ioapic_resources; | |
4174 | ||
4175 | if (!r) { | |
857fdc53 | 4176 | if (nr_ioapics > 0) |
04c93ce4 BZ |
4177 | printk(KERN_ERR |
4178 | "IO APIC resources couldn't be allocated.\n"); | |
857fdc53 | 4179 | return; |
54168ed7 IM |
4180 | } |
4181 | ||
4182 | for (i = 0; i < nr_ioapics; i++) { | |
4183 | insert_resource(&iomem_resource, r); | |
4184 | r++; | |
4185 | } | |
54168ed7 | 4186 | } |
2a4ab640 | 4187 | |
eddb0c55 | 4188 | int mp_find_ioapic(u32 gsi) |
2a4ab640 FT |
4189 | { |
4190 | int i = 0; | |
4191 | ||
4192 | /* Find the IOAPIC that manages this GSI. */ | |
4193 | for (i = 0; i < nr_ioapics; i++) { | |
4194 | if ((gsi >= mp_gsi_routing[i].gsi_base) | |
4195 | && (gsi <= mp_gsi_routing[i].gsi_end)) | |
4196 | return i; | |
4197 | } | |
54168ed7 | 4198 | |
2a4ab640 FT |
4199 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); |
4200 | return -1; | |
4201 | } | |
4202 | ||
eddb0c55 | 4203 | int mp_find_ioapic_pin(int ioapic, u32 gsi) |
2a4ab640 FT |
4204 | { |
4205 | if (WARN_ON(ioapic == -1)) | |
4206 | return -1; | |
4207 | if (WARN_ON(gsi > mp_gsi_routing[ioapic].gsi_end)) | |
4208 | return -1; | |
4209 | ||
4210 | return gsi - mp_gsi_routing[ioapic].gsi_base; | |
4211 | } | |
4212 | ||
4213 | static int bad_ioapic(unsigned long address) | |
4214 | { | |
4215 | if (nr_ioapics >= MAX_IO_APICS) { | |
4216 | printk(KERN_WARNING "WARING: Max # of I/O APICs (%d) exceeded " | |
4217 | "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics); | |
4218 | return 1; | |
4219 | } | |
4220 | if (!address) { | |
4221 | printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address" | |
4222 | " found in table, skipping!\n"); | |
4223 | return 1; | |
4224 | } | |
54168ed7 IM |
4225 | return 0; |
4226 | } | |
4227 | ||
2a4ab640 FT |
4228 | void __init mp_register_ioapic(int id, u32 address, u32 gsi_base) |
4229 | { | |
4230 | int idx = 0; | |
7716a5c4 | 4231 | int entries; |
2a4ab640 FT |
4232 | |
4233 | if (bad_ioapic(address)) | |
4234 | return; | |
4235 | ||
4236 | idx = nr_ioapics; | |
4237 | ||
4238 | mp_ioapics[idx].type = MP_IOAPIC; | |
4239 | mp_ioapics[idx].flags = MPC_APIC_USABLE; | |
4240 | mp_ioapics[idx].apicaddr = address; | |
4241 | ||
4242 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
4243 | mp_ioapics[idx].apicid = io_apic_unique_id(id); | |
4244 | mp_ioapics[idx].apicver = io_apic_get_version(idx); | |
4245 | ||
4246 | /* | |
4247 | * Build basic GSI lookup table to facilitate gsi->io_apic lookups | |
4248 | * and to prevent reprogramming of IOAPIC pins (PCI GSIs). | |
4249 | */ | |
7716a5c4 | 4250 | entries = io_apic_get_redir_entries(idx); |
2a4ab640 | 4251 | mp_gsi_routing[idx].gsi_base = gsi_base; |
7716a5c4 EB |
4252 | mp_gsi_routing[idx].gsi_end = gsi_base + entries - 1; |
4253 | ||
4254 | /* | |
4255 | * The number of IO-APIC IRQ registers (== #pins): | |
4256 | */ | |
4257 | nr_ioapic_registers[idx] = entries; | |
2a4ab640 | 4258 | |
a4384df3 EB |
4259 | if (mp_gsi_routing[idx].gsi_end >= gsi_top) |
4260 | gsi_top = mp_gsi_routing[idx].gsi_end + 1; | |
2a4ab640 FT |
4261 | |
4262 | printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, " | |
4263 | "GSI %d-%d\n", idx, mp_ioapics[idx].apicid, | |
4264 | mp_ioapics[idx].apicver, mp_ioapics[idx].apicaddr, | |
4265 | mp_gsi_routing[idx].gsi_base, mp_gsi_routing[idx].gsi_end); | |
4266 | ||
4267 | nr_ioapics++; | |
4268 | } | |
05ddafb1 JP |
4269 | |
4270 | /* Enable IOAPIC early just for system timer */ | |
4271 | void __init pre_init_apic_IRQ0(void) | |
4272 | { | |
4273 | struct irq_cfg *cfg; | |
4274 | struct irq_desc *desc; | |
4275 | ||
4276 | printk(KERN_INFO "Early APIC setup for system timer0\n"); | |
4277 | #ifndef CONFIG_SMP | |
4278 | phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid); | |
4279 | #endif | |
4280 | desc = irq_to_desc_alloc_node(0, 0); | |
4281 | ||
4282 | setup_local_APIC(); | |
4283 | ||
4284 | cfg = irq_cfg(0); | |
4285 | add_pin_to_irq_node(cfg, 0, 0, 0); | |
4286 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); | |
4287 | ||
4288 | setup_IO_APIC_irq(0, 0, 0, desc, 0, 0); | |
4289 | } |