[net-next-2.6.git] / arch / tile / include / asm / processor.h

/*
 * Copyright 2010 Tilera Corporation. All Rights Reserved.
 *
 *   This program is free software; you can redistribute it and/or
 *   modify it under the terms of the GNU General Public License
 *   as published by the Free Software Foundation, version 2.
 *
 *   This program is distributed in the hope that it will be useful, but
 *   WITHOUT ANY WARRANTY; without even the implied warranty of
 *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 *   NON INFRINGEMENT.  See the GNU General Public License for
 *   more details.
 */

#ifndef _ASM_TILE_PROCESSOR_H
#define _ASM_TILE_PROCESSOR_H

#ifndef __ASSEMBLY__

/*
 * NOTE: we don't include <linux/ptrace.h> or <linux/percpu.h> as one
 * normally would, due to #include dependencies.
 */
#include <linux/types.h>
#include <asm/ptrace.h>
#include <asm/percpu.h>

#include <arch/chip.h>
#include <arch/spr_def.h>

struct task_struct;
struct thread_struct;

typedef struct {
	unsigned long seg;
} mm_segment_t;

/*
 * Default implementation of macro that returns current
 * instruction pointer ("program counter").
 */
void *current_text_addr(void);

#if CHIP_HAS_TILE_DMA()
/* Capture the state of a suspended DMA. */
struct tile_dma_state {
	int enabled;
	unsigned long src;
	unsigned long dest;
	unsigned long strides;
	unsigned long chunk_size;
	unsigned long src_chunk;
	unsigned long dest_chunk;
	unsigned long byte;
	unsigned long status;
};

/*
 * A mask of the DMA status register for selecting only the 'running'
 * and 'done' bits.
 */
#define DMA_STATUS_MASK \
  (SPR_DMA_STATUS__RUNNING_MASK | SPR_DMA_STATUS__DONE_MASK)
#endif

/*
 * Track asynchronous TLB events (faults and access violations)
 * that occur while we are in kernel mode from DMA or the SN processor.
 */
struct async_tlb {
	short fault_num;         /* original fault number; 0 if none */
	char is_fault;           /* was it a fault (vs an access violation) */
	char is_write;           /* for fault: was it caused by a write? */
	unsigned long address;   /* what address faulted? */
};

#ifdef CONFIG_HARDWALL
struct hardwall_info;
#endif

struct thread_struct {
	/* kernel stack pointer */
	unsigned long  ksp;
	/* kernel PC */
	unsigned long  pc;
	/* starting user stack pointer (for page migration) */
	unsigned long  usp0;
	/* pid of process that created this one */
	pid_t creator_pid;
#if CHIP_HAS_TILE_DMA()
	/* DMA info for suspended threads (byte == 0 means no DMA state) */
	struct tile_dma_state tile_dma_state;
#endif
	/* User EX_CONTEXT registers */
	unsigned long ex_context[2];
	/* User SYSTEM_SAVE registers */
	unsigned long system_save[4];
	/* User interrupt mask */
	unsigned long long interrupt_mask;
	/* User interrupt-control 0 state */
	unsigned long intctrl_0;
#if CHIP_HAS_PROC_STATUS_SPR()
	/* Any other miscellaneous processor state bits */
	unsigned long proc_status;
#endif
#if !CHIP_HAS_FIXED_INTVEC_BASE()
	/* Interrupt base for PL0 interrupts */
	unsigned long interrupt_vector_base;
#endif
#if CHIP_HAS_TILE_RTF_HWM()
	/* Tile cache retry fifo high-water mark */
	unsigned long tile_rtf_hwm;
#endif
#if CHIP_HAS_DSTREAM_PF()
	/* Data stream prefetch control */
	unsigned long dstream_pf;
#endif
#ifdef CONFIG_HARDWALL
	/* Is this task tied to an activated hardwall? */
	struct hardwall_info *hardwall;
	/* Chains this task into the list at hardwall->list. */
	struct list_head hardwall_list;
#endif
#if CHIP_HAS_TILE_DMA()
	/* Async DMA TLB fault information */
	struct async_tlb dma_async_tlb;
#endif
#if CHIP_HAS_SN_PROC()
	/* Was static network processor when we were switched out? */
	int sn_proc_running;
	/* Async SNI TLB fault information */
	struct async_tlb sn_async_tlb;
#endif
};

#endif /* !__ASSEMBLY__ */

/*
 * Start with "sp" this many bytes below the top of the kernel stack.
 * This preserves the invariant that a called function may write to *sp.
 */
#define STACK_TOP_DELTA 8

/*
 * When entering the kernel via a fault, start with the top of the
 * pt_regs structure this many bytes below the top of the page.
 * This aligns the pt_regs structure optimally for cache-line access.
 */
#ifdef __tilegx__
#define KSTK_PTREGS_GAP  48
#else
#define KSTK_PTREGS_GAP  56
#endif

#ifndef __ASSEMBLY__

#ifdef __tilegx__
#define TASK_SIZE_MAX		(MEM_LOW_END + 1)
#else
#define TASK_SIZE_MAX		PAGE_OFFSET
#endif

/* TASK_SIZE and related variables are always checked in "current" context. */
#ifdef CONFIG_COMPAT
#define COMPAT_TASK_SIZE	(1UL << 31)
#define TASK_SIZE		((current_thread_info()->status & TS_COMPAT) ?\
				 COMPAT_TASK_SIZE : TASK_SIZE_MAX)
#else
#define TASK_SIZE		TASK_SIZE_MAX
#endif

/* We provide a minimal "vdso" a la x86; just the sigreturn code for now. */
#define VDSO_BASE		(TASK_SIZE - PAGE_SIZE)

#define STACK_TOP		VDSO_BASE

/* STACK_TOP_MAX is used temporarily in execve and should not check COMPAT. */
#define STACK_TOP_MAX		TASK_SIZE_MAX

/*
 * This decides where the kernel will search for a free chunk of vm
 * space during mmap's, if it is using bottom-up mapping.
 */
#define TASK_UNMAPPED_BASE	(PAGE_ALIGN(TASK_SIZE / 3))

#define HAVE_ARCH_PICK_MMAP_LAYOUT

#define INIT_THREAD {                                                   \
	.ksp = (unsigned long)init_stack + THREAD_SIZE - STACK_TOP_DELTA, \
	.interrupt_mask = -1ULL                                         \
}

/* Kernel stack top for the task that first boots on this cpu. */
DECLARE_PER_CPU(unsigned long, boot_sp);

/* PC to boot from on this cpu. */
DECLARE_PER_CPU(unsigned long, boot_pc);

/* Do necessary setup to start up a newly executed thread. */
static inline void start_thread(struct pt_regs *regs,
				unsigned long pc, unsigned long usp)
{
	regs->pc = pc;
	regs->sp = usp;
}

/* Free all resources held by a thread. */
static inline void release_thread(struct task_struct *dead_task)
{
	/* Nothing for now */
}

/* Prepare to copy thread state - unlazy all lazy status. */
#define prepare_to_copy(tsk)	do { } while (0)

extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);


/*
 * Return saved (kernel) PC of a blocked thread.
 * Only used in a printk() in kernel/sched.c, so don't work too hard.
 */
#define thread_saved_pc(t)   ((t)->thread.pc)

unsigned long get_wchan(struct task_struct *p);

/* Return initial ksp value for given task. */
#define task_ksp0(task) ((unsigned long)(task)->stack + THREAD_SIZE)

/* Return some info about the user process TASK. */
#define KSTK_TOP(task)	(task_ksp0(task) - STACK_TOP_DELTA)
#define task_pt_regs(task) \
  ((struct pt_regs *)(task_ksp0(task) - KSTK_PTREGS_GAP) - 1)
#define task_sp(task)	(task_pt_regs(task)->sp)
#define task_pc(task)	(task_pt_regs(task)->pc)
/* Aliases for pc and sp (used in fs/proc/array.c) */
#define KSTK_EIP(task)	task_pc(task)
#define KSTK_ESP(task)	task_sp(task)

/* Standard format for printing registers and other word-size data. */
#ifdef __tilegx__
# define REGFMT "0x%016lx"
#else
# define REGFMT "0x%08lx"
#endif

/*
 * Do some slow action (e.g. read a slow SPR).
 * Note that this must also have compiler-barrier semantics since
 * it may be used in a busy loop reading memory.
 */
static inline void cpu_relax(void)
{
	__insn_mfspr(SPR_PASS);
	barrier();
}

struct siginfo;
extern void arch_coredump_signal(struct siginfo *, struct pt_regs *);
#define arch_coredump_signal arch_coredump_signal

/* Info on this processor (see fs/proc/cpuinfo.c) */
struct seq_operations;
extern const struct seq_operations cpuinfo_op;

/* Provide information about the chip model. */
extern char chip_model[64];

/* Data on which physical memory controller corresponds to which NUMA node. */
extern int node_controller[];


/* Do we dump information to the console when a user application crashes? */
extern int show_crashinfo;

#if CHIP_HAS_CBOX_HOME_MAP()
/* Does the heap allocator return hash-for-home pages by default? */
extern int hash_default;

/* Should kernel stack pages be hash-for-home? */
extern int kstack_hash;

/* Does MAP_ANONYMOUS return hash-for-home pages by default? */
#define uheap_hash hash_default

#else
#define hash_default 0
#define kstack_hash 0
#define uheap_hash 0
#endif

/* Are we using huge pages in the TLB for kernel data? */
extern int kdata_huge;

#define PREFETCH_STRIDE CHIP_L2_LINE_SIZE()

#else /* __ASSEMBLY__ */

/* Do some slow action (e.g. read a slow SPR). */
#define CPU_RELAX       mfspr zero, SPR_PASS

#endif /* !__ASSEMBLY__ */

/* Assembly code assumes that the PL is in the low bits. */
#if SPR_EX_CONTEXT_1_1__PL_SHIFT != 0
# error Fix assembly assumptions about PL
#endif

/* We sometimes use these macros for EX_CONTEXT_0_1 as well. */
#if SPR_EX_CONTEXT_1_1__PL_SHIFT != SPR_EX_CONTEXT_0_1__PL_SHIFT || \
    SPR_EX_CONTEXT_1_1__PL_RMASK != SPR_EX_CONTEXT_0_1__PL_RMASK || \
    SPR_EX_CONTEXT_1_1__ICS_SHIFT != SPR_EX_CONTEXT_0_1__ICS_SHIFT || \
    SPR_EX_CONTEXT_1_1__ICS_RMASK != SPR_EX_CONTEXT_0_1__ICS_RMASK
# error Fix assumptions that EX1 macros work for both PL0 and PL1
#endif

/* Allow pulling apart and recombining the PL and ICS bits in EX_CONTEXT. */
#define EX1_PL(ex1) \
  (((ex1) >> SPR_EX_CONTEXT_1_1__PL_SHIFT) & SPR_EX_CONTEXT_1_1__PL_RMASK)
#define EX1_ICS(ex1) \
  (((ex1) >> SPR_EX_CONTEXT_1_1__ICS_SHIFT) & SPR_EX_CONTEXT_1_1__ICS_RMASK)
#define PL_ICS_EX1(pl, ics) \
  (((pl) << SPR_EX_CONTEXT_1_1__PL_SHIFT) | \
   ((ics) << SPR_EX_CONTEXT_1_1__ICS_SHIFT))

/*
 * Provide symbolic constants for PLs.
 * Note that assembly code assumes that USER_PL is zero.
 */
#define USER_PL 0
#define KERNEL_PL 1

/* SYSTEM_SAVE_1_0 holds the current cpu number ORed with ksp0. */
#define CPU_LOG_MASK_VALUE 12
#define CPU_MASK_VALUE ((1 << CPU_LOG_MASK_VALUE) - 1)
#if CONFIG_NR_CPUS > CPU_MASK_VALUE
# error Too many cpus!
#endif
#define raw_smp_processor_id() \
	((int)__insn_mfspr(SPR_SYSTEM_SAVE_1_0) & CPU_MASK_VALUE)
#define get_current_ksp0() \
	(__insn_mfspr(SPR_SYSTEM_SAVE_1_0) & ~CPU_MASK_VALUE)
#define next_current_ksp0(task) ({ \
	unsigned long __ksp0 = task_ksp0(task); \
	int __cpu = raw_smp_processor_id(); \
	BUG_ON(__ksp0 & CPU_MASK_VALUE); \
	__ksp0 | __cpu; \
})

#endif /* _ASM_TILE_PROCESSOR_H */
Commit	Line	Data
867e359b CM	1	/*
	2	* Copyright 2010 Tilera Corporation. All Rights Reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation, version 2.
	7	*
	8	* This program is distributed in the hope that it will be useful, but
	9	* WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
	11	* NON INFRINGEMENT. See the GNU General Public License for
	12	* more details.
	13	*/
	14
	15	#ifndef _ASM_TILE_PROCESSOR_H
	16	#define _ASM_TILE_PROCESSOR_H
	17
	18	#ifndef __ASSEMBLY__
	19
	20	/*
	21	* NOTE: we don't include <linux/ptrace.h> or <linux/percpu.h> as one
	22	* normally would, due to #include dependencies.
	23	*/
9f9c0382	24	#include <linux/types.h>
867e359b CM	25	#include <asm/ptrace.h>
	26	#include <asm/percpu.h>
	27
	28	#include <arch/chip.h>
	29	#include <arch/spr_def.h>
	30
	31	struct task_struct;
	32	struct thread_struct;
867e359b CM	33
	34	typedef struct {
	35	unsigned long seg;
	36	} mm_segment_t;
	37
	38	/*
	39	* Default implementation of macro that returns current
	40	* instruction pointer ("program counter").
	41	*/
	42	void *current_text_addr(void);
	43
	44	#if CHIP_HAS_TILE_DMA()
	45	/* Capture the state of a suspended DMA. */
	46	struct tile_dma_state {
	47	int enabled;
	48	unsigned long src;
	49	unsigned long dest;
	50	unsigned long strides;
	51	unsigned long chunk_size;
	52	unsigned long src_chunk;
	53	unsigned long dest_chunk;
	54	unsigned long byte;
	55	unsigned long status;
	56	};
	57
	58	/*
	59	* A mask of the DMA status register for selecting only the 'running'
	60	* and 'done' bits.
	61	*/
	62	#define DMA_STATUS_MASK \
	63	(SPR_DMA_STATUS__RUNNING_MASK \| SPR_DMA_STATUS__DONE_MASK)
	64	#endif
	65
	66	/*
	67	* Track asynchronous TLB events (faults and access violations)
	68	* that occur while we are in kernel mode from DMA or the SN processor.
	69	*/
	70	struct async_tlb {
	71	short fault_num; /* original fault number; 0 if none */
	72	char is_fault; /* was it a fault (vs an access violation) */
	73	char is_write; /* for fault: was it caused by a write? */
	74	unsigned long address; /* what address faulted? */
	75	};
	76
9f9c0382 CM	77	#ifdef CONFIG_HARDWALL
	78	struct hardwall_info;
	79	#endif
867e359b CM	80
	81	struct thread_struct {
	82	/* kernel stack pointer */
	83	unsigned long ksp;
	84	/* kernel PC */
	85	unsigned long pc;
	86	/* starting user stack pointer (for page migration) */
	87	unsigned long usp0;
	88	/* pid of process that created this one */
	89	pid_t creator_pid;
	90	#if CHIP_HAS_TILE_DMA()
	91	/* DMA info for suspended threads (byte == 0 means no DMA state) */
	92	struct tile_dma_state tile_dma_state;
	93	#endif
	94	/* User EX_CONTEXT registers */
	95	unsigned long ex_context[2];
	96	/* User SYSTEM_SAVE registers */
	97	unsigned long system_save[4];
	98	/* User interrupt mask */
	99	unsigned long long interrupt_mask;
	100	/* User interrupt-control 0 state */
	101	unsigned long intctrl_0;
	102	#if CHIP_HAS_PROC_STATUS_SPR()
	103	/* Any other miscellaneous processor state bits */
	104	unsigned long proc_status;
	105	#endif
a802fc68 CM	106	#if !CHIP_HAS_FIXED_INTVEC_BASE()
	107	/* Interrupt base for PL0 interrupts */
	108	unsigned long interrupt_vector_base;
	109	#endif
	110	#if CHIP_HAS_TILE_RTF_HWM()
	111	/* Tile cache retry fifo high-water mark */
	112	unsigned long tile_rtf_hwm;
	113	#endif
	114	#if CHIP_HAS_DSTREAM_PF()
	115	/* Data stream prefetch control */
	116	unsigned long dstream_pf;
	117	#endif
9f9c0382 CM	118	#ifdef CONFIG_HARDWALL
	119	/* Is this task tied to an activated hardwall? */
	120	struct hardwall_info *hardwall;
	121	/* Chains this task into the list at hardwall->list. */
	122	struct list_head hardwall_list;
	123	#endif
867e359b CM	124	#if CHIP_HAS_TILE_DMA()
	125	/* Async DMA TLB fault information */
	126	struct async_tlb dma_async_tlb;
	127	#endif
	128	#if CHIP_HAS_SN_PROC()
	129	/* Was static network processor when we were switched out? */
	130	int sn_proc_running;
	131	/* Async SNI TLB fault information */
	132	struct async_tlb sn_async_tlb;
	133	#endif
	134	};
	135
	136	#endif /* !__ASSEMBLY__ */
	137
	138	/*
	139	* Start with "sp" this many bytes below the top of the kernel stack.
	140	* This preserves the invariant that a called function may write to *sp.
	141	*/
	142	#define STACK_TOP_DELTA 8
	143
	144	/*
	145	* When entering the kernel via a fault, start with the top of the
	146	* pt_regs structure this many bytes below the top of the page.
	147	* This aligns the pt_regs structure optimally for cache-line access.
	148	*/
	149	#ifdef __tilegx__
	150	#define KSTK_PTREGS_GAP 48
	151	#else
	152	#define KSTK_PTREGS_GAP 56
	153	#endif
	154
	155	#ifndef __ASSEMBLY__
	156
	157	#ifdef __tilegx__
	158	#define TASK_SIZE_MAX (MEM_LOW_END + 1)
	159	#else
	160	#define TASK_SIZE_MAX PAGE_OFFSET
	161	#endif
	162
	163	/* TASK_SIZE and related variables are always checked in "current" context. */
	164	#ifdef CONFIG_COMPAT
	165	#define COMPAT_TASK_SIZE (1UL << 31)
	166	#define TASK_SIZE ((current_thread_info()->status & TS_COMPAT) ?\
	167	COMPAT_TASK_SIZE : TASK_SIZE_MAX)
	168	#else
	169	#define TASK_SIZE TASK_SIZE_MAX
	170	#endif
	171
	172	/* We provide a minimal "vdso" a la x86; just the sigreturn code for now. */
	173	#define VDSO_BASE (TASK_SIZE - PAGE_SIZE)
	174
	175	#define STACK_TOP VDSO_BASE
	176
	177	/* STACK_TOP_MAX is used temporarily in execve and should not check COMPAT. */
	178	#define STACK_TOP_MAX TASK_SIZE_MAX
	179
	180	/*
	181	* This decides where the kernel will search for a free chunk of vm
	182	* space during mmap's, if it is using bottom-up mapping.
	183	*/
	184	#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
	185
	186	#define HAVE_ARCH_PICK_MMAP_LAYOUT
	187
188	#define INIT_THREAD { \
189	.ksp = (unsigned long)init_stack + THREAD_SIZE - STACK_TOP_DELTA, \
190	.interrupt_mask = -1ULL \
191	}
192
193	/* Kernel stack top for the task that first boots on this cpu. */
194	DECLARE_PER_CPU(unsigned long, boot_sp);
195
196	/* PC to boot from on this cpu. */
197	DECLARE_PER_CPU(unsigned long, boot_pc);
198
199	/* Do necessary setup to start up a newly executed thread. */
200	static inline void start_thread(struct pt_regs *regs,
201	unsigned long pc, unsigned long usp)
202	{
203	regs->pc = pc;
204	regs->sp = usp;
205	}
206
207	/* Free all resources held by a thread. */
208	static inline void release_thread(struct task_struct *dead_task)
209	{
210	/* Nothing for now */
211	}
212
213	/* Prepare to copy thread state - unlazy all lazy status. */
214	#define prepare_to_copy(tsk) do { } while (0)
215
216	extern int kernel_thread(int (fn)(void ), void *arg, unsigned long flags);
217
867e359b CM	218
	219	/*
	220	* Return saved (kernel) PC of a blocked thread.
	221	* Only used in a printk() in kernel/sched.c, so don't work too hard.
	222	*/
	223	#define thread_saved_pc(t) ((t)->thread.pc)
	224
	225	unsigned long get_wchan(struct task_struct *p);
	226
	227	/* Return initial ksp value for given task. */
	228	#define task_ksp0(task) ((unsigned long)(task)->stack + THREAD_SIZE)
	229
	230	/* Return some info about the user process TASK. */
	231	#define KSTK_TOP(task) (task_ksp0(task) - STACK_TOP_DELTA)
	232	#define task_pt_regs(task) \
	233	((struct pt_regs *)(task_ksp0(task) - KSTK_PTREGS_GAP) - 1)
	234	#define task_sp(task) (task_pt_regs(task)->sp)
	235	#define task_pc(task) (task_pt_regs(task)->pc)
	236	/* Aliases for pc and sp (used in fs/proc/array.c) */
	237	#define KSTK_EIP(task) task_pc(task)
	238	#define KSTK_ESP(task) task_sp(task)
	239
	240	/* Standard format for printing registers and other word-size data. */
	241	#ifdef __tilegx__
	242	# define REGFMT "0x%016lx"
	243	#else
	244	# define REGFMT "0x%08lx"
	245	#endif
	246
	247	/*
	248	* Do some slow action (e.g. read a slow SPR).
	249	* Note that this must also have compiler-barrier semantics since
	250	* it may be used in a busy loop reading memory.
	251	*/
	252	static inline void cpu_relax(void)
	253	{
	254	__insn_mfspr(SPR_PASS);
	255	barrier();
	256	}
	257
	258	struct siginfo;
	259	extern void arch_coredump_signal(struct siginfo , struct pt_regs );
	260	#define arch_coredump_signal arch_coredump_signal
	261
9f9c0382 CM	262	/* Info on this processor (see fs/proc/cpuinfo.c) */
	263	struct seq_operations;
	264	extern const struct seq_operations cpuinfo_op;
	265
867e359b CM	266	/* Provide information about the chip model. */
	267	extern char chip_model[64];
	268
	269	/* Data on which physical memory controller corresponds to which NUMA node. */
	270	extern int node_controller[];
	271
	272
	273	/* Do we dump information to the console when a user application crashes? */
	274	extern int show_crashinfo;
	275
	276	#if CHIP_HAS_CBOX_HOME_MAP()
	277	/* Does the heap allocator return hash-for-home pages by default? */
	278	extern int hash_default;
	279
	280	/* Should kernel stack pages be hash-for-home? */
	281	extern int kstack_hash;
ef06f55a CM	282
	283	/* Does MAP_ANONYMOUS return hash-for-home pages by default? */
	284	#define uheap_hash hash_default
	285
867e359b CM	286	#else
	287	#define hash_default 0
	288	#define kstack_hash 0
ef06f55a	289	#define uheap_hash 0
867e359b CM	290	#endif
	291
	292	/* Are we using huge pages in the TLB for kernel data? */
	293	extern int kdata_huge;
	294
ef06f55a	295	#define PREFETCH_STRIDE CHIP_L2_LINE_SIZE()
867e359b CM	296
	297	#else /* __ASSEMBLY__ */
	298
	299	/* Do some slow action (e.g. read a slow SPR). */
	300	#define CPU_RELAX mfspr zero, SPR_PASS
	301
	302	#endif /* !__ASSEMBLY__ */
	303
	304	/* Assembly code assumes that the PL is in the low bits. */
	305	#if SPR_EX_CONTEXT_1_1__PL_SHIFT != 0
	306	# error Fix assembly assumptions about PL
	307	#endif
	308
	309	/* We sometimes use these macros for EX_CONTEXT_0_1 as well. */
	310	#if SPR_EX_CONTEXT_1_1__PL_SHIFT != SPR_EX_CONTEXT_0_1__PL_SHIFT \|\| \
	311	SPR_EX_CONTEXT_1_1__PL_RMASK != SPR_EX_CONTEXT_0_1__PL_RMASK \|\| \
	312	SPR_EX_CONTEXT_1_1__ICS_SHIFT != SPR_EX_CONTEXT_0_1__ICS_SHIFT \|\| \
	313	SPR_EX_CONTEXT_1_1__ICS_RMASK != SPR_EX_CONTEXT_0_1__ICS_RMASK
	314	# error Fix assumptions that EX1 macros work for both PL0 and PL1
	315	#endif
	316
	317	/* Allow pulling apart and recombining the PL and ICS bits in EX_CONTEXT. */
	318	#define EX1_PL(ex1) \
	319	(((ex1) >> SPR_EX_CONTEXT_1_1__PL_SHIFT) & SPR_EX_CONTEXT_1_1__PL_RMASK)
	320	#define EX1_ICS(ex1) \
	321	(((ex1) >> SPR_EX_CONTEXT_1_1__ICS_SHIFT) & SPR_EX_CONTEXT_1_1__ICS_RMASK)
	322	#define PL_ICS_EX1(pl, ics) \
	323	(((pl) << SPR_EX_CONTEXT_1_1__PL_SHIFT) \| \
	324	((ics) << SPR_EX_CONTEXT_1_1__ICS_SHIFT))
	325
	326	/*
	327	* Provide symbolic constants for PLs.
	328	* Note that assembly code assumes that USER_PL is zero.
	329	*/
	330	#define USER_PL 0
	331	#define KERNEL_PL 1
	332
	333	/* SYSTEM_SAVE_1_0 holds the current cpu number ORed with ksp0. */
	334	#define CPU_LOG_MASK_VALUE 12
	335	#define CPU_MASK_VALUE ((1 << CPU_LOG_MASK_VALUE) - 1)
	336	#if CONFIG_NR_CPUS > CPU_MASK_VALUE
	337	# error Too many cpus!
	338	#endif
	339	#define raw_smp_processor_id() \
	340	((int)__insn_mfspr(SPR_SYSTEM_SAVE_1_0) & CPU_MASK_VALUE)
	341	#define get_current_ksp0() \
	342	(__insn_mfspr(SPR_SYSTEM_SAVE_1_0) & ~CPU_MASK_VALUE)
	343	#define next_current_ksp0(task) ({ \
	344	unsigned long __ksp0 = task_ksp0(task); \
	345	int __cpu = raw_smp_processor_id(); \
	346	BUG_ON(__ksp0 & CPU_MASK_VALUE); \
	347	__ksp0 \| __cpu; \
	348	})
	349
	350	#endif /* _ASM_TILE_PROCESSOR_H */