[net-next-2.6.git] / arch / tile / include / asm / cache.h

/*
 * Copyright 2010 Tilera Corporation. All Rights Reserved.
 *
 *   This program is free software; you can redistribute it and/or
 *   modify it under the terms of the GNU General Public License
 *   as published by the Free Software Foundation, version 2.
 *
 *   This program is distributed in the hope that it will be useful, but
 *   WITHOUT ANY WARRANTY; without even the implied warranty of
 *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 *   NON INFRINGEMENT.  See the GNU General Public License for
 *   more details.
 */

#ifndef _ASM_TILE_CACHE_H
#define _ASM_TILE_CACHE_H

#include <arch/chip.h>

/* bytes per L1 data cache line */
#define L1_CACHE_SHIFT		CHIP_L1D_LOG_LINE_SIZE()
#define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)

/* bytes per L2 cache line */
#define L2_CACHE_SHIFT		CHIP_L2_LOG_LINE_SIZE()
#define L2_CACHE_BYTES		(1 << L2_CACHE_SHIFT)
#define L2_CACHE_ALIGN(x)	(((x)+(L2_CACHE_BYTES-1)) & -L2_CACHE_BYTES)

/*
 * TILE-Gx is fully coherent so we don't need to define ARCH_DMA_MINALIGN.
 */
#ifndef __tilegx__
#define ARCH_DMA_MINALIGN	L2_CACHE_BYTES
#endif

/* use the cache line size for the L2, which is where it counts */
#define SMP_CACHE_BYTES_SHIFT	L2_CACHE_SHIFT
#define SMP_CACHE_BYTES		L2_CACHE_BYTES
#define INTERNODE_CACHE_SHIFT   L2_CACHE_SHIFT
#define INTERNODE_CACHE_BYTES   L2_CACHE_BYTES

/* Group together read-mostly things to avoid cache false sharing */
#define __read_mostly __attribute__((__section__(".data.read_mostly")))

/*
 * Attribute for data that is kept read/write coherent until the end of
 * initialization, then bumped to read/only incoherent for performance.
 */
#define __write_once __attribute__((__section__(".w1data")))

#endif /* _ASM_TILE_CACHE_H */
Commit	Line	Data
867e359b CM	1	/*
	2	* Copyright 2010 Tilera Corporation. All Rights Reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation, version 2.
	7	*
	8	* This program is distributed in the hope that it will be useful, but
	9	* WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
	11	* NON INFRINGEMENT. See the GNU General Public License for
	12	* more details.
	13	*/
	14
	15	#ifndef _ASM_TILE_CACHE_H
	16	#define _ASM_TILE_CACHE_H
	17
	18	#include <arch/chip.h>
	19
	20	/* bytes per L1 data cache line */
	21	#define L1_CACHE_SHIFT CHIP_L1D_LOG_LINE_SIZE()
	22	#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
867e359b	23
867e359b CM	24	/* bytes per L2 cache line */
	25	#define L2_CACHE_SHIFT CHIP_L2_LOG_LINE_SIZE()
	26	#define L2_CACHE_BYTES (1 << L2_CACHE_SHIFT)
	27	#define L2_CACHE_ALIGN(x) (((x)+(L2_CACHE_BYTES-1)) & -L2_CACHE_BYTES)
	28
c6673cb5	29	/*
b3ae98ab	30	* TILE-Gx is fully coherent so we don't need to define ARCH_DMA_MINALIGN.
c6673cb5 FT	31	*/
c6673cb5 FT	32	#ifndef __tilegx__
b3ae98ab	33	#define ARCH_DMA_MINALIGN L2_CACHE_BYTES
c6673cb5 FT	34	#endif
c6673cb5 FT	35
867e359b CM	36	/* use the cache line size for the L2, which is where it counts */
	37	#define SMP_CACHE_BYTES_SHIFT L2_CACHE_SHIFT
	38	#define SMP_CACHE_BYTES L2_CACHE_BYTES
	39	#define INTERNODE_CACHE_SHIFT L2_CACHE_SHIFT
	40	#define INTERNODE_CACHE_BYTES L2_CACHE_BYTES
	41
	42	/* Group together read-mostly things to avoid cache false sharing */
	43	#define __read_mostly __attribute__((__section__(".data.read_mostly")))
	44
	45	/*
	46	* Attribute for data that is kept read/write coherent until the end of
	47	* initialization, then bumped to read/only incoherent for performance.
	48	*/
	49	#define __write_once __attribute__((__section__(".w1data")))
	50
	51	#endif /* _ASM_TILE_CACHE_H */