[net-next-2.6.git] / arch / tile / include / arch / chip_tile64.h

/*
 * Copyright 2010 Tilera Corporation. All Rights Reserved.
 *
 *   This program is free software; you can redistribute it and/or
 *   modify it under the terms of the GNU General Public License
 *   as published by the Free Software Foundation, version 2.
 *
 *   This program is distributed in the hope that it will be useful, but
 *   WITHOUT ANY WARRANTY; without even the implied warranty of
 *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 *   NON INFRINGEMENT.  See the GNU General Public License for
 *   more details.
 */

/*
 * @file
 * Global header file.
 * This header file specifies defines for TILE64.
 */

#ifndef __ARCH_CHIP_H__
#define __ARCH_CHIP_H__

/** Specify chip version.
 * When possible, prefer the CHIP_xxx symbols below for future-proofing.
 * This is intended for cross-compiling; native compilation should
 * use the predefined __tile_chip__ symbol.
 */
#define TILE_CHIP 0

/** Specify chip revision.
 * This provides for the case of a respin of a particular chip type;
 * the normal value for this symbol is "0".
 * This is intended for cross-compiling; native compilation should
 * use the predefined __tile_chip_rev__ symbol.
 */
#define TILE_CHIP_REV 0

/** The name of this architecture. */
#define CHIP_ARCH_NAME "tile64"

/** The ELF e_machine type for binaries for this chip. */
#define CHIP_ELF_TYPE() EM_TILE64

/** The alternate ELF e_machine type for binaries for this chip. */
#define CHIP_COMPAT_ELF_TYPE() 0x2506

/** What is the native word size of the machine? */
#define CHIP_WORD_SIZE() 32

/** How many bits of a virtual address are used. Extra bits must be
 * the sign extension of the low bits.
 */
#define CHIP_VA_WIDTH() 32

/** How many bits are in a physical address? */
#define CHIP_PA_WIDTH() 36

/** Size of the L2 cache, in bytes. */
#define CHIP_L2_CACHE_SIZE() 65536

/** Log size of an L2 cache line in bytes. */
#define CHIP_L2_LOG_LINE_SIZE() 6

/** Size of an L2 cache line, in bytes. */
#define CHIP_L2_LINE_SIZE() (1 << CHIP_L2_LOG_LINE_SIZE())

/** Associativity of the L2 cache. */
#define CHIP_L2_ASSOC() 2

/** Size of the L1 data cache, in bytes. */
#define CHIP_L1D_CACHE_SIZE() 8192

/** Log size of an L1 data cache line in bytes. */
#define CHIP_L1D_LOG_LINE_SIZE() 4

/** Size of an L1 data cache line, in bytes. */
#define CHIP_L1D_LINE_SIZE() (1 << CHIP_L1D_LOG_LINE_SIZE())

/** Associativity of the L1 data cache. */
#define CHIP_L1D_ASSOC() 2

/** Size of the L1 instruction cache, in bytes. */
#define CHIP_L1I_CACHE_SIZE() 8192

/** Log size of an L1 instruction cache line in bytes. */
#define CHIP_L1I_LOG_LINE_SIZE() 6

/** Size of an L1 instruction cache line, in bytes. */
#define CHIP_L1I_LINE_SIZE() (1 << CHIP_L1I_LOG_LINE_SIZE())

/** Associativity of the L1 instruction cache. */
#define CHIP_L1I_ASSOC() 1

/** Stride with which flush instructions must be issued. */
#define CHIP_FLUSH_STRIDE() CHIP_L2_LINE_SIZE()

/** Stride with which inv instructions must be issued. */
#define CHIP_INV_STRIDE() CHIP_L1D_LINE_SIZE()

/** Stride with which finv instructions must be issued. */
#define CHIP_FINV_STRIDE() CHIP_L1D_LINE_SIZE()

/** Can the local cache coherently cache data that is homed elsewhere? */
#define CHIP_HAS_COHERENT_LOCAL_CACHE() 0

/** How many simultaneous outstanding victims can the L2 cache have? */
#define CHIP_MAX_OUTSTANDING_VICTIMS() 2

/** Does the TLB support the NC and NOALLOC bits? */
#define CHIP_HAS_NC_AND_NOALLOC_BITS() 0

/** Does the chip support hash-for-home caching? */
#define CHIP_HAS_CBOX_HOME_MAP() 0

/** Number of entries in the chip's home map tables. */
/* #define CHIP_CBOX_HOME_MAP_SIZE() -- does not apply to chip 0 */

/** Do uncacheable requests miss in the cache regardless of whether
 * there is matching data? */
#define CHIP_HAS_ENFORCED_UNCACHEABLE_REQUESTS() 0

/** Does the mf instruction wait for victims? */
#define CHIP_HAS_MF_WAITS_FOR_VICTIMS() 1

/** Does the chip have an "inv" instruction that doesn't also flush? */
#define CHIP_HAS_INV() 0

/** Does the chip have a "wh64" instruction? */
#define CHIP_HAS_WH64() 0

/** Does this chip have a 'dword_align' instruction? */
#define CHIP_HAS_DWORD_ALIGN() 0

/** Number of performance counters. */
#define CHIP_PERFORMANCE_COUNTERS() 2

/** Does this chip have auxiliary performance counters? */
#define CHIP_HAS_AUX_PERF_COUNTERS() 0

/** Is the CBOX_MSR1 SPR supported? */
#define CHIP_HAS_CBOX_MSR1() 0

/** Is the TILE_RTF_HWM SPR supported? */
#define CHIP_HAS_TILE_RTF_HWM() 0

/** Is the TILE_WRITE_PENDING SPR supported? */
#define CHIP_HAS_TILE_WRITE_PENDING() 0

/** Is the PROC_STATUS SPR supported? */
#define CHIP_HAS_PROC_STATUS_SPR() 0

/** Is the DSTREAM_PF SPR supported? */
#define CHIP_HAS_DSTREAM_PF() 0

/** Log of the number of mshims we have. */
#define CHIP_LOG_NUM_MSHIMS() 2

/** Are the bases of the interrupt vector areas fixed? */
#define CHIP_HAS_FIXED_INTVEC_BASE() 1

/** Are the interrupt masks split up into 2 SPRs? */
#define CHIP_HAS_SPLIT_INTR_MASK() 1

/** Is the cycle count split up into 2 SPRs? */
#define CHIP_HAS_SPLIT_CYCLE() 1

/** Does the chip have a static network? */
#define CHIP_HAS_SN() 1

/** Does the chip have a static network processor? */
#define CHIP_HAS_SN_PROC() 1

/** Size of the L1 static network processor instruction cache, in bytes. */
#define CHIP_L1SNI_CACHE_SIZE() 2048

/** Does the chip have DMA support in each tile? */
#define CHIP_HAS_TILE_DMA() 1

/** Does the chip have the second revision of the directly accessible
 *  dynamic networks?  This encapsulates a number of characteristics,
 *  including the absence of the catch-all, the absence of inline message
 *  tags, the absence of support for network context-switching, and so on.
 */
#define CHIP_HAS_REV1_XDN() 0

/** Does the chip have cmpexch and similar (fetchadd, exch, etc.)? */
#define CHIP_HAS_CMPEXCH() 0

/** Does the chip have memory-mapped I/O support? */
#define CHIP_HAS_MMIO() 0

/** Does the chip have post-completion interrupts? */
#define CHIP_HAS_POST_COMPLETION_INTERRUPTS() 0

/** Does the chip have native single step support? */
#define CHIP_HAS_SINGLE_STEP() 0

#ifndef __OPEN_SOURCE__  /* features only relevant to hypervisor-level code */

/** How many entries are present in the instruction TLB? */
#define CHIP_ITLB_ENTRIES() 8

/** How many entries are present in the data TLB? */
#define CHIP_DTLB_ENTRIES() 16

/** How many MAF entries does the XAUI shim have? */
#define CHIP_XAUI_MAF_ENTRIES() 16

/** Does the memory shim have a source-id table? */
#define CHIP_HAS_MSHIM_SRCID_TABLE() 1

/** Does the L1 instruction cache clear on reset? */
#define CHIP_HAS_L1I_CLEAR_ON_RESET() 0

/** Does the chip come out of reset with valid coordinates on all tiles?
 * Note that if defined, this also implies that the upper left is 1,1.
 */
#define CHIP_HAS_VALID_TILE_COORD_RESET() 0

/** Does the chip have unified packet formats? */
#define CHIP_HAS_UNIFIED_PACKET_FORMATS() 0

/** Does the chip support write reordering? */
#define CHIP_HAS_WRITE_REORDERING() 0

/** Does the chip support Y-X routing as well as X-Y? */
#define CHIP_HAS_Y_X_ROUTING() 0

/** Is INTCTRL_3 managed with the correct MPL? */
#define CHIP_HAS_INTCTRL_3_STATUS_FIX() 0

/** Is it possible to configure the chip to be big-endian? */
#define CHIP_HAS_BIG_ENDIAN_CONFIG() 0

/** Is the CACHE_RED_WAY_OVERRIDDEN SPR supported? */
#define CHIP_HAS_CACHE_RED_WAY_OVERRIDDEN() 0

/** Is the DIAG_TRACE_WAY SPR supported? */
#define CHIP_HAS_DIAG_TRACE_WAY() 0

/** Is the MEM_STRIPE_CONFIG SPR supported? */
#define CHIP_HAS_MEM_STRIPE_CONFIG() 0

/** Are the TLB_PERF SPRs supported? */
#define CHIP_HAS_TLB_PERF() 0

/** Is the VDN_SNOOP_SHIM_CTL SPR supported? */
#define CHIP_HAS_VDN_SNOOP_SHIM_CTL() 0

/** Does the chip support rev1 DMA packets? */
#define CHIP_HAS_REV1_DMA_PACKETS() 0

/** Does the chip have an IPI shim? */
#define CHIP_HAS_IPI() 0

#endif /* !__OPEN_SOURCE__ */
#endif /* __ARCH_CHIP_H__ */
Commit	Line	Data
867e359b CM	1	/*
	2	* Copyright 2010 Tilera Corporation. All Rights Reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation, version 2.
	7	*
	8	* This program is distributed in the hope that it will be useful, but
	9	* WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
	11	* NON INFRINGEMENT. See the GNU General Public License for
	12	* more details.
	13	*/
	14
	15	/*
	16	* @file
	17	* Global header file.
	18	* This header file specifies defines for TILE64.
	19	*/
	20
	21	#ifndef __ARCH_CHIP_H__
	22	#define __ARCH_CHIP_H__
	23
	24	/** Specify chip version.
	25	* When possible, prefer the CHIP_xxx symbols below for future-proofing.
	26	* This is intended for cross-compiling; native compilation should
	27	* use the predefined __tile_chip__ symbol.
	28	*/
	29	#define TILE_CHIP 0
	30
	31	/** Specify chip revision.
	32	* This provides for the case of a respin of a particular chip type;
	33	* the normal value for this symbol is "0".
	34	* This is intended for cross-compiling; native compilation should
	35	* use the predefined __tile_chip_rev__ symbol.
	36	*/
	37	#define TILE_CHIP_REV 0
	38
	39	/** The name of this architecture. */
	40	#define CHIP_ARCH_NAME "tile64"
	41
	42	/** The ELF e_machine type for binaries for this chip. */
	43	#define CHIP_ELF_TYPE() EM_TILE64
	44
	45	/** The alternate ELF e_machine type for binaries for this chip. */
	46	#define CHIP_COMPAT_ELF_TYPE() 0x2506
	47
	48	/** What is the native word size of the machine? */
	49	#define CHIP_WORD_SIZE() 32
	50
	51	/** How many bits of a virtual address are used. Extra bits must be
	52	* the sign extension of the low bits.
	53	*/
	54	#define CHIP_VA_WIDTH() 32
	55
	56	/** How many bits are in a physical address? */
	57	#define CHIP_PA_WIDTH() 36
	58
	59	/** Size of the L2 cache, in bytes. */
	60	#define CHIP_L2_CACHE_SIZE() 65536
	61
	62	/** Log size of an L2 cache line in bytes. */
	63	#define CHIP_L2_LOG_LINE_SIZE() 6
	64
65	/** Size of an L2 cache line, in bytes. */
66	#define CHIP_L2_LINE_SIZE() (1 << CHIP_L2_LOG_LINE_SIZE())
67
68	/** Associativity of the L2 cache. */
69	#define CHIP_L2_ASSOC() 2
70
71	/** Size of the L1 data cache, in bytes. */
72	#define CHIP_L1D_CACHE_SIZE() 8192
73
74	/** Log size of an L1 data cache line in bytes. */
75	#define CHIP_L1D_LOG_LINE_SIZE() 4
76
77	/** Size of an L1 data cache line, in bytes. */
78	#define CHIP_L1D_LINE_SIZE() (1 << CHIP_L1D_LOG_LINE_SIZE())
79
80	/** Associativity of the L1 data cache. */
81	#define CHIP_L1D_ASSOC() 2
82
83	/** Size of the L1 instruction cache, in bytes. */
84	#define CHIP_L1I_CACHE_SIZE() 8192
85
86	/** Log size of an L1 instruction cache line in bytes. */
87	#define CHIP_L1I_LOG_LINE_SIZE() 6
88
89	/** Size of an L1 instruction cache line, in bytes. */
90	#define CHIP_L1I_LINE_SIZE() (1 << CHIP_L1I_LOG_LINE_SIZE())
91
92	/** Associativity of the L1 instruction cache. */
93	#define CHIP_L1I_ASSOC() 1
94
95	/** Stride with which flush instructions must be issued. */
96	#define CHIP_FLUSH_STRIDE() CHIP_L2_LINE_SIZE()
97
98	/** Stride with which inv instructions must be issued. */
99	#define CHIP_INV_STRIDE() CHIP_L1D_LINE_SIZE()
100
101	/** Stride with which finv instructions must be issued. */
102	#define CHIP_FINV_STRIDE() CHIP_L1D_LINE_SIZE()
103
104	/** Can the local cache coherently cache data that is homed elsewhere? */
105	#define CHIP_HAS_COHERENT_LOCAL_CACHE() 0
106
107	/** How many simultaneous outstanding victims can the L2 cache have? */
108	#define CHIP_MAX_OUTSTANDING_VICTIMS() 2
109
110	/** Does the TLB support the NC and NOALLOC bits? */
111	#define CHIP_HAS_NC_AND_NOALLOC_BITS() 0
112
113	/** Does the chip support hash-for-home caching? */
114	#define CHIP_HAS_CBOX_HOME_MAP() 0
115
116	/** Number of entries in the chip's home map tables. */
117	/* #define CHIP_CBOX_HOME_MAP_SIZE() -- does not apply to chip 0 */
118
119	/** Do uncacheable requests miss in the cache regardless of whether
120	* there is matching data? */
121	#define CHIP_HAS_ENFORCED_UNCACHEABLE_REQUESTS() 0
122
123	/** Does the mf instruction wait for victims? */
124	#define CHIP_HAS_MF_WAITS_FOR_VICTIMS() 1
125
126	/** Does the chip have an "inv" instruction that doesn't also flush? */
127	#define CHIP_HAS_INV() 0
128
129	/** Does the chip have a "wh64" instruction? */
130	#define CHIP_HAS_WH64() 0
131
132	/** Does this chip have a 'dword_align' instruction? */
133	#define CHIP_HAS_DWORD_ALIGN() 0
134
135	/** Number of performance counters. */
136	#define CHIP_PERFORMANCE_COUNTERS() 2
137
138	/** Does this chip have auxiliary performance counters? */
139	#define CHIP_HAS_AUX_PERF_COUNTERS() 0
140
141	/** Is the CBOX_MSR1 SPR supported? */
142	#define CHIP_HAS_CBOX_MSR1() 0
143
144	/** Is the TILE_RTF_HWM SPR supported? */
145	#define CHIP_HAS_TILE_RTF_HWM() 0
146
147	/** Is the TILE_WRITE_PENDING SPR supported? */
148	#define CHIP_HAS_TILE_WRITE_PENDING() 0
149
150	/** Is the PROC_STATUS SPR supported? */
151	#define CHIP_HAS_PROC_STATUS_SPR() 0
152
a802fc68 CM	153	/** Is the DSTREAM_PF SPR supported? */
	154	#define CHIP_HAS_DSTREAM_PF() 0
	155
867e359b CM	156	/** Log of the number of mshims we have. */
	157	#define CHIP_LOG_NUM_MSHIMS() 2
	158
	159	/** Are the bases of the interrupt vector areas fixed? */
	160	#define CHIP_HAS_FIXED_INTVEC_BASE() 1
	161
	162	/** Are the interrupt masks split up into 2 SPRs? */
	163	#define CHIP_HAS_SPLIT_INTR_MASK() 1
	164
	165	/** Is the cycle count split up into 2 SPRs? */
	166	#define CHIP_HAS_SPLIT_CYCLE() 1
	167
	168	/** Does the chip have a static network? */
	169	#define CHIP_HAS_SN() 1
	170
	171	/** Does the chip have a static network processor? */
	172	#define CHIP_HAS_SN_PROC() 1
	173
	174	/** Size of the L1 static network processor instruction cache, in bytes. */
	175	#define CHIP_L1SNI_CACHE_SIZE() 2048
	176
	177	/** Does the chip have DMA support in each tile? */
	178	#define CHIP_HAS_TILE_DMA() 1
	179
	180	/** Does the chip have the second revision of the directly accessible
	181	* dynamic networks? This encapsulates a number of characteristics,
	182	* including the absence of the catch-all, the absence of inline message
	183	* tags, the absence of support for network context-switching, and so on.
	184	*/
	185	#define CHIP_HAS_REV1_XDN() 0
	186
	187	/** Does the chip have cmpexch and similar (fetchadd, exch, etc.)? */
	188	#define CHIP_HAS_CMPEXCH() 0
	189
	190	/** Does the chip have memory-mapped I/O support? */
	191	#define CHIP_HAS_MMIO() 0
	192
	193	/** Does the chip have post-completion interrupts? */
	194	#define CHIP_HAS_POST_COMPLETION_INTERRUPTS() 0
	195
	196	/** Does the chip have native single step support? */
	197	#define CHIP_HAS_SINGLE_STEP() 0
	198
	199	#ifndef __OPEN_SOURCE__ /* features only relevant to hypervisor-level code */
	200
	201	/** How many entries are present in the instruction TLB? */
	202	#define CHIP_ITLB_ENTRIES() 8
	203
	204	/** How many entries are present in the data TLB? */
	205	#define CHIP_DTLB_ENTRIES() 16
	206
	207	/** How many MAF entries does the XAUI shim have? */
	208	#define CHIP_XAUI_MAF_ENTRIES() 16
	209
	210	/** Does the memory shim have a source-id table? */
	211	#define CHIP_HAS_MSHIM_SRCID_TABLE() 1
	212
	213	/** Does the L1 instruction cache clear on reset? */
	214	#define CHIP_HAS_L1I_CLEAR_ON_RESET() 0
	215
	216	/** Does the chip come out of reset with valid coordinates on all tiles?
	217	* Note that if defined, this also implies that the upper left is 1,1.
	218	*/
	219	#define CHIP_HAS_VALID_TILE_COORD_RESET() 0
220
221	/** Does the chip have unified packet formats? */
222	#define CHIP_HAS_UNIFIED_PACKET_FORMATS() 0
223
224	/** Does the chip support write reordering? */
225	#define CHIP_HAS_WRITE_REORDERING() 0
226
227	/** Does the chip support Y-X routing as well as X-Y? */
228	#define CHIP_HAS_Y_X_ROUTING() 0
229
230	/** Is INTCTRL_3 managed with the correct MPL? */
231	#define CHIP_HAS_INTCTRL_3_STATUS_FIX() 0
232
233	/** Is it possible to configure the chip to be big-endian? */
234	#define CHIP_HAS_BIG_ENDIAN_CONFIG() 0
235
236	/** Is the CACHE_RED_WAY_OVERRIDDEN SPR supported? */
237	#define CHIP_HAS_CACHE_RED_WAY_OVERRIDDEN() 0
238
239	/** Is the DIAG_TRACE_WAY SPR supported? */
240	#define CHIP_HAS_DIAG_TRACE_WAY() 0
241
242	/** Is the MEM_STRIPE_CONFIG SPR supported? */
243	#define CHIP_HAS_MEM_STRIPE_CONFIG() 0
244
245	/** Are the TLB_PERF SPRs supported? */
246	#define CHIP_HAS_TLB_PERF() 0
247
248	/** Is the VDN_SNOOP_SHIM_CTL SPR supported? */
249	#define CHIP_HAS_VDN_SNOOP_SHIM_CTL() 0
250
251	/** Does the chip support rev1 DMA packets? */
252	#define CHIP_HAS_REV1_DMA_PACKETS() 0
253
fb702b94 CM	254	/** Does the chip have an IPI shim? */
	255	#define CHIP_HAS_IPI() 0
	256
867e359b CM	257	#endif /* !__OPEN_SOURCE__ */
867e359b CM	258	#endif /* __ARCH_CHIP_H__ */