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Commit | Line | Data |
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1da177e4 | 1 | /* |
54dfe5dd | 2 | * arch/s390/kernel/entry64.S |
1da177e4 LT |
3 | * S390 low-level entry points. |
4 | * | |
cd3b70f5 | 5 | * Copyright (C) IBM Corp. 1999,2010 |
1da177e4 | 6 | * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com), |
25d83cbf HC |
7 | * Hartmut Penner (hp@de.ibm.com), |
8 | * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com), | |
77fa2245 | 9 | * Heiko Carstens <heiko.carstens@de.ibm.com> |
1da177e4 LT |
10 | */ |
11 | ||
1da177e4 | 12 | #include <linux/linkage.h> |
2bc89b5e | 13 | #include <linux/init.h> |
1da177e4 | 14 | #include <asm/cache.h> |
1da177e4 LT |
15 | #include <asm/errno.h> |
16 | #include <asm/ptrace.h> | |
17 | #include <asm/thread_info.h> | |
0013a854 | 18 | #include <asm/asm-offsets.h> |
1da177e4 LT |
19 | #include <asm/unistd.h> |
20 | #include <asm/page.h> | |
21 | ||
22 | /* | |
23 | * Stack layout for the system_call stack entry. | |
24 | * The first few entries are identical to the user_regs_struct. | |
25 | */ | |
25d83cbf HC |
26 | SP_PTREGS = STACK_FRAME_OVERHEAD |
27 | SP_ARGS = STACK_FRAME_OVERHEAD + __PT_ARGS | |
28 | SP_PSW = STACK_FRAME_OVERHEAD + __PT_PSW | |
29 | SP_R0 = STACK_FRAME_OVERHEAD + __PT_GPRS | |
30 | SP_R1 = STACK_FRAME_OVERHEAD + __PT_GPRS + 8 | |
31 | SP_R2 = STACK_FRAME_OVERHEAD + __PT_GPRS + 16 | |
32 | SP_R3 = STACK_FRAME_OVERHEAD + __PT_GPRS + 24 | |
33 | SP_R4 = STACK_FRAME_OVERHEAD + __PT_GPRS + 32 | |
34 | SP_R5 = STACK_FRAME_OVERHEAD + __PT_GPRS + 40 | |
35 | SP_R6 = STACK_FRAME_OVERHEAD + __PT_GPRS + 48 | |
36 | SP_R7 = STACK_FRAME_OVERHEAD + __PT_GPRS + 56 | |
37 | SP_R8 = STACK_FRAME_OVERHEAD + __PT_GPRS + 64 | |
38 | SP_R9 = STACK_FRAME_OVERHEAD + __PT_GPRS + 72 | |
39 | SP_R10 = STACK_FRAME_OVERHEAD + __PT_GPRS + 80 | |
40 | SP_R11 = STACK_FRAME_OVERHEAD + __PT_GPRS + 88 | |
41 | SP_R12 = STACK_FRAME_OVERHEAD + __PT_GPRS + 96 | |
42 | SP_R13 = STACK_FRAME_OVERHEAD + __PT_GPRS + 104 | |
43 | SP_R14 = STACK_FRAME_OVERHEAD + __PT_GPRS + 112 | |
44 | SP_R15 = STACK_FRAME_OVERHEAD + __PT_GPRS + 120 | |
45 | SP_ORIG_R2 = STACK_FRAME_OVERHEAD + __PT_ORIG_GPR2 | |
46 | SP_ILC = STACK_FRAME_OVERHEAD + __PT_ILC | |
59da2139 | 47 | SP_SVCNR = STACK_FRAME_OVERHEAD + __PT_SVCNR |
25d83cbf | 48 | SP_SIZE = STACK_FRAME_OVERHEAD + __PT_SIZE |
1da177e4 LT |
49 | |
50 | STACK_SHIFT = PAGE_SHIFT + THREAD_ORDER | |
51 | STACK_SIZE = 1 << STACK_SHIFT | |
52 | ||
753c4dd6 | 53 | _TIF_WORK_SVC = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \ |
54dfe5dd | 54 | _TIF_MCCK_PENDING | _TIF_RESTART_SVC | _TIF_SINGLE_STEP ) |
753c4dd6 | 55 | _TIF_WORK_INT = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \ |
54dfe5dd | 56 | _TIF_MCCK_PENDING) |
9bf1226b | 57 | _TIF_SYSCALL = (_TIF_SYSCALL_TRACE>>8 | _TIF_SYSCALL_AUDIT>>8 | \ |
66700001 | 58 | _TIF_SECCOMP>>8 | _TIF_SYSCALL_TRACEPOINT>>8) |
1da177e4 LT |
59 | |
60 | #define BASED(name) name-system_call(%r13) | |
61 | ||
cd3b70f5 CO |
62 | .macro HANDLE_SIE_INTERCEPT |
63 | #if defined(CONFIG_KVM) || defined(CONFIG_KVM_MODULE) | |
64 | lg %r3,__LC_SIE_HOOK | |
65 | ltgr %r3,%r3 | |
66 | jz 0f | |
67 | basr %r14,%r3 | |
2ffbb3f6 | 68 | 0: |
cd3b70f5 CO |
69 | #endif |
70 | .endm | |
71 | ||
1f194a4c HC |
72 | #ifdef CONFIG_TRACE_IRQFLAGS |
73 | .macro TRACE_IRQS_ON | |
6a2df3a8 MS |
74 | basr %r2,%r0 |
75 | brasl %r14,trace_hardirqs_on_caller | |
1f194a4c HC |
76 | .endm |
77 | ||
78 | .macro TRACE_IRQS_OFF | |
6a2df3a8 MS |
79 | basr %r2,%r0 |
80 | brasl %r14,trace_hardirqs_off_caller | |
1f194a4c | 81 | .endm |
523b44cf | 82 | |
6a2df3a8 | 83 | .macro TRACE_IRQS_CHECK_ON |
411788ea HC |
84 | tm SP_PSW(%r15),0x03 # irqs enabled? |
85 | jz 0f | |
6a2df3a8 MS |
86 | TRACE_IRQS_ON |
87 | 0: | |
88 | .endm | |
89 | ||
90 | .macro TRACE_IRQS_CHECK_OFF | |
91 | tm SP_PSW(%r15),0x03 # irqs enabled? | |
92 | jz 0f | |
93 | TRACE_IRQS_OFF | |
94 | 0: | |
523b44cf | 95 | .endm |
1f194a4c HC |
96 | #else |
97 | #define TRACE_IRQS_ON | |
98 | #define TRACE_IRQS_OFF | |
6a2df3a8 MS |
99 | #define TRACE_IRQS_CHECK_ON |
100 | #define TRACE_IRQS_CHECK_OFF | |
411788ea HC |
101 | #endif |
102 | ||
103 | #ifdef CONFIG_LOCKDEP | |
104 | .macro LOCKDEP_SYS_EXIT | |
105 | tm SP_PSW+1(%r15),0x01 # returning to user ? | |
106 | jz 0f | |
107 | brasl %r14,lockdep_sys_exit | |
108 | 0: | |
109 | .endm | |
110 | #else | |
523b44cf | 111 | #define LOCKDEP_SYS_EXIT |
1f194a4c HC |
112 | #endif |
113 | ||
25d83cbf | 114 | .macro UPDATE_VTIME lc_from,lc_to,lc_sum |
1da177e4 LT |
115 | lg %r10,\lc_from |
116 | slg %r10,\lc_to | |
117 | alg %r10,\lc_sum | |
118 | stg %r10,\lc_sum | |
119 | .endm | |
1da177e4 LT |
120 | |
121 | /* | |
122 | * Register usage in interrupt handlers: | |
123 | * R9 - pointer to current task structure | |
124 | * R13 - pointer to literal pool | |
125 | * R14 - return register for function calls | |
126 | * R15 - kernel stack pointer | |
127 | */ | |
128 | ||
987ad70a | 129 | .macro SAVE_ALL_SVC psworg,savearea |
86f2552b | 130 | stmg %r11,%r15,\savearea |
987ad70a | 131 | lg %r15,__LC_KERNEL_STACK # problem state -> load ksp |
86f2552b MS |
132 | aghi %r15,-SP_SIZE # make room for registers & psw |
133 | lg %r11,__LC_LAST_BREAK | |
987ad70a MS |
134 | .endm |
135 | ||
86f2552b MS |
136 | .macro SAVE_ALL_PGM psworg,savearea |
137 | stmg %r11,%r15,\savearea | |
1da177e4 | 138 | tm \psworg+1,0x01 # test problem state bit |
63b12246 | 139 | #ifdef CONFIG_CHECK_STACK |
86f2552b MS |
140 | jnz 1f |
141 | tml %r15,STACK_SIZE - CONFIG_STACK_GUARD | |
142 | jnz 2f | |
143 | la %r12,\psworg | |
144 | j stack_overflow | |
145 | #else | |
146 | jz 2f | |
63b12246 | 147 | #endif |
86f2552b MS |
148 | 1: lg %r15,__LC_KERNEL_STACK # problem state -> load ksp |
149 | 2: aghi %r15,-SP_SIZE # make room for registers & psw | |
150 | larl %r13,system_call | |
151 | lg %r11,__LC_LAST_BREAK | |
63b12246 MS |
152 | .endm |
153 | ||
154 | .macro SAVE_ALL_ASYNC psworg,savearea | |
86f2552b MS |
155 | stmg %r11,%r15,\savearea |
156 | larl %r13,system_call | |
157 | lg %r11,__LC_LAST_BREAK | |
63b12246 | 158 | la %r12,\psworg |
1da177e4 LT |
159 | tm \psworg+1,0x01 # test problem state bit |
160 | jnz 1f # from user -> load kernel stack | |
161 | clc \psworg+8(8),BASED(.Lcritical_end) | |
162 | jhe 0f | |
163 | clc \psworg+8(8),BASED(.Lcritical_start) | |
164 | jl 0f | |
165 | brasl %r14,cleanup_critical | |
6add9f7f | 166 | tm 1(%r12),0x01 # retest problem state after cleanup |
1da177e4 LT |
167 | jnz 1f |
168 | 0: lg %r14,__LC_ASYNC_STACK # are we already on the async. stack ? | |
169 | slgr %r14,%r15 | |
170 | srag %r14,%r14,STACK_SHIFT | |
1da177e4 | 171 | #ifdef CONFIG_CHECK_STACK |
86f2552b MS |
172 | jnz 1f |
173 | tml %r15,STACK_SIZE - CONFIG_STACK_GUARD | |
174 | jnz 2f | |
175 | j stack_overflow | |
176 | #else | |
177 | jz 2f | |
1da177e4 | 178 | #endif |
86f2552b MS |
179 | 1: lg %r15,__LC_ASYNC_STACK # load async stack |
180 | 2: aghi %r15,-SP_SIZE # make room for registers & psw | |
77fa2245 HC |
181 | .endm |
182 | ||
86f2552b MS |
183 | .macro CREATE_STACK_FRAME savearea |
184 | xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) | |
1da177e4 | 185 | stg %r2,SP_ORIG_R2(%r15) # store original content of gpr 2 |
86f2552b MS |
186 | mvc SP_R11(40,%r15),\savearea # move %r11-%r15 to stack |
187 | stmg %r0,%r10,SP_R0(%r15) # store gprs %r0-%r10 to kernel stack | |
25d83cbf | 188 | .endm |
1da177e4 | 189 | |
ae6aa2ea MS |
190 | .macro RESTORE_ALL psworg,sync |
191 | mvc \psworg(16),SP_PSW(%r15) # move user PSW to lowcore | |
1da177e4 | 192 | .if !\sync |
ae6aa2ea | 193 | ni \psworg+1,0xfd # clear wait state bit |
1da177e4 | 194 | .endif |
c742b31c MS |
195 | lg %r14,__LC_VDSO_PER_CPU |
196 | lmg %r0,%r13,SP_R0(%r15) # load gprs 0-13 of user | |
c185b783 | 197 | stpt __LC_EXIT_TIMER |
c742b31c MS |
198 | mvc __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER |
199 | lmg %r14,%r15,SP_R14(%r15) # load grps 14-15 of user | |
ae6aa2ea | 200 | lpswe \psworg # back to caller |
1da177e4 LT |
201 | .endm |
202 | ||
86f2552b MS |
203 | .macro LAST_BREAK |
204 | srag %r10,%r11,23 | |
205 | jz 0f | |
206 | stg %r11,__TI_last_break(%r12) | |
207 | 0: | |
208 | .endm | |
209 | ||
1da177e4 LT |
210 | /* |
211 | * Scheduler resume function, called by switch_to | |
212 | * gpr2 = (task_struct *) prev | |
213 | * gpr3 = (task_struct *) next | |
214 | * Returns: | |
215 | * gpr2 = prev | |
216 | */ | |
25d83cbf | 217 | .globl __switch_to |
1da177e4 LT |
218 | __switch_to: |
219 | tm __THREAD_per+4(%r3),0xe8 # is the new process using per ? | |
220 | jz __switch_to_noper # if not we're fine | |
25d83cbf HC |
221 | stctg %c9,%c11,__SF_EMPTY(%r15)# We are using per stuff |
222 | clc __THREAD_per(24,%r3),__SF_EMPTY(%r15) | |
223 | je __switch_to_noper # we got away without bashing TLB's | |
224 | lctlg %c9,%c11,__THREAD_per(%r3) # Nope we didn't | |
1da177e4 | 225 | __switch_to_noper: |
25d83cbf | 226 | lg %r4,__THREAD_info(%r2) # get thread_info of prev |
77fa2245 HC |
227 | tm __TI_flags+7(%r4),_TIF_MCCK_PENDING # machine check pending? |
228 | jz __switch_to_no_mcck | |
229 | ni __TI_flags+7(%r4),255-_TIF_MCCK_PENDING # clear flag in prev | |
230 | lg %r4,__THREAD_info(%r3) # get thread_info of next | |
231 | oi __TI_flags+7(%r4),_TIF_MCCK_PENDING # set it in next | |
232 | __switch_to_no_mcck: | |
25d83cbf | 233 | stmg %r6,%r15,__SF_GPRS(%r15)# store __switch_to registers of prev task |
1da177e4 LT |
234 | stg %r15,__THREAD_ksp(%r2) # store kernel stack to prev->tss.ksp |
235 | lg %r15,__THREAD_ksp(%r3) # load kernel stack from next->tss.ksp | |
25d83cbf | 236 | lmg %r6,%r15,__SF_GPRS(%r15)# load __switch_to registers of next task |
1da177e4 LT |
237 | stg %r3,__LC_CURRENT # __LC_CURRENT = current task struct |
238 | lctl %c4,%c4,__TASK_pid(%r3) # load pid to control reg. 4 | |
25d83cbf | 239 | lg %r3,__THREAD_info(%r3) # load thread_info from task struct |
1da177e4 LT |
240 | stg %r3,__LC_THREAD_INFO |
241 | aghi %r3,STACK_SIZE | |
242 | stg %r3,__LC_KERNEL_STACK # __LC_KERNEL_STACK = new kernel stack | |
243 | br %r14 | |
244 | ||
245 | __critical_start: | |
246 | /* | |
247 | * SVC interrupt handler routine. System calls are synchronous events and | |
248 | * are executed with interrupts enabled. | |
249 | */ | |
250 | ||
25d83cbf | 251 | .globl system_call |
1da177e4 | 252 | system_call: |
c185b783 | 253 | stpt __LC_SYNC_ENTER_TIMER |
1da177e4 | 254 | sysc_saveall: |
987ad70a | 255 | SAVE_ALL_SVC __LC_SVC_OLD_PSW,__LC_SAVE_AREA |
86f2552b MS |
256 | CREATE_STACK_FRAME __LC_SAVE_AREA |
257 | mvc SP_PSW(16,%r15),__LC_SVC_OLD_PSW | |
258 | mvc SP_ILC(4,%r15),__LC_SVC_ILC | |
259 | stg %r7,SP_ARGS(%r15) | |
260 | lg %r12,__LC_THREAD_INFO # load pointer to thread_info struct | |
1da177e4 | 261 | sysc_vtime: |
1da177e4 LT |
262 | UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER |
263 | sysc_stime: | |
264 | UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER | |
265 | sysc_update: | |
266 | mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER | |
86f2552b | 267 | LAST_BREAK |
1da177e4 | 268 | sysc_do_svc: |
86f2552b MS |
269 | llgh %r7,SP_SVCNR(%r15) |
270 | slag %r7,%r7,2 # shift and test for svc 0 | |
1da177e4 LT |
271 | jnz sysc_nr_ok |
272 | # svc 0: system call number in %r1 | |
86f2552b MS |
273 | llgfr %r1,%r1 # clear high word in r1 |
274 | cghi %r1,NR_syscalls | |
1da177e4 | 275 | jnl sysc_nr_ok |
86f2552b MS |
276 | sth %r1,SP_SVCNR(%r15) |
277 | slag %r7,%r1,2 # shift and test for svc 0 | |
1da177e4 | 278 | sysc_nr_ok: |
25d83cbf | 279 | larl %r10,sys_call_table |
347a8dc3 | 280 | #ifdef CONFIG_COMPAT |
86f2552b | 281 | tm __TI_flags+5(%r12),(_TIF_31BIT>>16) # running in 31 bit mode ? |
c563077e | 282 | jno sysc_noemu |
25d83cbf | 283 | larl %r10,sys_call_table_emu # use 31 bit emulation system calls |
1da177e4 LT |
284 | sysc_noemu: |
285 | #endif | |
86f2552b | 286 | tm __TI_flags+6(%r12),_TIF_SYSCALL |
25d83cbf HC |
287 | lgf %r8,0(%r7,%r10) # load address of system call routine |
288 | jnz sysc_tracesys | |
289 | basr %r14,%r8 # call sys_xxxx | |
290 | stg %r2,SP_R2(%r15) # store return value (change R2 on stack) | |
1da177e4 LT |
291 | |
292 | sysc_return: | |
6a2df3a8 MS |
293 | LOCKDEP_SYS_EXIT |
294 | sysc_tif: | |
86f2552b | 295 | tm __TI_flags+7(%r12),_TIF_WORK_SVC |
25d83cbf | 296 | jnz sysc_work # there is work to do (signals etc.) |
411788ea | 297 | sysc_restore: |
25d83cbf | 298 | RESTORE_ALL __LC_RETURN_PSW,1 |
411788ea HC |
299 | sysc_done: |
300 | ||
1da177e4 | 301 | # |
43d399d2 | 302 | # There is work to do, but first we need to check if we return to userspace. |
1da177e4 LT |
303 | # |
304 | sysc_work: | |
2688905e MS |
305 | tm SP_PSW+1(%r15),0x01 # returning to user ? |
306 | jno sysc_restore | |
43d399d2 MS |
307 | |
308 | # | |
309 | # One of the work bits is on. Find out which one. | |
310 | # | |
6a2df3a8 | 311 | sysc_work_tif: |
86f2552b | 312 | tm __TI_flags+7(%r12),_TIF_MCCK_PENDING |
77fa2245 | 313 | jo sysc_mcck_pending |
86f2552b | 314 | tm __TI_flags+7(%r12),_TIF_NEED_RESCHED |
1da177e4 | 315 | jo sysc_reschedule |
86f2552b | 316 | tm __TI_flags+7(%r12),_TIF_SIGPENDING |
43d399d2 | 317 | jo sysc_sigpending |
86f2552b | 318 | tm __TI_flags+7(%r12),_TIF_NOTIFY_RESUME |
43d399d2 | 319 | jo sysc_notify_resume |
86f2552b | 320 | tm __TI_flags+7(%r12),_TIF_RESTART_SVC |
1da177e4 | 321 | jo sysc_restart |
86f2552b | 322 | tm __TI_flags+7(%r12),_TIF_SINGLE_STEP |
1da177e4 | 323 | jo sysc_singlestep |
43d399d2 | 324 | j sysc_return # beware of critical section cleanup |
1da177e4 LT |
325 | |
326 | # | |
327 | # _TIF_NEED_RESCHED is set, call schedule | |
25d83cbf HC |
328 | # |
329 | sysc_reschedule: | |
6a2df3a8 MS |
330 | larl %r14,sysc_return |
331 | jg schedule # return point is sysc_return | |
1da177e4 | 332 | |
77fa2245 HC |
333 | # |
334 | # _TIF_MCCK_PENDING is set, call handler | |
335 | # | |
336 | sysc_mcck_pending: | |
6a2df3a8 | 337 | larl %r14,sysc_return |
25d83cbf | 338 | jg s390_handle_mcck # TIF bit will be cleared by handler |
77fa2245 | 339 | |
1da177e4 | 340 | # |
02a029b3 | 341 | # _TIF_SIGPENDING is set, call do_signal |
1da177e4 | 342 | # |
25d83cbf | 343 | sysc_sigpending: |
86f2552b | 344 | ni __TI_flags+7(%r12),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP |
25d83cbf HC |
345 | la %r2,SP_PTREGS(%r15) # load pt_regs |
346 | brasl %r14,do_signal # call do_signal | |
86f2552b | 347 | tm __TI_flags+7(%r12),_TIF_RESTART_SVC |
1da177e4 | 348 | jo sysc_restart |
86f2552b | 349 | tm __TI_flags+7(%r12),_TIF_SINGLE_STEP |
1da177e4 | 350 | jo sysc_singlestep |
6a2df3a8 | 351 | j sysc_return |
1da177e4 | 352 | |
753c4dd6 MS |
353 | # |
354 | # _TIF_NOTIFY_RESUME is set, call do_notify_resume | |
355 | # | |
356 | sysc_notify_resume: | |
357 | la %r2,SP_PTREGS(%r15) # load pt_regs | |
6a2df3a8 | 358 | larl %r14,sysc_return |
753c4dd6 MS |
359 | jg do_notify_resume # call do_notify_resume |
360 | ||
1da177e4 LT |
361 | # |
362 | # _TIF_RESTART_SVC is set, set up registers and restart svc | |
363 | # | |
364 | sysc_restart: | |
86f2552b | 365 | ni __TI_flags+7(%r12),255-_TIF_RESTART_SVC # clear TIF_RESTART_SVC |
25d83cbf | 366 | lg %r7,SP_R2(%r15) # load new svc number |
1da177e4 | 367 | mvc SP_R2(8,%r15),SP_ORIG_R2(%r15) # restore first argument |
25d83cbf | 368 | lmg %r2,%r6,SP_R2(%r15) # load svc arguments |
86f2552b MS |
369 | sth %r7,SP_SVCNR(%r15) |
370 | slag %r7,%r7,2 | |
371 | j sysc_nr_ok # restart svc | |
1da177e4 LT |
372 | |
373 | # | |
374 | # _TIF_SINGLE_STEP is set, call do_single_step | |
375 | # | |
376 | sysc_singlestep: | |
86f2552b | 377 | ni __TI_flags+7(%r12),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP |
59da2139 | 378 | xc SP_SVCNR(2,%r15),SP_SVCNR(%r15) # clear svc number |
1da177e4 | 379 | la %r2,SP_PTREGS(%r15) # address of register-save area |
6a2df3a8 | 380 | larl %r14,sysc_return # load adr. of system return |
1da177e4 LT |
381 | jg do_single_step # branch to do_sigtrap |
382 | ||
1da177e4 | 383 | # |
753c4dd6 MS |
384 | # call tracehook_report_syscall_entry/tracehook_report_syscall_exit before |
385 | # and after the system call | |
1da177e4 LT |
386 | # |
387 | sysc_tracesys: | |
25d83cbf | 388 | la %r2,SP_PTREGS(%r15) # load pt_regs |
1da177e4 | 389 | la %r3,0 |
86f2552b MS |
390 | llgh %r0,SP_SVCNR(%r15) |
391 | stg %r0,SP_R2(%r15) | |
753c4dd6 | 392 | brasl %r14,do_syscall_trace_enter |
1da177e4 | 393 | lghi %r0,NR_syscalls |
753c4dd6 | 394 | clgr %r0,%r2 |
1da177e4 | 395 | jnh sysc_tracenogo |
59da2139 | 396 | sllg %r7,%r2,2 # svc number *4 |
1da177e4 LT |
397 | lgf %r8,0(%r7,%r10) |
398 | sysc_tracego: | |
25d83cbf HC |
399 | lmg %r3,%r6,SP_R3(%r15) |
400 | lg %r2,SP_ORIG_R2(%r15) | |
401 | basr %r14,%r8 # call sys_xxx | |
402 | stg %r2,SP_R2(%r15) # store return value | |
1da177e4 | 403 | sysc_tracenogo: |
86f2552b | 404 | tm __TI_flags+6(%r12),_TIF_SYSCALL |
25d83cbf HC |
405 | jz sysc_return |
406 | la %r2,SP_PTREGS(%r15) # load pt_regs | |
25d83cbf | 407 | larl %r14,sysc_return # return point is sysc_return |
753c4dd6 | 408 | jg do_syscall_trace_exit |
1da177e4 LT |
409 | |
410 | # | |
411 | # a new process exits the kernel with ret_from_fork | |
412 | # | |
25d83cbf | 413 | .globl ret_from_fork |
1da177e4 LT |
414 | ret_from_fork: |
415 | lg %r13,__LC_SVC_NEW_PSW+8 | |
86f2552b | 416 | lg %r12,__LC_THREAD_INFO # load pointer to thread_info struct |
1da177e4 LT |
417 | tm SP_PSW+1(%r15),0x01 # forking a kernel thread ? |
418 | jo 0f | |
419 | stg %r15,SP_R15(%r15) # store stack pointer for new kthread | |
25d83cbf | 420 | 0: brasl %r14,schedule_tail |
1f194a4c | 421 | TRACE_IRQS_ON |
25d83cbf | 422 | stosm 24(%r15),0x03 # reenable interrupts |
8f2961c3 | 423 | j sysc_tracenogo |
1da177e4 LT |
424 | |
425 | # | |
03ff9a23 MS |
426 | # kernel_execve function needs to deal with pt_regs that is not |
427 | # at the usual place | |
1da177e4 | 428 | # |
03ff9a23 MS |
429 | .globl kernel_execve |
430 | kernel_execve: | |
431 | stmg %r12,%r15,96(%r15) | |
432 | lgr %r14,%r15 | |
433 | aghi %r15,-SP_SIZE | |
434 | stg %r14,__SF_BACKCHAIN(%r15) | |
435 | la %r12,SP_PTREGS(%r15) | |
436 | xc 0(__PT_SIZE,%r12),0(%r12) | |
437 | lgr %r5,%r12 | |
438 | brasl %r14,do_execve | |
439 | ltgfr %r2,%r2 | |
440 | je 0f | |
441 | aghi %r15,SP_SIZE | |
442 | lmg %r12,%r15,96(%r15) | |
443 | br %r14 | |
444 | # execve succeeded. | |
445 | 0: stnsm __SF_EMPTY(%r15),0xfc # disable interrupts | |
6a2df3a8 | 446 | # TRACE_IRQS_OFF |
03ff9a23 MS |
447 | lg %r15,__LC_KERNEL_STACK # load ksp |
448 | aghi %r15,-SP_SIZE # make room for registers & psw | |
449 | lg %r13,__LC_SVC_NEW_PSW+8 | |
03ff9a23 | 450 | mvc SP_PTREGS(__PT_SIZE,%r15),0(%r12) # copy pt_regs |
86f2552b | 451 | lg %r12,__LC_THREAD_INFO |
03ff9a23 | 452 | xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) |
6a2df3a8 | 453 | # TRACE_IRQS_ON |
03ff9a23 MS |
454 | stosm __SF_EMPTY(%r15),0x03 # reenable interrupts |
455 | brasl %r14,execve_tail | |
456 | j sysc_return | |
1da177e4 LT |
457 | |
458 | /* | |
459 | * Program check handler routine | |
460 | */ | |
461 | ||
25d83cbf | 462 | .globl pgm_check_handler |
1da177e4 LT |
463 | pgm_check_handler: |
464 | /* | |
465 | * First we need to check for a special case: | |
466 | * Single stepping an instruction that disables the PER event mask will | |
467 | * cause a PER event AFTER the mask has been set. Example: SVC or LPSW. | |
468 | * For a single stepped SVC the program check handler gets control after | |
469 | * the SVC new PSW has been loaded. But we want to execute the SVC first and | |
470 | * then handle the PER event. Therefore we update the SVC old PSW to point | |
471 | * to the pgm_check_handler and branch to the SVC handler after we checked | |
472 | * if we have to load the kernel stack register. | |
473 | * For every other possible cause for PER event without the PER mask set | |
474 | * we just ignore the PER event (FIXME: is there anything we have to do | |
475 | * for LPSW?). | |
476 | */ | |
c185b783 | 477 | stpt __LC_SYNC_ENTER_TIMER |
25d83cbf HC |
478 | tm __LC_PGM_INT_CODE+1,0x80 # check whether we got a per exception |
479 | jnz pgm_per # got per exception -> special case | |
86f2552b MS |
480 | SAVE_ALL_PGM __LC_PGM_OLD_PSW,__LC_SAVE_AREA |
481 | CREATE_STACK_FRAME __LC_SAVE_AREA | |
482 | xc SP_ILC(4,%r15),SP_ILC(%r15) | |
483 | mvc SP_PSW(16,%r15),__LC_PGM_OLD_PSW | |
484 | lg %r12,__LC_THREAD_INFO # load pointer to thread_info struct | |
1da177e4 LT |
485 | tm SP_PSW+1(%r15),0x01 # interrupting from user ? |
486 | jz pgm_no_vtime | |
487 | UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER | |
488 | UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER | |
489 | mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER | |
86f2552b | 490 | LAST_BREAK |
1da177e4 | 491 | pgm_no_vtime: |
cd3b70f5 | 492 | HANDLE_SIE_INTERCEPT |
6a2df3a8 | 493 | TRACE_IRQS_CHECK_OFF |
86f2552b | 494 | stg %r11,SP_ARGS(%r15) |
25d83cbf | 495 | lgf %r3,__LC_PGM_ILC # load program interruption code |
1da177e4 LT |
496 | lghi %r8,0x7f |
497 | ngr %r8,%r3 | |
498 | pgm_do_call: | |
25d83cbf HC |
499 | sll %r8,3 |
500 | larl %r1,pgm_check_table | |
501 | lg %r1,0(%r8,%r1) # load address of handler routine | |
502 | la %r2,SP_PTREGS(%r15) # address of register-save area | |
6a2df3a8 MS |
503 | basr %r14,%r1 # branch to interrupt-handler |
504 | pgm_exit: | |
505 | TRACE_IRQS_CHECK_ON | |
506 | j sysc_return | |
1da177e4 LT |
507 | |
508 | # | |
509 | # handle per exception | |
510 | # | |
511 | pgm_per: | |
25d83cbf HC |
512 | tm __LC_PGM_OLD_PSW,0x40 # test if per event recording is on |
513 | jnz pgm_per_std # ok, normal per event from user space | |
1da177e4 | 514 | # ok its one of the special cases, now we need to find out which one |
25d83cbf HC |
515 | clc __LC_PGM_OLD_PSW(16),__LC_SVC_NEW_PSW |
516 | je pgm_svcper | |
1da177e4 | 517 | # no interesting special case, ignore PER event |
25d83cbf | 518 | lpswe __LC_PGM_OLD_PSW |
1da177e4 LT |
519 | |
520 | # | |
521 | # Normal per exception | |
522 | # | |
523 | pgm_per_std: | |
86f2552b MS |
524 | SAVE_ALL_PGM __LC_PGM_OLD_PSW,__LC_SAVE_AREA |
525 | CREATE_STACK_FRAME __LC_SAVE_AREA | |
526 | mvc SP_PSW(16,%r15),__LC_PGM_OLD_PSW | |
527 | lg %r12,__LC_THREAD_INFO # load pointer to thread_info struct | |
1da177e4 LT |
528 | tm SP_PSW+1(%r15),0x01 # interrupting from user ? |
529 | jz pgm_no_vtime2 | |
530 | UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER | |
531 | UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER | |
532 | mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER | |
86f2552b | 533 | LAST_BREAK |
1da177e4 | 534 | pgm_no_vtime2: |
cd3b70f5 | 535 | HANDLE_SIE_INTERCEPT |
6a2df3a8 | 536 | TRACE_IRQS_CHECK_OFF |
86f2552b | 537 | lg %r1,__TI_task(%r12) |
4ba069b8 MG |
538 | tm SP_PSW+1(%r15),0x01 # kernel per event ? |
539 | jz kernel_per | |
1da177e4 LT |
540 | mvc __THREAD_per+__PER_atmid(2,%r1),__LC_PER_ATMID |
541 | mvc __THREAD_per+__PER_address(8,%r1),__LC_PER_ADDRESS | |
542 | mvc __THREAD_per+__PER_access_id(1,%r1),__LC_PER_ACCESS_ID | |
86f2552b | 543 | oi __TI_flags+7(%r12),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP |
25d83cbf | 544 | lgf %r3,__LC_PGM_ILC # load program interruption code |
1da177e4 | 545 | lghi %r8,0x7f |
25d83cbf | 546 | ngr %r8,%r3 # clear per-event-bit and ilc |
f5cdac27 HC |
547 | je pgm_exit2 |
548 | sll %r8,3 | |
549 | larl %r1,pgm_check_table | |
550 | lg %r1,0(%r8,%r1) # load address of handler routine | |
551 | la %r2,SP_PTREGS(%r15) # address of register-save area | |
552 | basr %r14,%r1 # branch to interrupt-handler | |
553 | pgm_exit2: | |
554 | TRACE_IRQS_ON | |
555 | stosm __SF_EMPTY(%r15),0x03 # reenable interrupts | |
556 | j sysc_return | |
1da177e4 LT |
557 | |
558 | # | |
559 | # it was a single stepped SVC that is causing all the trouble | |
560 | # | |
561 | pgm_svcper: | |
86f2552b MS |
562 | SAVE_ALL_PGM __LC_SVC_OLD_PSW,__LC_SAVE_AREA |
563 | CREATE_STACK_FRAME __LC_SAVE_AREA | |
564 | mvc SP_PSW(16,%r15),__LC_SVC_OLD_PSW | |
565 | mvc SP_ILC(4,%r15),__LC_SVC_ILC | |
566 | lg %r12,__LC_THREAD_INFO # load pointer to thread_info struct | |
1da177e4 LT |
567 | UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER |
568 | UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER | |
569 | mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER | |
86f2552b | 570 | LAST_BREAK |
6a2df3a8 | 571 | TRACE_IRQS_OFF |
86f2552b | 572 | lg %r8,__TI_task(%r12) |
bcc6525f CB |
573 | mvc __THREAD_per+__PER_atmid(2,%r8),__LC_PER_ATMID |
574 | mvc __THREAD_per+__PER_address(8,%r8),__LC_PER_ADDRESS | |
575 | mvc __THREAD_per+__PER_access_id(1,%r8),__LC_PER_ACCESS_ID | |
86f2552b | 576 | oi __TI_flags+7(%r12),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP |
1f194a4c | 577 | TRACE_IRQS_ON |
1da177e4 | 578 | stosm __SF_EMPTY(%r15),0x03 # reenable interrupts |
6a2df3a8 | 579 | lmg %r2,%r6,SP_R2(%r15) # load svc arguments |
1da177e4 LT |
580 | j sysc_do_svc |
581 | ||
4ba069b8 MG |
582 | # |
583 | # per was called from kernel, must be kprobes | |
584 | # | |
585 | kernel_per: | |
59da2139 | 586 | xc SP_SVCNR(2,%r15),SP_SVCNR(%r15) # clear svc number |
4ba069b8 | 587 | la %r2,SP_PTREGS(%r15) # address of register-save area |
6a2df3a8 MS |
588 | brasl %r14,do_single_step |
589 | j pgm_exit | |
4ba069b8 | 590 | |
1da177e4 LT |
591 | /* |
592 | * IO interrupt handler routine | |
593 | */ | |
25d83cbf | 594 | .globl io_int_handler |
1da177e4 | 595 | io_int_handler: |
1da177e4 | 596 | stck __LC_INT_CLOCK |
9cfb9b3c | 597 | stpt __LC_ASYNC_ENTER_TIMER |
86f2552b MS |
598 | SAVE_ALL_ASYNC __LC_IO_OLD_PSW,__LC_SAVE_AREA+40 |
599 | CREATE_STACK_FRAME __LC_SAVE_AREA+40 | |
600 | mvc SP_PSW(16,%r15),0(%r12) # move user PSW to stack | |
601 | lg %r12,__LC_THREAD_INFO # load pointer to thread_info struct | |
1da177e4 LT |
602 | tm SP_PSW+1(%r15),0x01 # interrupting from user ? |
603 | jz io_no_vtime | |
604 | UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER | |
605 | UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER | |
606 | mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER | |
86f2552b | 607 | LAST_BREAK |
1da177e4 | 608 | io_no_vtime: |
cd3b70f5 | 609 | HANDLE_SIE_INTERCEPT |
1f194a4c | 610 | TRACE_IRQS_OFF |
25d83cbf HC |
611 | la %r2,SP_PTREGS(%r15) # address of register-save area |
612 | brasl %r14,do_IRQ # call standard irq handler | |
1da177e4 | 613 | io_return: |
6a2df3a8 MS |
614 | LOCKDEP_SYS_EXIT |
615 | TRACE_IRQS_ON | |
616 | io_tif: | |
86f2552b | 617 | tm __TI_flags+7(%r12),_TIF_WORK_INT |
25d83cbf | 618 | jnz io_work # there is work to do (signals etc.) |
411788ea | 619 | io_restore: |
25d83cbf | 620 | RESTORE_ALL __LC_RETURN_PSW,0 |
ae6aa2ea | 621 | io_done: |
1da177e4 | 622 | |
2688905e | 623 | # |
43d399d2 MS |
624 | # There is work todo, find out in which context we have been interrupted: |
625 | # 1) if we return to user space we can do all _TIF_WORK_INT work | |
626 | # 2) if we return to kernel code and kvm is enabled check if we need to | |
627 | # modify the psw to leave SIE | |
628 | # 3) if we return to kernel code and preemptive scheduling is enabled check | |
629 | # the preemption counter and if it is zero call preempt_schedule_irq | |
630 | # Before any work can be done, a switch to the kernel stack is required. | |
2688905e MS |
631 | # |
632 | io_work: | |
633 | tm SP_PSW+1(%r15),0x01 # returning to user ? | |
43d399d2 | 634 | jo io_work_user # yes -> do resched & signal |
43d399d2 | 635 | #ifdef CONFIG_PREEMPT |
2688905e | 636 | # check for preemptive scheduling |
86f2552b | 637 | icm %r0,15,__TI_precount(%r12) |
2688905e | 638 | jnz io_restore # preemption is disabled |
6a2df3a8 MS |
639 | tm __TI_flags+7(%r12),_TIF_NEED_RESCHED |
640 | jno io_restore | |
1da177e4 LT |
641 | # switch to kernel stack |
642 | lg %r1,SP_R15(%r15) | |
643 | aghi %r1,-SP_SIZE | |
644 | mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15) | |
25d83cbf | 645 | xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain |
1da177e4 | 646 | lgr %r15,%r1 |
6a2df3a8 MS |
647 | # TRACE_IRQS_ON already done at io_return, call |
648 | # TRACE_IRQS_OFF to keep things symmetrical | |
649 | TRACE_IRQS_OFF | |
650 | brasl %r14,preempt_schedule_irq | |
651 | j io_return | |
652 | #else | |
43d399d2 | 653 | j io_restore |
6a2df3a8 | 654 | #endif |
1da177e4 | 655 | |
43d399d2 MS |
656 | # |
657 | # Need to do work before returning to userspace, switch to kernel stack | |
658 | # | |
2688905e | 659 | io_work_user: |
1da177e4 LT |
660 | lg %r1,__LC_KERNEL_STACK |
661 | aghi %r1,-SP_SIZE | |
662 | mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15) | |
25d83cbf | 663 | xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain |
1da177e4 | 664 | lgr %r15,%r1 |
43d399d2 | 665 | |
1da177e4 LT |
666 | # |
667 | # One of the work bits is on. Find out which one. | |
43d399d2 | 668 | # Checked are: _TIF_SIGPENDING, _TIF_NOTIFY_RESUME, _TIF_NEED_RESCHED |
54dfe5dd | 669 | # and _TIF_MCCK_PENDING |
1da177e4 | 670 | # |
6a2df3a8 | 671 | io_work_tif: |
86f2552b | 672 | tm __TI_flags+7(%r12),_TIF_MCCK_PENDING |
77fa2245 | 673 | jo io_mcck_pending |
86f2552b | 674 | tm __TI_flags+7(%r12),_TIF_NEED_RESCHED |
1da177e4 | 675 | jo io_reschedule |
86f2552b | 676 | tm __TI_flags+7(%r12),_TIF_SIGPENDING |
43d399d2 | 677 | jo io_sigpending |
86f2552b | 678 | tm __TI_flags+7(%r12),_TIF_NOTIFY_RESUME |
43d399d2 MS |
679 | jo io_notify_resume |
680 | j io_return # beware of critical section cleanup | |
0eaeafa1 | 681 | |
77fa2245 HC |
682 | # |
683 | # _TIF_MCCK_PENDING is set, call handler | |
684 | # | |
685 | io_mcck_pending: | |
6a2df3a8 | 686 | # TRACE_IRQS_ON already done at io_return |
b771aeac | 687 | brasl %r14,s390_handle_mcck # TIF bit will be cleared by handler |
6a2df3a8 MS |
688 | TRACE_IRQS_OFF |
689 | j io_return | |
77fa2245 | 690 | |
1da177e4 LT |
691 | # |
692 | # _TIF_NEED_RESCHED is set, call schedule | |
25d83cbf HC |
693 | # |
694 | io_reschedule: | |
6a2df3a8 | 695 | # TRACE_IRQS_ON already done at io_return |
25d83cbf HC |
696 | stosm __SF_EMPTY(%r15),0x03 # reenable interrupts |
697 | brasl %r14,schedule # call scheduler | |
698 | stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts | |
411788ea | 699 | TRACE_IRQS_OFF |
6a2df3a8 | 700 | j io_return |
1da177e4 LT |
701 | |
702 | # | |
02a029b3 | 703 | # _TIF_SIGPENDING or is set, call do_signal |
1da177e4 | 704 | # |
25d83cbf | 705 | io_sigpending: |
6a2df3a8 | 706 | # TRACE_IRQS_ON already done at io_return |
25d83cbf HC |
707 | stosm __SF_EMPTY(%r15),0x03 # reenable interrupts |
708 | la %r2,SP_PTREGS(%r15) # load pt_regs | |
1da177e4 | 709 | brasl %r14,do_signal # call do_signal |
25d83cbf | 710 | stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts |
411788ea | 711 | TRACE_IRQS_OFF |
6a2df3a8 | 712 | j io_return |
1da177e4 | 713 | |
753c4dd6 MS |
714 | # |
715 | # _TIF_NOTIFY_RESUME or is set, call do_notify_resume | |
716 | # | |
717 | io_notify_resume: | |
6a2df3a8 | 718 | # TRACE_IRQS_ON already done at io_return |
753c4dd6 MS |
719 | stosm __SF_EMPTY(%r15),0x03 # reenable interrupts |
720 | la %r2,SP_PTREGS(%r15) # load pt_regs | |
721 | brasl %r14,do_notify_resume # call do_notify_resume | |
722 | stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts | |
723 | TRACE_IRQS_OFF | |
6a2df3a8 | 724 | j io_return |
753c4dd6 | 725 | |
1da177e4 LT |
726 | /* |
727 | * External interrupt handler routine | |
728 | */ | |
25d83cbf | 729 | .globl ext_int_handler |
1da177e4 | 730 | ext_int_handler: |
1da177e4 | 731 | stck __LC_INT_CLOCK |
9cfb9b3c | 732 | stpt __LC_ASYNC_ENTER_TIMER |
86f2552b MS |
733 | SAVE_ALL_ASYNC __LC_EXT_OLD_PSW,__LC_SAVE_AREA+40 |
734 | CREATE_STACK_FRAME __LC_SAVE_AREA+40 | |
735 | mvc SP_PSW(16,%r15),0(%r12) # move user PSW to stack | |
736 | lg %r12,__LC_THREAD_INFO # load pointer to thread_info struct | |
1da177e4 LT |
737 | tm SP_PSW+1(%r15),0x01 # interrupting from user ? |
738 | jz ext_no_vtime | |
739 | UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER | |
740 | UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER | |
741 | mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER | |
86f2552b | 742 | LAST_BREAK |
1da177e4 | 743 | ext_no_vtime: |
cd3b70f5 | 744 | HANDLE_SIE_INTERCEPT |
1f194a4c | 745 | TRACE_IRQS_OFF |
25d83cbf HC |
746 | la %r2,SP_PTREGS(%r15) # address of register-save area |
747 | llgh %r3,__LC_EXT_INT_CODE # get interruption code | |
748 | brasl %r14,do_extint | |
1da177e4 LT |
749 | j io_return |
750 | ||
ae6aa2ea MS |
751 | __critical_end: |
752 | ||
1da177e4 LT |
753 | /* |
754 | * Machine check handler routines | |
755 | */ | |
25d83cbf | 756 | .globl mcck_int_handler |
1da177e4 | 757 | mcck_int_handler: |
6377981f | 758 | stck __LC_MCCK_CLOCK |
77fa2245 HC |
759 | la %r1,4095 # revalidate r1 |
760 | spt __LC_CPU_TIMER_SAVE_AREA-4095(%r1) # revalidate cpu timer | |
25d83cbf | 761 | lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)# revalidate gprs |
86f2552b MS |
762 | stmg %r11,%r15,__LC_SAVE_AREA+80 |
763 | larl %r13,system_call | |
764 | lg %r11,__LC_LAST_BREAK | |
77fa2245 | 765 | la %r12,__LC_MCK_OLD_PSW |
25d83cbf | 766 | tm __LC_MCCK_CODE,0x80 # system damage? |
77fa2245 | 767 | jo mcck_int_main # yes -> rest of mcck code invalid |
63b12246 | 768 | la %r14,4095 |
6377981f | 769 | mvc __LC_MCCK_ENTER_TIMER(8),__LC_CPU_TIMER_SAVE_AREA-4095(%r14) |
63b12246 MS |
770 | tm __LC_MCCK_CODE+5,0x02 # stored cpu timer value valid? |
771 | jo 1f | |
772 | la %r14,__LC_SYNC_ENTER_TIMER | |
773 | clc 0(8,%r14),__LC_ASYNC_ENTER_TIMER | |
774 | jl 0f | |
775 | la %r14,__LC_ASYNC_ENTER_TIMER | |
776 | 0: clc 0(8,%r14),__LC_EXIT_TIMER | |
777 | jl 0f | |
778 | la %r14,__LC_EXIT_TIMER | |
779 | 0: clc 0(8,%r14),__LC_LAST_UPDATE_TIMER | |
780 | jl 0f | |
781 | la %r14,__LC_LAST_UPDATE_TIMER | |
782 | 0: spt 0(%r14) | |
6377981f | 783 | mvc __LC_MCCK_ENTER_TIMER(8),0(%r14) |
c185b783 | 784 | 1: tm __LC_MCCK_CODE+2,0x09 # mwp + ia of old psw valid? |
77fa2245 | 785 | jno mcck_int_main # no -> skip cleanup critical |
25d83cbf | 786 | tm __LC_MCK_OLD_PSW+1,0x01 # test problem state bit |
77fa2245 HC |
787 | jnz mcck_int_main # from user -> load kernel stack |
788 | clc __LC_MCK_OLD_PSW+8(8),BASED(.Lcritical_end) | |
789 | jhe mcck_int_main | |
25d83cbf | 790 | clc __LC_MCK_OLD_PSW+8(8),BASED(.Lcritical_start) |
77fa2245 | 791 | jl mcck_int_main |
25d83cbf | 792 | brasl %r14,cleanup_critical |
77fa2245 | 793 | mcck_int_main: |
25d83cbf | 794 | lg %r14,__LC_PANIC_STACK # are we already on the panic stack? |
77fa2245 HC |
795 | slgr %r14,%r15 |
796 | srag %r14,%r14,PAGE_SHIFT | |
797 | jz 0f | |
25d83cbf | 798 | lg %r15,__LC_PANIC_STACK # load panic stack |
86f2552b MS |
799 | 0: aghi %r15,-SP_SIZE # make room for registers & psw |
800 | CREATE_STACK_FRAME __LC_SAVE_AREA+80 | |
801 | mvc SP_PSW(16,%r15),0(%r12) | |
802 | lg %r12,__LC_THREAD_INFO # load pointer to thread_info struct | |
ae6aa2ea MS |
803 | tm __LC_MCCK_CODE+2,0x08 # mwp of old psw valid? |
804 | jno mcck_no_vtime # no -> no timer update | |
63b12246 | 805 | tm SP_PSW+1(%r15),0x01 # interrupting from user ? |
ae6aa2ea | 806 | jz mcck_no_vtime |
6377981f | 807 | UPDATE_VTIME __LC_EXIT_TIMER,__LC_MCCK_ENTER_TIMER,__LC_USER_TIMER |
ae6aa2ea | 808 | UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER |
6377981f | 809 | mvc __LC_LAST_UPDATE_TIMER(8),__LC_MCCK_ENTER_TIMER |
86f2552b | 810 | LAST_BREAK |
ae6aa2ea | 811 | mcck_no_vtime: |
77fa2245 HC |
812 | la %r2,SP_PTREGS(%r15) # load pt_regs |
813 | brasl %r14,s390_do_machine_check | |
25d83cbf | 814 | tm SP_PSW+1(%r15),0x01 # returning to user ? |
77fa2245 HC |
815 | jno mcck_return |
816 | lg %r1,__LC_KERNEL_STACK # switch to kernel stack | |
817 | aghi %r1,-SP_SIZE | |
818 | mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15) | |
819 | xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain | |
820 | lgr %r15,%r1 | |
821 | stosm __SF_EMPTY(%r15),0x04 # turn dat on | |
86f2552b | 822 | tm __TI_flags+7(%r12),_TIF_MCCK_PENDING |
77fa2245 | 823 | jno mcck_return |
cd3b70f5 | 824 | HANDLE_SIE_INTERCEPT |
1f194a4c | 825 | TRACE_IRQS_OFF |
77fa2245 | 826 | brasl %r14,s390_handle_mcck |
1f194a4c | 827 | TRACE_IRQS_ON |
1da177e4 | 828 | mcck_return: |
63b12246 MS |
829 | mvc __LC_RETURN_MCCK_PSW(16),SP_PSW(%r15) # move return PSW |
830 | ni __LC_RETURN_MCCK_PSW+1,0xfd # clear wait state bit | |
831 | lmg %r0,%r15,SP_R0(%r15) # load gprs 0-15 | |
63b12246 MS |
832 | tm __LC_RETURN_MCCK_PSW+1,0x01 # returning to user ? |
833 | jno 0f | |
834 | stpt __LC_EXIT_TIMER | |
c185b783 | 835 | 0: lpswe __LC_RETURN_MCCK_PSW # back to caller |
86f2552b | 836 | mcck_done: |
1da177e4 | 837 | |
1da177e4 LT |
838 | /* |
839 | * Restart interruption handler, kick starter for additional CPUs | |
840 | */ | |
84b36a8e | 841 | #ifdef CONFIG_SMP |
2bc89b5e | 842 | __CPUINIT |
25d83cbf | 843 | .globl restart_int_handler |
1da177e4 | 844 | restart_int_handler: |
5b409ed1 MS |
845 | basr %r1,0 |
846 | restart_base: | |
847 | spt restart_vtime-restart_base(%r1) | |
848 | stck __LC_LAST_UPDATE_CLOCK | |
849 | mvc __LC_LAST_UPDATE_TIMER(8),restart_vtime-restart_base(%r1) | |
850 | mvc __LC_EXIT_TIMER(8),restart_vtime-restart_base(%r1) | |
25d83cbf HC |
851 | lg %r15,__LC_SAVE_AREA+120 # load ksp |
852 | lghi %r10,__LC_CREGS_SAVE_AREA | |
853 | lctlg %c0,%c15,0(%r10) # get new ctl regs | |
854 | lghi %r10,__LC_AREGS_SAVE_AREA | |
855 | lam %a0,%a15,0(%r10) | |
856 | lmg %r6,%r15,__SF_GPRS(%r15) # load registers from clone | |
5b409ed1 MS |
857 | lg %r1,__LC_THREAD_INFO |
858 | mvc __LC_USER_TIMER(8),__TI_user_timer(%r1) | |
859 | mvc __LC_SYSTEM_TIMER(8),__TI_system_timer(%r1) | |
860 | xc __LC_STEAL_TIMER(8),__LC_STEAL_TIMER | |
25d83cbf HC |
861 | stosm __SF_EMPTY(%r15),0x04 # now we can turn dat on |
862 | jg start_secondary | |
5b409ed1 MS |
863 | .align 8 |
864 | restart_vtime: | |
865 | .long 0x7fffffff,0xffffffff | |
84b36a8e | 866 | .previous |
1da177e4 LT |
867 | #else |
868 | /* | |
869 | * If we do not run with SMP enabled, let the new CPU crash ... | |
870 | */ | |
25d83cbf | 871 | .globl restart_int_handler |
1da177e4 | 872 | restart_int_handler: |
25d83cbf | 873 | basr %r1,0 |
1da177e4 | 874 | restart_base: |
25d83cbf HC |
875 | lpswe restart_crash-restart_base(%r1) |
876 | .align 8 | |
1da177e4 | 877 | restart_crash: |
25d83cbf | 878 | .long 0x000a0000,0x00000000,0x00000000,0x00000000 |
1da177e4 LT |
879 | restart_go: |
880 | #endif | |
881 | ||
882 | #ifdef CONFIG_CHECK_STACK | |
883 | /* | |
884 | * The synchronous or the asynchronous stack overflowed. We are dead. | |
885 | * No need to properly save the registers, we are going to panic anyway. | |
886 | * Setup a pt_regs so that show_trace can provide a good call trace. | |
887 | */ | |
888 | stack_overflow: | |
889 | lg %r15,__LC_PANIC_STACK # change to panic stack | |
9514e231 | 890 | aghi %r15,-SP_SIZE |
1da177e4 | 891 | mvc SP_PSW(16,%r15),0(%r12) # move user PSW to stack |
86f2552b | 892 | stmg %r0,%r10,SP_R0(%r15) # store gprs %r0-%r10 to kernel stack |
1da177e4 LT |
893 | la %r1,__LC_SAVE_AREA |
894 | chi %r12,__LC_SVC_OLD_PSW | |
895 | je 0f | |
896 | chi %r12,__LC_PGM_OLD_PSW | |
897 | je 0f | |
86f2552b MS |
898 | la %r1,__LC_SAVE_AREA+40 |
899 | 0: mvc SP_R11(40,%r15),0(%r1) # move %r11-%r15 to stack | |
9e74a6b8 | 900 | mvc SP_ARGS(8,%r15),__LC_LAST_BREAK |
25d83cbf HC |
901 | xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) # clear back chain |
902 | la %r2,SP_PTREGS(%r15) # load pt_regs | |
1da177e4 LT |
903 | jg kernel_stack_overflow |
904 | #endif | |
905 | ||
906 | cleanup_table_system_call: | |
907 | .quad system_call, sysc_do_svc | |
6a2df3a8 MS |
908 | cleanup_table_sysc_tif: |
909 | .quad sysc_tif, sysc_restore | |
910 | cleanup_table_sysc_restore: | |
911 | .quad sysc_restore, sysc_done | |
912 | cleanup_table_io_tif: | |
913 | .quad io_tif, io_restore | |
914 | cleanup_table_io_restore: | |
915 | .quad io_restore, io_done | |
1da177e4 LT |
916 | |
917 | cleanup_critical: | |
918 | clc 8(8,%r12),BASED(cleanup_table_system_call) | |
919 | jl 0f | |
920 | clc 8(8,%r12),BASED(cleanup_table_system_call+8) | |
921 | jl cleanup_system_call | |
922 | 0: | |
6a2df3a8 | 923 | clc 8(8,%r12),BASED(cleanup_table_sysc_tif) |
1da177e4 | 924 | jl 0f |
6a2df3a8 MS |
925 | clc 8(8,%r12),BASED(cleanup_table_sysc_tif+8) |
926 | jl cleanup_sysc_tif | |
1da177e4 | 927 | 0: |
6a2df3a8 | 928 | clc 8(8,%r12),BASED(cleanup_table_sysc_restore) |
1da177e4 | 929 | jl 0f |
6a2df3a8 MS |
930 | clc 8(8,%r12),BASED(cleanup_table_sysc_restore+8) |
931 | jl cleanup_sysc_restore | |
63b12246 | 932 | 0: |
6a2df3a8 | 933 | clc 8(8,%r12),BASED(cleanup_table_io_tif) |
63b12246 | 934 | jl 0f |
6a2df3a8 MS |
935 | clc 8(8,%r12),BASED(cleanup_table_io_tif+8) |
936 | jl cleanup_io_tif | |
ae6aa2ea | 937 | 0: |
6a2df3a8 | 938 | clc 8(8,%r12),BASED(cleanup_table_io_restore) |
ae6aa2ea | 939 | jl 0f |
6a2df3a8 MS |
940 | clc 8(8,%r12),BASED(cleanup_table_io_restore+8) |
941 | jl cleanup_io_restore | |
1da177e4 LT |
942 | 0: |
943 | br %r14 | |
944 | ||
945 | cleanup_system_call: | |
946 | mvc __LC_RETURN_PSW(16),0(%r12) | |
1da177e4 LT |
947 | clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+8) |
948 | jh 0f | |
6377981f MS |
949 | mvc __LC_SYNC_ENTER_TIMER(8),__LC_MCCK_ENTER_TIMER |
950 | cghi %r12,__LC_MCK_OLD_PSW | |
951 | je 0f | |
1da177e4 | 952 | mvc __LC_SYNC_ENTER_TIMER(8),__LC_ASYNC_ENTER_TIMER |
6377981f | 953 | 0: cghi %r12,__LC_MCK_OLD_PSW |
86f2552b | 954 | la %r12,__LC_SAVE_AREA+80 |
6377981f | 955 | je 0f |
86f2552b | 956 | la %r12,__LC_SAVE_AREA+40 |
1da177e4 LT |
957 | 0: clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+16) |
958 | jhe cleanup_vtime | |
1da177e4 LT |
959 | clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn) |
960 | jh 0f | |
86f2552b MS |
961 | mvc __LC_SAVE_AREA(40),0(%r12) |
962 | 0: lg %r15,__LC_KERNEL_STACK # problem state -> load ksp | |
963 | aghi %r15,-SP_SIZE # make room for registers & psw | |
964 | stg %r15,32(%r12) | |
965 | stg %r11,0(%r12) | |
966 | CREATE_STACK_FRAME __LC_SAVE_AREA | |
967 | mvc SP_PSW(16,%r15),__LC_SVC_OLD_PSW | |
968 | mvc SP_ILC(4,%r15),__LC_SVC_ILC | |
969 | stg %r7,SP_ARGS(%r15) | |
970 | mvc 8(8,%r12),__LC_THREAD_INFO | |
1da177e4 LT |
971 | cleanup_vtime: |
972 | clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+24) | |
973 | jhe cleanup_stime | |
1da177e4 LT |
974 | UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER |
975 | cleanup_stime: | |
976 | clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+32) | |
977 | jh cleanup_update | |
978 | UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER | |
979 | cleanup_update: | |
980 | mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER | |
86f2552b MS |
981 | srag %r12,%r11,23 |
982 | lg %r12,__LC_THREAD_INFO | |
983 | jz 0f | |
984 | stg %r11,__TI_last_break(%r12) | |
985 | 0: mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_system_call+8) | |
1da177e4 LT |
986 | la %r12,__LC_RETURN_PSW |
987 | br %r14 | |
988 | cleanup_system_call_insn: | |
989 | .quad sysc_saveall | |
25d83cbf HC |
990 | .quad system_call |
991 | .quad sysc_vtime | |
992 | .quad sysc_stime | |
993 | .quad sysc_update | |
1da177e4 | 994 | |
6a2df3a8 | 995 | cleanup_sysc_tif: |
1da177e4 | 996 | mvc __LC_RETURN_PSW(8),0(%r12) |
6a2df3a8 | 997 | mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_sysc_tif) |
1da177e4 LT |
998 | la %r12,__LC_RETURN_PSW |
999 | br %r14 | |
1000 | ||
6a2df3a8 MS |
1001 | cleanup_sysc_restore: |
1002 | clc 8(8,%r12),BASED(cleanup_sysc_restore_insn) | |
6377981f | 1003 | je 2f |
6a2df3a8 | 1004 | clc 8(8,%r12),BASED(cleanup_sysc_restore_insn+8) |
c742b31c | 1005 | jhe 0f |
6377981f MS |
1006 | mvc __LC_EXIT_TIMER(8),__LC_MCCK_ENTER_TIMER |
1007 | cghi %r12,__LC_MCK_OLD_PSW | |
1008 | je 0f | |
c742b31c MS |
1009 | mvc __LC_EXIT_TIMER(8),__LC_ASYNC_ENTER_TIMER |
1010 | 0: mvc __LC_RETURN_PSW(16),SP_PSW(%r15) | |
ae6aa2ea | 1011 | cghi %r12,__LC_MCK_OLD_PSW |
86f2552b | 1012 | la %r12,__LC_SAVE_AREA+80 |
6377981f | 1013 | je 1f |
86f2552b MS |
1014 | la %r12,__LC_SAVE_AREA+40 |
1015 | 1: mvc 0(40,%r12),SP_R11(%r15) | |
1016 | lmg %r0,%r10,SP_R0(%r15) | |
1da177e4 | 1017 | lg %r15,SP_R15(%r15) |
6377981f | 1018 | 2: la %r12,__LC_RETURN_PSW |
1da177e4 | 1019 | br %r14 |
6a2df3a8 | 1020 | cleanup_sysc_restore_insn: |
411788ea | 1021 | .quad sysc_done - 4 |
c742b31c | 1022 | .quad sysc_done - 16 |
1da177e4 | 1023 | |
6a2df3a8 | 1024 | cleanup_io_tif: |
176b1803 | 1025 | mvc __LC_RETURN_PSW(8),0(%r12) |
6a2df3a8 | 1026 | mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_io_tif) |
176b1803 MS |
1027 | la %r12,__LC_RETURN_PSW |
1028 | br %r14 | |
1029 | ||
6a2df3a8 MS |
1030 | cleanup_io_restore: |
1031 | clc 8(8,%r12),BASED(cleanup_io_restore_insn) | |
6377981f | 1032 | je 1f |
6a2df3a8 | 1033 | clc 8(8,%r12),BASED(cleanup_io_restore_insn+8) |
c742b31c | 1034 | jhe 0f |
6377981f | 1035 | mvc __LC_EXIT_TIMER(8),__LC_MCCK_ENTER_TIMER |
c742b31c | 1036 | 0: mvc __LC_RETURN_PSW(16),SP_PSW(%r15) |
86f2552b MS |
1037 | mvc __LC_SAVE_AREA+80(40),SP_R11(%r15) |
1038 | lmg %r0,%r10,SP_R0(%r15) | |
ae6aa2ea | 1039 | lg %r15,SP_R15(%r15) |
6377981f | 1040 | 1: la %r12,__LC_RETURN_PSW |
ae6aa2ea | 1041 | br %r14 |
6a2df3a8 | 1042 | cleanup_io_restore_insn: |
411788ea | 1043 | .quad io_done - 4 |
c742b31c | 1044 | .quad io_done - 16 |
ae6aa2ea | 1045 | |
1da177e4 LT |
1046 | /* |
1047 | * Integer constants | |
1048 | */ | |
25d83cbf | 1049 | .align 4 |
1da177e4 | 1050 | .Lcritical_start: |
25d83cbf | 1051 | .quad __critical_start |
1da177e4 | 1052 | .Lcritical_end: |
25d83cbf | 1053 | .quad __critical_end |
1da177e4 | 1054 | |
25d83cbf | 1055 | .section .rodata, "a" |
1da177e4 | 1056 | #define SYSCALL(esa,esame,emu) .long esame |
9bf1226b | 1057 | .globl sys_call_table |
1da177e4 LT |
1058 | sys_call_table: |
1059 | #include "syscalls.S" | |
1060 | #undef SYSCALL | |
1061 | ||
347a8dc3 | 1062 | #ifdef CONFIG_COMPAT |
1da177e4 LT |
1063 | |
1064 | #define SYSCALL(esa,esame,emu) .long emu | |
1da177e4 LT |
1065 | sys_call_table_emu: |
1066 | #include "syscalls.S" | |
1067 | #undef SYSCALL | |
1068 | #endif |