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5cd16ee9 ME |
1 | #ifndef _ASM_POWERPC_PAGE_32_H |
2 | #define _ASM_POWERPC_PAGE_32_H | |
3 | ||
37dd2bad KG |
4 | #if defined(CONFIG_PHYSICAL_ALIGN) && (CONFIG_PHYSICAL_START != 0) |
5 | #if (CONFIG_PHYSICAL_START % CONFIG_PHYSICAL_ALIGN) != 0 | |
6 | #error "CONFIG_PHYSICAL_START must be a multiple of CONFIG_PHYSICAL_ALIGN" | |
7 | #endif | |
8 | #endif | |
9 | ||
5cd16ee9 ME |
10 | #define VM_DATA_DEFAULT_FLAGS VM_DATA_DEFAULT_FLAGS32 |
11 | ||
52142e75 | 12 | #ifdef CONFIG_NOT_COHERENT_CACHE |
a6eb9fe1 | 13 | #define ARCH_DMA_MINALIGN L1_CACHE_BYTES |
52142e75 BH |
14 | #endif |
15 | ||
4ee7084e BB |
16 | #ifdef CONFIG_PTE_64BIT |
17 | #define PTE_FLAGS_OFFSET 4 /* offset of PTE flags, in bytes */ | |
18 | #else | |
19 | #define PTE_FLAGS_OFFSET 0 | |
20 | #endif | |
21 | ||
e1240122 YT |
22 | #ifdef CONFIG_PPC_256K_PAGES |
23 | #define PTE_SHIFT (PAGE_SHIFT - PTE_T_LOG2 - 2) /* 1/4 of a page */ | |
24 | #else | |
ca9153a3 | 25 | #define PTE_SHIFT (PAGE_SHIFT - PTE_T_LOG2) /* full page */ |
e1240122 | 26 | #endif |
ca9153a3 | 27 | |
5cd16ee9 ME |
28 | #ifndef __ASSEMBLY__ |
29 | /* | |
30 | * The basic type of a PTE - 64 bits for those CPUs with > 32 bit | |
4ee7084e | 31 | * physical addressing. |
5cd16ee9 ME |
32 | */ |
33 | #ifdef CONFIG_PTE_64BIT | |
34 | typedef unsigned long long pte_basic_t; | |
5cd16ee9 ME |
35 | #else |
36 | typedef unsigned long pte_basic_t; | |
5cd16ee9 ME |
37 | #endif |
38 | ||
39 | struct page; | |
40 | extern void clear_pages(void *page, int order); | |
41 | static inline void clear_page(void *page) { clear_pages(page, 0); } | |
42 | extern void copy_page(void *to, void *from); | |
43 | ||
5b17e1cd | 44 | #include <asm-generic/getorder.h> |
5cd16ee9 | 45 | |
ca9153a3 IY |
46 | #define PGD_T_LOG2 (__builtin_ffs(sizeof(pgd_t)) - 1) |
47 | #define PTE_T_LOG2 (__builtin_ffs(sizeof(pte_t)) - 1) | |
48 | ||
5cd16ee9 ME |
49 | #endif /* __ASSEMBLY__ */ |
50 | ||
51 | #endif /* _ASM_POWERPC_PAGE_32_H */ |