[net-next-2.6.git] / arch / mips / oprofile / op_model_loongson2.c

/*
 * Loongson2 performance counter driver for oprofile
 *
 * Copyright (C) 2009 Lemote Inc.
 * Author: Yanhua <yanh@lemote.com>
 * Author: Wu Zhangjin <wuzhangjin@gmail.com>
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/init.h>
#include <linux/oprofile.h>
#include <linux/interrupt.h>

#include <loongson.h>			/* LOONGSON2_PERFCNT_IRQ */
#include "op_impl.h"

#define LOONGSON2_CPU_TYPE	"mips/loongson2"

#define LOONGSON2_PERFCNT_OVERFLOW		(1ULL   << 31)

#define LOONGSON2_PERFCTRL_EXL			(1UL	<<  0)
#define LOONGSON2_PERFCTRL_KERNEL		(1UL    <<  1)
#define LOONGSON2_PERFCTRL_SUPERVISOR		(1UL    <<  2)
#define LOONGSON2_PERFCTRL_USER			(1UL    <<  3)
#define LOONGSON2_PERFCTRL_ENABLE		(1UL    <<  4)
#define LOONGSON2_PERFCTRL_EVENT(idx, event) \
	(((event) & 0x0f) << ((idx) ? 9 : 5))

#define read_c0_perfctrl() __read_64bit_c0_register($24, 0)
#define write_c0_perfctrl(val) __write_64bit_c0_register($24, 0, val)
#define read_c0_perfcnt() __read_64bit_c0_register($25, 0)
#define write_c0_perfcnt(val) __write_64bit_c0_register($25, 0, val)

static struct loongson2_register_config {
	unsigned int ctrl;
	unsigned long long reset_counter1;
	unsigned long long reset_counter2;
	int cnt1_enabled, cnt2_enabled;
} reg;

static char *oprofid = "LoongsonPerf";
static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id);

static void reset_counters(void *arg)
{
	write_c0_perfctrl(0);
	write_c0_perfcnt(0);
}

static void loongson2_reg_setup(struct op_counter_config *cfg)
{
	unsigned int ctrl = 0;

	reg.reset_counter1 = 0;
	reg.reset_counter2 = 0;

	/*
	 * Compute the performance counter ctrl word.
	 * For now, count kernel and user mode.
	 */
	if (cfg[0].enabled) {
		ctrl |= LOONGSON2_PERFCTRL_EVENT(0, cfg[0].event);
		reg.reset_counter1 = 0x80000000ULL - cfg[0].count;
	}

	if (cfg[1].enabled) {
		ctrl |= LOONGSON2_PERFCTRL_EVENT(1, cfg[1].event);
		reg.reset_counter2 = 0x80000000ULL - cfg[1].count;
	}

	if (cfg[0].enabled || cfg[1].enabled) {
		ctrl |= LOONGSON2_PERFCTRL_EXL | LOONGSON2_PERFCTRL_ENABLE;
		if (cfg[0].kernel || cfg[1].kernel)
			ctrl |= LOONGSON2_PERFCTRL_KERNEL;
		if (cfg[0].user || cfg[1].user)
			ctrl |= LOONGSON2_PERFCTRL_USER;
	}

	reg.ctrl = ctrl;

	reg.cnt1_enabled = cfg[0].enabled;
	reg.cnt2_enabled = cfg[1].enabled;
}

static void loongson2_cpu_setup(void *args)
{
	write_c0_perfcnt((reg.reset_counter2 << 32) | reg.reset_counter1);
}

static void loongson2_cpu_start(void *args)
{
	/* Start all counters on current CPU */
	if (reg.cnt1_enabled || reg.cnt2_enabled)
		write_c0_perfctrl(reg.ctrl);
}

static void loongson2_cpu_stop(void *args)
{
	/* Stop all counters on current CPU */
	write_c0_perfctrl(0);
	memset(&reg, 0, sizeof(reg));
}

static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id)
{
	uint64_t counter, counter1, counter2;
	struct pt_regs *regs = get_irq_regs();
	int enabled;

	/* Check whether the irq belongs to me */
	enabled = read_c0_perfctrl() & LOONGSON2_PERFCTRL_ENABLE;
	if (!enabled)
		return IRQ_NONE;
	enabled = reg.cnt1_enabled | reg.cnt2_enabled;
	if (!enabled)
		return IRQ_NONE;

	counter = read_c0_perfcnt();
	counter1 = counter & 0xffffffff;
	counter2 = counter >> 32;

	if (counter1 & LOONGSON2_PERFCNT_OVERFLOW) {
		if (reg.cnt1_enabled)
			oprofile_add_sample(regs, 0);
		counter1 = reg.reset_counter1;
	}
	if (counter2 & LOONGSON2_PERFCNT_OVERFLOW) {
		if (reg.cnt2_enabled)
			oprofile_add_sample(regs, 1);
		counter2 = reg.reset_counter2;
	}

	write_c0_perfcnt((counter2 << 32) | counter1);

	return IRQ_HANDLED;
}

static int __init loongson2_init(void)
{
	return request_irq(LOONGSON2_PERFCNT_IRQ, loongson2_perfcount_handler,
			   IRQF_SHARED, "Perfcounter", oprofid);
}

static void loongson2_exit(void)
{
	reset_counters(NULL);
	free_irq(LOONGSON2_PERFCNT_IRQ, oprofid);
}

struct op_mips_model op_model_loongson2_ops = {
	.reg_setup = loongson2_reg_setup,
	.cpu_setup = loongson2_cpu_setup,
	.init = loongson2_init,
	.exit = loongson2_exit,
	.cpu_start = loongson2_cpu_start,
	.cpu_stop = loongson2_cpu_stop,
	.cpu_type = LOONGSON2_CPU_TYPE,
	.num_counters = 2
};
Commit	Line	Data
67b35e5d WZ	1	/*
	2	* Loongson2 performance counter driver for oprofile
	3	*
937893cf	4	* Copyright (C) 2009 Lemote Inc.
67b35e5d	5	* Author: Yanhua <yanh@lemote.com>
f7a904df	6	* Author: Wu Zhangjin <wuzhangjin@gmail.com>
67b35e5d WZ	7	*
	8	* This file is subject to the terms and conditions of the GNU General Public
	9	* License. See the file "COPYING" in the main directory of this archive
	10	* for more details.
67b35e5d WZ	11	*/
	12	#include <linux/init.h>
	13	#include <linux/oprofile.h>
	14	#include <linux/interrupt.h>
	15
	16	#include <loongson.h> /* LOONGSON2_PERFCNT_IRQ */
	17	#include "op_impl.h"
	18
55f4e1d4	19	#define LOONGSON2_CPU_TYPE "mips/loongson2"
67b35e5d	20
852151bd WZ	21	#define LOONGSON2_PERFCNT_OVERFLOW (1ULL << 31)
	22
	23	#define LOONGSON2_PERFCTRL_EXL (1UL << 0)
	24	#define LOONGSON2_PERFCTRL_KERNEL (1UL << 1)
	25	#define LOONGSON2_PERFCTRL_SUPERVISOR (1UL << 2)
	26	#define LOONGSON2_PERFCTRL_USER (1UL << 3)
	27	#define LOONGSON2_PERFCTRL_ENABLE (1UL << 4)
86e5a520 WZ	28	#define LOONGSON2_PERFCTRL_EVENT(idx, event) \
86e5a520 WZ	29	(((event) & 0x0f) << ((idx) ? 9 : 5))
67b35e5d	30
67b35e5d WZ	31	#define read_c0_perfctrl() __read_64bit_c0_register($24, 0)
	32	#define write_c0_perfctrl(val) __write_64bit_c0_register($24, 0, val)
	33	#define read_c0_perfcnt() __read_64bit_c0_register($25, 0)
	34	#define write_c0_perfcnt(val) __write_64bit_c0_register($25, 0, val)
	35
	36	static struct loongson2_register_config {
	37	unsigned int ctrl;
	38	unsigned long long reset_counter1;
	39	unsigned long long reset_counter2;
8813d33e	40	int cnt1_enabled, cnt2_enabled;
67b35e5d WZ	41	} reg;
67b35e5d WZ	42
67b35e5d WZ	43	static char *oprofid = "LoongsonPerf";
67b35e5d WZ	44	static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id);
67b35e5d	45
1d842674 WZ	46	static void reset_counters(void *arg)
	47	{
	48	write_c0_perfctrl(0);
	49	write_c0_perfcnt(0);
	50	}
	51
67b35e5d WZ	52	static void loongson2_reg_setup(struct op_counter_config *cfg)
	53	{
	54	unsigned int ctrl = 0;
	55
	56	reg.reset_counter1 = 0;
	57	reg.reset_counter2 = 0;
893556e6 WZ	58
	59	/*
	60	* Compute the performance counter ctrl word.
	61	* For now, count kernel and user mode.
	62	*/
67b35e5d	63	if (cfg[0].enabled) {
86e5a520	64	ctrl \|= LOONGSON2_PERFCTRL_EVENT(0, cfg[0].event);
67b35e5d WZ	65	reg.reset_counter1 = 0x80000000ULL - cfg[0].count;
	66	}
	67
	68	if (cfg[1].enabled) {
86e5a520	69	ctrl \|= LOONGSON2_PERFCTRL_EVENT(1, cfg[1].event);
c838abc5	70	reg.reset_counter2 = 0x80000000ULL - cfg[1].count;
67b35e5d WZ	71	}
	72
	73	if (cfg[0].enabled \|\| cfg[1].enabled) {
852151bd	74	ctrl \|= LOONGSON2_PERFCTRL_EXL \| LOONGSON2_PERFCTRL_ENABLE;
67b35e5d	75	if (cfg[0].kernel \|\| cfg[1].kernel)
852151bd	76	ctrl \|= LOONGSON2_PERFCTRL_KERNEL;
67b35e5d	77	if (cfg[0].user \|\| cfg[1].user)
852151bd	78	ctrl \|= LOONGSON2_PERFCTRL_USER;
67b35e5d WZ	79	}
	80
	81	reg.ctrl = ctrl;
	82
8813d33e UKK	83	reg.cnt1_enabled = cfg[0].enabled;
8813d33e UKK	84	reg.cnt2_enabled = cfg[1].enabled;
67b35e5d WZ	85	}
67b35e5d WZ	86
67b35e5d WZ	87	static void loongson2_cpu_setup(void *args)
67b35e5d WZ	88	{
6d8c2873	89	write_c0_perfcnt((reg.reset_counter2 << 32) \| reg.reset_counter1);
67b35e5d WZ	90	}
	91
	92	static void loongson2_cpu_start(void *args)
	93	{
	94	/* Start all counters on current CPU */
8813d33e	95	if (reg.cnt1_enabled \|\| reg.cnt2_enabled)
67b35e5d WZ	96	write_c0_perfctrl(reg.ctrl);
	97	}
	98
	99	static void loongson2_cpu_stop(void *args)
	100	{
	101	/* Stop all counters on current CPU */
	102	write_c0_perfctrl(0);
	103	memset(&reg, 0, sizeof(reg));
	104	}
	105
	106	static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id)
	107	{
	108	uint64_t counter, counter1, counter2;
	109	struct pt_regs *regs = get_irq_regs();
	110	int enabled;
67b35e5d	111
67b35e5d	112	/* Check whether the irq belongs to me */
852151bd	113	enabled = read_c0_perfctrl() & LOONGSON2_PERFCTRL_ENABLE;
937893cf WZ	114	if (!enabled)
937893cf WZ	115	return IRQ_NONE;
8813d33e	116	enabled = reg.cnt1_enabled \| reg.cnt2_enabled;
67b35e5d WZ	117	if (!enabled)
	118	return IRQ_NONE;
	119
	120	counter = read_c0_perfcnt();
	121	counter1 = counter & 0xffffffff;
	122	counter2 = counter >> 32;
	123
67b35e5d	124	if (counter1 & LOONGSON2_PERFCNT_OVERFLOW) {
8813d33e	125	if (reg.cnt1_enabled)
67b35e5d WZ	126	oprofile_add_sample(regs, 0);
	127	counter1 = reg.reset_counter1;
	128	}
	129	if (counter2 & LOONGSON2_PERFCNT_OVERFLOW) {
8813d33e	130	if (reg.cnt2_enabled)
67b35e5d WZ	131	oprofile_add_sample(regs, 1);
	132	counter2 = reg.reset_counter2;
	133	}
	134
67b35e5d WZ	135	write_c0_perfcnt((counter2 << 32) \| counter1);
	136
	137	return IRQ_HANDLED;
	138	}
	139
	140	static int __init loongson2_init(void)
	141	{
	142	return request_irq(LOONGSON2_PERFCNT_IRQ, loongson2_perfcount_handler,
	143	IRQF_SHARED, "Perfcounter", oprofid);
	144	}
	145
	146	static void loongson2_exit(void)
	147	{
1d842674	148	reset_counters(NULL);
67b35e5d WZ	149	free_irq(LOONGSON2_PERFCNT_IRQ, oprofid);
	150	}
	151
	152	struct op_mips_model op_model_loongson2_ops = {
	153	.reg_setup = loongson2_reg_setup,
	154	.cpu_setup = loongson2_cpu_setup,
	155	.init = loongson2_init,
	156	.exit = loongson2_exit,
	157	.cpu_start = loongson2_cpu_start,
	158	.cpu_stop = loongson2_cpu_stop,
	159	.cpu_type = LOONGSON2_CPU_TYPE,
	160	.num_counters = 2
	161	};