[net-next-2.6.git] / arch / ia64 / include / asm / dma-mapping.h

#ifndef _ASM_IA64_DMA_MAPPING_H
#define _ASM_IA64_DMA_MAPPING_H

/*
 * Copyright (C) 2003-2004 Hewlett-Packard Co
 *	David Mosberger-Tang <davidm@hpl.hp.com>
 */
#include <asm/machvec.h>
#include <linux/scatterlist.h>
#include <asm/swiotlb.h>
#include <linux/dma-debug.h>

#define ARCH_HAS_DMA_GET_REQUIRED_MASK

extern struct dma_map_ops *dma_ops;
extern struct ia64_machine_vector ia64_mv;
extern void set_iommu_machvec(void);

extern void machvec_dma_sync_single(struct device *, dma_addr_t, size_t,
				    enum dma_data_direction);
extern void machvec_dma_sync_sg(struct device *, struct scatterlist *, int,
				enum dma_data_direction);

static inline void *dma_alloc_coherent(struct device *dev, size_t size,
				       dma_addr_t *daddr, gfp_t gfp)
{
	struct dma_map_ops *ops = platform_dma_get_ops(dev);
	void *caddr;

	caddr = ops->alloc_coherent(dev, size, daddr, gfp);
	debug_dma_alloc_coherent(dev, size, *daddr, caddr);
	return caddr;
}

static inline void dma_free_coherent(struct device *dev, size_t size,
				     void *caddr, dma_addr_t daddr)
{
	struct dma_map_ops *ops = platform_dma_get_ops(dev);
	debug_dma_free_coherent(dev, size, caddr, daddr);
	ops->free_coherent(dev, size, caddr, daddr);
}

#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)

#define get_dma_ops(dev) platform_dma_get_ops(dev)

#include <asm-generic/dma-mapping-common.h>

static inline int dma_mapping_error(struct device *dev, dma_addr_t daddr)
{
	struct dma_map_ops *ops = platform_dma_get_ops(dev);
	return ops->mapping_error(dev, daddr);
}

static inline int dma_supported(struct device *dev, u64 mask)
{
	struct dma_map_ops *ops = platform_dma_get_ops(dev);
	return ops->dma_supported(dev, mask);
}

static inline int
dma_set_mask (struct device *dev, u64 mask)
{
	if (!dev->dma_mask || !dma_supported(dev, mask))
		return -EIO;
	*dev->dma_mask = mask;
	return 0;
}

static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
{
	if (!dev->dma_mask)
		return 0;

	return addr + size - 1 <= *dev->dma_mask;
}

static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
{
	return paddr;
}

static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
{
	return daddr;
}

static inline void
dma_cache_sync (struct device *dev, void *vaddr, size_t size,
	enum dma_data_direction dir)
{
	/*
	 * IA-64 is cache-coherent, so this is mostly a no-op.  However, we do need to
	 * ensure that dma_cache_sync() enforces order, hence the mb().
	 */
	mb();
}

#define dma_is_consistent(d, h)	(1)	/* all we do is coherent memory... */

#endif /* _ASM_IA64_DMA_MAPPING_H */
Commit	Line	Data
1da177e4 LT	1	#ifndef _ASM_IA64_DMA_MAPPING_H
	2	#define _ASM_IA64_DMA_MAPPING_H
	3
	4	/*
	5	* Copyright (C) 2003-2004 Hewlett-Packard Co
	6	* David Mosberger-Tang <davidm@hpl.hp.com>
	7	*/
1da177e4	8	#include <asm/machvec.h>
9b6eccfc	9	#include <linux/scatterlist.h>
62fdd767	10	#include <asm/swiotlb.h>
99162195	11	#include <linux/dma-debug.h>
62fdd767	12
175add19 JK	13	#define ARCH_HAS_DMA_GET_REQUIRED_MASK
175add19 JK	14
160c1d8e	15	extern struct dma_map_ops *dma_ops;
62fdd767 FY	16	extern struct ia64_machine_vector ia64_mv;
62fdd767 FY	17	extern void set_iommu_machvec(void);
1da177e4	18
c2990307 FT	19	extern void machvec_dma_sync_single(struct device *, dma_addr_t, size_t,
	20	enum dma_data_direction);
	21	extern void machvec_dma_sync_sg(struct device , struct scatterlist , int,
	22	enum dma_data_direction);
	23
b7ea6e95 FT	24	static inline void dma_alloc_coherent(struct device dev, size_t size,
	25	dma_addr_t *daddr, gfp_t gfp)
	26	{
160c1d8e	27	struct dma_map_ops *ops = platform_dma_get_ops(dev);
99162195 FT	28	void *caddr;
	29
	30	caddr = ops->alloc_coherent(dev, size, daddr, gfp);
	31	debug_dma_alloc_coherent(dev, size, *daddr, caddr);
	32	return caddr;
b7ea6e95	33	}
3a80b6aa	34
b7ea6e95 FT	35	static inline void dma_free_coherent(struct device *dev, size_t size,
b7ea6e95 FT	36	void *caddr, dma_addr_t daddr)
b7de8e7e	37	{
160c1d8e	38	struct dma_map_ops *ops = platform_dma_get_ops(dev);
99162195	39	debug_dma_free_coherent(dev, size, caddr, daddr);
c190ab0b	40	ops->free_coherent(dev, size, caddr, daddr);
b7de8e7e	41	}
b7ea6e95 FT	42
	43	#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
	44	#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
	45
d6d0a6ae	46	#define get_dma_ops(dev) platform_dma_get_ops(dev)
b7ea6e95	47
d6d0a6ae	48	#include <asm-generic/dma-mapping-common.h>
b7ea6e95 FT	49
	50	static inline int dma_mapping_error(struct device *dev, dma_addr_t daddr)
	51	{
160c1d8e	52	struct dma_map_ops *ops = platform_dma_get_ops(dev);
c190ab0b	53	return ops->mapping_error(dev, daddr);
309df0c5	54	}
1da177e4	55
b7ea6e95 FT	56	static inline int dma_supported(struct device *dev, u64 mask)
b7ea6e95 FT	57	{
160c1d8e FT	58	struct dma_map_ops *ops = platform_dma_get_ops(dev);
160c1d8e FT	59	return ops->dma_supported(dev, mask);
b7ea6e95	60	}
1da177e4 LT	61
	62	static inline int
	63	dma_set_mask (struct device *dev, u64 mask)
	64	{
	65	if (!dev->dma_mask \|\| !dma_supported(dev, mask))
	66	return -EIO;
	67	*dev->dma_mask = mask;
	68	return 0;
	69	}
	70
a0b00ca8 FT	71	static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
	72	{
	73	if (!dev->dma_mask)
	74	return 0;
	75
ac2b3e67	76	return addr + size - 1 <= *dev->dma_mask;
a0b00ca8 FT	77	}
a0b00ca8 FT	78
8d4f5339 FT	79	static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
	80	{
	81	return paddr;
	82	}
	83
	84	static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
	85	{
	86	return daddr;
	87	}
	88
1da177e4	89	static inline void
d3fa72e4 RB	90	dma_cache_sync (struct device dev, void vaddr, size_t size,
d3fa72e4 RB	91	enum dma_data_direction dir)
1da177e4 LT	92	{
	93	/*
	94	* IA-64 is cache-coherent, so this is mostly a no-op. However, we do need to
	95	* ensure that dma_cache_sync() enforces order, hence the mb().
	96	*/
	97	mb();
	98	}
	99
f67637ee	100	#define dma_is_consistent(d, h) (1) /* all we do is coherent memory... */
1da177e4 LT	101
1da177e4 LT	102	#endif /* _ASM_IA64_DMA_MAPPING_H */