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Blackfin: bf52x/bf54x boards: drop unused nand page size
[net-next-2.6.git] / arch / blackfin / mach-bf548 / boards / ezkit.c
CommitLineData
24a07a12 1/*
96f1050d
RG		 2 * Copyright 2004-2009 Analog Devices Inc.
3 * 2005 National ICT Australia (NICTA)
4 * Aidan Williams <aidan@nicta.com.au>
24a07a12 5 *
96f1050d 6 * Licensed under the GPL-2 or later.
24a07a12
RH		 7 */
8
9#include <linux/device.h>
10#include <linux/platform_device.h>
11#include <linux/mtd/mtd.h>
12#include <linux/mtd/partitions.h>
de8c43f2 13#include <linux/mtd/physmap.h>
24a07a12
RH		 14#include <linux/spi/spi.h>
15#include <linux/spi/flash.h>
1f83b8f1 16#include <linux/irq.h>
81d9c7f2 17#include <linux/i2c.h>
24a07a12 18#include <linux/interrupt.h>
c6c4d7bb 19#include <linux/usb/musb.h>
24a07a12 20#include <asm/bfin5xx_spi.h>
c6c4d7bb
BW		 21#include <asm/dma.h>
22#include <asm/gpio.h>
23#include <asm/nand.h>
14b03204 24#include <asm/dpmc.h>
5d448dd5 25#include <asm/portmux.h>
501674a5 26#include <asm/bfin_sdh.h>
639f6571 27#include <mach/bf54x_keys.h>
c6c4d7bb
BW		 28#include <linux/input.h>
29#include <linux/spi/ad7877.h>
24a07a12
RH		 30
31/*
32 * Name the Board for the /proc/cpuinfo
33 */
fe85cad2 34const char bfin_board_name[] = "ADI BF548-EZKIT";
24a07a12
RH		 35
36/*
37 * Driver needs to know address, irq and flag pin.
38 */
39
0a6304a9 40#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
3f375690
MH		 41#include <linux/usb/isp1760.h>
42static struct resource bfin_isp1760_resources[] = {
0a6304a9 43 [0] = {
0a6304a9
MH		 44 .start = 0x2C0C0000,
45 .end = 0x2C0C0000 + 0xfffff,
46 .flags = IORESOURCE_MEM,
47 },
48 [1] = {
49 .start = IRQ_PG7,
50 .end = IRQ_PG7,
51 .flags = IORESOURCE_IRQ,
52 },
53};
54
3f375690
MH		 55static struct isp1760_platform_data isp1760_priv = {
56 .is_isp1761 = 0,
3f375690
MH		 57 .bus_width_16 = 1,
58 .port1_otg = 0,
59 .analog_oc = 0,
60 .dack_polarity_high = 0,
61 .dreq_polarity_high = 0,
0a6304a9
MH		 62};
63
3f375690 64static struct platform_device bfin_isp1760_device = {
c6feb768 65 .name = "isp1760",
3f375690
MH		 66 .id = 0,
67 .dev = {
68 .platform_data = &isp1760_priv,
69 },
70 .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
71 .resource = bfin_isp1760_resources,
0a6304a9 72};
0a6304a9
MH		 73#endif
74
c6c4d7bb
BW		 75#if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE)
76
639f6571 77#include <mach/bf54x-lq043.h>
c6c4d7bb
BW		 78
79static struct bfin_bf54xfb_mach_info bf54x_lq043_data = {
0e101ec1
SP		 80 .width = 95,
81 .height = 54,
c6c4d7bb
BW		 82 .xres = {480, 480, 480},
83 .yres = {272, 272, 272},
84 .bpp = {24, 24, 24},
85 .disp = GPIO_PE3,
86};
87
88static struct resource bf54x_lq043_resources[] = {
89 {
90 .start = IRQ_EPPI0_ERR,
91 .end = IRQ_EPPI0_ERR,
92 .flags = IORESOURCE_IRQ,
93 },
94};
95
96static struct platform_device bf54x_lq043_device = {
97 .name = "bf54x-lq043",
98 .id = -1,
99 .num_resources = ARRAY_SIZE(bf54x_lq043_resources),
100 .resource = bf54x_lq043_resources,
101 .dev = {
102 .platform_data = &bf54x_lq043_data,
103 },
104};
105#endif
106
107#if defined(CONFIG_KEYBOARD_BFIN) || defined(CONFIG_KEYBOARD_BFIN_MODULE)
8f740ef3 108static const unsigned int bf548_keymap[] = {
c6c4d7bb
BW		 109 KEYVAL(0, 0, KEY_ENTER),
110 KEYVAL(0, 1, KEY_HELP),
111 KEYVAL(0, 2, KEY_0),
112 KEYVAL(0, 3, KEY_BACKSPACE),
113 KEYVAL(1, 0, KEY_TAB),
114 KEYVAL(1, 1, KEY_9),
115 KEYVAL(1, 2, KEY_8),
116 KEYVAL(1, 3, KEY_7),
117 KEYVAL(2, 0, KEY_DOWN),
118 KEYVAL(2, 1, KEY_6),
119 KEYVAL(2, 2, KEY_5),
120 KEYVAL(2, 3, KEY_4),
121 KEYVAL(3, 0, KEY_UP),
122 KEYVAL(3, 1, KEY_3),
123 KEYVAL(3, 2, KEY_2),
124 KEYVAL(3, 3, KEY_1),
125};
126
127static struct bfin_kpad_platform_data bf54x_kpad_data = {
128 .rows = 4,
129 .cols = 4,
8f740ef3
MH		 130 .keymap = bf548_keymap,
131 .keymapsize = ARRAY_SIZE(bf548_keymap),
c6c4d7bb
BW		 132 .repeat = 0,
133 .debounce_time = 5000, /* ns (5ms) */
134 .coldrive_time = 1000, /* ns (1ms) */
135 .keyup_test_interval = 50, /* ms (50ms) */
136};
137
138static struct resource bf54x_kpad_resources[] = {
139 {
140 .start = IRQ_KEY,
141 .end = IRQ_KEY,
142 .flags = IORESOURCE_IRQ,
143 },
144};
145
146static struct platform_device bf54x_kpad_device = {
147 .name = "bf54x-keys",
148 .id = -1,
149 .num_resources = ARRAY_SIZE(bf54x_kpad_resources),
150 .resource = bf54x_kpad_resources,
151 .dev = {
152 .platform_data = &bf54x_kpad_data,
153 },
154};
155#endif
156
adfc0467 157#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
aca5e4aa
MH		 158#include <asm/bfin_rotary.h>
159
160static struct bfin_rotary_platform_data bfin_rotary_data = {
161 /*.rotary_up_key = KEY_UP,*/
162 /*.rotary_down_key = KEY_DOWN,*/
163 .rotary_rel_code = REL_WHEEL,
164 .rotary_button_key = KEY_ENTER,
165 .debounce = 10, /* 0..17 */
166 .mode = ROT_QUAD_ENC | ROT_DEBE,
167};
168
169static struct resource bfin_rotary_resources[] = {
170 {
171 .start = IRQ_CNT,
172 .end = IRQ_CNT,
173 .flags = IORESOURCE_IRQ,
174 },
175};
176
177static struct platform_device bfin_rotary_device = {
178 .name = "bfin-rotary",
179 .id = -1,
180 .num_resources = ARRAY_SIZE(bfin_rotary_resources),
181 .resource = bfin_rotary_resources,
182 .dev = {
183 .platform_data = &bfin_rotary_data,
184 },
185};
186#endif
187
ffc4d8bc 188#if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE)
57af8edf 189#include <linux/input/adxl34x.h>
ffc4d8bc
MH		 190static const struct adxl34x_platform_data adxl34x_info = {
191 .x_axis_offset = 0,
192 .y_axis_offset = 0,
193 .z_axis_offset = 0,
194 .tap_threshold = 0x31,
195 .tap_duration = 0x10,
196 .tap_latency = 0x60,
197 .tap_window = 0xF0,
198 .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
199 .act_axis_control = 0xFF,
200 .activity_threshold = 5,
201 .inactivity_threshold = 3,
202 .inactivity_time = 4,
203 .free_fall_threshold = 0x7,
204 .free_fall_time = 0x20,
205 .data_rate = 0x8,
206 .data_range = ADXL_FULL_RES,
207
208 .ev_type = EV_ABS,
209 .ev_code_x = ABS_X, /* EV_REL */
210 .ev_code_y = ABS_Y, /* EV_REL */
211 .ev_code_z = ABS_Z, /* EV_REL */
212
57af8edf 213 .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
ffc4d8bc
MH		 214
215/* .ev_code_ff = KEY_F,*/ /* EV_KEY */
216/* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */
217 .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
218 .fifo_mode = ADXL_FIFO_STREAM,
5db4036b
MH		 219 .orientation_enable = ADXL_EN_ORIENTATION_3D,
220 .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8,
221 .divisor_length = ADXL_LP_FILTER_DIVISOR_16,
222 /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */
223 .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C},
ffc4d8bc
MH		 224};
225#endif
226
24a07a12
RH		 227#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
228static struct platform_device rtc_device = {
229 .name = "rtc-bfin",
230 .id = -1,
231};
232#endif
233
234#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
24a07a12 235#ifdef CONFIG_SERIAL_BFIN_UART0
6bd1fbea 236static struct resource bfin_uart0_resources[] = {
24a07a12 237 {
6bd1fbea
SZ		 238 .start = UART0_DLL,
239 .end = UART0_RBR+2,
24a07a12
RH		 240 .flags = IORESOURCE_MEM,
241 },
6bd1fbea
SZ		 242 {
243 .start = IRQ_UART0_RX,
244 .end = IRQ_UART0_RX+1,
245 .flags = IORESOURCE_IRQ,
246 },
247 {
248 .start = IRQ_UART0_ERROR,
249 .end = IRQ_UART0_ERROR,
250 .flags = IORESOURCE_IRQ,
251 },
252 {
253 .start = CH_UART0_TX,
254 .end = CH_UART0_TX,
255 .flags = IORESOURCE_DMA,
256 },
257 {
258 .start = CH_UART0_RX,
259 .end = CH_UART0_RX,
260 .flags = IORESOURCE_DMA,
261 },
262};
263
264unsigned short bfin_uart0_peripherals[] = {
265 P_UART0_TX, P_UART0_RX, 0
266};
267
268static struct platform_device bfin_uart0_device = {
269 .name = "bfin-uart",
270 .id = 0,
271 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
272 .resource = bfin_uart0_resources,
273 .dev = {
274 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
275 },
276};
24a07a12
RH		 277#endif
278#ifdef CONFIG_SERIAL_BFIN_UART1
6bd1fbea 279static struct resource bfin_uart1_resources[] = {
24a07a12 280 {
6bd1fbea
SZ		 281 .start = UART1_DLL,
282 .end = UART1_RBR+2,
24a07a12
RH		 283 .flags = IORESOURCE_MEM,
284 },
6bd1fbea
SZ		 285 {
286 .start = IRQ_UART1_RX,
287 .end = IRQ_UART1_RX+1,
288 .flags = IORESOURCE_IRQ,
289 },
290 {
291 .start = IRQ_UART1_ERROR,
292 .end = IRQ_UART1_ERROR,
293 .flags = IORESOURCE_IRQ,
294 },
295 {
296 .start = CH_UART1_TX,
297 .end = CH_UART1_TX,
298 .flags = IORESOURCE_DMA,
299 },
300 {
301 .start = CH_UART1_RX,
302 .end = CH_UART1_RX,
303 .flags = IORESOURCE_DMA,
304 },
305#ifdef CONFIG_BFIN_UART1_CTSRTS
306 { /* CTS pin -- 0 means not supported */
307 .start = GPIO_PE10,
308 .end = GPIO_PE10,
309 .flags = IORESOURCE_IO,
310 },
311 { /* RTS pin -- 0 means not supported */
312 .start = GPIO_PE9,
313 .end = GPIO_PE9,
314 .flags = IORESOURCE_IO,
315 },
316#endif
317};
318
319unsigned short bfin_uart1_peripherals[] = {
320 P_UART1_TX, P_UART1_RX,
321#ifdef CONFIG_BFIN_UART1_CTSRTS
322 P_UART1_RTS, P_UART1_CTS,
323#endif
324 0
325};
326
327static struct platform_device bfin_uart1_device = {
328 .name = "bfin-uart",
329 .id = 1,
330 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
331 .resource = bfin_uart1_resources,
332 .dev = {
333 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
334 },
335};
24a07a12
RH		 336#endif
337#ifdef CONFIG_SERIAL_BFIN_UART2
6bd1fbea 338static struct resource bfin_uart2_resources[] = {
24a07a12 339 {
6bd1fbea
SZ		 340 .start = UART2_DLL,
341 .end = UART2_RBR+2,
24a07a12
RH		 342 .flags = IORESOURCE_MEM,
343 },
6bd1fbea
SZ		 344 {
345 .start = IRQ_UART2_RX,
346 .end = IRQ_UART2_RX+1,
347 .flags = IORESOURCE_IRQ,
348 },
349 {
350 .start = IRQ_UART2_ERROR,
351 .end = IRQ_UART2_ERROR,
352 .flags = IORESOURCE_IRQ,
353 },
354 {
355 .start = CH_UART2_TX,
356 .end = CH_UART2_TX,
357 .flags = IORESOURCE_DMA,
358 },
359 {
360 .start = CH_UART2_RX,
361 .end = CH_UART2_RX,
362 .flags = IORESOURCE_DMA,
363 },
364};
365
366unsigned short bfin_uart2_peripherals[] = {
367 P_UART2_TX, P_UART2_RX, 0
368};
369
370static struct platform_device bfin_uart2_device = {
371 .name = "bfin-uart",
372 .id = 2,
373 .num_resources = ARRAY_SIZE(bfin_uart2_resources),
374 .resource = bfin_uart2_resources,
375 .dev = {
376 .platform_data = &bfin_uart2_peripherals, /* Passed to driver */
377 },
378};
24a07a12
RH		 379#endif
380#ifdef CONFIG_SERIAL_BFIN_UART3
6bd1fbea 381static struct resource bfin_uart3_resources[] = {
24a07a12 382 {
6bd1fbea
SZ		 383 .start = UART3_DLL,
384 .end = UART3_RBR+2,
cc2e16bd 385 .flags = IORESOURCE_MEM,
24a07a12 386 },
6bd1fbea
SZ		 387 {
388 .start = IRQ_UART3_RX,
389 .end = IRQ_UART3_RX+1,
390 .flags = IORESOURCE_IRQ,
391 },
392 {
393 .start = IRQ_UART3_ERROR,
394 .end = IRQ_UART3_ERROR,
395 .flags = IORESOURCE_IRQ,
396 },
397 {
398 .start = CH_UART3_TX,
399 .end = CH_UART3_TX,
400 .flags = IORESOURCE_DMA,
401 },
402 {
403 .start = CH_UART3_RX,
404 .end = CH_UART3_RX,
405 .flags = IORESOURCE_DMA,
406 },
407#ifdef CONFIG_BFIN_UART3_CTSRTS
408 { /* CTS pin -- 0 means not supported */
409 .start = GPIO_PB3,
410 .end = GPIO_PB3,
411 .flags = IORESOURCE_IO,
412 },
413 { /* RTS pin -- 0 means not supported */
414 .start = GPIO_PB2,
415 .end = GPIO_PB2,
416 .flags = IORESOURCE_IO,
417 },
24a07a12
RH		 418#endif
419};
420
6bd1fbea
SZ		 421unsigned short bfin_uart3_peripherals[] = {
422 P_UART3_TX, P_UART3_RX,
423#ifdef CONFIG_BFIN_UART3_CTSRTS
424 P_UART3_RTS, P_UART3_CTS,
425#endif
426 0
427};
428
429static struct platform_device bfin_uart3_device = {
24a07a12 430 .name = "bfin-uart",
6bd1fbea
SZ		 431 .id = 3,
432 .num_resources = ARRAY_SIZE(bfin_uart3_resources),
433 .resource = bfin_uart3_resources,
434 .dev = {
435 .platform_data = &bfin_uart3_peripherals, /* Passed to driver */
436 },
24a07a12
RH		 437};
438#endif
6bd1fbea 439#endif
24a07a12 440
5be36d22 441#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
5be36d22 442#ifdef CONFIG_BFIN_SIR0
42bd8bcb 443static struct resource bfin_sir0_resources[] = {
5be36d22
GY		 444 {
445 .start = 0xFFC00400,
446 .end = 0xFFC004FF,
447 .flags = IORESOURCE_MEM,
448 },
42bd8bcb
GY		 449 {
450 .start = IRQ_UART0_RX,
451 .end = IRQ_UART0_RX+1,
452 .flags = IORESOURCE_IRQ,
453 },
454 {
455 .start = CH_UART0_RX,
456 .end = CH_UART0_RX+1,
457 .flags = IORESOURCE_DMA,
458 },
459};
460static struct platform_device bfin_sir0_device = {
461 .name = "bfin_sir",
462 .id = 0,
463 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
464 .resource = bfin_sir0_resources,
465};
5be36d22
GY		 466#endif
467#ifdef CONFIG_BFIN_SIR1
42bd8bcb 468static struct resource bfin_sir1_resources[] = {
5be36d22
GY		 469 {
470 .start = 0xFFC02000,
471 .end = 0xFFC020FF,
472 .flags = IORESOURCE_MEM,
473 },
42bd8bcb
GY		 474 {
475 .start = IRQ_UART1_RX,
476 .end = IRQ_UART1_RX+1,
477 .flags = IORESOURCE_IRQ,
478 },
479 {
480 .start = CH_UART1_RX,
481 .end = CH_UART1_RX+1,
482 .flags = IORESOURCE_DMA,
483 },
484};
485static struct platform_device bfin_sir1_device = {
486 .name = "bfin_sir",
487 .id = 1,
488 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
489 .resource = bfin_sir1_resources,
490};
5be36d22
GY		 491#endif
492#ifdef CONFIG_BFIN_SIR2
42bd8bcb 493static struct resource bfin_sir2_resources[] = {
5be36d22
GY		 494 {
495 .start = 0xFFC02100,
496 .end = 0xFFC021FF,
497 .flags = IORESOURCE_MEM,
498 },
42bd8bcb
GY		 499 {
500 .start = IRQ_UART2_RX,
501 .end = IRQ_UART2_RX+1,
502 .flags = IORESOURCE_IRQ,
503 },
504 {
505 .start = CH_UART2_RX,
506 .end = CH_UART2_RX+1,
507 .flags = IORESOURCE_DMA,
508 },
509};
510static struct platform_device bfin_sir2_device = {
511 .name = "bfin_sir",
512 .id = 2,
513 .num_resources = ARRAY_SIZE(bfin_sir2_resources),
514 .resource = bfin_sir2_resources,
515};
5be36d22
GY		 516#endif
517#ifdef CONFIG_BFIN_SIR3
42bd8bcb 518static struct resource bfin_sir3_resources[] = {
5be36d22
GY		 519 {
520 .start = 0xFFC03100,
521 .end = 0xFFC031FF,
522 .flags = IORESOURCE_MEM,
523 },
42bd8bcb
GY		 524 {
525 .start = IRQ_UART3_RX,
526 .end = IRQ_UART3_RX+1,
527 .flags = IORESOURCE_IRQ,
528 },
529 {
530 .start = CH_UART3_RX,
531 .end = CH_UART3_RX+1,
532 .flags = IORESOURCE_DMA,
533 },
5be36d22 534};
42bd8bcb 535static struct platform_device bfin_sir3_device = {
5be36d22 536 .name = "bfin_sir",
42bd8bcb
GY		 537 .id = 3,
538 .num_resources = ARRAY_SIZE(bfin_sir3_resources),
539 .resource = bfin_sir3_resources,
5be36d22
GY		 540};
541#endif
42bd8bcb 542#endif
5be36d22 543
c6c4d7bb 544#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
7a8b71db
MF		 545#include <linux/smsc911x.h>
546
c6c4d7bb
BW		 547static struct resource smsc911x_resources[] = {
548 {
549 .name = "smsc911x-memory",
550 .start = 0x24000000,
551 .end = 0x24000000 + 0xFF,
552 .flags = IORESOURCE_MEM,
553 },
554 {
555 .start = IRQ_PE8,
556 .end = IRQ_PE8,
557 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
558 },
559};
7a8b71db
MF		 560
561static struct smsc911x_platform_config smsc911x_config = {
562 .flags = SMSC911X_USE_32BIT,
563 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
564 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
565 .phy_interface = PHY_INTERFACE_MODE_MII,
566};
567
c6c4d7bb
BW		 568static struct platform_device smsc911x_device = {
569 .name = "smsc911x",
570 .id = 0,
571 .num_resources = ARRAY_SIZE(smsc911x_resources),
572 .resource = smsc911x_resources,
7a8b71db
MF		 573 .dev = {
574 .platform_data = &smsc911x_config,
575 },
c6c4d7bb
BW		 576};
577#endif
578
c6c4d7bb
BW		 579#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
580static struct resource musb_resources[] = {
581 [0] = {
582 .start = 0xFFC03C00,
583 .end = 0xFFC040FF,
584 .flags = IORESOURCE_MEM,
585 },
586 [1] = { /* general IRQ */
587 .start = IRQ_USB_INT0,
588 .end = IRQ_USB_INT0,
589 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
590 },
591 [2] = { /* DMA IRQ */
592 .start = IRQ_USB_DMA,
593 .end = IRQ_USB_DMA,
594 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
595 },
596};
597
50041acb
BW		 598static struct musb_hdrc_config musb_config = {
599 .multipoint = 0,
600 .dyn_fifo = 0,
601 .soft_con = 1,
602 .dma = 1,
fea05dac
BW		 603 .num_eps = 8,
604 .dma_channels = 8,
50041acb 605 .gpio_vrsel = GPIO_PE7,
85eb0e4b
CC		 606 /* Some custom boards need to be active low, just set it to "0"
607 * if it is the case.
608 */
609 .gpio_vrsel_active = 1,
50041acb
BW		 610};
611
c6c4d7bb 612static struct musb_hdrc_platform_data musb_plat = {
2935077e 613#if defined(CONFIG_USB_MUSB_OTG)
c6c4d7bb 614 .mode = MUSB_OTG,
2935077e 615#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
c6c4d7bb 616 .mode = MUSB_HOST,
2935077e 617#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
c6c4d7bb
BW		 618 .mode = MUSB_PERIPHERAL,
619#endif
50041acb 620 .config = &musb_config,
c6c4d7bb
BW		 621};
622
623static u64 musb_dmamask = ~(u32)0;
624
625static struct platform_device musb_device = {
626 .name = "musb_hdrc",
627 .id = 0,
628 .dev = {
629 .dma_mask = &musb_dmamask,
630 .coherent_dma_mask = 0xffffffff,
631 .platform_data = &musb_plat,
632 },
633 .num_resources = ARRAY_SIZE(musb_resources),
634 .resource = musb_resources,
635};
636#endif
637
df5de261
SZ		 638#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
639#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
640static struct resource bfin_sport0_uart_resources[] = {
641 {
642 .start = SPORT0_TCR1,
643 .end = SPORT0_MRCS3+4,
644 .flags = IORESOURCE_MEM,
645 },
646 {
647 .start = IRQ_SPORT0_RX,
648 .end = IRQ_SPORT0_RX+1,
649 .flags = IORESOURCE_IRQ,
650 },
651 {
652 .start = IRQ_SPORT0_ERROR,
653 .end = IRQ_SPORT0_ERROR,
654 .flags = IORESOURCE_IRQ,
655 },
656};
657
658unsigned short bfin_sport0_peripherals[] = {
659 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
660 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
661};
662
663static struct platform_device bfin_sport0_uart_device = {
664 .name = "bfin-sport-uart",
665 .id = 0,
666 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
667 .resource = bfin_sport0_uart_resources,
668 .dev = {
669 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
670 },
671};
672#endif
673#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
674static struct resource bfin_sport1_uart_resources[] = {
675 {
676 .start = SPORT1_TCR1,
677 .end = SPORT1_MRCS3+4,
678 .flags = IORESOURCE_MEM,
679 },
680 {
681 .start = IRQ_SPORT1_RX,
682 .end = IRQ_SPORT1_RX+1,
683 .flags = IORESOURCE_IRQ,
684 },
685 {
686 .start = IRQ_SPORT1_ERROR,
687 .end = IRQ_SPORT1_ERROR,
688 .flags = IORESOURCE_IRQ,
689 },
690};
691
692unsigned short bfin_sport1_peripherals[] = {
693 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
694 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
695};
696
697static struct platform_device bfin_sport1_uart_device = {
698 .name = "bfin-sport-uart",
699 .id = 1,
700 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
701 .resource = bfin_sport1_uart_resources,
702 .dev = {
703 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
704 },
705};
706#endif
707#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
708static struct resource bfin_sport2_uart_resources[] = {
709 {
710 .start = SPORT2_TCR1,
711 .end = SPORT2_MRCS3+4,
712 .flags = IORESOURCE_MEM,
713 },
714 {
715 .start = IRQ_SPORT2_RX,
716 .end = IRQ_SPORT2_RX+1,
717 .flags = IORESOURCE_IRQ,
718 },
719 {
720 .start = IRQ_SPORT2_ERROR,
721 .end = IRQ_SPORT2_ERROR,
722 .flags = IORESOURCE_IRQ,
723 },
724};
725
726unsigned short bfin_sport2_peripherals[] = {
727 P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
728 P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
729};
730
731static struct platform_device bfin_sport2_uart_device = {
732 .name = "bfin-sport-uart",
733 .id = 2,
734 .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
735 .resource = bfin_sport2_uart_resources,
736 .dev = {
737 .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
738 },
739};
740#endif
741#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
742static struct resource bfin_sport3_uart_resources[] = {
743 {
744 .start = SPORT3_TCR1,
745 .end = SPORT3_MRCS3+4,
746 .flags = IORESOURCE_MEM,
747 },
748 {
749 .start = IRQ_SPORT3_RX,
750 .end = IRQ_SPORT3_RX+1,
751 .flags = IORESOURCE_IRQ,
752 },
753 {
754 .start = IRQ_SPORT3_ERROR,
755 .end = IRQ_SPORT3_ERROR,
756 .flags = IORESOURCE_IRQ,
757 },
758};
759
760unsigned short bfin_sport3_peripherals[] = {
761 P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS,
762 P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0
763};
764
765static struct platform_device bfin_sport3_uart_device = {
766 .name = "bfin-sport-uart",
767 .id = 3,
768 .num_resources = ARRAY_SIZE(bfin_sport3_uart_resources),
769 .resource = bfin_sport3_uart_resources,
770 .dev = {
771 .platform_data = &bfin_sport3_peripherals, /* Passed to driver */
772 },
773};
774#endif
775#endif
776
706a01b1
BS		 777#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
778unsigned short bfin_can_peripherals[] = {
779 P_CAN0_RX, P_CAN0_TX, 0
780};
781
782static struct resource bfin_can_resources[] = {
783 {
784 .start = 0xFFC02A00,
785 .end = 0xFFC02FFF,
786 .flags = IORESOURCE_MEM,
787 },
788 {
789 .start = IRQ_CAN0_RX,
790 .end = IRQ_CAN0_RX,
791 .flags = IORESOURCE_IRQ,
792 },
793 {
794 .start = IRQ_CAN0_TX,
795 .end = IRQ_CAN0_TX,
796 .flags = IORESOURCE_IRQ,
797 },
798 {
799 .start = IRQ_CAN0_ERROR,
800 .end = IRQ_CAN0_ERROR,
801 .flags = IORESOURCE_IRQ,
802 },
803};
804
805static struct platform_device bfin_can_device = {
806 .name = "bfin_can",
807 .num_resources = ARRAY_SIZE(bfin_can_resources),
808 .resource = bfin_can_resources,
809 .dev = {
810 .platform_data = &bfin_can_peripherals, /* Passed to driver */
811 },
812};
813#endif
814
c6c4d7bb
BW		 815#if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE)
816static struct resource bfin_atapi_resources[] = {
817 {
818 .start = 0xFFC03800,
819 .end = 0xFFC0386F,
820 .flags = IORESOURCE_MEM,
821 },
822 {
823 .start = IRQ_ATAPI_ERR,
824 .end = IRQ_ATAPI_ERR,
825 .flags = IORESOURCE_IRQ,
826 },
827};
828
829static struct platform_device bfin_atapi_device = {
830 .name = "pata-bf54x",
831 .id = -1,
832 .num_resources = ARRAY_SIZE(bfin_atapi_resources),
833 .resource = bfin_atapi_resources,
834};
835#endif
836
837#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
838static struct mtd_partition partition_info[] = {
839 {
aa582977 840 .name = "linux kernel(nand)",
c6c4d7bb 841 .offset = 0,
f4585a08 842 .size = 4 * 1024 * 1024,
c6c4d7bb
BW		 843 },
844 {
aa582977 845 .name = "file system(nand)",
edf05641
MF		 846 .offset = MTDPART_OFS_APPEND,
847 .size = MTDPART_SIZ_FULL,
c6c4d7bb
BW		 848 },
849};
850
851static struct bf5xx_nand_platform bf5xx_nand_platform = {
c6c4d7bb
BW		 852 .data_width = NFC_NWIDTH_8,
853 .partitions = partition_info,
854 .nr_partitions = ARRAY_SIZE(partition_info),
855 .rd_dly = 3,
856 .wr_dly = 3,
857};
858
859static struct resource bf5xx_nand_resources[] = {
860 {
861 .start = 0xFFC03B00,
862 .end = 0xFFC03B4F,
863 .flags = IORESOURCE_MEM,
864 },
865 {
866 .start = CH_NFC,
867 .end = CH_NFC,
868 .flags = IORESOURCE_IRQ,
869 },
870};
871
872static struct platform_device bf5xx_nand_device = {
873 .name = "bf5xx-nand",
874 .id = 0,
875 .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
876 .resource = bf5xx_nand_resources,
877 .dev = {
878 .platform_data = &bf5xx_nand_platform,
879 },
880};
881#endif
882
3d7e6cf8 883#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
501674a5
CC		 884
885static struct bfin_sd_host bfin_sdh_data = {
886 .dma_chan = CH_SDH,
887 .irq_int0 = IRQ_SDH_MASK0,
888 .pin_req = {P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0},
889};
890
c6c4d7bb
BW		 891static struct platform_device bf54x_sdh_device = {
892 .name = "bfin-sdh",
893 .id = 0,
501674a5
CC		 894 .dev = {
895 .platform_data = &bfin_sdh_data,
896 },
c6c4d7bb
BW		 897};
898#endif
899
793dc27b 900#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
de8c43f2
MF		 901static struct mtd_partition ezkit_partitions[] = {
902 {
aa582977 903 .name = "bootloader(nor)",
edf05641 904 .size = 0x40000,
de8c43f2
MF		 905 .offset = 0,
906 }, {
aa582977 907 .name = "linux kernel(nor)",
664d0403 908 .size = 0x400000,
de8c43f2
MF		 909 .offset = MTDPART_OFS_APPEND,
910 }, {
aa582977 911 .name = "file system(nor)",
de8c43f2
MF		 912 .size = MTDPART_SIZ_FULL,
913 .offset = MTDPART_OFS_APPEND,
914 }
915};
916
917static struct physmap_flash_data ezkit_flash_data = {
918 .width = 2,
919 .parts = ezkit_partitions,
920 .nr_parts = ARRAY_SIZE(ezkit_partitions),
921};
922
923static struct resource ezkit_flash_resource = {
924 .start = 0x20000000,
664d0403 925 .end = 0x21ffffff,
de8c43f2
MF		 926 .flags = IORESOURCE_MEM,
927};
928
929static struct platform_device ezkit_flash_device = {
930 .name = "physmap-flash",
931 .id = 0,
932 .dev = {
933 .platform_data = &ezkit_flash_data,
934 },
935 .num_resources = 1,
936 .resource = &ezkit_flash_resource,
937};
793dc27b 938#endif
de8c43f2 939
c6c4d7bb
BW		 940#if defined(CONFIG_MTD_M25P80) \
941 || defined(CONFIG_MTD_M25P80_MODULE)
942/* SPI flash chip (m25p16) */
943static struct mtd_partition bfin_spi_flash_partitions[] = {
944 {
aa582977 945 .name = "bootloader(spi)",
c6c4d7bb
BW		 946 .size = 0x00040000,
947 .offset = 0,
948 .mask_flags = MTD_CAP_ROM
949 }, {
aa582977 950 .name = "linux kernel(spi)",
edf05641
MF		 951 .size = MTDPART_SIZ_FULL,
952 .offset = MTDPART_OFS_APPEND,
c6c4d7bb
BW		 953 }
954};
955
956static struct flash_platform_data bfin_spi_flash_data = {
957 .name = "m25p80",
958 .parts = bfin_spi_flash_partitions,
959 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
960 .type = "m25p16",
961};
962
963static struct bfin5xx_spi_chip spi_flash_chip_info = {
964 .enable_dma = 0, /* use dma transfer with this chip*/
965 .bits_per_word = 8,
c6c4d7bb
BW		 966};
967#endif
968
d40bd71f
BS		 969#if defined(CONFIG_SND_BLACKFIN_AD183X) \
970 || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE)
37fa2421
BS		 971static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
972 .enable_dma = 0,
973 .bits_per_word = 16,
974};
975#endif
976
c6c4d7bb
BW		 977#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
978static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
c6c4d7bb
BW		 979 .enable_dma = 0,
980 .bits_per_word = 16,
981};
982
983static const struct ad7877_platform_data bfin_ad7877_ts_info = {
984 .model = 7877,
985 .vref_delay_usecs = 50, /* internal, no capacitor */
986 .x_plate_ohms = 419,
987 .y_plate_ohms = 486,
988 .pressure_max = 1000,
989 .pressure_min = 0,
990 .stopacq_polarity = 1,
991 .first_conversion_delay = 3,
992 .acquisition_time = 1,
993 .averaging = 1,
994 .pen_down_acc_interval = 1,
995};
996#endif
997
6e668936
MH		 998#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
999static struct bfin5xx_spi_chip spidev_chip_info = {
1000 .enable_dma = 0,
1001 .bits_per_word = 8,
1002};
1003#endif
1004
ffc4d8bc
MH		 1005#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
1006static struct bfin5xx_spi_chip spi_adxl34x_chip_info = {
1007 .enable_dma = 0, /* use dma transfer with this chip*/
1008 .bits_per_word = 8,
ffc4d8bc
MH		 1009};
1010#endif
1011
5bda2723 1012static struct spi_board_info bfin_spi_board_info[] __initdata = {
c6c4d7bb
BW		 1013#if defined(CONFIG_MTD_M25P80) \
1014 || defined(CONFIG_MTD_M25P80_MODULE)
1015 {
1016 /* the modalias must be the same as spi device driver name */
1017 .modalias = "m25p80", /* Name of spi_driver for this device */
1018 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
1019 .bus_num = 0, /* Framework bus number */
1020 .chip_select = 1, /* SPI_SSEL1*/
1021 .platform_data = &bfin_spi_flash_data,
1022 .controller_data = &spi_flash_chip_info,
1023 .mode = SPI_MODE_3,
1024 },
1025#endif
d40bd71f
BS		 1026#if defined(CONFIG_SND_BLACKFIN_AD183X) \
1027 || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE)
37fa2421 1028 {
dac98174 1029 .modalias = "ad1836",
37fa2421
BS		 1030 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
1031 .bus_num = 1,
1032 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
1033 .controller_data = &ad1836_spi_chip_info,
1034 },
1035#endif
c6c4d7bb 1036#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
ffc4d8bc
MH		 1037 {
1038 .modalias = "ad7877",
1039 .platform_data = &bfin_ad7877_ts_info,
1040 .irq = IRQ_PB4, /* old boards (<=Rev 1.3) use IRQ_PJ11 */
1041 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
1042 .bus_num = 0,
1043 .chip_select = 2,
1044 .controller_data = &spi_ad7877_chip_info,
1045 },
c6c4d7bb 1046#endif
6e668936
MH		 1047#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
1048 {
1049 .modalias = "spidev",
1050 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
1051 .bus_num = 0,
1052 .chip_select = 1,
1053 .controller_data = &spidev_chip_info,
1054 },
1055#endif
ffc4d8bc
MH		 1056#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
1057 {
1058 .modalias = "adxl34x",
1059 .platform_data = &adxl34x_info,
1060 .irq = IRQ_PC5,
1061 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
1062 .bus_num = 1,
1063 .chip_select = 2,
1064 .controller_data = &spi_adxl34x_chip_info,
1065 .mode = SPI_MODE_3,
1066 },
1067#endif
c6c4d7bb 1068};
5bda2723 1069#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
c6c4d7bb
BW		 1070/* SPI (0) */
1071static struct resource bfin_spi0_resource[] = {
1072 [0] = {
1073 .start = SPI0_REGBASE,
1074 .end = SPI0_REGBASE + 0xFF,
1075 .flags = IORESOURCE_MEM,
1076 },
1077 [1] = {
1078 .start = CH_SPI0,
1079 .end = CH_SPI0,
53122693
YL		 1080 .flags = IORESOURCE_DMA,
1081 },
1082 [2] = {
1083 .start = IRQ_SPI0,
1084 .end = IRQ_SPI0,
c6c4d7bb
BW		 1085 .flags = IORESOURCE_IRQ,
1086 }
1087};
1088
1089/* SPI (1) */
1090static struct resource bfin_spi1_resource[] = {
1091 [0] = {
1092 .start = SPI1_REGBASE,
1093 .end = SPI1_REGBASE + 0xFF,
1094 .flags = IORESOURCE_MEM,
1095 },
1096 [1] = {
1097 .start = CH_SPI1,
1098 .end = CH_SPI1,
53122693
YL		 1099 .flags = IORESOURCE_DMA,
1100 },
1101 [2] = {
1102 .start = IRQ_SPI1,
1103 .end = IRQ_SPI1,
c6c4d7bb
BW		 1104 .flags = IORESOURCE_IRQ,
1105 }
1106};
1107
1108/* SPI controller data */
5d448dd5 1109static struct bfin5xx_spi_master bf54x_spi_master_info0 = {
4e4d496e 1110 .num_chipselect = 3,
c6c4d7bb 1111 .enable_dma = 1, /* master has the ability to do dma transfer */
5d448dd5 1112 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
c6c4d7bb
BW		 1113};
1114
1115static struct platform_device bf54x_spi_master0 = {
1116 .name = "bfin-spi",
1117 .id = 0, /* Bus number */
1118 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
1119 .resource = bfin_spi0_resource,
1120 .dev = {
5d448dd5 1121 .platform_data = &bf54x_spi_master_info0, /* Passed to driver */
c6c4d7bb
BW		 1122 },
1123};
1124
5d448dd5 1125static struct bfin5xx_spi_master bf54x_spi_master_info1 = {
4e4d496e 1126 .num_chipselect = 3,
5d448dd5
BW		 1127 .enable_dma = 1, /* master has the ability to do dma transfer */
1128 .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
1129};
1130
c6c4d7bb
BW		 1131static struct platform_device bf54x_spi_master1 = {
1132 .name = "bfin-spi",
1133 .id = 1, /* Bus number */
1134 .num_resources = ARRAY_SIZE(bfin_spi1_resource),
1135 .resource = bfin_spi1_resource,
1136 .dev = {
5d448dd5 1137 .platform_data = &bf54x_spi_master_info1, /* Passed to driver */
c6c4d7bb
BW		 1138 },
1139};
1140#endif /* spi master and devices */
1141
1142#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
1143static struct resource bfin_twi0_resource[] = {
1144 [0] = {
1145 .start = TWI0_REGBASE,
1146 .end = TWI0_REGBASE + 0xFF,
1147 .flags = IORESOURCE_MEM,
1148 },
1149 [1] = {
1150 .start = IRQ_TWI0,
1151 .end = IRQ_TWI0,
1152 .flags = IORESOURCE_IRQ,
1153 },
1154};
1155
1156static struct platform_device i2c_bfin_twi0_device = {
1157 .name = "i2c-bfin-twi",
1158 .id = 0,
1159 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
1160 .resource = bfin_twi0_resource,
1161};
1162
7160e950 1163#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
c6c4d7bb
BW		 1164static struct resource bfin_twi1_resource[] = {
1165 [0] = {
1166 .start = TWI1_REGBASE,
1167 .end = TWI1_REGBASE + 0xFF,
1168 .flags = IORESOURCE_MEM,
1169 },
1170 [1] = {
1171 .start = IRQ_TWI1,
1172 .end = IRQ_TWI1,
1173 .flags = IORESOURCE_IRQ,
1174 },
1175};
1176
1177static struct platform_device i2c_bfin_twi1_device = {
1178 .name = "i2c-bfin-twi",
1179 .id = 1,
1180 .num_resources = ARRAY_SIZE(bfin_twi1_resource),
1181 .resource = bfin_twi1_resource,
1182};
1183#endif
7160e950 1184#endif
c6c4d7bb 1185
81d9c7f2
BW		 1186static struct i2c_board_info __initdata bfin_i2c_board_info0[] = {
1187};
1188
1189#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
1190static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
ebd58333 1191#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
81d9c7f2
BW		 1192 {
1193 I2C_BOARD_INFO("pcf8574_lcd", 0x22),
81d9c7f2
BW		 1194 },
1195#endif
204844eb 1196#if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE)
81d9c7f2
BW		 1197 {
1198 I2C_BOARD_INFO("pcf8574_keypad", 0x27),
81d9c7f2
BW		 1199 .irq = 212,
1200 },
1201#endif
ffc4d8bc
MH		 1202#if defined(CONFIG_INPUT_ADXL34X_I2C) || defined(CONFIG_INPUT_ADXL34X_I2C_MODULE)
1203 {
1204 I2C_BOARD_INFO("adxl34x", 0x53),
1205 .irq = IRQ_PC5,
1206 .platform_data = (void *)&adxl34x_info,
1207 },
1208#endif
81d9c7f2
BW		 1209};
1210#endif
81d9c7f2 1211
2463ef22
MH		 1212#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
1213#include <linux/gpio_keys.h>
1214
1215static struct gpio_keys_button bfin_gpio_keys_table[] = {
1216 {BTN_0, GPIO_PB8, 1, "gpio-keys: BTN0"},
1217 {BTN_1, GPIO_PB9, 1, "gpio-keys: BTN1"},
1218 {BTN_2, GPIO_PB10, 1, "gpio-keys: BTN2"},
1219 {BTN_3, GPIO_PB11, 1, "gpio-keys: BTN3"},
1220};
1221
1222static struct gpio_keys_platform_data bfin_gpio_keys_data = {
1223 .buttons = bfin_gpio_keys_table,
1224 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
1225};
1226
1227static struct platform_device bfin_device_gpiokeys = {
1228 .name = "gpio-keys",
1229 .dev = {
1230 .platform_data = &bfin_gpio_keys_data,
1231 },
1232};
1233#endif
1234
14b03204
MH		 1235static const unsigned int cclk_vlev_datasheet[] =
1236{
1237/*
1238 * Internal VLEV BF54XSBBC1533
1239 ****temporarily using these values until data sheet is updated
1240 */
1241 VRPAIR(VLEV_085, 150000000),
1242 VRPAIR(VLEV_090, 250000000),
1243 VRPAIR(VLEV_110, 276000000),
1244 VRPAIR(VLEV_115, 301000000),
1245 VRPAIR(VLEV_120, 525000000),
1246 VRPAIR(VLEV_125, 550000000),
1247 VRPAIR(VLEV_130, 600000000),
1248};
1249
1250static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
1251 .tuple_tab = cclk_vlev_datasheet,
1252 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
1253 .vr_settling_time = 25 /* us */,
1254};
1255
1256static struct platform_device bfin_dpmc = {
1257 .name = "bfin dpmc",
1258 .dev = {
1259 .platform_data = &bfin_dmpc_vreg_data,
1260 },
1261};
1262
439b4867
BS		 1263#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
1264static struct platform_device bfin_i2s = {
1265 .name = "bfin-i2s",
1266 .id = CONFIG_SND_BF5XX_SPORT_NUM,
1267 /* TODO: add platform data here */
1268};
1269#endif
1270
1271#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
1272static struct platform_device bfin_tdm = {
1273 .name = "bfin-tdm",
1274 .id = CONFIG_SND_BF5XX_SPORT_NUM,
1275 /* TODO: add platform data here */
1276};
1277#endif
1278
1279#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
1280static struct platform_device bfin_ac97 = {
1281 .name = "bfin-ac97",
1282 .id = CONFIG_SND_BF5XX_SPORT_NUM,
1283 /* TODO: add platform data here */
1284};
1285#endif
1286
24a07a12 1287static struct platform_device *ezkit_devices[] __initdata = {
14b03204
MH		 1288
1289 &bfin_dpmc,
1290
24a07a12
RH		 1291#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
1292 &rtc_device,
1293#endif
1294
1295#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
6bd1fbea
SZ		 1296#ifdef CONFIG_SERIAL_BFIN_UART0
1297 &bfin_uart0_device,
1298#endif
1299#ifdef CONFIG_SERIAL_BFIN_UART1
1300 &bfin_uart1_device,
1301#endif
1302#ifdef CONFIG_SERIAL_BFIN_UART2
1303 &bfin_uart2_device,
1304#endif
1305#ifdef CONFIG_SERIAL_BFIN_UART3
1306 &bfin_uart3_device,
1307#endif
24a07a12 1308#endif
c6c4d7bb 1309
5be36d22 1310#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
42bd8bcb
GY		 1311#ifdef CONFIG_BFIN_SIR0
1312 &bfin_sir0_device,
1313#endif
1314#ifdef CONFIG_BFIN_SIR1
1315 &bfin_sir1_device,
1316#endif
1317#ifdef CONFIG_BFIN_SIR2
1318 &bfin_sir2_device,
1319#endif
1320#ifdef CONFIG_BFIN_SIR3
1321 &bfin_sir3_device,
1322#endif
5be36d22
GY		 1323#endif
1324
c6c4d7bb
BW		 1325#if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE)
1326 &bf54x_lq043_device,
1327#endif
1328
1329#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
1330 &smsc911x_device,
1331#endif
1332
c6c4d7bb
BW		 1333#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
1334 &musb_device,
1335#endif
1336
3f375690
MH		 1337#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
1338 &bfin_isp1760_device,
1339#endif
1340
df5de261
SZ		 1341#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
1342#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
1343 &bfin_sport0_uart_device,
1344#endif
1345#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
1346 &bfin_sport1_uart_device,
1347#endif
1348#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
1349 &bfin_sport2_uart_device,
1350#endif
1351#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
1352 &bfin_sport3_uart_device,
1353#endif
1354#endif
1355
706a01b1
BS		 1356#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
1357 &bfin_can_device,
1358#endif
1359
c6c4d7bb
BW		 1360#if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE)
1361 &bfin_atapi_device,
1362#endif
1363
1364#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
1365 &bf5xx_nand_device,
1366#endif
1367
3d7e6cf8 1368#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
c6c4d7bb
BW		 1369 &bf54x_sdh_device,
1370#endif
1371
1372#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
1373 &bf54x_spi_master0,
d4b1d273 1374 &bf54x_spi_master1,
c6c4d7bb
BW		 1375#endif
1376
1377#if defined(CONFIG_KEYBOARD_BFIN) || defined(CONFIG_KEYBOARD_BFIN_MODULE)
1378 &bf54x_kpad_device,
1379#endif
1380
adfc0467 1381#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
aca5e4aa
MH		 1382 &bfin_rotary_device,
1383#endif
1384
c6c4d7bb
BW		 1385#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
1386 &i2c_bfin_twi0_device,
7160e950 1387#if !defined(CONFIG_BF542)
c6c4d7bb
BW		 1388 &i2c_bfin_twi1_device,
1389#endif
7160e950 1390#endif
2463ef22
MH		 1391
1392#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
1393 &bfin_device_gpiokeys,
1394#endif
cad2ab65 1395
793dc27b 1396#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
de8c43f2 1397 &ezkit_flash_device,
793dc27b 1398#endif
439b4867
BS		 1399
1400#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
1401 &bfin_i2s,
1402#endif
1403
1404#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
1405 &bfin_tdm,
1406#endif
1407
1408#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
1409 &bfin_ac97,
1410#endif
24a07a12
RH		 1411};
1412
a01d7a76 1413static int __init ezkit_init(void)
24a07a12 1414{
b85d858b 1415 printk(KERN_INFO "%s(): registering device resources\n", __func__);
81d9c7f2 1416
81d9c7f2
BW		 1417 i2c_register_board_info(0, bfin_i2c_board_info0,
1418 ARRAY_SIZE(bfin_i2c_board_info0));
1419#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
1420 i2c_register_board_info(1, bfin_i2c_board_info1,
1421 ARRAY_SIZE(bfin_i2c_board_info1));
81d9c7f2
BW		 1422#endif
1423
24a07a12 1424 platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
c6c4d7bb 1425
5bda2723 1426 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
c6c4d7bb 1427
24a07a12
RH		 1428 return 0;
1429}
1430
a01d7a76 1431arch_initcall(ezkit_init);
c13ce9fd
SZ		 1432
1433static struct platform_device *ezkit_early_devices[] __initdata = {
1434#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
1435#ifdef CONFIG_SERIAL_BFIN_UART0
1436 &bfin_uart0_device,
1437#endif
1438#ifdef CONFIG_SERIAL_BFIN_UART1
1439 &bfin_uart1_device,
1440#endif
1441#ifdef CONFIG_SERIAL_BFIN_UART2
1442 &bfin_uart2_device,
1443#endif
1444#ifdef CONFIG_SERIAL_BFIN_UART3
1445 &bfin_uart3_device,
1446#endif
1447#endif
1448
1449#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
1450#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
1451 &bfin_sport0_uart_device,
1452#endif
1453#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
1454 &bfin_sport1_uart_device,
1455#endif
1456#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
1457 &bfin_sport2_uart_device,
1458#endif
1459#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
1460 &bfin_sport3_uart_device,
1461#endif
1462#endif
1463};
1464
1465void __init native_machine_early_platform_add_devices(void)
1466{
1467 printk(KERN_INFO "register early platform devices\n");
1468 early_platform_add_devices(ezkit_early_devices,
1469 ARRAY_SIZE(ezkit_early_devices));
1470}
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