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Blackfin: bf52x/bf54x boards: drop unused nand page size
[net-next-2.6.git] / arch / blackfin / mach-bf548 / boards / cm_bf548.c
CommitLineData
db68254f 1/*
96f1050d
RG		 2 * Copyright 2004-2009 Analog Devices Inc.
3 * 2008-2009 Bluetechnix
4 * 2005 National ICT Australia (NICTA)
5 * Aidan Williams <aidan@nicta.com.au>
db68254f 6 *
96f1050d 7 * Licensed under the GPL-2 or later.
db68254f
MH		 8 */
9
10#include <linux/device.h>
11#include <linux/platform_device.h>
12#include <linux/mtd/mtd.h>
13#include <linux/mtd/partitions.h>
2de73e71 14#include <linux/mtd/physmap.h>
db68254f
MH		 15#include <linux/spi/spi.h>
16#include <linux/spi/flash.h>
17#include <linux/irq.h>
18#include <linux/interrupt.h>
19#include <linux/usb/musb.h>
20#include <asm/bfin5xx_spi.h>
db68254f
MH		 21#include <asm/dma.h>
22#include <asm/gpio.h>
23#include <asm/nand.h>
24#include <asm/portmux.h>
8d8921a2 25#include <asm/bfin_sdh.h>
639f6571 26#include <mach/bf54x_keys.h>
14b03204 27#include <asm/dpmc.h>
db68254f
MH		 28#include <linux/input.h>
29#include <linux/spi/ad7877.h>
30
31/*
32 * Name the Board for the /proc/cpuinfo
33 */
34const char bfin_board_name[] = "Bluetechnix CM-BF548";
35
36/*
37 * Driver needs to know address, irq and flag pin.
38 */
39
40#if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE)
41
639f6571 42#include <mach/bf54x-lq043.h>
db68254f
MH		 43
44static struct bfin_bf54xfb_mach_info bf54x_lq043_data = {
45 .width = 480,
46 .height = 272,
47 .xres = {480, 480, 480},
48 .yres = {272, 272, 272},
49 .bpp = {24, 24, 24},
50 .disp = GPIO_PE3,
51};
52
53static struct resource bf54x_lq043_resources[] = {
54 {
55 .start = IRQ_EPPI0_ERR,
56 .end = IRQ_EPPI0_ERR,
57 .flags = IORESOURCE_IRQ,
58 },
59};
60
61static struct platform_device bf54x_lq043_device = {
62 .name = "bf54x-lq043",
63 .id = -1,
64 .num_resources = ARRAY_SIZE(bf54x_lq043_resources),
65 .resource = bf54x_lq043_resources,
66 .dev = {
67 .platform_data = &bf54x_lq043_data,
68 },
69};
70#endif
71
72#if defined(CONFIG_KEYBOARD_BFIN) || defined(CONFIG_KEYBOARD_BFIN_MODULE)
73static unsigned int bf548_keymap[] = {
74 KEYVAL(0, 0, KEY_ENTER),
75 KEYVAL(0, 1, KEY_HELP),
76 KEYVAL(0, 2, KEY_0),
77 KEYVAL(0, 3, KEY_BACKSPACE),
78 KEYVAL(1, 0, KEY_TAB),
79 KEYVAL(1, 1, KEY_9),
80 KEYVAL(1, 2, KEY_8),
81 KEYVAL(1, 3, KEY_7),
82 KEYVAL(2, 0, KEY_DOWN),
83 KEYVAL(2, 1, KEY_6),
84 KEYVAL(2, 2, KEY_5),
85 KEYVAL(2, 3, KEY_4),
86 KEYVAL(3, 0, KEY_UP),
87 KEYVAL(3, 1, KEY_3),
88 KEYVAL(3, 2, KEY_2),
89 KEYVAL(3, 3, KEY_1),
90};
91
92static struct bfin_kpad_platform_data bf54x_kpad_data = {
93 .rows = 4,
94 .cols = 4,
95 .keymap = bf548_keymap,
96 .keymapsize = ARRAY_SIZE(bf548_keymap),
97 .repeat = 0,
98 .debounce_time = 5000, /* ns (5ms) */
99 .coldrive_time = 1000, /* ns (1ms) */
100 .keyup_test_interval = 50, /* ms (50ms) */
101};
102
103static struct resource bf54x_kpad_resources[] = {
104 {
105 .start = IRQ_KEY,
106 .end = IRQ_KEY,
107 .flags = IORESOURCE_IRQ,
108 },
109};
110
111static struct platform_device bf54x_kpad_device = {
112 .name = "bf54x-keys",
113 .id = -1,
114 .num_resources = ARRAY_SIZE(bf54x_kpad_resources),
115 .resource = bf54x_kpad_resources,
116 .dev = {
117 .platform_data = &bf54x_kpad_data,
118 },
119};
120#endif
121
122#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
123static struct platform_device rtc_device = {
124 .name = "rtc-bfin",
125 .id = -1,
126};
127#endif
128
129#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
db68254f 130#ifdef CONFIG_SERIAL_BFIN_UART0
6bd1fbea 131static struct resource bfin_uart0_resources[] = {
db68254f 132 {
6bd1fbea
SZ		 133 .start = UART0_DLL,
134 .end = UART0_RBR+2,
db68254f
MH		 135 .flags = IORESOURCE_MEM,
136 },
6bd1fbea
SZ		 137 {
138 .start = IRQ_UART0_RX,
139 .end = IRQ_UART0_RX+1,
140 .flags = IORESOURCE_IRQ,
141 },
142 {
143 .start = IRQ_UART0_ERROR,
144 .end = IRQ_UART0_ERROR,
145 .flags = IORESOURCE_IRQ,
146 },
147 {
148 .start = CH_UART0_TX,
149 .end = CH_UART0_TX,
150 .flags = IORESOURCE_DMA,
151 },
152 {
153 .start = CH_UART0_RX,
154 .end = CH_UART0_RX,
155 .flags = IORESOURCE_DMA,
156 },
157};
158
159unsigned short bfin_uart0_peripherals[] = {
160 P_UART0_TX, P_UART0_RX, 0
161};
162
163static struct platform_device bfin_uart0_device = {
164 .name = "bfin-uart",
165 .id = 0,
166 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
167 .resource = bfin_uart0_resources,
168 .dev = {
169 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
170 },
171};
db68254f
MH		 172#endif
173#ifdef CONFIG_SERIAL_BFIN_UART1
6bd1fbea 174static struct resource bfin_uart1_resources[] = {
db68254f 175 {
6bd1fbea
SZ		 176 .start = UART1_DLL,
177 .end = UART1_RBR+2,
db68254f
MH		 178 .flags = IORESOURCE_MEM,
179 },
6bd1fbea
SZ		 180 {
181 .start = IRQ_UART1_RX,
182 .end = IRQ_UART1_RX+1,
183 .flags = IORESOURCE_IRQ,
184 },
185 {
186 .start = IRQ_UART1_ERROR,
187 .end = IRQ_UART1_ERROR,
188 .flags = IORESOURCE_IRQ,
189 },
190 {
191 .start = CH_UART1_TX,
192 .end = CH_UART1_TX,
193 .flags = IORESOURCE_DMA,
194 },
195 {
196 .start = CH_UART1_RX,
197 .end = CH_UART1_RX,
198 .flags = IORESOURCE_DMA,
199 },
200#ifdef CONFIG_BFIN_UART1_CTSRTS
201 { /* CTS pin -- 0 means not supported */
202 .start = GPIO_PE10,
203 .end = GPIO_PE10,
204 .flags = IORESOURCE_IO,
205 },
206 { /* RTS pin -- 0 means not supported */
207 .start = GPIO_PE9,
208 .end = GPIO_PE9,
209 .flags = IORESOURCE_IO,
210 },
211#endif
212};
213
214unsigned short bfin_uart1_peripherals[] = {
215 P_UART1_TX, P_UART1_RX,
216#ifdef CONFIG_BFIN_UART1_CTSRTS
217 P_UART1_RTS, P_UART1_CTS,
218#endif
219 0
220};
221
222static struct platform_device bfin_uart1_device = {
223 .name = "bfin-uart",
224 .id = 1,
225 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
226 .resource = bfin_uart1_resources,
227 .dev = {
228 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
229 },
230};
db68254f
MH		 231#endif
232#ifdef CONFIG_SERIAL_BFIN_UART2
6bd1fbea 233static struct resource bfin_uart2_resources[] = {
db68254f 234 {
6bd1fbea
SZ		 235 .start = UART2_DLL,
236 .end = UART2_RBR+2,
db68254f
MH		 237 .flags = IORESOURCE_MEM,
238 },
6bd1fbea
SZ		 239 {
240 .start = IRQ_UART2_RX,
241 .end = IRQ_UART2_RX+1,
242 .flags = IORESOURCE_IRQ,
243 },
244 {
245 .start = IRQ_UART2_ERROR,
246 .end = IRQ_UART2_ERROR,
247 .flags = IORESOURCE_IRQ,
248 },
249 {
250 .start = CH_UART2_TX,
251 .end = CH_UART2_TX,
252 .flags = IORESOURCE_DMA,
253 },
254 {
255 .start = CH_UART2_RX,
256 .end = CH_UART2_RX,
257 .flags = IORESOURCE_DMA,
258 },
259};
260
261unsigned short bfin_uart2_peripherals[] = {
262 P_UART2_TX, P_UART2_RX, 0
263};
264
265static struct platform_device bfin_uart2_device = {
266 .name = "bfin-uart",
267 .id = 2,
268 .num_resources = ARRAY_SIZE(bfin_uart2_resources),
269 .resource = bfin_uart2_resources,
270 .dev = {
271 .platform_data = &bfin_uart2_peripherals, /* Passed to driver */
272 },
273};
db68254f
MH		 274#endif
275#ifdef CONFIG_SERIAL_BFIN_UART3
6bd1fbea 276static struct resource bfin_uart3_resources[] = {
db68254f 277 {
6bd1fbea
SZ		 278 .start = UART3_DLL,
279 .end = UART3_RBR+2,
8606801b 280 .flags = IORESOURCE_MEM,
db68254f 281 },
6bd1fbea
SZ		 282 {
283 .start = IRQ_UART3_RX,
284 .end = IRQ_UART3_RX+1,
285 .flags = IORESOURCE_IRQ,
286 },
287 {
288 .start = IRQ_UART3_ERROR,
289 .end = IRQ_UART3_ERROR,
290 .flags = IORESOURCE_IRQ,
291 },
292 {
293 .start = CH_UART3_TX,
294 .end = CH_UART3_TX,
295 .flags = IORESOURCE_DMA,
296 },
297 {
298 .start = CH_UART3_RX,
299 .end = CH_UART3_RX,
300 .flags = IORESOURCE_DMA,
301 },
302#ifdef CONFIG_BFIN_UART3_CTSRTS
303 { /* CTS pin -- 0 means not supported */
304 .start = GPIO_PB3,
305 .end = GPIO_PB3,
306 .flags = IORESOURCE_IO,
307 },
308 { /* RTS pin -- 0 means not supported */
309 .start = GPIO_PB2,
310 .end = GPIO_PB2,
311 .flags = IORESOURCE_IO,
312 },
db68254f
MH		 313#endif
314};
315
6bd1fbea
SZ		 316unsigned short bfin_uart3_peripherals[] = {
317 P_UART3_TX, P_UART3_RX,
318#ifdef CONFIG_BFIN_UART3_CTSRTS
319 P_UART3_RTS, P_UART3_CTS,
320#endif
321 0
322};
323
324static struct platform_device bfin_uart3_device = {
db68254f 325 .name = "bfin-uart",
6bd1fbea
SZ		 326 .id = 3,
327 .num_resources = ARRAY_SIZE(bfin_uart3_resources),
328 .resource = bfin_uart3_resources,
329 .dev = {
330 .platform_data = &bfin_uart3_peripherals, /* Passed to driver */
331 },
db68254f
MH		 332};
333#endif
6bd1fbea 334#endif
db68254f 335
5be36d22 336#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
5be36d22 337#ifdef CONFIG_BFIN_SIR0
42bd8bcb 338static struct resource bfin_sir0_resources[] = {
5be36d22
GY		 339 {
340 .start = 0xFFC00400,
341 .end = 0xFFC004FF,
342 .flags = IORESOURCE_MEM,
343 },
42bd8bcb
GY		 344 {
345 .start = IRQ_UART0_RX,
346 .end = IRQ_UART0_RX+1,
347 .flags = IORESOURCE_IRQ,
348 },
349 {
350 .start = CH_UART0_RX,
351 .end = CH_UART0_RX+1,
352 .flags = IORESOURCE_DMA,
353 },
354};
355static struct platform_device bfin_sir0_device = {
356 .name = "bfin_sir",
357 .id = 0,
358 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
359 .resource = bfin_sir0_resources,
360};
5be36d22
GY		 361#endif
362#ifdef CONFIG_BFIN_SIR1
42bd8bcb 363static struct resource bfin_sir1_resources[] = {
5be36d22
GY		 364 {
365 .start = 0xFFC02000,
366 .end = 0xFFC020FF,
367 .flags = IORESOURCE_MEM,
368 },
42bd8bcb
GY		 369 {
370 .start = IRQ_UART1_RX,
371 .end = IRQ_UART1_RX+1,
372 .flags = IORESOURCE_IRQ,
373 },
374 {
375 .start = CH_UART1_RX,
376 .end = CH_UART1_RX+1,
377 .flags = IORESOURCE_DMA,
378 },
379};
380static struct platform_device bfin_sir1_device = {
381 .name = "bfin_sir",
382 .id = 1,
383 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
384 .resource = bfin_sir1_resources,
385};
5be36d22
GY		 386#endif
387#ifdef CONFIG_BFIN_SIR2
42bd8bcb 388static struct resource bfin_sir2_resources[] = {
5be36d22
GY		 389 {
390 .start = 0xFFC02100,
391 .end = 0xFFC021FF,
392 .flags = IORESOURCE_MEM,
393 },
42bd8bcb
GY		 394 {
395 .start = IRQ_UART2_RX,
396 .end = IRQ_UART2_RX+1,
397 .flags = IORESOURCE_IRQ,
398 },
399 {
400 .start = CH_UART2_RX,
401 .end = CH_UART2_RX+1,
402 .flags = IORESOURCE_DMA,
403 },
404};
405static struct platform_device bfin_sir2_device = {
406 .name = "bfin_sir",
407 .id = 2,
408 .num_resources = ARRAY_SIZE(bfin_sir2_resources),
409 .resource = bfin_sir2_resources,
410};
5be36d22
GY		 411#endif
412#ifdef CONFIG_BFIN_SIR3
42bd8bcb 413static struct resource bfin_sir3_resources[] = {
5be36d22
GY		 414 {
415 .start = 0xFFC03100,
416 .end = 0xFFC031FF,
417 .flags = IORESOURCE_MEM,
418 },
42bd8bcb
GY		 419 {
420 .start = IRQ_UART3_RX,
421 .end = IRQ_UART3_RX+1,
422 .flags = IORESOURCE_IRQ,
423 },
424 {
425 .start = CH_UART3_RX,
426 .end = CH_UART3_RX+1,
427 .flags = IORESOURCE_DMA,
428 },
5be36d22 429};
42bd8bcb 430static struct platform_device bfin_sir3_device = {
5be36d22 431 .name = "bfin_sir",
42bd8bcb
GY		 432 .id = 3,
433 .num_resources = ARRAY_SIZE(bfin_sir3_resources),
434 .resource = bfin_sir3_resources,
5be36d22
GY		 435};
436#endif
42bd8bcb 437#endif
5be36d22 438
db68254f 439#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
9c21453e
HK		 440#include <linux/smsc911x.h>
441
db68254f
MH		 442static struct resource smsc911x_resources[] = {
443 {
444 .name = "smsc911x-memory",
445 .start = 0x24000000,
446 .end = 0x24000000 + 0xFF,
447 .flags = IORESOURCE_MEM,
448 },
449 {
450 .start = IRQ_PE6,
451 .end = IRQ_PE6,
452 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
453 },
454};
9c21453e
HK		 455
456static struct smsc911x_platform_config smsc911x_config = {
457 .flags = SMSC911X_USE_16BIT,
458 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
459 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
460 .phy_interface = PHY_INTERFACE_MODE_MII,
461};
462
db68254f
MH		 463static struct platform_device smsc911x_device = {
464 .name = "smsc911x",
465 .id = 0,
466 .num_resources = ARRAY_SIZE(smsc911x_resources),
467 .resource = smsc911x_resources,
9c21453e
HK		 468 .dev = {
469 .platform_data = &smsc911x_config,
470 },
db68254f
MH		 471};
472#endif
473
474#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
475static struct resource musb_resources[] = {
476 [0] = {
477 .start = 0xFFC03C00,
478 .end = 0xFFC040FF,
479 .flags = IORESOURCE_MEM,
480 },
481 [1] = { /* general IRQ */
482 .start = IRQ_USB_INT0,
483 .end = IRQ_USB_INT0,
484 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
485 },
486 [2] = { /* DMA IRQ */
487 .start = IRQ_USB_DMA,
488 .end = IRQ_USB_DMA,
489 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
490 },
491};
492
50041acb
BW		 493static struct musb_hdrc_config musb_config = {
494 .multipoint = 0,
495 .dyn_fifo = 0,
496 .soft_con = 1,
497 .dma = 1,
fea05dac
BW		 498 .num_eps = 8,
499 .dma_channels = 8,
50041acb 500 .gpio_vrsel = GPIO_PH6,
85eb0e4b
CC		 501 /* Some custom boards need to be active low, just set it to "0"
502 * if it is the case.
503 */
504 .gpio_vrsel_active = 1,
50041acb
BW		 505};
506
db68254f
MH		 507static struct musb_hdrc_platform_data musb_plat = {
508#if defined(CONFIG_USB_MUSB_OTG)
509 .mode = MUSB_OTG,
510#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
511 .mode = MUSB_HOST,
512#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
513 .mode = MUSB_PERIPHERAL,
514#endif
50041acb 515 .config = &musb_config,
db68254f
MH		 516};
517
518static u64 musb_dmamask = ~(u32)0;
519
520static struct platform_device musb_device = {
521 .name = "musb_hdrc",
522 .id = 0,
523 .dev = {
524 .dma_mask = &musb_dmamask,
525 .coherent_dma_mask = 0xffffffff,
526 .platform_data = &musb_plat,
527 },
528 .num_resources = ARRAY_SIZE(musb_resources),
529 .resource = musb_resources,
530};
531#endif
532
df5de261
SZ		 533#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
534#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
535static struct resource bfin_sport0_uart_resources[] = {
536 {
537 .start = SPORT0_TCR1,
538 .end = SPORT0_MRCS3+4,
539 .flags = IORESOURCE_MEM,
540 },
541 {
542 .start = IRQ_SPORT0_RX,
543 .end = IRQ_SPORT0_RX+1,
544 .flags = IORESOURCE_IRQ,
545 },
546 {
547 .start = IRQ_SPORT0_ERROR,
548 .end = IRQ_SPORT0_ERROR,
549 .flags = IORESOURCE_IRQ,
550 },
551};
552
553unsigned short bfin_sport0_peripherals[] = {
554 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
555 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
556};
557
558static struct platform_device bfin_sport0_uart_device = {
559 .name = "bfin-sport-uart",
560 .id = 0,
561 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
562 .resource = bfin_sport0_uart_resources,
563 .dev = {
564 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
565 },
566};
567#endif
568#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
569static struct resource bfin_sport1_uart_resources[] = {
570 {
571 .start = SPORT1_TCR1,
572 .end = SPORT1_MRCS3+4,
573 .flags = IORESOURCE_MEM,
574 },
575 {
576 .start = IRQ_SPORT1_RX,
577 .end = IRQ_SPORT1_RX+1,
578 .flags = IORESOURCE_IRQ,
579 },
580 {
581 .start = IRQ_SPORT1_ERROR,
582 .end = IRQ_SPORT1_ERROR,
583 .flags = IORESOURCE_IRQ,
584 },
585};
586
587unsigned short bfin_sport1_peripherals[] = {
588 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
589 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
590};
591
592static struct platform_device bfin_sport1_uart_device = {
593 .name = "bfin-sport-uart",
594 .id = 1,
595 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
596 .resource = bfin_sport1_uart_resources,
597 .dev = {
598 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
599 },
600};
601#endif
602#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
603static struct resource bfin_sport2_uart_resources[] = {
604 {
605 .start = SPORT2_TCR1,
606 .end = SPORT2_MRCS3+4,
607 .flags = IORESOURCE_MEM,
608 },
609 {
610 .start = IRQ_SPORT2_RX,
611 .end = IRQ_SPORT2_RX+1,
612 .flags = IORESOURCE_IRQ,
613 },
614 {
615 .start = IRQ_SPORT2_ERROR,
616 .end = IRQ_SPORT2_ERROR,
617 .flags = IORESOURCE_IRQ,
618 },
619};
620
621unsigned short bfin_sport2_peripherals[] = {
622 P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
623 P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
624};
625
626static struct platform_device bfin_sport2_uart_device = {
627 .name = "bfin-sport-uart",
628 .id = 2,
629 .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
630 .resource = bfin_sport2_uart_resources,
631 .dev = {
632 .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
633 },
634};
635#endif
636#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
637static struct resource bfin_sport3_uart_resources[] = {
638 {
639 .start = SPORT3_TCR1,
640 .end = SPORT3_MRCS3+4,
641 .flags = IORESOURCE_MEM,
642 },
643 {
644 .start = IRQ_SPORT3_RX,
645 .end = IRQ_SPORT3_RX+1,
646 .flags = IORESOURCE_IRQ,
647 },
648 {
649 .start = IRQ_SPORT3_ERROR,
650 .end = IRQ_SPORT3_ERROR,
651 .flags = IORESOURCE_IRQ,
652 },
653};
654
655unsigned short bfin_sport3_peripherals[] = {
656 P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS,
657 P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0
658};
659
660static struct platform_device bfin_sport3_uart_device = {
661 .name = "bfin-sport-uart",
662 .id = 3,
663 .num_resources = ARRAY_SIZE(bfin_sport3_uart_resources),
664 .resource = bfin_sport3_uart_resources,
665 .dev = {
666 .platform_data = &bfin_sport3_peripherals, /* Passed to driver */
667 },
668};
669#endif
670#endif
671
db68254f
MH		 672#if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE)
673static struct resource bfin_atapi_resources[] = {
674 {
675 .start = 0xFFC03800,
676 .end = 0xFFC0386F,
677 .flags = IORESOURCE_MEM,
678 },
679 {
680 .start = IRQ_ATAPI_ERR,
681 .end = IRQ_ATAPI_ERR,
682 .flags = IORESOURCE_IRQ,
683 },
684};
685
686static struct platform_device bfin_atapi_device = {
687 .name = "pata-bf54x",
688 .id = -1,
689 .num_resources = ARRAY_SIZE(bfin_atapi_resources),
690 .resource = bfin_atapi_resources,
691};
692#endif
693
694#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
695static struct mtd_partition partition_info[] = {
696 {
aa582977 697 .name = "linux kernel(nand)",
db68254f 698 .offset = 0,
f4585a08 699 .size = 4 * 1024 * 1024,
db68254f
MH		 700 },
701 {
aa582977 702 .name = "file system(nand)",
f4585a08
MF		 703 .offset = 4 * 1024 * 1024,
704 .size = (256 - 4) * 1024 * 1024,
db68254f
MH		 705 },
706};
707
708static struct bf5xx_nand_platform bf5xx_nand_platform = {
db68254f
MH		 709 .data_width = NFC_NWIDTH_8,
710 .partitions = partition_info,
711 .nr_partitions = ARRAY_SIZE(partition_info),
712 .rd_dly = 3,
713 .wr_dly = 3,
714};
715
716static struct resource bf5xx_nand_resources[] = {
717 {
718 .start = 0xFFC03B00,
719 .end = 0xFFC03B4F,
720 .flags = IORESOURCE_MEM,
721 },
722 {
723 .start = CH_NFC,
724 .end = CH_NFC,
725 .flags = IORESOURCE_IRQ,
726 },
727};
728
729static struct platform_device bf5xx_nand_device = {
730 .name = "bf5xx-nand",
731 .id = 0,
732 .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
733 .resource = bf5xx_nand_resources,
734 .dev = {
735 .platform_data = &bf5xx_nand_platform,
736 },
737};
738#endif
739
740#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
8d8921a2
MF		 741static struct bfin_sd_host bfin_sdh_data = {
742 .dma_chan = CH_SDH,
743 .irq_int0 = IRQ_SDH_MASK0,
744 .pin_req = {P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0},
745};
746
db68254f
MH		 747static struct platform_device bf54x_sdh_device = {
748 .name = "bfin-sdh",
749 .id = 0,
8d8921a2
MF		 750 .dev = {
751 .platform_data = &bfin_sdh_data,
752 },
db68254f
MH		 753};
754#endif
755
2de73e71
MF		 756#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
757static struct mtd_partition para_partitions[] = {
758 {
759 .name = "bootloader(nor)",
760 .size = 0x40000,
761 .offset = 0,
762 }, {
763 .name = "linux kernel(nor)",
9c21453e 764 .size = 0x100000,
2de73e71
MF		 765 .offset = MTDPART_OFS_APPEND,
766 }, {
767 .name = "file system(nor)",
768 .size = MTDPART_SIZ_FULL,
769 .offset = MTDPART_OFS_APPEND,
770 }
771};
772
773static struct physmap_flash_data para_flash_data = {
774 .width = 2,
775 .parts = para_partitions,
776 .nr_parts = ARRAY_SIZE(para_partitions),
777};
778
779static struct resource para_flash_resource = {
780 .start = 0x20000000,
781 .end = 0x207fffff,
782 .flags = IORESOURCE_MEM,
783};
784
785static struct platform_device para_flash_device = {
786 .name = "physmap-flash",
787 .id = 0,
788 .dev = {
789 .platform_data = &para_flash_data,
790 },
791 .num_resources = 1,
792 .resource = &para_flash_resource,
793};
794#endif
795
db68254f
MH		 796#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
797/* all SPI peripherals info goes here */
798#if defined(CONFIG_MTD_M25P80) \
799 || defined(CONFIG_MTD_M25P80_MODULE)
800/* SPI flash chip (m25p16) */
801static struct mtd_partition bfin_spi_flash_partitions[] = {
802 {
aa582977 803 .name = "bootloader(spi)",
db68254f
MH		 804 .size = 0x00040000,
805 .offset = 0,
806 .mask_flags = MTD_CAP_ROM
807 }, {
aa582977 808 .name = "linux kernel(spi)",
db68254f
MH		 809 .size = 0x1c0000,
810 .offset = 0x40000
811 }
812};
813
814static struct flash_platform_data bfin_spi_flash_data = {
815 .name = "m25p80",
816 .parts = bfin_spi_flash_partitions,
817 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
818 .type = "m25p16",
819};
820
821static struct bfin5xx_spi_chip spi_flash_chip_info = {
822 .enable_dma = 0, /* use dma transfer with this chip*/
823 .bits_per_word = 8,
db68254f
MH		 824};
825#endif
826
827#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
828static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
db68254f
MH		 829 .enable_dma = 0,
830 .bits_per_word = 16,
831};
832
833static const struct ad7877_platform_data bfin_ad7877_ts_info = {
834 .model = 7877,
835 .vref_delay_usecs = 50, /* internal, no capacitor */
836 .x_plate_ohms = 419,
837 .y_plate_ohms = 486,
838 .pressure_max = 1000,
839 .pressure_min = 0,
840 .stopacq_polarity = 1,
841 .first_conversion_delay = 3,
842 .acquisition_time = 1,
843 .averaging = 1,
844 .pen_down_acc_interval = 1,
845};
846#endif
847
848#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
849static struct bfin5xx_spi_chip spidev_chip_info = {
850 .enable_dma = 0,
851 .bits_per_word = 8,
852};
853#endif
854
855static struct spi_board_info bf54x_spi_board_info[] __initdata = {
856#if defined(CONFIG_MTD_M25P80) \
857 || defined(CONFIG_MTD_M25P80_MODULE)
858 {
859 /* the modalias must be the same as spi device driver name */
860 .modalias = "m25p80", /* Name of spi_driver for this device */
861 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
862 .bus_num = 0, /* Framework bus number */
863 .chip_select = 1, /* SPI_SSEL1*/
864 .platform_data = &bfin_spi_flash_data,
865 .controller_data = &spi_flash_chip_info,
866 .mode = SPI_MODE_3,
867 },
868#endif
869#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
870{
871 .modalias = "ad7877",
872 .platform_data = &bfin_ad7877_ts_info,
873 .irq = IRQ_PJ11,
874 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
875 .bus_num = 0,
876 .chip_select = 2,
877 .controller_data = &spi_ad7877_chip_info,
878},
879#endif
880#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
881 {
882 .modalias = "spidev",
883 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
884 .bus_num = 0,
885 .chip_select = 1,
886 .controller_data = &spidev_chip_info,
887 },
888#endif
889};
890
891/* SPI (0) */
892static struct resource bfin_spi0_resource[] = {
893 [0] = {
894 .start = SPI0_REGBASE,
895 .end = SPI0_REGBASE + 0xFF,
896 .flags = IORESOURCE_MEM,
897 },
898 [1] = {
899 .start = CH_SPI0,
900 .end = CH_SPI0,
53122693
YL		 901 .flags = IORESOURCE_DMA,
902 },
903 [2] = {
904 .start = IRQ_SPI0,
905 .end = IRQ_SPI0,
db68254f
MH		 906 .flags = IORESOURCE_IRQ,
907 }
908};
909
910/* SPI (1) */
911static struct resource bfin_spi1_resource[] = {
912 [0] = {
913 .start = SPI1_REGBASE,
914 .end = SPI1_REGBASE + 0xFF,
915 .flags = IORESOURCE_MEM,
916 },
917 [1] = {
918 .start = CH_SPI1,
919 .end = CH_SPI1,
53122693
YL		 920 .flags = IORESOURCE_DMA,
921 },
922 [2] = {
923 .start = IRQ_SPI1,
924 .end = IRQ_SPI1,
db68254f
MH		 925 .flags = IORESOURCE_IRQ,
926 }
927};
928
929/* SPI controller data */
930static struct bfin5xx_spi_master bf54x_spi_master_info0 = {
4e4d496e 931 .num_chipselect = 3,
db68254f
MH		 932 .enable_dma = 1, /* master has the ability to do dma transfer */
933 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
934};
935
936static struct platform_device bf54x_spi_master0 = {
937 .name = "bfin-spi",
938 .id = 0, /* Bus number */
939 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
940 .resource = bfin_spi0_resource,
941 .dev = {
942 .platform_data = &bf54x_spi_master_info0, /* Passed to driver */
943 },
944};
945
946static struct bfin5xx_spi_master bf54x_spi_master_info1 = {
4e4d496e 947 .num_chipselect = 3,
db68254f
MH		 948 .enable_dma = 1, /* master has the ability to do dma transfer */
949 .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
950};
951
952static struct platform_device bf54x_spi_master1 = {
953 .name = "bfin-spi",
954 .id = 1, /* Bus number */
955 .num_resources = ARRAY_SIZE(bfin_spi1_resource),
956 .resource = bfin_spi1_resource,
957 .dev = {
958 .platform_data = &bf54x_spi_master_info1, /* Passed to driver */
959 },
960};
961#endif /* spi master and devices */
962
963#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
964static struct resource bfin_twi0_resource[] = {
965 [0] = {
966 .start = TWI0_REGBASE,
967 .end = TWI0_REGBASE + 0xFF,
968 .flags = IORESOURCE_MEM,
969 },
970 [1] = {
971 .start = IRQ_TWI0,
972 .end = IRQ_TWI0,
973 .flags = IORESOURCE_IRQ,
974 },
975};
976
977static struct platform_device i2c_bfin_twi0_device = {
978 .name = "i2c-bfin-twi",
979 .id = 0,
980 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
981 .resource = bfin_twi0_resource,
982};
983
984#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
985static struct resource bfin_twi1_resource[] = {
986 [0] = {
987 .start = TWI1_REGBASE,
988 .end = TWI1_REGBASE + 0xFF,
989 .flags = IORESOURCE_MEM,
990 },
991 [1] = {
992 .start = IRQ_TWI1,
993 .end = IRQ_TWI1,
994 .flags = IORESOURCE_IRQ,
995 },
996};
997
998static struct platform_device i2c_bfin_twi1_device = {
999 .name = "i2c-bfin-twi",
1000 .id = 1,
1001 .num_resources = ARRAY_SIZE(bfin_twi1_resource),
1002 .resource = bfin_twi1_resource,
1003};
1004#endif
1005#endif
1006
1007#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
1008#include <linux/gpio_keys.h>
1009
1010static struct gpio_keys_button bfin_gpio_keys_table[] = {
1011 {BTN_0, GPIO_PH7, 1, "gpio-keys: BTN0"},
1012};
1013
1014static struct gpio_keys_platform_data bfin_gpio_keys_data = {
1015 .buttons = bfin_gpio_keys_table,
1016 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
1017};
1018
1019static struct platform_device bfin_device_gpiokeys = {
1020 .name = "gpio-keys",
1021 .dev = {
1022 .platform_data = &bfin_gpio_keys_data,
1023 },
1024};
1025#endif
1026
14b03204
MH		 1027static const unsigned int cclk_vlev_datasheet[] =
1028{
1029/*
1030 * Internal VLEV BF54XSBBC1533
1031 ****temporarily using these values until data sheet is updated
1032 */
1033 VRPAIR(VLEV_085, 150000000),
1034 VRPAIR(VLEV_090, 250000000),
1035 VRPAIR(VLEV_110, 276000000),
1036 VRPAIR(VLEV_115, 301000000),
1037 VRPAIR(VLEV_120, 525000000),
1038 VRPAIR(VLEV_125, 550000000),
1039 VRPAIR(VLEV_130, 600000000),
1040};
1041
1042static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
1043 .tuple_tab = cclk_vlev_datasheet,
1044 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
1045 .vr_settling_time = 25 /* us */,
1046};
1047
1048static struct platform_device bfin_dpmc = {
1049 .name = "bfin dpmc",
1050 .dev = {
1051 .platform_data = &bfin_dmpc_vreg_data,
1052 },
1053};
1054
db68254f 1055static struct platform_device *cm_bf548_devices[] __initdata = {
14b03204
MH		 1056
1057 &bfin_dpmc,
1058
db68254f
MH		 1059#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
1060 &rtc_device,
1061#endif
1062
1063#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
6bd1fbea
SZ		 1064#ifdef CONFIG_SERIAL_BFIN_UART0
1065 &bfin_uart0_device,
1066#endif
1067#ifdef CONFIG_SERIAL_BFIN_UART1
1068 &bfin_uart1_device,
1069#endif
1070#ifdef CONFIG_SERIAL_BFIN_UART2
1071 &bfin_uart2_device,
1072#endif
1073#ifdef CONFIG_SERIAL_BFIN_UART3
1074 &bfin_uart3_device,
1075#endif
db68254f
MH		 1076#endif
1077
5be36d22 1078#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
42bd8bcb
GY		 1079#ifdef CONFIG_BFIN_SIR0
1080 &bfin_sir0_device,
1081#endif
1082#ifdef CONFIG_BFIN_SIR1
1083 &bfin_sir1_device,
1084#endif
1085#ifdef CONFIG_BFIN_SIR2
1086 &bfin_sir2_device,
1087#endif
1088#ifdef CONFIG_BFIN_SIR3
1089 &bfin_sir3_device,
1090#endif
5be36d22
GY		 1091#endif
1092
db68254f
MH		 1093#if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE)
1094 &bf54x_lq043_device,
1095#endif
1096
1097#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
1098 &smsc911x_device,
1099#endif
1100
1101#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
1102 &musb_device,
1103#endif
1104
df5de261
SZ		 1105#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
1106#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
1107 &bfin_sport0_uart_device,
1108#endif
1109#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
1110 &bfin_sport1_uart_device,
1111#endif
1112#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
1113 &bfin_sport2_uart_device,
1114#endif
1115#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
1116 &bfin_sport3_uart_device,
1117#endif
1118#endif
1119
db68254f
MH		 1120#if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE)
1121 &bfin_atapi_device,
1122#endif
1123
1124#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
1125 &bf5xx_nand_device,
1126#endif
1127
1128#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
1129 &bf54x_sdh_device,
1130#endif
1131
1132#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
1133 &bf54x_spi_master0,
1134 &bf54x_spi_master1,
1135#endif
1136
1137#if defined(CONFIG_KEYBOARD_BFIN) || defined(CONFIG_KEYBOARD_BFIN_MODULE)
1138 &bf54x_kpad_device,
1139#endif
1140
1141#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
10a88a2b 1142 &i2c_bfin_twi0_device,
db68254f
MH		 1143#if !defined(CONFIG_BF542)
1144 &i2c_bfin_twi1_device,
1145#endif
1146#endif
1147
1148#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
1149 &bfin_device_gpiokeys,
1150#endif
2de73e71
MF		 1151
1152#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
1153 &para_flash_device,
1154#endif
db68254f
MH		 1155};
1156
1157static int __init cm_bf548_init(void)
1158{
f086f234 1159 printk(KERN_INFO "%s(): registering device resources\n", __func__);
db68254f
MH		 1160 platform_add_devices(cm_bf548_devices, ARRAY_SIZE(cm_bf548_devices));
1161
1162#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
1163 spi_register_board_info(bf54x_spi_board_info,
1164 ARRAY_SIZE(bf54x_spi_board_info));
1165#endif
1166
1167 return 0;
1168}
1169
1170arch_initcall(cm_bf548_init);
c13ce9fd
SZ		 1171
1172static struct platform_device *cm_bf548_early_devices[] __initdata = {
1173#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
1174#ifdef CONFIG_SERIAL_BFIN_UART0
1175 &bfin_uart0_device,
1176#endif
1177#ifdef CONFIG_SERIAL_BFIN_UART1
1178 &bfin_uart1_device,
1179#endif
1180#ifdef CONFIG_SERIAL_BFIN_UART2
1181 &bfin_uart2_device,
1182#endif
1183#ifdef CONFIG_SERIAL_BFIN_UART3
1184 &bfin_uart3_device,
1185#endif
1186#endif
1187
1188#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
1189#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
1190 &bfin_sport0_uart_device,
1191#endif
1192#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
1193 &bfin_sport1_uart_device,
1194#endif
1195#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
1196 &bfin_sport2_uart_device,
1197#endif
1198#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
1199 &bfin_sport3_uart_device,
1200#endif
1201#endif
1202};
1203
1204void __init native_machine_early_platform_add_devices(void)
1205{
1206 printk(KERN_INFO "register early platform devices\n");
1207 early_platform_add_devices(cm_bf548_early_devices,
1208 ARRAY_SIZE(cm_bf548_early_devices));
1209}
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