[net-next-2.6.git] / arch / arm / mach-u300 / include / mach / coh901318.h

/*
 *
 * include/linux/coh901318.h
 *
 *
 * Copyright (C) 2007-2009 ST-Ericsson
 * License terms: GNU General Public License (GPL) version 2
 * DMA driver for COH 901 318
 * Author: Per Friden <per.friden@stericsson.com>
 */

#ifndef COH901318_H
#define COH901318_H

#include <linux/device.h>
#include <linux/dmaengine.h>

#define MAX_DMA_PACKET_SIZE_SHIFT 11
#define MAX_DMA_PACKET_SIZE (1 << MAX_DMA_PACKET_SIZE_SHIFT)

/**
 * struct coh901318_lli - linked list item for DMAC
 * @control: control settings for DMAC
 * @src_addr: transfer source address
 * @dst_addr: transfer destination address
 * @link_addr:  physical address to next lli
 * @virt_link_addr: virtual addres of next lli (only used by pool_free)
 * @phy_this: physical address of current lli (only used by pool_free)
 */
struct coh901318_lli {
	u32 control;
	dma_addr_t src_addr;
	dma_addr_t dst_addr;
	dma_addr_t link_addr;

	void *virt_link_addr;
	dma_addr_t phy_this;
};
/**
 * struct coh901318_params - parameters for DMAC configuration
 * @config: DMA config register
 * @ctrl_lli_last: DMA control register for the last lli in the list
 * @ctrl_lli: DMA control register for an lli
 * @ctrl_lli_chained: DMA control register for a chained lli
 */
struct coh901318_params {
	u32 config;
	u32 ctrl_lli_last;
	u32 ctrl_lli;
	u32 ctrl_lli_chained;
};
/**
 * struct coh_dma_channel - dma channel base
 * @name: ascii name of dma channel
 * @number: channel id number
 * @desc_nbr_max: number of preallocated descriptors
 * @priority_high: prio of channel, 0 low otherwise high.
 * @param: configuration parameters
 * @dev_addr: physical address of periphal connected to channel
 */
struct coh_dma_channel {
	const char name[32];
	const int number;
	const int desc_nbr_max;
	const int priority_high;
	const struct coh901318_params param;
	const dma_addr_t dev_addr;
};

/**
 * dma_access_memory_state_t - register dma for memory access
 *
 * @dev: The dma device
 * @active:  1 means dma intends to access memory
 *           0 means dma wont access memory
 */
typedef void (*dma_access_memory_state_t)(struct device *dev,
					  bool active);

/**
 * struct powersave - DMA power save structure
 * @lock: lock protecting data in this struct
 * @started_channels: bit mask indicating active dma channels
 */
struct powersave {
	spinlock_t lock;
	u64 started_channels;
};
/**
 * struct coh901318_platform - platform arch structure
 * @chans_slave: specifying dma slave channels
 * @chans_memcpy: specifying dma memcpy channels
 * @access_memory_state: requesting DMA memeory access (on / off)
 * @chan_conf: dma channel configurations
 * @max_channels: max number of dma chanenls
 */
struct coh901318_platform {
	const int *chans_slave;
	const int *chans_memcpy;
	const dma_access_memory_state_t access_memory_state;
	const struct coh_dma_channel *chan_conf;
	const int max_channels;
};

/**
 * coh901318_filter_id() - DMA channel filter function
 * @chan: dma channel handle
 * @chan_id: id of dma channel to be filter out
 *
 * In dma_request_channel() it specifies what channel id to be requested
 */
bool coh901318_filter_id(struct dma_chan *chan, void *chan_id);

/*
 * DMA Controller - this access the static mappings of the coh901318 dma.
 *
 */

#define COH901318_MOD32_MASK					(0x1F)
#define COH901318_WORD_MASK					(0xFFFFFFFF)
/* INT_STATUS - Interrupt Status Registers 32bit (R/-) */
#define COH901318_INT_STATUS1					(0x0000)
#define COH901318_INT_STATUS2					(0x0004)
/* TC_INT_STATUS - Terminal Count Interrupt Status Registers 32bit (R/-) */
#define COH901318_TC_INT_STATUS1				(0x0008)
#define COH901318_TC_INT_STATUS2				(0x000C)
/* TC_INT_CLEAR - Terminal Count Interrupt Clear Registers 32bit (-/W) */
#define COH901318_TC_INT_CLEAR1					(0x0010)
#define COH901318_TC_INT_CLEAR2					(0x0014)
/* RAW_TC_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
#define COH901318_RAW_TC_INT_STATUS1				(0x0018)
#define COH901318_RAW_TC_INT_STATUS2				(0x001C)
/* BE_INT_STATUS - Bus Error Interrupt Status Registers 32bit (R/-) */
#define COH901318_BE_INT_STATUS1				(0x0020)
#define COH901318_BE_INT_STATUS2				(0x0024)
/* BE_INT_CLEAR - Bus Error Interrupt Clear Registers 32bit (-/W) */
#define COH901318_BE_INT_CLEAR1					(0x0028)
#define COH901318_BE_INT_CLEAR2					(0x002C)
/* RAW_BE_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
#define COH901318_RAW_BE_INT_STATUS1				(0x0030)
#define COH901318_RAW_BE_INT_STATUS2				(0x0034)

/*
 * CX_CFG - Channel Configuration Registers 32bit (R/W)
 */
#define COH901318_CX_CFG					(0x0100)
#define COH901318_CX_CFG_SPACING				(0x04)
/* Channel enable activates tha dma job */
#define COH901318_CX_CFG_CH_ENABLE				(0x00000001)
#define COH901318_CX_CFG_CH_DISABLE				(0x00000000)
/* Request Mode */
#define COH901318_CX_CFG_RM_MASK				(0x00000006)
#define COH901318_CX_CFG_RM_MEMORY_TO_MEMORY			(0x0 << 1)
#define COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY			(0x1 << 1)
#define COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY			(0x1 << 1)
#define COH901318_CX_CFG_RM_PRIMARY_TO_SECONDARY		(0x3 << 1)
#define COH901318_CX_CFG_RM_SECONDARY_TO_PRIMARY		(0x3 << 1)
/* Linked channel request field. RM must == 11 */
#define COH901318_CX_CFG_LCRF_SHIFT				3
#define COH901318_CX_CFG_LCRF_MASK				(0x000001F8)
#define COH901318_CX_CFG_LCR_DISABLE				(0x00000000)
/* Terminal Counter Interrupt Request Mask */
#define COH901318_CX_CFG_TC_IRQ_ENABLE				(0x00000200)
#define COH901318_CX_CFG_TC_IRQ_DISABLE				(0x00000000)
/* Bus Error interrupt Mask */
#define COH901318_CX_CFG_BE_IRQ_ENABLE				(0x00000400)
#define COH901318_CX_CFG_BE_IRQ_DISABLE				(0x00000000)

/*
 * CX_STAT - Channel Status Registers 32bit (R/-)
 */
#define COH901318_CX_STAT					(0x0200)
#define COH901318_CX_STAT_SPACING				(0x04)
#define COH901318_CX_STAT_RBE_IRQ_IND				(0x00000008)
#define COH901318_CX_STAT_RTC_IRQ_IND				(0x00000004)
#define COH901318_CX_STAT_ACTIVE				(0x00000002)
#define COH901318_CX_STAT_ENABLED				(0x00000001)

/*
 * CX_CTRL - Channel Control Registers 32bit (R/W)
 */
#define COH901318_CX_CTRL					(0x0400)
#define COH901318_CX_CTRL_SPACING				(0x10)
/* Transfer Count Enable */
#define COH901318_CX_CTRL_TC_ENABLE				(0x00001000)
#define COH901318_CX_CTRL_TC_DISABLE				(0x00000000)
/* Transfer Count Value 0 - 4095 */
#define COH901318_CX_CTRL_TC_VALUE_MASK				(0x00000FFF)
/* Burst count */
#define COH901318_CX_CTRL_BURST_COUNT_MASK			(0x0000E000)
#define COH901318_CX_CTRL_BURST_COUNT_64_BYTES			(0x7 << 13)
#define COH901318_CX_CTRL_BURST_COUNT_48_BYTES			(0x6 << 13)
#define COH901318_CX_CTRL_BURST_COUNT_32_BYTES			(0x5 << 13)
#define COH901318_CX_CTRL_BURST_COUNT_16_BYTES			(0x4 << 13)
#define COH901318_CX_CTRL_BURST_COUNT_8_BYTES			(0x3 << 13)
#define COH901318_CX_CTRL_BURST_COUNT_4_BYTES			(0x2 << 13)
#define COH901318_CX_CTRL_BURST_COUNT_2_BYTES			(0x1 << 13)
#define COH901318_CX_CTRL_BURST_COUNT_1_BYTE			(0x0 << 13)
/* Source bus size  */
#define COH901318_CX_CTRL_SRC_BUS_SIZE_MASK			(0x00030000)
#define COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS			(0x2 << 16)
#define COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS			(0x1 << 16)
#define COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS			(0x0 << 16)
/* Source address increment */
#define COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE			(0x00040000)
#define COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE			(0x00000000)
/* Destination Bus Size */
#define COH901318_CX_CTRL_DST_BUS_SIZE_MASK			(0x00180000)
#define COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS			(0x2 << 19)
#define COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS			(0x1 << 19)
#define COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS			(0x0 << 19)
/* Destination address increment */
#define COH901318_CX_CTRL_DST_ADDR_INC_ENABLE			(0x00200000)
#define COH901318_CX_CTRL_DST_ADDR_INC_DISABLE			(0x00000000)
/* Master Mode (Master2 is only connected to MSL) */
#define COH901318_CX_CTRL_MASTER_MODE_MASK			(0x00C00000)
#define COH901318_CX_CTRL_MASTER_MODE_M2R_M1W			(0x3 << 22)
#define COH901318_CX_CTRL_MASTER_MODE_M1R_M2W			(0x2 << 22)
#define COH901318_CX_CTRL_MASTER_MODE_M2RW			(0x1 << 22)
#define COH901318_CX_CTRL_MASTER_MODE_M1RW			(0x0 << 22)
/* Terminal Count flag to PER enable */
#define COH901318_CX_CTRL_TCP_ENABLE				(0x01000000)
#define COH901318_CX_CTRL_TCP_DISABLE				(0x00000000)
/* Terminal Count flags to CPU enable */
#define COH901318_CX_CTRL_TC_IRQ_ENABLE				(0x02000000)
#define COH901318_CX_CTRL_TC_IRQ_DISABLE			(0x00000000)
/* Hand shake to peripheral */
#define COH901318_CX_CTRL_HSP_ENABLE				(0x04000000)
#define COH901318_CX_CTRL_HSP_DISABLE				(0x00000000)
#define COH901318_CX_CTRL_HSS_ENABLE				(0x08000000)
#define COH901318_CX_CTRL_HSS_DISABLE				(0x00000000)
/* DMA mode */
#define COH901318_CX_CTRL_DDMA_MASK				(0x30000000)
#define COH901318_CX_CTRL_DDMA_LEGACY				(0x0 << 28)
#define COH901318_CX_CTRL_DDMA_DEMAND_DMA1			(0x1 << 28)
#define COH901318_CX_CTRL_DDMA_DEMAND_DMA2			(0x2 << 28)
/* Primary Request Data Destination */
#define COH901318_CX_CTRL_PRDD_MASK				(0x40000000)
#define COH901318_CX_CTRL_PRDD_DEST				(0x1 << 30)
#define COH901318_CX_CTRL_PRDD_SOURCE				(0x0 << 30)

/*
 * CX_SRC_ADDR - Channel Source Address Registers 32bit (R/W)
 */
#define COH901318_CX_SRC_ADDR					(0x0404)
#define COH901318_CX_SRC_ADDR_SPACING				(0x10)

/*
 * CX_DST_ADDR - Channel Destination Address Registers 32bit R/W
 */
#define COH901318_CX_DST_ADDR					(0x0408)
#define COH901318_CX_DST_ADDR_SPACING				(0x10)

/*
 * CX_LNK_ADDR - Channel Link Address Registers 32bit (R/W)
 */
#define COH901318_CX_LNK_ADDR					(0x040C)
#define COH901318_CX_LNK_ADDR_SPACING				(0x10)
#define COH901318_CX_LNK_LINK_IMMEDIATE				(0x00000001)
#endif /* COH901318_H */
Commit	Line	Data
61f135b9 LW	1	/*
	2	*
	3	* include/linux/coh901318.h
	4	*
	5	*
	6	* Copyright (C) 2007-2009 ST-Ericsson
	7	* License terms: GNU General Public License (GPL) version 2
	8	* DMA driver for COH 901 318
	9	* Author: Per Friden <per.friden@stericsson.com>
	10	*/
	11
	12	#ifndef COH901318_H
	13	#define COH901318_H
	14
	15	#include <linux/device.h>
	16	#include <linux/dmaengine.h>
	17
	18	#define MAX_DMA_PACKET_SIZE_SHIFT 11
	19	#define MAX_DMA_PACKET_SIZE (1 << MAX_DMA_PACKET_SIZE_SHIFT)
	20
	21	/**
	22	* struct coh901318_lli - linked list item for DMAC
	23	* @control: control settings for DMAC
	24	* @src_addr: transfer source address
	25	* @dst_addr: transfer destination address
	26	* @link_addr: physical address to next lli
	27	* @virt_link_addr: virtual addres of next lli (only used by pool_free)
	28	* @phy_this: physical address of current lli (only used by pool_free)
	29	*/
	30	struct coh901318_lli {
	31	u32 control;
	32	dma_addr_t src_addr;
	33	dma_addr_t dst_addr;
	34	dma_addr_t link_addr;
	35
	36	void *virt_link_addr;
	37	dma_addr_t phy_this;
	38	};
	39	/**
	40	* struct coh901318_params - parameters for DMAC configuration
	41	* @config: DMA config register
	42	* @ctrl_lli_last: DMA control register for the last lli in the list
	43	* @ctrl_lli: DMA control register for an lli
	44	* @ctrl_lli_chained: DMA control register for a chained lli
	45	*/
	46	struct coh901318_params {
	47	u32 config;
	48	u32 ctrl_lli_last;
	49	u32 ctrl_lli;
	50	u32 ctrl_lli_chained;
	51	};
	52	/**
	53	* struct coh_dma_channel - dma channel base
	54	* @name: ascii name of dma channel
	55	* @number: channel id number
b87108a7	56	* @desc_nbr_max: number of preallocated descriptors
61f135b9 LW	57	* @priority_high: prio of channel, 0 low otherwise high.
	58	* @param: configuration parameters
	59	* @dev_addr: physical address of periphal connected to channel
	60	*/
	61	struct coh_dma_channel {
	62	const char name[32];
	63	const int number;
	64	const int desc_nbr_max;
	65	const int priority_high;
	66	const struct coh901318_params param;
	67	const dma_addr_t dev_addr;
	68	};
	69
	70	/**
	71	* dma_access_memory_state_t - register dma for memory access
	72	*
	73	* @dev: The dma device
	74	* @active: 1 means dma intends to access memory
	75	* 0 means dma wont access memory
	76	*/
	77	typedef void (dma_access_memory_state_t)(struct device dev,
	78	bool active);
	79
	80	/**
	81	* struct powersave - DMA power save structure
	82	* @lock: lock protecting data in this struct
	83	* @started_channels: bit mask indicating active dma channels
	84	*/
	85	struct powersave {
	86	spinlock_t lock;
	87	u64 started_channels;
	88	};
	89	/**
	90	* struct coh901318_platform - platform arch structure
	91	* @chans_slave: specifying dma slave channels
	92	* @chans_memcpy: specifying dma memcpy channels
	93	* @access_memory_state: requesting DMA memeory access (on / off)
	94	* @chan_conf: dma channel configurations
	95	* @max_channels: max number of dma chanenls
	96	*/
	97	struct coh901318_platform {
	98	const int *chans_slave;
	99	const int *chans_memcpy;
	100	const dma_access_memory_state_t access_memory_state;
	101	const struct coh_dma_channel *chan_conf;
	102	const int max_channels;
	103	};
	104
61f135b9 LW	105	/**
	106	* coh901318_filter_id() - DMA channel filter function
	107	* @chan: dma channel handle
	108	* @chan_id: id of dma channel to be filter out
	109	*
	110	* In dma_request_channel() it specifies what channel id to be requested
	111	*/
	112	bool coh901318_filter_id(struct dma_chan chan, void chan_id);
	113
	114	/*
	115	* DMA Controller - this access the static mappings of the coh901318 dma.
	116	*
	117	*/
	118
	119	#define COH901318_MOD32_MASK (0x1F)
	120	#define COH901318_WORD_MASK (0xFFFFFFFF)
	121	/* INT_STATUS - Interrupt Status Registers 32bit (R/-) */
	122	#define COH901318_INT_STATUS1 (0x0000)
	123	#define COH901318_INT_STATUS2 (0x0004)
	124	/* TC_INT_STATUS - Terminal Count Interrupt Status Registers 32bit (R/-) */
	125	#define COH901318_TC_INT_STATUS1 (0x0008)
	126	#define COH901318_TC_INT_STATUS2 (0x000C)
	127	/* TC_INT_CLEAR - Terminal Count Interrupt Clear Registers 32bit (-/W) */
	128	#define COH901318_TC_INT_CLEAR1 (0x0010)
	129	#define COH901318_TC_INT_CLEAR2 (0x0014)
	130	/* RAW_TC_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
	131	#define COH901318_RAW_TC_INT_STATUS1 (0x0018)
	132	#define COH901318_RAW_TC_INT_STATUS2 (0x001C)
	133	/* BE_INT_STATUS - Bus Error Interrupt Status Registers 32bit (R/-) */
	134	#define COH901318_BE_INT_STATUS1 (0x0020)
	135	#define COH901318_BE_INT_STATUS2 (0x0024)
	136	/* BE_INT_CLEAR - Bus Error Interrupt Clear Registers 32bit (-/W) */
	137	#define COH901318_BE_INT_CLEAR1 (0x0028)
	138	#define COH901318_BE_INT_CLEAR2 (0x002C)
	139	/* RAW_BE_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
	140	#define COH901318_RAW_BE_INT_STATUS1 (0x0030)
	141	#define COH901318_RAW_BE_INT_STATUS2 (0x0034)
	142
	143	/*
	144	* CX_CFG - Channel Configuration Registers 32bit (R/W)
	145	*/
	146	#define COH901318_CX_CFG (0x0100)
	147	#define COH901318_CX_CFG_SPACING (0x04)
	148	/* Channel enable activates tha dma job */
	149	#define COH901318_CX_CFG_CH_ENABLE (0x00000001)
	150	#define COH901318_CX_CFG_CH_DISABLE (0x00000000)
	151	/* Request Mode */
	152	#define COH901318_CX_CFG_RM_MASK (0x00000006)
	153	#define COH901318_CX_CFG_RM_MEMORY_TO_MEMORY (0x0 << 1)
	154	#define COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY (0x1 << 1)
	155	#define COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY (0x1 << 1)
	156	#define COH901318_CX_CFG_RM_PRIMARY_TO_SECONDARY (0x3 << 1)
	157	#define COH901318_CX_CFG_RM_SECONDARY_TO_PRIMARY (0x3 << 1)
	158	/* Linked channel request field. RM must == 11 */
	159	#define COH901318_CX_CFG_LCRF_SHIFT 3
	160	#define COH901318_CX_CFG_LCRF_MASK (0x000001F8)
	161	#define COH901318_CX_CFG_LCR_DISABLE (0x00000000)
	162	/* Terminal Counter Interrupt Request Mask */
	163	#define COH901318_CX_CFG_TC_IRQ_ENABLE (0x00000200)
	164	#define COH901318_CX_CFG_TC_IRQ_DISABLE (0x00000000)
	165	/* Bus Error interrupt Mask */
	166	#define COH901318_CX_CFG_BE_IRQ_ENABLE (0x00000400)
	167	#define COH901318_CX_CFG_BE_IRQ_DISABLE (0x00000000)
	168
169	/*
170	* CX_STAT - Channel Status Registers 32bit (R/-)
171	*/
172	#define COH901318_CX_STAT (0x0200)
173	#define COH901318_CX_STAT_SPACING (0x04)
174	#define COH901318_CX_STAT_RBE_IRQ_IND (0x00000008)
175	#define COH901318_CX_STAT_RTC_IRQ_IND (0x00000004)
176	#define COH901318_CX_STAT_ACTIVE (0x00000002)
177	#define COH901318_CX_STAT_ENABLED (0x00000001)
178
179	/*
180	* CX_CTRL - Channel Control Registers 32bit (R/W)
181	*/
182	#define COH901318_CX_CTRL (0x0400)
183	#define COH901318_CX_CTRL_SPACING (0x10)
184	/* Transfer Count Enable */
185	#define COH901318_CX_CTRL_TC_ENABLE (0x00001000)
186	#define COH901318_CX_CTRL_TC_DISABLE (0x00000000)
187	/* Transfer Count Value 0 - 4095 */
188	#define COH901318_CX_CTRL_TC_VALUE_MASK (0x00000FFF)
189	/* Burst count */
190	#define COH901318_CX_CTRL_BURST_COUNT_MASK (0x0000E000)
191	#define COH901318_CX_CTRL_BURST_COUNT_64_BYTES (0x7 << 13)
192	#define COH901318_CX_CTRL_BURST_COUNT_48_BYTES (0x6 << 13)
193	#define COH901318_CX_CTRL_BURST_COUNT_32_BYTES (0x5 << 13)
194	#define COH901318_CX_CTRL_BURST_COUNT_16_BYTES (0x4 << 13)
195	#define COH901318_CX_CTRL_BURST_COUNT_8_BYTES (0x3 << 13)
196	#define COH901318_CX_CTRL_BURST_COUNT_4_BYTES (0x2 << 13)
197	#define COH901318_CX_CTRL_BURST_COUNT_2_BYTES (0x1 << 13)
198	#define COH901318_CX_CTRL_BURST_COUNT_1_BYTE (0x0 << 13)
199	/* Source bus size */
200	#define COH901318_CX_CTRL_SRC_BUS_SIZE_MASK (0x00030000)
201	#define COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS (0x2 << 16)
202	#define COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS (0x1 << 16)
203	#define COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS (0x0 << 16)
204	/* Source address increment */
205	#define COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE (0x00040000)
206	#define COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE (0x00000000)
207	/* Destination Bus Size */
208	#define COH901318_CX_CTRL_DST_BUS_SIZE_MASK (0x00180000)
209	#define COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS (0x2 << 19)
210	#define COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS (0x1 << 19)
211	#define COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS (0x0 << 19)
212	/* Destination address increment */
213	#define COH901318_CX_CTRL_DST_ADDR_INC_ENABLE (0x00200000)
214	#define COH901318_CX_CTRL_DST_ADDR_INC_DISABLE (0x00000000)
215	/* Master Mode (Master2 is only connected to MSL) */
216	#define COH901318_CX_CTRL_MASTER_MODE_MASK (0x00C00000)
217	#define COH901318_CX_CTRL_MASTER_MODE_M2R_M1W (0x3 << 22)
218	#define COH901318_CX_CTRL_MASTER_MODE_M1R_M2W (0x2 << 22)
219	#define COH901318_CX_CTRL_MASTER_MODE_M2RW (0x1 << 22)
220	#define COH901318_CX_CTRL_MASTER_MODE_M1RW (0x0 << 22)
221	/* Terminal Count flag to PER enable */
222	#define COH901318_CX_CTRL_TCP_ENABLE (0x01000000)
223	#define COH901318_CX_CTRL_TCP_DISABLE (0x00000000)
224	/* Terminal Count flags to CPU enable */
225	#define COH901318_CX_CTRL_TC_IRQ_ENABLE (0x02000000)
226	#define COH901318_CX_CTRL_TC_IRQ_DISABLE (0x00000000)
227	/* Hand shake to peripheral */
228	#define COH901318_CX_CTRL_HSP_ENABLE (0x04000000)
229	#define COH901318_CX_CTRL_HSP_DISABLE (0x00000000)
230	#define COH901318_CX_CTRL_HSS_ENABLE (0x08000000)
231	#define COH901318_CX_CTRL_HSS_DISABLE (0x00000000)
232	/* DMA mode */
233	#define COH901318_CX_CTRL_DDMA_MASK (0x30000000)
234	#define COH901318_CX_CTRL_DDMA_LEGACY (0x0 << 28)
235	#define COH901318_CX_CTRL_DDMA_DEMAND_DMA1 (0x1 << 28)
236	#define COH901318_CX_CTRL_DDMA_DEMAND_DMA2 (0x2 << 28)
237	/* Primary Request Data Destination */
238	#define COH901318_CX_CTRL_PRDD_MASK (0x40000000)
239	#define COH901318_CX_CTRL_PRDD_DEST (0x1 << 30)
240	#define COH901318_CX_CTRL_PRDD_SOURCE (0x0 << 30)
241
242	/*
243	* CX_SRC_ADDR - Channel Source Address Registers 32bit (R/W)
244	*/
245	#define COH901318_CX_SRC_ADDR (0x0404)
246	#define COH901318_CX_SRC_ADDR_SPACING (0x10)
247
248	/*
249	* CX_DST_ADDR - Channel Destination Address Registers 32bit R/W
250	*/
251	#define COH901318_CX_DST_ADDR (0x0408)
252	#define COH901318_CX_DST_ADDR_SPACING (0x10)
253
254	/*
255	* CX_LNK_ADDR - Channel Link Address Registers 32bit (R/W)
256	*/
257	#define COH901318_CX_LNK_ADDR (0x040C)
258	#define COH901318_CX_LNK_ADDR_SPACING (0x10)
259	#define COH901318_CX_LNK_LINK_IMMEDIATE (0x00000001)
260	#endif /* COH901318_H */