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davinci: da850/omap-l138 evm: account for DEFDCDC{2,3} being tied high
[net-next-2.6.git] / arch / arm / mach-davinci / board-da850-evm.c
CommitLineData
0fbc5592
SR		 1/*
2 * TI DA850/OMAP-L138 EVM board
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Derived from: arch/arm/mach-davinci/board-da830-evm.c
7 * Original Copyrights follow:
8 *
9 * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14#include <linux/kernel.h>
0fbc5592
SR		 15#include <linux/init.h>
16#include <linux/console.h>
17#include <linux/i2c.h>
18#include <linux/i2c/at24.h>
75e2ea64 19#include <linux/i2c/pca953x.h>
0bc20bba 20#include <linux/mfd/tps6507x.h>
5cbdf276 21#include <linux/gpio.h>
38beb929
SR		 22#include <linux/platform_device.h>
23#include <linux/mtd/mtd.h>
24#include <linux/mtd/nand.h>
25#include <linux/mtd/partitions.h>
7c5ec609 26#include <linux/mtd/physmap.h>
a9eb1f67 27#include <linux/regulator/machine.h>
8b24599e 28#include <linux/regulator/tps6507x.h>
da1e3680
TF		 29#include <linux/mfd/tps6507x.h>
30#include <linux/input/tps6507x-ts.h>
0fbc5592
SR		 31
32#include <asm/mach-types.h>
33#include <asm/mach/arch.h>
34
0fbc5592
SR		 35#include <mach/cp_intc.h>
36#include <mach/da8xx.h>
38beb929 37#include <mach/nand.h>
7761ef67 38#include <mach/mux.h>
0fbc5592 39
5a4b1315
SR		 40#define DA850_EVM_PHY_MASK 0x1
41#define DA850_EVM_MDIO_FREQUENCY 2200000 /* PHY bus frequency */
42
7761ef67 43#define DA850_LCD_PWR_PIN GPIO_TO_PIN(2, 8)
5cbdf276 44#define DA850_LCD_BL_PIN GPIO_TO_PIN(2, 15)
5cbdf276 45
700691f2
SR		 46#define DA850_MMCSD_CD_PIN GPIO_TO_PIN(4, 0)
47#define DA850_MMCSD_WP_PIN GPIO_TO_PIN(4, 1)
48
2206771c
C		 49#define DA850_MII_MDIO_CLKEN_PIN GPIO_TO_PIN(2, 6)
50
7c5ec609
SR		 51static struct mtd_partition da850_evm_norflash_partition[] = {
52 {
e2abd5a2 53 .name = "bootloaders + env",
7c5ec609 54 .offset = 0,
e2abd5a2
SR		 55 .size = SZ_512K,
56 .mask_flags = MTD_WRITEABLE,
57 },
58 {
59 .name = "kernel",
60 .offset = MTDPART_OFS_APPEND,
61 .size = SZ_2M,
62 .mask_flags = 0,
63 },
64 {
65 .name = "filesystem",
66 .offset = MTDPART_OFS_APPEND,
7c5ec609
SR		 67 .size = MTDPART_SIZ_FULL,
68 .mask_flags = 0,
69 },
70};
71
72static struct physmap_flash_data da850_evm_norflash_data = {
73 .width = 2,
74 .parts = da850_evm_norflash_partition,
75 .nr_parts = ARRAY_SIZE(da850_evm_norflash_partition),
76};
77
78static struct resource da850_evm_norflash_resource[] = {
79 {
80 .start = DA8XX_AEMIF_CS2_BASE,
81 .end = DA8XX_AEMIF_CS2_BASE + SZ_32M - 1,
82 .flags = IORESOURCE_MEM,
83 },
84};
85
86static struct platform_device da850_evm_norflash_device = {
87 .name = "physmap-flash",
88 .id = 0,
89 .dev = {
90 .platform_data = &da850_evm_norflash_data,
91 },
92 .num_resources = 1,
93 .resource = da850_evm_norflash_resource,
94};
95
63534443
SN		 96static struct davinci_pm_config da850_pm_pdata = {
97 .sleepcount = 128,
98};
99
100static struct platform_device da850_pm_device = {
101 .name = "pm-davinci",
102 .dev = {
103 .platform_data = &da850_pm_pdata,
104 },
105 .id = -1,
106};
107
38beb929
SR		 108/* DA850/OMAP-L138 EVM includes a 512 MByte large-page NAND flash
109 * (128K blocks). It may be used instead of the (default) SPI flash
110 * to boot, using TI's tools to install the secondary boot loader
111 * (UBL) and U-Boot.
112 */
113struct mtd_partition da850_evm_nandflash_partition[] = {
114 {
115 .name = "u-boot env",
116 .offset = 0,
117 .size = SZ_128K,
118 .mask_flags = MTD_WRITEABLE,
119 },
120 {
121 .name = "UBL",
122 .offset = MTDPART_OFS_APPEND,
123 .size = SZ_128K,
124 .mask_flags = MTD_WRITEABLE,
125 },
126 {
127 .name = "u-boot",
128 .offset = MTDPART_OFS_APPEND,
129 .size = 4 * SZ_128K,
130 .mask_flags = MTD_WRITEABLE,
131 },
132 {
133 .name = "kernel",
134 .offset = 0x200000,
135 .size = SZ_2M,
136 .mask_flags = 0,
137 },
138 {
139 .name = "filesystem",
140 .offset = MTDPART_OFS_APPEND,
141 .size = MTDPART_SIZ_FULL,
142 .mask_flags = 0,
143 },
144};
145
146static struct davinci_nand_pdata da850_evm_nandflash_data = {
147 .parts = da850_evm_nandflash_partition,
148 .nr_parts = ARRAY_SIZE(da850_evm_nandflash_partition),
149 .ecc_mode = NAND_ECC_HW,
fc42e335 150 .ecc_bits = 4,
38beb929
SR		 151 .options = NAND_USE_FLASH_BBT,
152};
153
154static struct resource da850_evm_nandflash_resource[] = {
155 {
156 .start = DA8XX_AEMIF_CS3_BASE,
157 .end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
158 .flags = IORESOURCE_MEM,
159 },
160 {
161 .start = DA8XX_AEMIF_CTL_BASE,
162 .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
163 .flags = IORESOURCE_MEM,
164 },
165};
166
167static struct platform_device da850_evm_nandflash_device = {
168 .name = "davinci_nand",
169 .id = 1,
170 .dev = {
171 .platform_data = &da850_evm_nandflash_data,
172 },
173 .num_resources = ARRAY_SIZE(da850_evm_nandflash_resource),
174 .resource = da850_evm_nandflash_resource,
175};
176
039c5ee3
SR		 177static struct platform_device *da850_evm_devices[] __initdata = {
178 &da850_evm_nandflash_device,
179 &da850_evm_norflash_device,
180};
181
182#define DA8XX_AEMIF_CE2CFG_OFFSET 0x10
183#define DA8XX_AEMIF_ASIZE_16BIT 0x1
184
185static void __init da850_evm_init_nor(void)
186{
187 void __iomem *aemif_addr;
188
189 aemif_addr = ioremap(DA8XX_AEMIF_CTL_BASE, SZ_32K);
190
191 /* Configure data bus width of CS2 to 16 bit */
192 writel(readl(aemif_addr + DA8XX_AEMIF_CE2CFG_OFFSET) |
193 DA8XX_AEMIF_ASIZE_16BIT,
194 aemif_addr + DA8XX_AEMIF_CE2CFG_OFFSET);
195
196 iounmap(aemif_addr);
197}
198
75e2ea64 199static u32 ui_card_detected;
039c5ee3
SR		 200
201#if defined(CONFIG_MMC_DAVINCI) || \
202 defined(CONFIG_MMC_DAVINCI_MODULE)
203#define HAS_MMC 1
204#else
205#define HAS_MMC 0
206#endif
207
1ef203c3 208static __init void da850_evm_setup_nor_nand(void)
039c5ee3
SR		 209{
210 int ret = 0;
211
212 if (ui_card_detected & !HAS_MMC) {
3821d10a 213 ret = davinci_cfg_reg_list(da850_nand_pins);
039c5ee3
SR		 214 if (ret)
215 pr_warning("da850_evm_init: nand mux setup failed: "
216 "%d\n", ret);
217
3821d10a 218 ret = davinci_cfg_reg_list(da850_nor_pins);
039c5ee3
SR		 219 if (ret)
220 pr_warning("da850_evm_init: nor mux setup failed: %d\n",
221 ret);
222
223 da850_evm_init_nor();
224
225 platform_add_devices(da850_evm_devices,
226 ARRAY_SIZE(da850_evm_devices));
227 }
228}
75e2ea64 229
bae10587
SN		 230#ifdef CONFIG_DA850_UI_RMII
231static inline void da850_evm_setup_emac_rmii(int rmii_sel)
232{
233 struct davinci_soc_info *soc_info = &davinci_soc_info;
234
235 soc_info->emac_pdata->rmii_en = 1;
236 gpio_set_value(rmii_sel, 0);
237}
238#else
239static inline void da850_evm_setup_emac_rmii(int rmii_sel) { }
240#endif
241
75e2ea64
C		 242static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio,
243 unsigned ngpio, void *c)
244{
245 int sel_a, sel_b, sel_c, ret;
246
247 sel_a = gpio + 7;
248 sel_b = gpio + 6;
249 sel_c = gpio + 5;
250
251 ret = gpio_request(sel_a, "sel_a");
252 if (ret) {
253 pr_warning("Cannot open UI expander pin %d\n", sel_a);
254 goto exp_setup_sela_fail;
255 }
256
257 ret = gpio_request(sel_b, "sel_b");
258 if (ret) {
259 pr_warning("Cannot open UI expander pin %d\n", sel_b);
260 goto exp_setup_selb_fail;
261 }
262
263 ret = gpio_request(sel_c, "sel_c");
264 if (ret) {
265 pr_warning("Cannot open UI expander pin %d\n", sel_c);
266 goto exp_setup_selc_fail;
267 }
268
269 /* deselect all functionalities */
270 gpio_direction_output(sel_a, 1);
271 gpio_direction_output(sel_b, 1);
272 gpio_direction_output(sel_c, 1);
273
274 ui_card_detected = 1;
275 pr_info("DA850/OMAP-L138 EVM UI card detected\n");
276
277 da850_evm_setup_nor_nand();
278
bae10587 279 da850_evm_setup_emac_rmii(sel_a);
2206771c 280
75e2ea64
C		 281 return 0;
282
283exp_setup_selc_fail:
284 gpio_free(sel_b);
285exp_setup_selb_fail:
286 gpio_free(sel_a);
287exp_setup_sela_fail:
288 return ret;
289}
290
291static int da850_evm_ui_expander_teardown(struct i2c_client *client,
292 unsigned gpio, unsigned ngpio, void *c)
293{
294 /* deselect all functionalities */
295 gpio_set_value(gpio + 5, 1);
296 gpio_set_value(gpio + 6, 1);
297 gpio_set_value(gpio + 7, 1);
298
299 gpio_free(gpio + 5);
300 gpio_free(gpio + 6);
301 gpio_free(gpio + 7);
302
303 return 0;
304}
305
306static struct pca953x_platform_data da850_evm_ui_expander_info = {
307 .gpio_base = DAVINCI_N_GPIO,
308 .setup = da850_evm_ui_expander_setup,
309 .teardown = da850_evm_ui_expander_teardown,
310};
311
1a7ff8ff
C		 312static struct i2c_board_info __initdata da850_evm_i2c_devices[] = {
313 {
314 I2C_BOARD_INFO("tlv320aic3x", 0x18),
75e2ea64
C		 315 },
316 {
317 I2C_BOARD_INFO("tca6416", 0x20),
318 .platform_data = &da850_evm_ui_expander_info,
319 },
1a7ff8ff
C		 320};
321
0fbc5592
SR		 322static struct davinci_i2c_platform_data da850_evm_i2c_0_pdata = {
323 .bus_freq = 100, /* kHz */
324 .bus_delay = 0, /* usec */
325};
326
327static struct davinci_uart_config da850_evm_uart_config __initdata = {
328 .enabled_uarts = 0x7,
329};
330
491214e1
C		 331/* davinci da850 evm audio machine driver */
332static u8 da850_iis_serializer_direction[] = {
333 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
334 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
335 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, TX_MODE,
336 RX_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
337};
338
339static struct snd_platform_data da850_evm_snd_data = {
340 .tx_dma_offset = 0x2000,
341 .rx_dma_offset = 0x2000,
342 .op_mode = DAVINCI_MCASP_IIS_MODE,
343 .num_serializer = ARRAY_SIZE(da850_iis_serializer_direction),
344 .tdm_slots = 2,
345 .serial_dir = da850_iis_serializer_direction,
346 .eventq_no = EVENTQ_1,
347 .version = MCASP_VERSION_2,
348 .txnumevt = 1,
349 .rxnumevt = 1,
350};
351
700691f2
SR		 352static int da850_evm_mmc_get_ro(int index)
353{
354 return gpio_get_value(DA850_MMCSD_WP_PIN);
355}
356
357static int da850_evm_mmc_get_cd(int index)
358{
359 return !gpio_get_value(DA850_MMCSD_CD_PIN);
360}
361
362static struct davinci_mmc_config da850_mmc_config = {
363 .get_ro = da850_evm_mmc_get_ro,
364 .get_cd = da850_evm_mmc_get_cd,
365 .wires = 4,
0046d0bf
C		 366 .max_freq = 50000000,
367 .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
700691f2
SR		 368 .version = MMC_CTLR_VERSION_2,
369};
370
d52f235f
C		 371static void da850_panel_power_ctrl(int val)
372{
373 /* lcd backlight */
374 gpio_set_value(DA850_LCD_BL_PIN, val);
375
376 /* lcd power */
377 gpio_set_value(DA850_LCD_PWR_PIN, val);
378}
379
5cbdf276
SR		 380static int da850_lcd_hw_init(void)
381{
382 int status;
383
384 status = gpio_request(DA850_LCD_BL_PIN, "lcd bl\n");
385 if (status < 0)
386 return status;
387
388 status = gpio_request(DA850_LCD_PWR_PIN, "lcd pwr\n");
389 if (status < 0) {
390 gpio_free(DA850_LCD_BL_PIN);
391 return status;
392 }
393
394 gpio_direction_output(DA850_LCD_BL_PIN, 0);
395 gpio_direction_output(DA850_LCD_PWR_PIN, 0);
396
d52f235f
C		 397 /* Switch off panel power and backlight */
398 da850_panel_power_ctrl(0);
5cbdf276 399
d52f235f
C		 400 /* Switch on panel power and backlight */
401 da850_panel_power_ctrl(1);
5cbdf276
SR		 402
403 return 0;
404}
491214e1 405
a9eb1f67
SN		 406/* TPS65070 voltage regulator support */
407
408/* 3.3V */
409struct regulator_consumer_supply tps65070_dcdc1_consumers[] = {
410 {
411 .supply = "usb0_vdda33",
412 },
413 {
414 .supply = "usb1_vdda33",
415 },
416};
417
418/* 3.3V or 1.8V */
419struct regulator_consumer_supply tps65070_dcdc2_consumers[] = {
420 {
421 .supply = "dvdd3318_a",
422 },
423 {
424 .supply = "dvdd3318_b",
425 },
426 {
427 .supply = "dvdd3318_c",
428 },
429};
430
431/* 1.2V */
432struct regulator_consumer_supply tps65070_dcdc3_consumers[] = {
433 {
434 .supply = "cvdd",
435 },
436};
437
438/* 1.8V LDO */
439struct regulator_consumer_supply tps65070_ldo1_consumers[] = {
440 {
441 .supply = "sata_vddr",
442 },
443 {
444 .supply = "usb0_vdda18",
445 },
446 {
447 .supply = "usb1_vdda18",
448 },
449 {
450 .supply = "ddr_dvdd18",
451 },
452};
453
454/* 1.2V LDO */
455struct regulator_consumer_supply tps65070_ldo2_consumers[] = {
456 {
457 .supply = "sata_vdd",
458 },
459 {
460 .supply = "pll0_vdda",
461 },
462 {
463 .supply = "pll1_vdda",
464 },
465 {
466 .supply = "usbs_cvdd",
467 },
468 {
469 .supply = "vddarnwa1",
470 },
471};
472
8b24599e
SN		 473/* We take advantage of the fact that both defdcdc{2,3} are tied high */
474static struct tps6507x_reg_platform_data tps6507x_platform_data = {
475 .defdcdc_default = true,
476};
477
a9eb1f67
SN		 478struct regulator_init_data tps65070_regulator_data[] = {
479 /* dcdc1 */
480 {
481 .constraints = {
482 .min_uV = 3150000,
483 .max_uV = 3450000,
484 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
485 REGULATOR_CHANGE_STATUS),
486 .boot_on = 1,
487 },
488 .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc1_consumers),
489 .consumer_supplies = tps65070_dcdc1_consumers,
490 },
491
492 /* dcdc2 */
493 {
494 .constraints = {
495 .min_uV = 1710000,
496 .max_uV = 3450000,
497 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
498 REGULATOR_CHANGE_STATUS),
499 .boot_on = 1,
500 },
501 .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc2_consumers),
502 .consumer_supplies = tps65070_dcdc2_consumers,
8b24599e 503 .driver_data = &tps6507x_platform_data,
a9eb1f67
SN		 504 },
505
506 /* dcdc3 */
507 {
508 .constraints = {
509 .min_uV = 950000,
510 .max_uV = 1320000,
511 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
512 REGULATOR_CHANGE_STATUS),
513 .boot_on = 1,
514 },
515 .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc3_consumers),
516 .consumer_supplies = tps65070_dcdc3_consumers,
8b24599e 517 .driver_data = &tps6507x_platform_data,
a9eb1f67
SN		 518 },
519
520 /* ldo1 */
521 {
522 .constraints = {
523 .min_uV = 1710000,
524 .max_uV = 1890000,
525 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
526 REGULATOR_CHANGE_STATUS),
527 .boot_on = 1,
528 },
529 .num_consumer_supplies = ARRAY_SIZE(tps65070_ldo1_consumers),
530 .consumer_supplies = tps65070_ldo1_consumers,
531 },
532
533 /* ldo2 */
534 {
535 .constraints = {
536 .min_uV = 1140000,
537 .max_uV = 1320000,
538 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
539 REGULATOR_CHANGE_STATUS),
540 .boot_on = 1,
541 },
542 .num_consumer_supplies = ARRAY_SIZE(tps65070_ldo2_consumers),
543 .consumer_supplies = tps65070_ldo2_consumers,
544 },
545};
546
da1e3680
TF		 547static struct touchscreen_init_data tps6507x_touchscreen_data = {
548 .poll_period = 30, /* ms between touch samples */
549 .min_pressure = 0x30, /* minimum pressure to trigger touch */
550 .vref = 0, /* turn off vref when not using A/D */
551 .vendor = 0, /* /sys/class/input/input?/id/vendor */
552 .product = 65070, /* /sys/class/input/input?/id/product */
553 .version = 0x100, /* /sys/class/input/input?/id/version */
554};
555
0bc20bba
TF		 556static struct tps6507x_board tps_board = {
557 .tps6507x_pmic_init_data = &tps65070_regulator_data[0],
da1e3680 558 .tps6507x_ts_init_data = &tps6507x_touchscreen_data,
0bc20bba
TF		 559};
560
a9eb1f67
SN		 561static struct i2c_board_info __initdata da850evm_tps65070_info[] = {
562 {
563 I2C_BOARD_INFO("tps6507x", 0x48),
0bc20bba 564 .platform_data = &tps_board,
a9eb1f67
SN		 565 },
566};
567
568static int __init pmic_tps65070_init(void)
569{
570 return i2c_register_board_info(1, da850evm_tps65070_info,
571 ARRAY_SIZE(da850evm_tps65070_info));
572}
573
7761ef67
SR		 574static const short da850_evm_lcdc_pins[] = {
575 DA850_GPIO2_8, DA850_GPIO2_15,
576 -1
577};
578
bae10587 579static int __init da850_evm_config_emac(void)
2206771c
C		 580{
581 void __iomem *cfg_chip3_base;
582 int ret;
583 u32 val;
bae10587
SN		 584 struct davinci_soc_info *soc_info = &davinci_soc_info;
585 u8 rmii_en = soc_info->emac_pdata->rmii_en;
586
587 if (!machine_is_davinci_da850_evm())
588 return 0;
2206771c 589
d2de0582 590 cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
2206771c 591
2206771c 592 val = __raw_readl(cfg_chip3_base);
17fadd9a
SN		 593
594 if (rmii_en) {
2206771c 595 val |= BIT(8);
3821d10a 596 ret = davinci_cfg_reg_list(da850_rmii_pins);
17fadd9a
SN		 597 pr_info("EMAC: RMII PHY configured, MII PHY will not be"
598 " functional\n");
599 } else {
2206771c 600 val &= ~BIT(8);
3821d10a 601 ret = davinci_cfg_reg_list(da850_cpgmac_pins);
17fadd9a
SN		 602 pr_info("EMAC: MII PHY configured, RMII PHY will not be"
603 " functional\n");
604 }
605
2206771c
C		 606 if (ret)
607 pr_warning("da850_evm_init: cpgmac/rmii mux setup failed: %d\n",
608 ret);
609
17fadd9a
SN		 610 /* configure the CFGCHIP3 register for RMII or MII */
611 __raw_writel(val, cfg_chip3_base);
612
2206771c
C		 613 ret = davinci_cfg_reg(DA850_GPIO2_6);
614 if (ret)
615 pr_warning("da850_evm_init:GPIO(2,6) mux setup "
616 "failed\n");
617
618 ret = gpio_request(DA850_MII_MDIO_CLKEN_PIN, "mdio_clk_en");
619 if (ret) {
620 pr_warning("Cannot open GPIO %d\n",
621 DA850_MII_MDIO_CLKEN_PIN);
622 return ret;
623 }
624
17fadd9a
SN		 625 /* Enable/Disable MII MDIO clock */
626 gpio_direction_output(DA850_MII_MDIO_CLKEN_PIN, rmii_en);
2206771c 627
bae10587
SN		 628 soc_info->emac_pdata->phy_mask = DA850_EVM_PHY_MASK;
629 soc_info->emac_pdata->mdio_max_freq = DA850_EVM_MDIO_FREQUENCY;
630
631 ret = da8xx_register_emac();
632 if (ret)
633 pr_warning("da850_evm_init: emac registration failed: %d\n",
634 ret);
635
2206771c
C		 636 return 0;
637}
bae10587 638device_initcall(da850_evm_config_emac);
2206771c 639
0fbc5592
SR		 640static __init void da850_evm_init(void)
641{
642 int ret;
643
a9eb1f67
SN		 644 ret = pmic_tps65070_init();
645 if (ret)
646 pr_warning("da850_evm_init: TPS65070 PMIC init failed: %d\n",
647 ret);
648
0fbc5592
SR		 649 ret = da8xx_register_edma();
650 if (ret)
651 pr_warning("da850_evm_init: edma registration failed: %d\n",
652 ret);
653
3821d10a 654 ret = davinci_cfg_reg_list(da850_i2c0_pins);
0fbc5592
SR		 655 if (ret)
656 pr_warning("da850_evm_init: i2c0 mux setup failed: %d\n",
657 ret);
658
659 ret = da8xx_register_i2c(0, &da850_evm_i2c_0_pdata);
660 if (ret)
661 pr_warning("da850_evm_init: i2c0 registration failed: %d\n",
662 ret);
663
5a4b1315 664
0fbc5592
SR		 665 ret = da8xx_register_watchdog();
666 if (ret)
667 pr_warning("da830_evm_init: watchdog registration failed: %d\n",
668 ret);
669
820c4fe3 670 if (HAS_MMC) {
3821d10a 671 ret = davinci_cfg_reg_list(da850_mmcsd0_pins);
820c4fe3
SR		 672 if (ret)
673 pr_warning("da850_evm_init: mmcsd0 mux setup failed:"
674 " %d\n", ret);
675
676 ret = gpio_request(DA850_MMCSD_CD_PIN, "MMC CD\n");
677 if (ret)
678 pr_warning("da850_evm_init: can not open GPIO %d\n",
679 DA850_MMCSD_CD_PIN);
680 gpio_direction_input(DA850_MMCSD_CD_PIN);
681
682 ret = gpio_request(DA850_MMCSD_WP_PIN, "MMC WP\n");
683 if (ret)
684 pr_warning("da850_evm_init: can not open GPIO %d\n",
685 DA850_MMCSD_WP_PIN);
686 gpio_direction_input(DA850_MMCSD_WP_PIN);
687
688 ret = da8xx_register_mmcsd0(&da850_mmc_config);
689 if (ret)
690 pr_warning("da850_evm_init: mmcsd0 registration failed:"
691 " %d\n", ret);
692 }
700691f2 693
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SR		 694 davinci_serial_init(&da850_evm_uart_config);
695
1a7ff8ff
C		 696 i2c_register_board_info(1, da850_evm_i2c_devices,
697 ARRAY_SIZE(da850_evm_i2c_devices));
698
0fbc5592
SR		 699 /*
700 * shut down uart 0 and 1; they are not used on the board and
701 * accessing them causes endless "too much work in irq53" messages
702 * with arago fs
703 */
704 __raw_writel(0, IO_ADDRESS(DA8XX_UART1_BASE) + 0x30);
705 __raw_writel(0, IO_ADDRESS(DA8XX_UART0_BASE) + 0x30);
491214e1 706
3821d10a 707 ret = davinci_cfg_reg_list(da850_mcasp_pins);
491214e1
C		 708 if (ret)
709 pr_warning("da850_evm_init: mcasp mux setup failed: %d\n",
710 ret);
711
b8864aa4 712 da8xx_register_mcasp(0, &da850_evm_snd_data);
5cbdf276 713
3821d10a 714 ret = davinci_cfg_reg_list(da850_lcdcntl_pins);
5cbdf276
SR		 715 if (ret)
716 pr_warning("da850_evm_init: lcdcntl mux setup failed: %d\n",
717 ret);
718
7761ef67 719 /* Handle board specific muxing for LCD here */
3821d10a 720 ret = davinci_cfg_reg_list(da850_evm_lcdc_pins);
7761ef67
SR		 721 if (ret)
722 pr_warning("da850_evm_init: evm specific lcd mux setup "
723 "failed: %d\n", ret);
724
5cbdf276
SR		 725 ret = da850_lcd_hw_init();
726 if (ret)
727 pr_warning("da850_evm_init: lcd initialization failed: %d\n",
728 ret);
729
d52f235f 730 sharp_lk043t1dg01_pdata.panel_power_ctrl = da850_panel_power_ctrl,
b9e6342b 731 ret = da8xx_register_lcdc(&sharp_lk043t1dg01_pdata);
5cbdf276
SR		 732 if (ret)
733 pr_warning("da850_evm_init: lcdc registration failed: %d\n",
734 ret);
c51df70b
MG		 735
736 ret = da8xx_register_rtc();
737 if (ret)
738 pr_warning("da850_evm_init: rtc setup failed: %d\n", ret);
09dc2d45
SN		 739
740 ret = da850_register_cpufreq();
741 if (ret)
742 pr_warning("da850_evm_init: cpufreq registration failed: %d\n",
743 ret);
5aeb15aa
SN		 744
745 ret = da8xx_register_cpuidle();
746 if (ret)
747 pr_warning("da850_evm_init: cpuidle registration failed: %d\n",
748 ret);
63534443
SN		 749
750 ret = da850_register_pm(&da850_pm_device);
751 if (ret)
752 pr_warning("da850_evm_init: suspend registration failed: %d\n",
753 ret);
0fbc5592
SR		 754}
755
756#ifdef CONFIG_SERIAL_8250_CONSOLE
757static int __init da850_evm_console_init(void)
758{
759 return add_preferred_console("ttyS", 2, "115200");
760}
761console_initcall(da850_evm_console_init);
762#endif
763
0fbc5592
SR		 764static void __init da850_evm_map_io(void)
765{
766 da850_init();
767}
768
769MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138 EVM")
770 .phys_io = IO_PHYS,
771 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
772 .boot_params = (DA8XX_DDR_BASE + 0x100),
773 .map_io = da850_evm_map_io,
bd808947 774 .init_irq = cp_intc_init,
0fbc5592
SR		 775 .timer = &davinci_timer,
776 .init_machine = da850_evm_init,
777MACHINE_END
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