}
static inline void
-jme_set_gmii(struct jme_adapter *jme)
+jme_set_phyfifoa(struct jme_adapter *jme)
{
jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
}
static inline void
-jme_set_rgmii(struct jme_adapter *jme)
+jme_set_phyfifob(struct jme_adapter *jme)
{
jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
}
case PHY_LINK_SPEED_10M:
ghc |= GHC_SPEED_10M;
strcat(linkmsg, "10 Mbps, ");
- if (jme->rev == 0x11)
- jme_set_gmii(jme);
+ if (is_buggy250(jme->pdev->device, jme->chiprev))
+ jme_set_phyfifoa(jme);
break;
case PHY_LINK_SPEED_100M:
ghc |= GHC_SPEED_100M;
strcat(linkmsg, "100 Mbps, ");
- if (jme->rev == 0x11)
- jme_set_rgmii(jme);
+ if (is_buggy250(jme->pdev->device, jme->chiprev))
+ jme_set_phyfifob(jme);
break;
case PHY_LINK_SPEED_1000M:
ghc |= GHC_SPEED_1000M;
strcat(linkmsg, "1000 Mbps, ");
- if (jme->rev == 0x11)
- jme_set_gmii(jme);
+ if (is_buggy250(jme->pdev->device, jme->chiprev))
+ jme_set_phyfifoa(jme);
break;
default:
break;
while (!atomic_dec_and_test(&jme->link_changing)) {
atomic_inc(&jme->link_changing);
msg_intr(jme, "Get link change lock failed.\n");
- while(atomic_read(&jme->link_changing) != 1)
+ while (atomic_read(&jme->link_changing) != 1)
msg_intr(jme, "Waiting link change lock.\n");
}
chipmode = jread32(jme, JME_CHIPMODE);
jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
- jme->chipver = (chipmode & CM_CHIPVER_MASK) >> CM_CHIPVER_SHIFT;
+ jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
}
static int __devinit
jme->mii_if.mdio_write = jme_mdio_write;
jme_clear_pm(jme);
- jme_set_gmii(jme);
+ jme_set_phyfifoa(jme);
pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev);
if (!jme->fpgaver)
jme_phy_init(jme);
}
msg_probe(jme,
- "JMC250 gigabit%s ver:%u rev:%1x.%1x "
+ "JMC250 gigabit%s ver:%x rev:%x "
"macaddr:%02x:%02x:%02x:%02x:%02x:%02x\n",
(jme->fpgaver != 0) ? " (FPGA)" : "",
- (jme->fpgaver != 0) ? jme->fpgaver : jme->chipver,
- jme->rev & 0xf, (jme->rev >> 4) & 0xf,
+ (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
+ jme->rev,
netdev->dev_addr[0],
netdev->dev_addr[1],
netdev->dev_addr[2],
#define __JME_H_INCLUDEE__
#define DRV_NAME "jme"
-#define DRV_VERSION "1.0"
+#define DRV_VERSION "1.0.2"
#define PFX DRV_NAME ": "
#define PCI_DEVICE_ID_JMICRON_JMC250 0x0250
u32 rx_ring_mask;
u8 mrrs;
unsigned int fpgaver;
- unsigned int chipver;
+ unsigned int chiprev;
u8 rev;
u32 msg_enable;
struct ethtool_cmd old_ecmd;
*/
enum jme_chipmode_bit_masks {
CM_FPGAVER_MASK = 0xFFFF0000,
- CM_CHIPVER_MASK = 0x0000FF00,
+ CM_CHIPREV_MASK = 0x0000FF00,
CM_CHIPMODE_MASK = 0x0000000F,
};
enum jme_chipmode_shifts {
CM_FPGAVER_SHIFT = 16,
- CM_CHIPVER_SHIFT = 8,
+ CM_CHIPREV_SHIFT = 8,
};
/*
const char *msg, u32 val, u32 reg)
{
const char *regname;
- switch(reg & 0xF00) {
+ switch (reg & 0xF00) {
case 0x000:
regname = MAC_REG_NAME[(reg & 0xFF) >> 2];
break;
regname = PE_REG_NAME[(reg & 0xFF) >> 2];
break;
case 0x800:
- regname = MISC_REG_NAME[(reg & 0xFF) >>2];
+ regname = MISC_REG_NAME[(reg & 0xFF) >> 2];
break;
default:
regname = PE_REG_NAME[0];
#define BMSR_ANCOMP 0x0020
+/*
+ * Workaround
+ */
+static inline int is_buggy250(unsigned short device, unsigned int chiprev)
+{
+ return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
+}
+
/*
* Function prototypes
*/