X-Git-Url: http://bbs.cooldavid.org/git/?p=jme.git;a=blobdiff_plain;f=jme.h;h=eac09264bf2a0da8d48247df6b8e482835a5a249;hp=317a28e7a02548a02b51a2e7a4191c553ce92a83;hb=eee57828a853e80515b43bfda3b517706e42bf46;hpb=cd0ff491e3c0fdb01fb189987c4d822b1113cc53 diff --git a/jme.h b/jme.h index 317a28e..eac0926 100644 --- a/jme.h +++ b/jme.h @@ -3,6 +3,7 @@ * * Copyright 2008 JMicron Technology Corporation * http://www.jmicron.com/ + * Copyright (c) 2009 - 2010 Guo-Fu Tseng * * Author: Guo-Fu Tseng * @@ -22,10 +23,10 @@ */ #ifndef __JME_H_INCLUDED__ -#define __JME_H_INCLUDEE__ +#define __JME_H_INCLUDED__ #define DRV_NAME "jme" -#define DRV_VERSION "1.0" +#define DRV_VERSION "1.0.7" #define PFX DRV_NAME ": " #define PCI_DEVICE_ID_JMICRON_JMC250 0x0250 @@ -41,47 +42,17 @@ NETIF_MSG_TX_ERR | \ NETIF_MSG_HW) -#define jeprintk(pdev, fmt, args...) \ - printk(KERN_ERR PFX fmt, ## args) - #ifdef TX_DEBUG -#define tx_dbg(priv, fmt, args...) \ - printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ## args) +#define tx_dbg(priv, fmt, args...) \ + printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args) #else -#define tx_dbg(priv, fmt, args...) +#define tx_dbg(priv, fmt, args...) \ +do { \ + if (0) \ + printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args); \ +} while (0) #endif -#define jme_msg(msglvl, type, priv, fmt, args...) \ - if (netif_msg_##type(priv)) \ - printk(msglvl "%s: " fmt, (priv)->dev->name, ## args) - -#define msg_probe(priv, fmt, args...) \ - jme_msg(KERN_INFO, probe, priv, fmt, ## args) - -#define msg_link(priv, fmt, args...) \ - jme_msg(KERN_INFO, link, priv, fmt, ## args) - -#define msg_intr(priv, fmt, args...) \ - jme_msg(KERN_INFO, intr, priv, fmt, ## args) - -#define msg_rx_err(priv, fmt, args...) \ - jme_msg(KERN_ERR, rx_err, priv, fmt, ## args) - -#define msg_rx_status(priv, fmt, args...) \ - jme_msg(KERN_INFO, rx_status, priv, fmt, ## args) - -#define msg_tx_err(priv, fmt, args...) \ - jme_msg(KERN_ERR, tx_err, priv, fmt, ## args) - -#define msg_tx_done(priv, fmt, args...) \ - jme_msg(KERN_INFO, tx_done, priv, fmt, ## args) - -#define msg_tx_queued(priv, fmt, args...) \ - jme_msg(KERN_INFO, tx_queued, priv, fmt, ## args) - -#define msg_hw(priv, fmt, args...) \ - jme_msg(KERN_ERR, hw, priv, fmt, ## args) - /* * Extra PCI Configuration space interface */ @@ -247,7 +218,7 @@ enum jme_txdesc_flags_bits { }; #define TXDESC_MSS_SHIFT 2 -enum jme_rxdescwb_flags_bits { +enum jme_txwbdesc_flags_bits { TXWBFLAG_OWN = 0x80, TXWBFLAG_INT = 0x40, TXWBFLAG_TMOUT = 0x20, @@ -372,7 +343,6 @@ struct jme_buffer_info { /* * The structure holding buffer information and ring descriptors all together. */ -#define MAX_RING_DESC_NR 1024 struct jme_ring { void *alloc; /* pointer to allocated memory */ void *desc; /* pointer to ring memory */ @@ -380,7 +350,7 @@ struct jme_ring { dma_addr_t dma; /* phys address for ring dma */ /* Buffer information corresponding to each descriptor */ - struct jme_buffer_info bufinf[MAX_RING_DESC_NR]; + struct jme_buffer_info *bufinf; int next_to_use; atomic_t next_to_clean; @@ -398,26 +368,23 @@ struct jme_ring { #define JME_NAPI_WEIGHT(w) int w #define JME_NAPI_WEIGHT_VAL(w) w #define JME_NAPI_WEIGHT_SET(w, r) -#define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev, napis) +#define JME_RX_COMPLETE(dev, napis) napi_complete(napis) #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi); #define JME_NAPI_DISABLE(priv) \ if (!napi_disable_pending(&priv->napi)) \ napi_disable(&priv->napi); #define JME_RX_SCHEDULE_PREP(priv) \ - netif_rx_schedule_prep(priv->dev, &priv->napi) + napi_schedule_prep(&priv->napi) #define JME_RX_SCHEDULE(priv) \ - __netif_rx_schedule(priv->dev, &priv->napi); + __napi_schedule(&priv->napi); /* * Jmac Adapter Private data */ -#define SHADOW_REG_NR 8 struct jme_adapter { struct pci_dev *pdev; struct net_device *dev; void __iomem *regs; - dma_addr_t shadow_dma; - u32 *shadow_regs; struct mii_if_info mii_if; struct jme_ring rxring[RX_RING_NR]; struct jme_ring txring[TX_RING_NR]; @@ -444,7 +411,7 @@ struct jme_adapter { u32 rx_ring_mask; u8 mrrs; unsigned int fpgaver; - unsigned int chipver; + unsigned int chiprev; u8 rev; u32 msg_enable; struct ethtool_cmd old_ecmd; @@ -464,10 +431,6 @@ struct jme_adapter { DECLARE_NET_DEVICE_STATS }; -enum shadow_reg_val { - SHADOW_IEVE = 0, -}; - enum jme_flags_bits { JME_FLAG_MSI = 1, JME_FLAG_SSET = 2, @@ -815,16 +778,30 @@ static inline u32 smi_phy_addr(int x) * Global Host Control */ enum jme_ghc_bit_mask { - GHC_SWRST = 0x40000000, - GHC_DPX = 0x00000040, - GHC_SPEED = 0x00000030, - GHC_LINK_POLL = 0x00000001, + GHC_SWRST = 0x40000000, + GHC_DPX = 0x00000040, + GHC_SPEED = 0x00000030, + GHC_LINK_POLL = 0x00000001, }; enum jme_ghc_speed_val { - GHC_SPEED_10M = 0x00000010, - GHC_SPEED_100M = 0x00000020, - GHC_SPEED_1000M = 0x00000030, + GHC_SPEED_10M = 0x00000010, + GHC_SPEED_100M = 0x00000020, + GHC_SPEED_1000M = 0x00000030, +}; + +enum jme_ghc_to_clk { + GHC_TO_CLK_OFF = 0x00000000, + GHC_TO_CLK_GPHY = 0x00400000, + GHC_TO_CLK_PCIE = 0x00800000, + GHC_TO_CLK_INVALID = 0x00C00000, +}; + +enum jme_ghc_txmac_clk { + GHC_TXMAC_CLK_OFF = 0x00000000, + GHC_TXMAC_CLK_GPHY = 0x00100000, + GHC_TXMAC_CLK_PCIE = 0x00200000, + GHC_TXMAC_CLK_INVALID = 0x00300000, }; /* @@ -963,6 +940,36 @@ enum jme_gpreg0_vals { GPREG0_PHYADDR_1, }; +/* + * General Purpose REG-1 + * Note: All theses bits defined here are for + * Chip mode revision 0x11 only + */ +enum jme_gpreg1_masks { + GPREG1_INTRDELAYUNIT = 0x00000018, + GPREG1_INTRDELAYENABLE = 0x00000007, +}; + +enum jme_gpreg1_vals { + GPREG1_RSSPATCH = 0x00000040, + GPREG1_HALFMODEPATCH = 0x00000020, + + GPREG1_INTDLYUNIT_16NS = 0x00000000, + GPREG1_INTDLYUNIT_256NS = 0x00000008, + GPREG1_INTDLYUNIT_1US = 0x00000010, + GPREG1_INTDLYUNIT_16US = 0x00000018, + + GPREG1_INTDLYEN_1U = 0x00000001, + GPREG1_INTDLYEN_2U = 0x00000002, + GPREG1_INTDLYEN_3U = 0x00000003, + GPREG1_INTDLYEN_4U = 0x00000004, + GPREG1_INTDLYEN_5U = 0x00000005, + GPREG1_INTDLYEN_6U = 0x00000006, + GPREG1_INTDLYEN_7U = 0x00000007, + + GPREG1_DEFAULT = 0x00000000, +}; + /* * Interrupt Status Bits */ @@ -1050,20 +1057,13 @@ enum jme_pcctx_bits { */ enum jme_chipmode_bit_masks { CM_FPGAVER_MASK = 0xFFFF0000, - CM_CHIPVER_MASK = 0x0000FF00, + CM_CHIPREV_MASK = 0x0000FF00, CM_CHIPMODE_MASK = 0x0000000F, }; enum jme_chipmode_shifts { CM_FPGAVER_SHIFT = 16, - CM_CHIPVER_SHIFT = 8, -}; - -/* - * Shadow base address register bits - */ -enum jme_shadow_base_address_bits { - SHBA_POSTEN = 0x1, + CM_CHIPREV_SHIFT = 8, }; /* @@ -1092,12 +1092,14 @@ static char *MAC_REG_NAME[] = { "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP", "JME_WFOI", "JME_SMI", "JME_GHC", "UNKNOWN", "UNKNOWN", "JME_PMCS"}; + static char *PE_REG_NAME[] = { "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "JME_PHY_CS", "UNKNOWN", "JME_PHY_LINK", "UNKNOWN", "UNKNOWN", "UNKNOWN", "JME_SMBCSR", "JME_SMBINTF"}; + static char *MISC_REG_NAME[] = { "JME_TMCSR", "JME_GPIO", "JME_GPREG0", "JME_GPREG1", "JME_IEVE", "JME_IREQ", "JME_IENS", "JME_IENC", @@ -1108,11 +1110,12 @@ static char *MISC_REG_NAME[] = { "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "JME_TIMER1", "JME_TIMER2", "UNKNOWN", "JME_APMC", "JME_PCCSRX0"}; + static inline void reg_dbg(const struct jme_adapter *jme, const char *msg, u32 val, u32 reg) { const char *regname; - switch(reg & 0xF00) { + switch (reg & 0xF00) { case 0x000: regname = MAC_REG_NAME[(reg & 0xFF) >> 2]; break; @@ -1120,7 +1123,7 @@ static inline void reg_dbg(const struct jme_adapter *jme, regname = PE_REG_NAME[(reg & 0xFF) >> 2]; break; case 0x800: - regname = MISC_REG_NAME[(reg & 0xFF) >>2]; + regname = MISC_REG_NAME[(reg & 0xFF) >> 2]; break; default: regname = PE_REG_NAME[0]; @@ -1178,6 +1181,14 @@ enum jme_phy_reg17_vals { #define BMSR_ANCOMP 0x0020 +/* + * Workaround + */ +static inline int is_buggy250(unsigned short device, unsigned int chiprev) +{ + return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11; +} + /* * Function prototypes */