X-Git-Url: http://bbs.cooldavid.org/git/?p=jme.git;a=blobdiff_plain;f=jme.h;h=944cf631438db978ff95c4e7e79d6ac28c392366;hp=2b12f0412891d8244f77d448dcd24a42551e6a51;hb=8d27293f4a6c7c2bfde177c16714956ba3764c96;hpb=fcf45b4ca68badd804155c5a14e4105bda8a7668 diff --git a/jme.h b/jme.h index 2b12f04..944cf63 100644 --- a/jme.h +++ b/jme.h @@ -24,12 +24,15 @@ #include #define DRV_NAME "jme" -#define DRV_VERSION "0.4" +#define DRV_VERSION "0.9d" #define PFX DRV_NAME ": " +#define JME_GE_DEVICE 0x250 +#define JME_FE_DEVICE 0x260 + #ifdef DEBUG #define dprintk(devname, fmt, args...) \ - printk(KERN_DEBUG PFX "%s: " fmt, devname, ## args) + printk(KERN_DEBUG "%s: " fmt, devname, ## args) #else #define dprintk(devname, fmt, args...) #endif @@ -46,13 +49,29 @@ #define rx_dbg(args...) #endif +#ifdef QUEUE_DEBUG +#define queue_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args) +#else +#define queue_dbg(args...) +#endif + +#ifdef CSUM_DEBUG +#define csum_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args) +#else +#define csum_dbg(args...) +#endif + +#ifdef VLAN_DEBUG +#define vlan_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args) +#else +#define vlan_dbg(args...) +#endif + #define jprintk(devname, fmt, args...) \ - printk(KERN_INFO PFX "%s: " fmt, devname, ## args) + printk(KERN_INFO "%s: " fmt, devname, ## args) #define jeprintk(devname, fmt, args...) \ - printk(KERN_ERR PFX "%s: " fmt, devname, ## args) - -#define USE_IEVE_SHADOW 0 + printk(KERN_ERR "%s: " fmt, devname, ## args) #define DEFAULT_MSG_ENABLE \ (NETIF_MSG_DRV | \ @@ -73,30 +92,40 @@ enum pci_conf_dcsr_mrrs_vals { MRRS_4096B = 0x50, }; +#define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216 +#define MIN_ETHERNET_PACKET_SIZE 60 + enum dynamic_pcc_values { + PCC_OFF = 0, PCC_P1 = 1, PCC_P2 = 2, PCC_P3 = 3, + PCC_OFF_TO = 0, PCC_P1_TO = 1, - PCC_P2_TO = 250, - PCC_P3_TO = 1000, + PCC_P2_TO = 64, + PCC_P3_TO = 128, + PCC_OFF_CNT = 0, PCC_P1_CNT = 1, - PCC_P2_CNT = 64, - PCC_P3_CNT = 255, + PCC_P2_CNT = 16, + PCC_P3_CNT = 32, }; struct dynpcc_info { - unsigned long check_point; unsigned long last_bytes; unsigned long last_pkts; + unsigned long intr_cnt; unsigned char cur; unsigned char attempt; unsigned char cnt; }; -#define PCC_INTERVAL (HZ / 10) -#define PCC_P3_THRESHOLD 3*1024*1024 -#define PCC_P2_THRESHOLD 1000 +#define PCC_INTERVAL_US 100000 +#define PCC_INTERVAL (HZ / (1000000/PCC_INTERVAL_US)) +#define PCC_P3_THRESHOLD 2*1024*1024 +#define PCC_P2_THRESHOLD 800 +#define PCC_INTR_THRESHOLD 800 +#define PCC_TX_TO 333 +#define PCC_TX_CNT 8 /* * TX/RX Descriptors @@ -104,13 +133,11 @@ struct dynpcc_info { * TX/RX Ring DESC Count Must be multiple of 16 * RX Ring DESC Count Must be <= 1024 */ -#define RING_DESC_NR 512 /* Must be power of 2 */ #define RING_DESC_ALIGN 16 /* Descriptor alignment */ #define TX_DESC_SIZE 16 #define TX_RING_NR 8 -#define TX_RING_ALLOC_SIZE (RING_DESC_NR * TX_DESC_SIZE) + TX_DESC_SIZE -#define TX_RING_SIZE (RING_DESC_NR * TX_DESC_SIZE) +#define TX_RING_ALLOC_SIZE(s) (s * TX_DESC_SIZE) + RING_DESC_ALIGN struct txdesc { union { @@ -149,9 +176,27 @@ struct txdesc { /* DW3 */ __u32 bufaddrl; } desc2; + struct { + /* DW0 */ + __u8 ehdrsz; + __u8 rsv1; + __u8 rsv2; + __u8 flags; + + /* DW1 */ + __u16 trycnt; + __u16 segcnt; + + /* DW2 */ + __u16 pktsz; + __u16 rsv3; + + /* DW3 */ + __u32 bufaddrl; + } descwb; }; }; -enum jme_txdesc_flag_bits { +enum jme_txdesc_flags_bits { TXFLAG_OWN = 0x80, TXFLAG_INT = 0x40, TXFLAG_64BIT = 0x20, @@ -161,23 +206,33 @@ enum jme_txdesc_flag_bits { TXFLAG_LSEN = 0x02, TXFLAG_TAGON = 0x01, }; +#define TXDESC_MSS_SHIFT 2 +enum jme_rxdescwb_flags_bits { + TXWBFLAG_OWN = 0x80, + TXWBFLAG_INT = 0x40, + TXWBFLAG_TMOUT = 0x20, + TXWBFLAG_TRYOUT = 0x10, + TXWBFLAG_COL = 0x08, + + TXWBFLAG_ALLERR = TXWBFLAG_TMOUT | + TXWBFLAG_TRYOUT | + TXWBFLAG_COL, +}; #define RX_DESC_SIZE 16 #define RX_RING_NR 4 -#define RX_RING_ALLOC_SIZE (RING_DESC_NR * RX_DESC_SIZE) + RX_DESC_SIZE -#define RX_RING_SIZE (RING_DESC_NR * RX_DESC_SIZE) +#define RX_RING_ALLOC_SIZE(s) (s * RX_DESC_SIZE) + RING_DESC_ALIGN #define RX_BUF_DMA_ALIGN 8 -//#define RX_BUF_SIZE 1600 -#define RX_BUF_SIZE 9200 -//#define RX_BUF_SIZE 4000 #define RX_PREPAD_SIZE 10 - -/* - * Will use mtu in the future - */ -#define RX_BUF_ALLOC_SIZE RX_BUF_SIZE + RX_BUF_DMA_ALIGN +#define ETH_CRC_LEN 2 +#define RX_VLANHDR_LEN 2 +#define RX_EXTRA_LEN (RX_PREPAD_SIZE + \ + ETH_HLEN + \ + ETH_CRC_LEN + \ + RX_VLANHDR_LEN + \ + RX_BUF_DMA_ALIGN) struct rxdesc { union { @@ -266,8 +321,10 @@ struct jme_buffer_info { dma_addr_t mapping; int len; int nr_desc; + unsigned long start_xmit; }; +#define MAX_RING_DESC_NR 1024 struct jme_ring { void* alloc; /* pointer to allocated memory */ volatile void* desc; /* pointer to ring memory */ @@ -275,12 +332,11 @@ struct jme_ring { dma_addr_t dma; /* phys address for ring dma */ /* Buffer information corresponding to each descriptor */ - struct jme_buffer_info bufinf[RING_DESC_NR]; + struct jme_buffer_info bufinf[MAX_RING_DESC_NR]; - u16 next_to_use; - u16 next_to_clean; - - u16 nr_free; + int next_to_use; + atomic_t next_to_clean; + atomic_t nr_free; }; #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21) @@ -294,6 +350,41 @@ struct jme_ring { #define DECLARE_NET_DEVICE_STATS #endif +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23) +#define DECLARE_NAPI_STRUCT +#define NETIF_NAPI_SET(dev, napis, pollfn, q) \ + dev->poll = pollfn; \ + dev->weight = q; +#define JME_NAPI_HOLDER(holder) struct net_device *holder +#define JME_NAPI_WEIGHT(w) int *w +#define JME_NAPI_WEIGHT_VAL(w) *w +#define JME_NAPI_WEIGHT_SET(w, r) *w = r +#define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev) +#define JME_NAPI_ENABLE(priv) netif_poll_enable(priv->dev); +#define JME_NAPI_DISABLE(priv) netif_poll_disable(priv->dev); +#define JME_RX_SCHEDULE_PREP(priv) \ + netif_rx_schedule_prep(priv->dev) +#define JME_RX_SCHEDULE(priv) \ + __netif_rx_schedule(priv->dev); +#else +#define DECLARE_NAPI_STRUCT struct napi_struct napi; +#define NETIF_NAPI_SET(dev, napis, pollfn, q) \ + netif_napi_add(dev, napis, pollfn, q); +#define JME_NAPI_HOLDER(holder) struct napi_struct *holder +#define JME_NAPI_WEIGHT(w) int w +#define JME_NAPI_WEIGHT_VAL(w) w +#define JME_NAPI_WEIGHT_SET(w, r) +#define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev, napis) +#define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi); +#define JME_NAPI_DISABLE(priv) \ + if(!napi_disable_pending(&priv->napi)) \ + napi_disable(&priv->napi); +#define JME_RX_SCHEDULE_PREP(priv) \ + netif_rx_schedule_prep(priv->dev, &priv->napi) +#define JME_RX_SCHEDULE(priv) \ + __netif_rx_schedule(priv->dev, &priv->napi); +#endif + /* * Jmac Adapter Private data */ @@ -307,29 +398,77 @@ struct jme_adapter { struct mii_if_info mii_if; struct jme_ring rxring[RX_RING_NR]; struct jme_ring txring[TX_RING_NR]; - spinlock_t tx_lock; spinlock_t phy_lock; spinlock_t macaddr_lock; + spinlock_t rxmcs_lock; struct tasklet_struct rxempty_task; struct tasklet_struct rxclean_task; struct tasklet_struct txclean_task; struct tasklet_struct linkch_task; + struct tasklet_struct pcc_task; + __u32 flags; __u32 reg_txcs; + __u32 reg_txpfc; + __u32 reg_rxcs; __u32 reg_rxmcs; __u32 reg_ghc; + __u32 reg_pmcs; __u32 phylink; + __u32 tx_ring_size; + __u32 tx_ring_mask; + __u32 tx_wake_threshold; + __u32 rx_ring_size; + __u32 rx_ring_mask; __u8 mrrs; + __u32 fpgaver; + __u32 chipver; + struct ethtool_cmd old_ecmd; + unsigned int old_mtu; + struct vlan_group* vlgrp; struct dynpcc_info dpi; atomic_t intr_sem; atomic_t link_changing; atomic_t tx_cleaning; atomic_t rx_cleaning; + atomic_t rx_empty; + int (*jme_rx)(struct sk_buff *skb); + int (*jme_vlan_rx)(struct sk_buff *skb, + struct vlan_group *grp, + unsigned short vlan_tag); + DECLARE_NAPI_STRUCT DECLARE_NET_DEVICE_STATS }; enum shadow_reg_val { SHADOW_IEVE = 0, }; +enum jme_flags_bits { + JME_FLAG_MSI = 0x00000001, + JME_FLAG_SSET = 0x00000002, + JME_FLAG_TXCSUM = 0x00000004, + JME_FLAG_TSO = 0x00000008, + JME_FLAG_POLL = 0x00000010, +}; #define WAIT_TASKLET_TIMEOUT 500 /* 500 ms */ +#define TX_TIMEOUT (5*HZ) +#define JME_REG_LEN 0x500 + +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23) +__always_inline static struct jme_adapter* +jme_napi_priv(struct net_device *holder) +{ + struct jme_adapter* jme; + jme = netdev_priv(holder); + return jme; +} +#else +__always_inline static struct jme_adapter* +jme_napi_priv(struct napi_struct *napi) +{ + struct jme_adapter* jme; + jme = container_of(napi, struct jme_adapter, napi); + return jme; +} +#endif /* * MMaped I/O Resters @@ -341,6 +480,13 @@ enum jme_iomap_offsets { JME_RSS = 0x0C00, }; +enum jme_iomap_lens { + JME_MAC_LEN = 0x80, + JME_PHY_LEN = 0x58, + JME_MISC_LEN = 0x98, + JME_RSS_LEN = 0xFF, +}; + enum jme_iomap_regs { JME_TXCS = JME_MAC | 0x00, /* Transmit Control and Status */ JME_TXDBA_LO = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */ @@ -372,8 +518,10 @@ enum jme_iomap_regs { JME_PHY_CS = JME_PHY | 0x28, /* PHY Ctrl and Status Register */ JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */ JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */ + JME_SMBINTF = JME_PHY | 0x44, /* SMB Interface */ + JME_TMCSR = JME_MISC| 0x00, /* Timer Control/Status Register */ JME_GPREG0 = JME_MISC| 0x08, /* General purpose REG-0 */ JME_GPREG1 = JME_MISC| 0x0C, /* General purpose REG-1 */ JME_IEVE = JME_MISC| 0x20, /* Interrupt Event Status */ @@ -382,6 +530,7 @@ enum jme_iomap_regs { JME_IENC = JME_MISC| 0x2C, /* Interrupt Enable - Clear Port */ JME_PCCRX0 = JME_MISC| 0x30, /* PCC Control for RX Queue 0 */ JME_PCCTX = JME_MISC| 0x40, /* PCC Control for TX Queues */ + JME_CHIPMODE = JME_MISC| 0x44, /* Identify FPGA Version */ JME_SHBA_HI = JME_MISC| 0x48, /* Shadow Register Base HI */ JME_SHBA_LO = JME_MISC| 0x4C, /* Shadow Register Base LO */ JME_PCCSRX0 = JME_MISC| 0x80, /* PCC Status of RX0 */ @@ -427,7 +576,7 @@ enum jme_txcs_value { TXCS_DEFAULT = TXCS_FIFOTH_4QW | TXCS_BURST, }; -#define JME_TX_DISABLE_TIMEOUT 100 /* 100 msec */ +#define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */ /* * TX MAC Control/Status Bits @@ -469,6 +618,23 @@ enum jme_txmcs_values { TXMCS_PADDING, }; +enum jme_txpfc_bits_masks { + TXPFC_VLAN_TAG = 0xFFFF0000, + TXPFC_VLAN_EN = 0x00008000, + TXPFC_PF_EN = 0x00000001, +}; + +enum jme_txtrhd_bits_masks { + TXTRHD_TXPEN = 0x80000000, + TXTRHD_TXP = 0x7FFFFF00, + TXTRHD_TXREN = 0x00000080, + TXTRHD_TXRL = 0x0000007F, +}; +enum jme_txtrhd_shifts { + TXTRHD_TXP_SHIFT = 8, + TXTRHD_TXRL_SHIFT = 0, +}; + /* * RX Control/Status Bits @@ -543,7 +709,7 @@ enum jme_rxcs_values { RXCS_RETRYGAP_256ns | RXCS_RETRYCNT_32, }; -#define JME_RX_DISABLE_TIMEOUT 100 /* 100 msec */ +#define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */ /* * RX MAC Control/Status Bits @@ -560,6 +726,25 @@ enum jme_rxmcs_bits { RXMCS_VTAGRM = 0x00000004, RXMCS_PREPAD = 0x00000002, RXMCS_CHECKSUM = 0x00000001, + + RXMCS_DEFAULT = RXMCS_VTAGRM | + RXMCS_PREPAD | + RXMCS_FLOWCTRL | + RXMCS_CHECKSUM, +}; + +/* + * Wakeup Frame setup interface registers + */ +#define WAKEUP_FRAME_NR 8 +#define WAKEUP_FRAME_MASK_DWNR 4 +enum jme_wfoi_bit_masks { + WFOI_MASK_SEL = 0x00000070, + WFOI_CRC_SEL = 0x00000008, + WFOI_FRAME_SEL = 0x00000007, +}; +enum jme_wfoi_shifts { + WFOI_MASK_SHIFT = 4, }; /* @@ -592,7 +777,8 @@ __always_inline __u32 smi_phy_addr(int x) { return (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK); } -#define JME_PHY_TIMEOUT 1000 /* 1000 usec */ +#define JME_PHY_TIMEOUT 100 /* 100 msec */ +#define JME_PHY_REG_NR 32 /* * Global Host Control @@ -609,6 +795,34 @@ enum jme_ghc_speed_val { GHC_SPEED_1000M = 0x00000030, }; +/* + * Power management control and status register + */ +enum jme_pmcs_bit_masks { + PMCS_WF7DET = 0x80000000, + PMCS_WF6DET = 0x40000000, + PMCS_WF5DET = 0x20000000, + PMCS_WF4DET = 0x10000000, + PMCS_WF3DET = 0x08000000, + PMCS_WF2DET = 0x04000000, + PMCS_WF1DET = 0x02000000, + PMCS_WF0DET = 0x01000000, + PMCS_LFDET = 0x00040000, + PMCS_LRDET = 0x00020000, + PMCS_MFDET = 0x00010000, + PMCS_WF7EN = 0x00008000, + PMCS_WF6EN = 0x00004000, + PMCS_WF5EN = 0x00002000, + PMCS_WF4EN = 0x00001000, + PMCS_WF3EN = 0x00000800, + PMCS_WF2EN = 0x00000400, + PMCS_WF1EN = 0x00000200, + PMCS_WF0EN = 0x00000100, + PMCS_LFEN = 0x00000004, + PMCS_LREN = 0x00000002, + PMCS_MFEN = 0x00000001, +}; + /* * Giga PHY Status Registers */ @@ -630,13 +844,46 @@ enum jme_phy_link_speed_val { /* * SMB Control and Status */ -enum jme_smbcsr_bit_mask -{ +enum jme_smbcsr_bit_mask { SMBCSR_CNACK = 0x00020000, SMBCSR_RELOAD = 0x00010000, SMBCSR_EEPROMD = 0x00000020, + SMBCSR_INITDONE = 0x00000010, + SMBCSR_BUSY = 0x0000000F, +}; +enum jme_smbintf_bit_mask { + SMBINTF_HWDATR = 0xFF000000, + SMBINTF_HWDATW = 0x00FF0000, + SMBINTF_HWADDR = 0x0000FF00, + SMBINTF_HWRWN = 0x00000020, + SMBINTF_HWCMD = 0x00000010, + SMBINTF_FASTM = 0x00000008, + SMBINTF_GPIOSCL = 0x00000004, + SMBINTF_GPIOSDA = 0x00000002, + SMBINTF_GPIOEN = 0x00000001, +}; +enum jme_smbintf_vals { + SMBINTF_HWRWN_READ = 0x00000020, + SMBINTF_HWRWN_WRITE = 0x00000000, +}; +enum jme_smbintf_shifts { + SMBINTF_HWDATR_SHIFT = 24, + SMBINTF_HWDATW_SHIFT = 16, + SMBINTF_HWADDR_SHIFT = 8, +}; +#define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */ +#define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */ +#define JME_SMB_LEN 256 +#define JME_EEPROM_MAGIC 0x250 + +/* + * Timer Control/Status Register + */ +enum jme_tmcsr_bit_masks { + TMCSR_SWIT = 0x80000000, + TMCSR_EN = 0x01000000, + TMCSR_CNT = 0x00FFFFFF, }; -#define JME_SMB_TIMEOUT 10 /* 10 msec */ /* @@ -646,6 +893,7 @@ enum jme_gpreg0_masks { GPREG0_DISSH = 0xFF000000, GPREG0_PCIRLMT = 0x00300000, GPREG0_PCCNOMUTCLR = 0x00040000, + GPREG0_LNKINTPOLL = 0x00001000, GPREG0_PCCTMR = 0x00000300, GPREG0_PHYADDR = 0x0000001F, }; @@ -716,12 +964,14 @@ enum jme_interrupt_bits INTR_TX1 = 0x00000002, INTR_TX0 = 0x00000001, }; -static const __u32 INTR_ENABLE = INTR_LINKCH | - INTR_RX0EMP | +static const __u32 INTR_ENABLE = INTR_SWINTR | + INTR_TMINTR | + INTR_LINKCH | INTR_PCCRX0TO | INTR_PCCRX0 | INTR_PCCTXTO | - INTR_PCCTX; + INTR_PCCTX | + INTR_RX0EMP; /* * PCC Control Registers @@ -754,6 +1004,18 @@ enum jme_pcctx_bits { PCCTXQ7_EN = 0x00000080, }; +/* + * Chip Mode Register + */ +enum jme_chipmode_bit_masks { + CM_FPGAVER_MASK = 0xFFFF0000, + CM_CHIPVER_MASK = 0x0000FF00, + CM_CHIPMODE_MASK = 0x0000000F, +}; +enum jme_chipmode_shifts { + CM_FPGAVER_SHIFT = 16, + CM_CHIPVER_SHIFT = 8, +}; /* * Shadow base address register bits @@ -767,21 +1029,38 @@ enum jme_shadow_base_address_bits { */ __always_inline __u32 jread32(struct jme_adapter *jme, __u32 reg) { - return le32_to_cpu(readl(jme->regs + reg)); + return le32_to_cpu(readl((__u8*)jme->regs + reg)); } __always_inline void jwrite32(struct jme_adapter *jme, __u32 reg, __u32 val) { - writel(cpu_to_le32(val), jme->regs + reg); + writel(cpu_to_le32(val), (__u8*)jme->regs + reg); } __always_inline void jwrite32f(struct jme_adapter *jme, __u32 reg, __u32 val) { /* * Read after write should cause flush */ - writel(cpu_to_le32(val), jme->regs + reg); - readl(jme->regs + reg); + writel(cpu_to_le32(val), (__u8*)jme->regs + reg); + readl((__u8*)jme->regs + reg); } +/* + * PHY Regs + */ +enum jme_phy_reg17_bit_masks { + PREG17_SPEED = 0xC000, + PREG17_DUPLEX = 0x2000, + PREG17_SPDRSV = 0x0800, + PREG17_LNKUP = 0x0400, + PREG17_MDI = 0x0040, +}; +enum jme_phy_reg17_vals { + PREG17_SPEED_10M = 0x0000, + PREG17_SPEED_100M = 0x4000, + PREG17_SPEED_1000M = 0x8000, +}; +#define BMSR_ANCOMP 0x0020 + /* * Function prototypes for ethtool */ @@ -803,4 +1082,3 @@ static int jme_start_xmit(struct sk_buff *skb, struct net_device *netdev); static int jme_set_macaddr(struct net_device *netdev, void *p); static void jme_set_multi(struct net_device *netdev); -