fixv6sum

[jme.git] / jme.h

diff --git a/jme.h b/jme.h
index 2ea31868e66fdb05f0b0e3eb3ac65ed0689a0d05..fff5d6b076860f03cd84473803efacebc4d4d6d1 100644 (file)
--- a/jme.h
+++ b/jme.h
@@ -26,7 +26,7 @@
 #define __JME_H_INCLUDED__
 
 #define DRV_NAME       "jme"
-#define DRV_VERSION    "1.0.7-jmmod"
+#define DRV_VERSION    "1.0.8-jmmod"
 #define PFX            DRV_NAME ": "
 
 #define PCI_DEVICE_ID_JMICRON_JMC250   0x0250
@@ -555,6 +555,7 @@ struct jme_adapter {
        u32                     reg_rxmcs;
        u32                     reg_ghc;
        u32                     reg_pmcs;
+       u32                     reg_gpreg1;
        u32                     phylink;
        u32                     tx_ring_size;
        u32                     tx_ring_mask;
@@ -637,7 +638,7 @@ enum jme_iomap_offsets {
 
 enum jme_iomap_lens {
        JME_MAC_LEN     = 0x80,
-       JME_PHY_LEN     = 0x58,
+       JME_PHY_LEN     = 0x70,
        JME_MISC_LEN    = 0x98,
        JME_RSS_LEN     = 0xFF,
 };
@@ -675,7 +676,7 @@ enum jme_iomap_regs {
        JME_PHY_LINK    = JME_PHY | 0x30, /* PHY Link Status Register */
        JME_SMBCSR      = JME_PHY | 0x40, /* SMB Control and Status */
        JME_SMBINTF     = JME_PHY | 0x44, /* SMB Interface */
-
+       JME_EXGP2       = JME_PHY | 0x60, /* General Purpose */                 //Aries undo
 
        JME_TMCSR       = JME_MISC | 0x00, /* Timer Control/Status Register */
        JME_GPREG0      = JME_MISC | 0x08, /* General purpose REG-0 */
@@ -798,6 +799,14 @@ enum jme_txtrhd_shifts {
        TXTRHD_TXRL_SHIFT       = 0,
 };
 
+enum jme_txtrhd_values {
+       TXTRHD_FULLDUPLEX       = 0x00000000,
+       TXTRHD_HALFDUPLEX       = TXTRHD_TXPEN |
+                                 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
+                                 TXTRHD_TXREN |
+                                 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL),
+};
+
 /*
  * RX Control/Status Bits
  */
@@ -934,6 +943,10 @@ enum jme_smi_bit_shift {
        SMI_REG_ADDR_SHIFT      = 11,
        SMI_PHY_ADDR_SHIFT      = 6,
 };
+//Aries undo
+enum jme_phy_GeneralPurpose_bit {
+       FIX_IPV6_CHECKSUM               = 0x40000000,
+};
 
 static inline u32 smi_reg_addr(int x)
 {
@@ -953,6 +966,8 @@ static inline u32 smi_phy_addr(int x)
  */
 enum jme_ghc_bit_mask {
        GHC_SWRST               = 0x40000000,
+       GHC_TO_CLK_SRC          = 0x00C00000,
+       GHC_TXMAC_CLK_SRC       = 0x00300000,
        GHC_DPX                 = 0x00000040,
        GHC_SPEED               = 0x00000030,
        GHC_LINK_POLL           = 0x00000001,
@@ -1131,18 +1146,17 @@ enum jme_gpreg0_vals {
 
 /*
  * General Purpose REG-1
- * Note: All theses bits defined here are for
- *       Chip mode revision 0x11 only
  */
-enum jme_gpreg1_masks {
+enum jme_gpreg1_bit_masks {
+       GPREG1_RXCLKOFF         = 0x04000000,
+       GPREG1_PCREQN           = 0x00020000,
+       GPREG1_HALFMODEPATCH    = 0x00000040, /* For Chip revision 0x11 only */
+       GPREG1_RSSPATCH         = 0x00000020, /* For Chip revision 0x11 only */
        GPREG1_INTRDELAYUNIT    = 0x00000018,
        GPREG1_INTRDELAYENABLE  = 0x00000007,
 };
 
 enum jme_gpreg1_vals {
-       GPREG1_HALFMODEPATCH    = 0x00000040,
-       GPREG1_RSSPATCH         = 0x00000020,
-
        GPREG1_INTDLYUNIT_16NS  = 0x00000000,
        GPREG1_INTDLYUNIT_256NS = 0x00000008,
        GPREG1_INTDLYUNIT_1US   = 0x00000010,
@@ -1156,7 +1170,7 @@ enum jme_gpreg1_vals {
        GPREG1_INTDLYEN_6U      = 0x00000006,
        GPREG1_INTDLYEN_7U      = 0x00000007,
 
-       GPREG1_DEFAULT          = 0x00000000,
+       GPREG1_DEFAULT          = GPREG1_PCREQN,
 };
 
 /*
@@ -1388,6 +1402,7 @@ static inline int new_phy_power_ctrl(u8 chip_main_rev)
  */
 static int jme_set_settings(struct net_device *netdev,
                                struct ethtool_cmd *ecmd);
+static void jme_set_unicastaddr(struct net_device *netdev);
 static void jme_set_multi(struct net_device *netdev);
 
 #endif