AudoSpeedDown

[jme.git] / jme.h

diff --git a/jme.h b/jme.h
index 1f65208758c90a12150f53aabf56f20301324e73..1fabbce4d33f5b816d12aac305a91ec200f74e16 100644 (file)
--- a/jme.h
+++ b/jme.h
@@ -582,6 +582,13 @@ struct jme_adapter {
        int                     (*jme_vlan_rx)(struct sk_buff *skb,
                                          struct vlan_group *grp,
                                          unsigned short vlan_tag);
+
+       u8                                              flag_run_asd;                                           /*      Is Auto Speed Down polling function running*/
+       u32                                             mc_count;                                                       /*      second counter as RJ45 is attached      */
+       u8                                              flag_media_connected;                           /*      Because PHY 0x13 is read and clear, we need to record it */
+       struct timer_list               asd_timer;
+               
+               
        DECLARE_NAPI_STRUCT
        DECLARE_NET_DEVICE_STATS
 };
@@ -605,7 +612,7 @@ enum jme_flags_bits {
 };
 
 #define TX_TIMEOUT             (5 * HZ)
-#define JME_REG_LEN            0x600
+#define JME_REG_LEN            0x500
 #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
 
 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
@@ -956,7 +963,6 @@ static inline u32 smi_phy_addr(int x)
 
 #define JME_PHY_TIMEOUT 100 /* 100 msec */
 #define JME_PHY_REG_NR 32
-#define JME_PHY_SPEC_REG_NR 128
 
 /*
  * Global Host Control
@@ -1032,6 +1038,13 @@ enum jme_phy_pwr_bit_masks {
                                       * 1: xtl_out = phy_giga.PD_OSC
                                       */
 };
+/*
+ * False carrier Counter
+ */
+ enum jme_phy_an_status {
+       PHY_SPEC_STATUS_AN_COMPLETE             = 0x00000800,
+       PHY_SPEC_STATUS_AN_FAIL                 = 0x00008000,
+};
 
 /*
  * Giga PHY Status Registers
@@ -1379,37 +1392,8 @@ enum jme_phy_reg17_vals {
        PREG17_SPEED_1000M      = 0x8000,
 };
 
-enum jme_phy_gctrl_masks {
-       JME_PHY_GCTRL_TESTMASK  = 0xA000,
-};
-
-enum jme_phy_gctrl_vals {
-       JME_PHY_GCTRL_TESTOFF   = 0x0000,
-       JME_PHY_GCTRL_TESTMODE1 = 0x2000,
-       JME_PHY_GCTRL_TESTMODE2 = 0x4000,
-       JME_PHY_GCTRL_TESTMODE3 = 0x6000,
-       JME_PHY_GCTRL_TESTMODE4 = 0x8000,
-};
-
 #define BMSR_ANCOMP               0x0020
 
-/*
- * For extended PHY register interface
- */
-enum jme_phy_spec_regs {
-       JME_PHY_SPEC_ADDR_REG   = 0x1E,
-       JME_PHY_SPEC_DATA_REG   = 0x1F,
-};
-enum jme_phy_spec_addr_bits {
-       JME_PHY_SPEC_REG_READ   = 0x4000u,
-       JME_PHY_SPEC_REG_WRITE  = 0x8000u,
-};
-enum jme_extphy_regs {
-       JME_PHYEXT_COMM0        = 0x30,
-       JME_PHYEXT_COMM1        = 0x31,
-       JME_PHYEXT_COMM2        = 0x32,
-};
-
 /*
  * Workaround
  */