pr_err("phy(%d) write timeout : %d\n", phy, reg);
}
+static int
+jme_phyext_read(struct jme_adapter *jme, int reg)
+{
+ jme_mdio_write(jme->dev, jme->mii_if.phy_id,
+ JME_PHY_SPEC_ADDR_REG,
+ JME_PHY_SPEC_REG_READ | (reg & 0x3FFF));
+ return jme_mdio_read(jme->dev, jme->mii_if.phy_id,
+ JME_PHY_SPEC_DATA_REG);
+}
+
+static void
+jme_phyext_write(struct jme_adapter *jme, int reg, int val)
+{
+ jme_mdio_write(jme->dev, jme->mii_if.phy_id,
+ JME_PHY_SPEC_DATA_REG, val);
+ jme_mdio_write(jme->dev, jme->mii_if.phy_id,
+ JME_PHY_SPEC_ADDR_REG,
+ JME_PHY_SPEC_REG_WRITE | (reg & 0x3FFF));
+}
+
+static void
+jme_phyext_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
+{
+ int i;
+ u16 *p16 = (u16 *)p;
+
+ for (i = 0; i < reg_nr; ++i)
+ p16[i] = jme_phyext_read(jme, i);
+}
+
static inline void
jme_reset_phy_processor(struct jme_adapter *jme)
{
pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
}
+static inline void
+jme_recal_phy(struct jme_adapter *jme)
+{
+ u32 miictl1000, comm2;
+
+ miictl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000);
+ miictl1000 &= ~JME_PHY_GCTRL_TESTMASK;
+ miictl1000 |= JME_PHY_GCTRL_TESTMODE1;
+ jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, miictl1000);
+
+ comm2 = jme_phyext_read(jme, JME_PHYEXT_COMM2);
+ comm2 &= ~(0x0001u);
+ comm2 |= 0x0011u;
+ jme_phyext_write(jme, JME_PHYEXT_COMM2, comm2);
+
+ mdelay(20);
+
+ comm2 = jme_phyext_read(jme, JME_PHYEXT_COMM2);
+ comm2 &= ~(0x0013u);
+ jme_phyext_write(jme, JME_PHYEXT_COMM2, comm2);
+
+ miictl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000);
+ miictl1000 &= ~JME_PHY_GCTRL_TESTMASK;
+ jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, miictl1000);
+}
+
+static inline void
+jme_refill_phyparm(struct jme_adapter *jme)
+{
+ if (jme->chip_main_rev >= 6 ||
+ (jme->chip_main_rev == 5 &&
+ (jme->chip_sub_rev == 0 ||
+ jme->chip_sub_rev == 1 ||
+ jme->chip_sub_rev == 3))) {
+ jme_phyext_write(jme, JME_PHYEXT_COMM0, 0x008Au);
+ jme_phyext_write(jme, JME_PHYEXT_COMM1, 0x4109u);
+ } else if (jme->chip_main_rev == 3 &&
+ (jme->chip_sub_rev == 1 ||
+ jme->chip_sub_rev == 2)) {
+ jme_phyext_write(jme, JME_PHYEXT_COMM0, 0xE088u);
+// jme_phyext_write(jme, JME_PHYEXT_COMM1, 0x4108u);
+ } else if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260 &&
+ jme->chip_main_rev == 2) {
+ if (jme->chip_sub_rev == 0) {
+ jme_phyext_write(jme, JME_PHYEXT_COMM0, 0x608Au);
+// jme_phyext_write(jme, JME_PHYEXT_COMM1, 0x4108u);
+ } else if (jme->chip_sub_rev == 2) {
+ jme_phyext_write(jme, JME_PHYEXT_COMM0, 0x408Au);
+// jme_phyext_write(jme, JME_PHYEXT_COMM1, 0x4108u);
+ }
+ }
+}
+
static inline void
jme_phy_on(struct jme_adapter *jme)
{
u32 bmcr;
+ if (new_phy_power_ctrl(jme->chip_main_rev))
+ jme_new_phy_on(jme);
+
bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
bmcr &= ~BMCR_PDOWN;
jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
- if (new_phy_power_ctrl(jme->chip_main_rev))
- jme_new_phy_on(jme);
+ jme_recal_phy(jme);
+ jme_refill_phyparm(jme);
}
static inline void
p32 += 0x100 >> 2;
mdio_memcpy(jme, p32, JME_PHY_REG_NR);
+
+ p32 += 0x100 >> 2;
+ jme_phyext_memcpy(jme, p32, JME_PHY_SPEC_REG_NR);
}
static int