+static inline void
+jme_new_phy_on(struct jme_adapter *jme)
+{
+ u32 reg;
+
+ reg = jread32(jme, JME_PHY_PWR);
+ reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
+ PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
+ jwrite32(jme, JME_PHY_PWR, reg);
+
+ pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, ®);
+ reg &= ~PE1_GPREG0_PBG;
+ reg |= PE1_GPREG0_ENBG;
+ pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
+}
+
+static inline void
+jme_new_phy_off(struct jme_adapter *jme)
+{
+ u32 reg;
+
+ reg = jread32(jme, JME_PHY_PWR);
+ reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
+ PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
+ jwrite32(jme, JME_PHY_PWR, reg);
+
+ pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, ®);
+ reg &= ~PE1_GPREG0_PBG;
+ reg |= PE1_GPREG0_PDD3COLD;
+ pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
+}
+
+static inline void
+jme_recal_phy(struct jme_adapter *jme)
+{
+ u32 miictl1000, comm2;
+
+ miictl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000);
+ miictl1000 &= ~JME_PHY_GCTRL_TESTMASK;
+ miictl1000 |= JME_PHY_GCTRL_TESTMODE1;
+ jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, miictl1000);
+
+ comm2 = jme_phyext_read(jme, JME_PHYEXT_COMM2);
+ comm2 &= ~(0x0001u);
+ comm2 |= 0x0011u;
+ jme_phyext_write(jme, JME_PHYEXT_COMM2, comm2);
+
+ mdelay(20);
+
+ comm2 = jme_phyext_read(jme, JME_PHYEXT_COMM2);
+ comm2 &= ~(0x0013u);
+ jme_phyext_write(jme, JME_PHYEXT_COMM2, comm2);
+
+ miictl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000);
+ miictl1000 &= ~JME_PHY_GCTRL_TESTMASK;
+ jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, miictl1000);
+}
+
+static inline void
+jme_refill_phyparm(struct jme_adapter *jme)
+{
+ if (jme->chip_main_rev >= 6 ||
+ (jme->chip_main_rev == 5 &&
+ (jme->chip_sub_rev == 0 ||
+ jme->chip_sub_rev == 1 ||
+ jme->chip_sub_rev == 3))) {
+ jme_phyext_write(jme, JME_PHYEXT_COMM0, 0x008Au);
+ jme_phyext_write(jme, JME_PHYEXT_COMM1, 0x4109u);
+ } else if (jme->chip_main_rev == 3 &&
+ (jme->chip_sub_rev == 1 ||
+ jme->chip_sub_rev == 2)) {
+ jme_phyext_write(jme, JME_PHYEXT_COMM0, 0xE088u);
+// jme_phyext_write(jme, JME_PHYEXT_COMM1, 0x4108u);
+ } else if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260 &&
+ jme->chip_main_rev == 2) {
+ if (jme->chip_sub_rev == 0) {
+ jme_phyext_write(jme, JME_PHYEXT_COMM0, 0x608Au);
+// jme_phyext_write(jme, JME_PHYEXT_COMM1, 0x4108u);
+ } else if (jme->chip_sub_rev == 2) {
+ jme_phyext_write(jme, JME_PHYEXT_COMM0, 0x408Au);
+// jme_phyext_write(jme, JME_PHYEXT_COMM1, 0x4108u);
+ }
+ }
+}
+
+static inline void
+jme_phy_on(struct jme_adapter *jme)
+{
+ u32 bmcr;
+
+ if (new_phy_power_ctrl(jme->chip_main_rev))
+ jme_new_phy_on(jme);
+
+ bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
+ bmcr &= ~BMCR_PDOWN;
+ jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
+
+ jme_recal_phy(jme);
+ jme_refill_phyparm(jme);
+}
+
+static inline void
+jme_phy_off(struct jme_adapter *jme)
+{
+ u32 bmcr;
+
+ bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
+ bmcr |= BMCR_PDOWN;
+ jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
+
+ if (new_phy_power_ctrl(jme->chip_main_rev))
+ jme_new_phy_off(jme);
+}
+