else
gpreg0 = GPREG0_DEFAULT;
jwrite32(jme, JME_GPREG0, gpreg0);
- jwrite32(jme, JME_GPREG1, 0);
+ jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
}
static inline void
}
static inline void
-jme_set_gmii(struct jme_adapter *jme)
+jme_set_phyfifoa(struct jme_adapter *jme)
{
jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
}
static inline void
-jme_set_rgmii(struct jme_adapter *jme)
+jme_set_phyfifob(struct jme_adapter *jme)
{
jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
}
jme_check_link(struct net_device *netdev, int testonly)
{
struct jme_adapter *jme = netdev_priv(netdev);
- u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr;
+ u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
char linkmsg[64];
int rc = 0;
case PHY_LINK_SPEED_10M:
ghc |= GHC_SPEED_10M;
strcat(linkmsg, "10 Mbps, ");
- if (jme->rev == 0x11)
- jme_set_gmii(jme);
break;
case PHY_LINK_SPEED_100M:
ghc |= GHC_SPEED_100M;
strcat(linkmsg, "100 Mbps, ");
- if (jme->rev == 0x11)
- jme_set_rgmii(jme);
break;
case PHY_LINK_SPEED_1000M:
ghc |= GHC_SPEED_1000M;
strcat(linkmsg, "1000 Mbps, ");
- if (jme->rev == 0x11)
- jme_set_gmii(jme);
break;
default:
break;
}
- ghc |= (phylink & PHY_LINK_DUPLEX) ? GHC_DPX : 0;
-
- strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
- "Full-Duplex, " :
- "Half-Duplex, ");
-
- if (phylink & PHY_LINK_MDI_STAT)
- strcat(linkmsg, "MDI-X");
- else
- strcat(linkmsg, "MDI");
if (phylink & PHY_LINK_DUPLEX) {
jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
+ ghc |= GHC_DPX;
} else {
jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
TXMCS_BACKOFF |
TXTRHD_TXREN |
((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
}
+ strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
+ "Full-Duplex, " :
+ "Half-Duplex, ");
+
+ if (phylink & PHY_LINK_MDI_STAT)
+ strcat(linkmsg, "MDI-X");
+ else
+ strcat(linkmsg, "MDI");
+
+ gpreg1 = GPREG1_DEFAULT;
+ if (is_buggy250(jme->pdev->device, jme->chiprev)) {
+ if (!(phylink & PHY_LINK_DUPLEX))
+ gpreg1 |= GPREG1_HALFMODEPATCH;
+ switch (phylink & PHY_LINK_SPEED_MASK) {
+ case PHY_LINK_SPEED_10M:
+ jme_set_phyfifoa(jme);
+ gpreg1 |= GPREG1_RSSPATCH;
+ break;
+ case PHY_LINK_SPEED_100M:
+ jme_set_phyfifob(jme);
+ gpreg1 |= GPREG1_RSSPATCH;
+ break;
+ case PHY_LINK_SPEED_1000M:
+ jme_set_phyfifoa(jme);
+ break;
+ default:
+ break;
+ }
+ }
+ jwrite32(jme, JME_GPREG1, gpreg1);
jme->reg_ghc = ghc;
jwrite32(jme, JME_GHC, ghc);
while (!atomic_dec_and_test(&jme->link_changing)) {
atomic_inc(&jme->link_changing);
msg_intr(jme, "Get link change lock failed.\n");
- while(atomic_read(&jme->link_changing) != 1)
+ while (atomic_read(&jme->link_changing) != 1)
msg_intr(jme, "Waiting link change lock.\n");
}
/*
* Check if it's really an interrupt for us
*/
- if (unlikely(intrstat == 0))
+ if (unlikely((intrstat & INTR_ENABLE) == 0))
return IRQ_NONE;
/*
return rc;
}
+#ifdef CONFIG_PM
static void
jme_set_100m_half(struct jme_adapter *jme)
{
phylink = jme_linkstat_from_phy(jme);
}
}
+#endif
static inline void
jme_phy_off(struct jme_adapter *jme)
chipmode = jread32(jme, JME_CHIPMODE);
jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
- jme->chipver = (chipmode & CM_CHIPVER_MASK) >> CM_CHIPVER_SHIFT;
+ jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
}
static int __devinit
jme->mii_if.mdio_write = jme_mdio_write;
jme_clear_pm(jme);
- jme_set_gmii(jme);
+ jme_set_phyfifoa(jme);
pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev);
if (!jme->fpgaver)
jme_phy_init(jme);
}
msg_probe(jme,
- "JMC250 gigabit%s ver:%u rev:%1x.%1x "
+ "JMC250 gigabit%s ver:%x rev:%x "
"macaddr:%02x:%02x:%02x:%02x:%02x:%02x\n",
(jme->fpgaver != 0) ? " (FPGA)" : "",
- (jme->fpgaver != 0) ? jme->fpgaver : jme->chipver,
- jme->rev & 0xf, (jme->rev >> 4) & 0xf,
+ (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
+ jme->rev,
netdev->dev_addr[0],
netdev->dev_addr[1],
netdev->dev_addr[2],
}
+#ifdef CONFIG_PM
static int
jme_suspend(struct pci_dev *pdev, pm_message_t state)
{
return 0;
}
+#endif
static struct pci_device_id jme_pci_tbl[] = {
{ PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },