jme.h

   1 /*
   2  * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
   3  *
   4  * Copyright 2008 JMicron Technology Corporation
   5  * http://www.jmicron.com/
   6  * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
   7  *
   8  * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22  *
  23  */
  24
  25 #ifndef __JME_H_INCLUDED__
  26 #define __JME_H_INCLUDED__
  27
  28 #define DRV_NAME        "jme"
  29 #define DRV_VERSION     "1.0.7-jmmod"
  30 #define PFX             DRV_NAME ": "
  31
  32 #define PCI_DEVICE_ID_JMICRON_JMC250    0x0250
  33 #define PCI_DEVICE_ID_JMICRON_JMC260    0x0260
  34
  35 /*
  36  * Message related definitions
  37  */
  38 #define JME_DEF_MSG_ENABLE \
  39         (NETIF_MSG_PROBE | \
  40         NETIF_MSG_LINK | \
  41         NETIF_MSG_RX_ERR | \
  42         NETIF_MSG_TX_ERR | \
  43         NETIF_MSG_HW)
  44
  45 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
  46 #define pr_err(fmt, arg...) \
  47         printk(KERN_ERR fmt, ##arg)
  48 #endif
  49 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
  50 #define netdev_err(netdev, fmt, arg...) \
  51         pr_err(fmt, ##arg)
  52 #endif
  53
  54 #ifdef TX_DEBUG
  55 #define tx_dbg(priv, fmt, args...)                                      \
  56         printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args)
  57 #else
  58 #define tx_dbg(priv, fmt, args...)                                      \
  59 do {                                                                    \
  60         if (0)                                                          \
  61                 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args); \
  62 } while (0)
  63 #endif
  64
  65 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
  66 #define jme_msg(msglvl, type, priv, fmt, args...) \
  67         if (netif_msg_##type(priv)) \
  68                 printk(msglvl "%s: " fmt, (priv)->dev->name, ## args)
  69
  70 #define msg_probe(priv, fmt, args...) \
  71         jme_msg(KERN_INFO, probe, priv, fmt, ## args)
  72
  73 #define msg_link(priv, fmt, args...) \
  74         jme_msg(KERN_INFO, link, priv, fmt, ## args)
  75
  76 #define msg_intr(priv, fmt, args...) \
  77         jme_msg(KERN_INFO, intr, priv, fmt, ## args)
  78
  79 #define msg_rx_err(priv, fmt, args...) \
  80         jme_msg(KERN_ERR, rx_err, priv, fmt, ## args)
  81
  82 #define msg_rx_status(priv, fmt, args...) \
  83         jme_msg(KERN_INFO, rx_status, priv, fmt, ## args)
  84
  85 #define msg_tx_err(priv, fmt, args...) \
  86         jme_msg(KERN_ERR, tx_err, priv, fmt, ## args)
  87
  88 #define msg_tx_done(priv, fmt, args...) \
  89         jme_msg(KERN_INFO, tx_done, priv, fmt, ## args)
  90
  91 #define msg_tx_queued(priv, fmt, args...) \
  92         jme_msg(KERN_INFO, tx_queued, priv, fmt, ## args)
  93
  94 #define msg_hw(priv, fmt, args...) \
  95         jme_msg(KERN_ERR, hw, priv, fmt, ## args)
  96
  97 #define netif_info(priv, type, dev, fmt, args...) \
  98         msg_ ## type(priv, fmt, ## args)
  99 #define netif_err(priv, type, dev, fmt, args...) \
 100         msg_ ## type(priv, fmt, ## args)
 101 #endif
 102
 103 #ifndef NETIF_F_TSO6
 104 #define NETIF_F_TSO6 0
 105 #endif
 106 #ifndef NETIF_F_IPV6_CSUM
 107 #define NETIF_F_IPV6_CSUM 0
 108 #endif
 109
 110 /*
 111  * Extra PCI Configuration space interface
 112  */
 113 #define PCI_DCSR_MRRS           0x59
 114 #define PCI_DCSR_MRRS_MASK      0x70
 115
 116 enum pci_dcsr_mrrs_vals {
 117         MRRS_128B       = 0x00,
 118         MRRS_256B       = 0x10,
 119         MRRS_512B       = 0x20,
 120         MRRS_1024B      = 0x30,
 121         MRRS_2048B      = 0x40,
 122         MRRS_4096B      = 0x50,
 123 };
 124
 125 #define PCI_SPI                 0xB0
 126
 127 enum pci_spi_bits {
 128         SPI_EN          = 0x10,
 129         SPI_MISO        = 0x08,
 130         SPI_MOSI        = 0x04,
 131         SPI_SCLK        = 0x02,
 132         SPI_CS          = 0x01,
 133 };
 134
 135 struct jme_spi_op {
 136         void __user *uwbuf;
 137         void __user *urbuf;
 138         __u8    wn;     /* Number of write actions */
 139         __u8    rn;     /* Number of read actions */
 140         __u8    bitn;   /* Number of bits per action */
 141         __u8    spd;    /* The maxim acceptable speed of controller, in MHz.*/
 142         __u8    mode;   /* CPOL, CPHA, and Duplex mode of SPI */
 143
 144         /* Internal use only */
 145         u8      *kwbuf;
 146         u8      *krbuf;
 147         u8      sr;
 148         u16     halfclk; /* Half of clock cycle calculated from spd, in ns */
 149 };
 150
 151 enum jme_spi_op_bits {
 152         SPI_MODE_CPHA   = 0x01,
 153         SPI_MODE_CPOL   = 0x02,
 154         SPI_MODE_DUP    = 0x80,
 155 };
 156
 157 #define HALF_US 500     /* 500 ns */
 158 #define JMESPIIOCTL     SIOCDEVPRIVATE
 159
 160 /*
 161  * Dynamic(adaptive)/Static PCC values
 162  */
 163 enum dynamic_pcc_values {
 164         PCC_OFF         = 0,
 165         PCC_P1          = 1,
 166         PCC_P2          = 2,
 167         PCC_P3          = 3,
 168
 169         PCC_OFF_TO      = 0,
 170         PCC_P1_TO       = 1,
 171         PCC_P2_TO       = 64,
 172         PCC_P3_TO       = 128,
 173
 174         PCC_OFF_CNT     = 0,
 175         PCC_P1_CNT      = 1,
 176         PCC_P2_CNT      = 16,
 177         PCC_P3_CNT      = 32,
 178 };
 179 struct dynpcc_info {
 180         unsigned long   last_bytes;
 181         unsigned long   last_pkts;
 182         unsigned long   intr_cnt;
 183         unsigned char   cur;
 184         unsigned char   attempt;
 185         unsigned char   cnt;
 186 };
 187 #define PCC_INTERVAL_US 100000
 188 #define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
 189 #define PCC_P3_THRESHOLD (2 * 1024 * 1024)
 190 #define PCC_P2_THRESHOLD 800
 191 #define PCC_INTR_THRESHOLD 800
 192 #define PCC_TX_TO 1000
 193 #define PCC_TX_CNT 8
 194
 195 /*
 196  * TX/RX Descriptors
 197  *
 198  * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
 199  */
 200 #define RING_DESC_ALIGN         16      /* Descriptor alignment */
 201 #define TX_DESC_SIZE            16
 202 #define TX_RING_NR              8
 203 #define TX_RING_ALLOC_SIZE(s)   ((s * TX_DESC_SIZE) + RING_DESC_ALIGN)
 204
 205 struct txdesc {
 206         union {
 207                 __u8    all[16];
 208                 __le32  dw[4];
 209                 struct {
 210                         /* DW0 */
 211                         __le16  vlan;
 212                         __u8    rsv1;
 213                         __u8    flags;
 214
 215                         /* DW1 */
 216                         __le16  datalen;
 217                         __le16  mss;
 218
 219                         /* DW2 */
 220                         __le16  pktsize;
 221                         __le16  rsv2;
 222
 223                         /* DW3 */
 224                         __le32  bufaddr;
 225                 } desc1;
 226                 struct {
 227                         /* DW0 */
 228                         __le16  rsv1;
 229                         __u8    rsv2;
 230                         __u8    flags;
 231
 232                         /* DW1 */
 233                         __le16  datalen;
 234                         __le16  rsv3;
 235
 236                         /* DW2 */
 237                         __le32  bufaddrh;
 238
 239                         /* DW3 */
 240                         __le32  bufaddrl;
 241                 } desc2;
 242                 struct {
 243                         /* DW0 */
 244                         __u8    ehdrsz;
 245                         __u8    rsv1;
 246                         __u8    rsv2;
 247                         __u8    flags;
 248
 249                         /* DW1 */
 250                         __le16  trycnt;
 251                         __le16  segcnt;
 252
 253                         /* DW2 */
 254                         __le16  pktsz;
 255                         __le16  rsv3;
 256
 257                         /* DW3 */
 258                         __le32  bufaddrl;
 259                 } descwb;
 260         };
 261 };
 262
 263 enum jme_txdesc_flags_bits {
 264         TXFLAG_OWN      = 0x80,
 265         TXFLAG_INT      = 0x40,
 266         TXFLAG_64BIT    = 0x20,
 267         TXFLAG_TCPCS    = 0x10,
 268         TXFLAG_UDPCS    = 0x08,
 269         TXFLAG_IPCS     = 0x04,
 270         TXFLAG_LSEN     = 0x02,
 271         TXFLAG_TAGON    = 0x01,
 272 };
 273
 274 #define TXDESC_MSS_SHIFT        2
 275 enum jme_txwbdesc_flags_bits {
 276         TXWBFLAG_OWN    = 0x80,
 277         TXWBFLAG_INT    = 0x40,
 278         TXWBFLAG_TMOUT  = 0x20,
 279         TXWBFLAG_TRYOUT = 0x10,
 280         TXWBFLAG_COL    = 0x08,
 281
 282         TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
 283                           TXWBFLAG_TRYOUT |
 284                           TXWBFLAG_COL,
 285 };
 286
 287 #define RX_DESC_SIZE            16
 288 #define RX_RING_NR              4
 289 #define RX_RING_ALLOC_SIZE(s)   ((s * RX_DESC_SIZE) + RING_DESC_ALIGN)
 290 #define RX_BUF_DMA_ALIGN        8
 291 #define RX_PREPAD_SIZE          10
 292 #define ETH_CRC_LEN             2
 293 #define RX_VLANHDR_LEN          2
 294 #define RX_EXTRA_LEN            (RX_PREPAD_SIZE + \
 295                                 ETH_HLEN + \
 296                                 ETH_CRC_LEN + \
 297                                 RX_VLANHDR_LEN + \
 298                                 RX_BUF_DMA_ALIGN)
 299
 300 struct rxdesc {
 301         union {
 302                 __u8    all[16];
 303                 __le32  dw[4];
 304                 struct {
 305                         /* DW0 */
 306                         __le16  rsv2;
 307                         __u8    rsv1;
 308                         __u8    flags;
 309
 310                         /* DW1 */
 311                         __le16  datalen;
 312                         __le16  wbcpl;
 313
 314                         /* DW2 */
 315                         __le32  bufaddrh;
 316
 317                         /* DW3 */
 318                         __le32  bufaddrl;
 319                 } desc1;
 320                 struct {
 321                         /* DW0 */
 322                         __le16  vlan;
 323                         __le16  flags;
 324
 325                         /* DW1 */
 326                         __le16  framesize;
 327                         __u8    errstat;
 328                         __u8    desccnt;
 329
 330                         /* DW2 */
 331                         __le32  rsshash;
 332
 333                         /* DW3 */
 334                         __u8    hashfun;
 335                         __u8    hashtype;
 336                         __le16  resrv;
 337                 } descwb;
 338         };
 339 };
 340
 341 enum jme_rxdesc_flags_bits {
 342         RXFLAG_OWN      = 0x80,
 343         RXFLAG_INT      = 0x40,
 344         RXFLAG_64BIT    = 0x20,
 345 };
 346
 347 enum jme_rxwbdesc_flags_bits {
 348         RXWBFLAG_OWN            = 0x8000,
 349         RXWBFLAG_INT            = 0x4000,
 350         RXWBFLAG_MF             = 0x2000,
 351         RXWBFLAG_64BIT          = 0x2000,
 352         RXWBFLAG_TCPON          = 0x1000,
 353         RXWBFLAG_UDPON          = 0x0800,
 354         RXWBFLAG_IPCS           = 0x0400,
 355         RXWBFLAG_TCPCS          = 0x0200,
 356         RXWBFLAG_UDPCS          = 0x0100,
 357         RXWBFLAG_TAGON          = 0x0080,
 358         RXWBFLAG_IPV4           = 0x0040,
 359         RXWBFLAG_IPV6           = 0x0020,
 360         RXWBFLAG_PAUSE          = 0x0010,
 361         RXWBFLAG_MAGIC          = 0x0008,
 362         RXWBFLAG_WAKEUP         = 0x0004,
 363         RXWBFLAG_DEST           = 0x0003,
 364         RXWBFLAG_DEST_UNI       = 0x0001,
 365         RXWBFLAG_DEST_MUL       = 0x0002,
 366         RXWBFLAG_DEST_BRO       = 0x0003,
 367 };
 368
 369 enum jme_rxwbdesc_desccnt_mask {
 370         RXWBDCNT_WBCPL  = 0x80,
 371         RXWBDCNT_DCNT   = 0x7F,
 372 };
 373
 374 enum jme_rxwbdesc_errstat_bits {
 375         RXWBERR_LIMIT   = 0x80,
 376         RXWBERR_MIIER   = 0x40,
 377         RXWBERR_NIBON   = 0x20,
 378         RXWBERR_COLON   = 0x10,
 379         RXWBERR_ABORT   = 0x08,
 380         RXWBERR_SHORT   = 0x04,
 381         RXWBERR_OVERUN  = 0x02,
 382         RXWBERR_CRCERR  = 0x01,
 383         RXWBERR_ALLERR  = 0xFF,
 384 };
 385
 386 /*
 387  * Buffer information corresponding to ring descriptors.
 388  */
 389 struct jme_buffer_info {
 390         struct sk_buff *skb;
 391         dma_addr_t mapping;
 392         int len;
 393         int nr_desc;
 394         unsigned long start_xmit;
 395 };
 396
 397 /*
 398  * The structure holding buffer information and ring descriptors all together.
 399  */
 400 struct jme_ring {
 401         void *alloc;            /* pointer to allocated memory */
 402         void *desc;             /* pointer to ring memory  */
 403         dma_addr_t dmaalloc;    /* phys address of ring alloc */
 404         dma_addr_t dma;         /* phys address for ring dma */
 405
 406         /* Buffer information corresponding to each descriptor */
 407         struct jme_buffer_info *bufinf;
 408
 409         int next_to_use;
 410         atomic_t next_to_clean;
 411         atomic_t nr_free;
 412 };
 413
 414 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
 415 #define false 0
 416 #define true 0
 417 #define netdev_alloc_skb(dev, len) dev_alloc_skb(len)
 418 #define PCI_VENDOR_ID_JMICRON           0x197B
 419 #endif
 420
 421 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,19)
 422 #define PCI_VDEVICE(vendor, device)             \
 423         PCI_VENDOR_ID_##vendor, (device),       \
 424         PCI_ANY_ID, PCI_ANY_ID, 0, 0
 425 #endif
 426
 427 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
 428 #define NET_STAT(priv) priv->stats
 429 #define NETDEV_GET_STATS(netdev, fun_ptr) \
 430         netdev->get_stats = fun_ptr
 431 #define DECLARE_NET_DEVICE_STATS struct net_device_stats stats;
 432 /*
 433  * CentOS 5.5 have *_hdr helpers back-ported
 434  */
 435 #ifdef RHEL_RELEASE_CODE
 436 #if RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,5)
 437 #define __DEFINE_IPHDR_HELPERS__
 438 #endif
 439 #else
 440 #define __DEFINE_IPHDR_HELPERS__
 441 #endif
 442 #else
 443 #define NET_STAT(priv) (priv->dev->stats)
 444 #define NETDEV_GET_STATS(netdev, fun_ptr)
 445 #define DECLARE_NET_DEVICE_STATS
 446 #endif
 447
 448 #ifdef __DEFINE_IPHDR_HELPERS__
 449 static inline struct iphdr *ip_hdr(const struct sk_buff *skb)
 450 {
 451         return skb->nh.iph;
 452 }
 453
 454 static inline struct ipv6hdr *ipv6_hdr(const struct sk_buff *skb)
 455 {
 456         return skb->nh.ipv6h;
 457 }
 458
 459 static inline struct tcphdr *tcp_hdr(const struct sk_buff *skb)
 460 {
 461         return skb->h.th;
 462 }
 463 #endif
 464
 465 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
 466 #define DECLARE_NAPI_STRUCT
 467 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
 468         dev->poll = pollfn; \
 469         dev->weight = q;
 470 #define JME_NAPI_HOLDER(holder) struct net_device *holder
 471 #define JME_NAPI_WEIGHT(w) int *w
 472 #define JME_NAPI_WEIGHT_VAL(w) *w
 473 #define JME_NAPI_WEIGHT_SET(w, r) *w = r
 474 #define DECLARE_NETDEV struct net_device *netdev = jme->dev;
 475 #define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev)
 476 #define JME_NAPI_ENABLE(priv) netif_poll_enable(priv->dev);
 477 #define JME_NAPI_DISABLE(priv) netif_poll_disable(priv->dev);
 478 #define JME_RX_SCHEDULE_PREP(priv) \
 479         netif_rx_schedule_prep(priv->dev)
 480 #define JME_RX_SCHEDULE(priv) \
 481         __netif_rx_schedule(priv->dev);
 482 #else
 483 #define DECLARE_NAPI_STRUCT struct napi_struct napi;
 484 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
 485         netif_napi_add(dev, napis, pollfn, q);
 486 #define JME_NAPI_HOLDER(holder) struct napi_struct *holder
 487 #define JME_NAPI_WEIGHT(w) int w
 488 #define JME_NAPI_WEIGHT_VAL(w) w
 489 #define JME_NAPI_WEIGHT_SET(w, r)
 490 #define DECLARE_NETDEV
 491 #define JME_RX_COMPLETE(dev, napis) napi_complete(napis)
 492 #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
 493 #define JME_NAPI_DISABLE(priv) \
 494         if (!napi_disable_pending(&priv->napi)) \
 495                 napi_disable(&priv->napi);
 496 #define JME_RX_SCHEDULE_PREP(priv) \
 497         napi_schedule_prep(&priv->napi)
 498 #define JME_RX_SCHEDULE(priv) \
 499         __napi_schedule(&priv->napi);
 500 #endif
 501
 502 /*
 503  * Jmac Adapter Private data
 504  */
 505 struct jme_adapter {
 506         struct pci_dev          *pdev;
 507         struct net_device       *dev;
 508         void __iomem            *regs;
 509         struct mii_if_info      mii_if;
 510         struct jme_ring         rxring[RX_RING_NR];
 511         struct jme_ring         txring[TX_RING_NR];
 512         spinlock_t              phy_lock;
 513         spinlock_t              macaddr_lock;
 514         spinlock_t              rxmcs_lock;
 515         struct tasklet_struct   rxempty_task;
 516         struct tasklet_struct   rxclean_task;
 517         struct tasklet_struct   txclean_task;
 518         struct tasklet_struct   linkch_task;
 519         struct tasklet_struct   pcc_task;
 520         unsigned long           flags;
 521         u32                     reg_txcs;
 522         u32                     reg_txpfc;
 523         u32                     reg_rxcs;
 524         u32                     reg_rxmcs;
 525         u32                     reg_ghc;
 526         u32                     reg_pmcs;
 527         u32                     phylink;
 528         u32                     tx_ring_size;
 529         u32                     tx_ring_mask;
 530         u32                     tx_wake_threshold;
 531         u32                     rx_ring_size;
 532         u32                     rx_ring_mask;
 533         u8                      mrrs;
 534         unsigned int            fpgaver;
 535         u8                      chiprev;
 536         u8                      chip_main_rev;
 537         u8                      chip_sub_rev;
 538         u8                      pcirev;
 539         u32                     msg_enable;
 540         struct ethtool_cmd      old_ecmd;
 541         unsigned int            old_mtu;
 542         struct vlan_group       *vlgrp;
 543         struct dynpcc_info      dpi;
 544         atomic_t                intr_sem;
 545         atomic_t                link_changing;
 546         atomic_t                tx_cleaning;
 547         atomic_t                rx_cleaning;
 548         atomic_t                rx_empty;
 549         int                     (*jme_rx)(struct sk_buff *skb);
 550         int                     (*jme_vlan_rx)(struct sk_buff *skb,
 551                                           struct vlan_group *grp,
 552                                           unsigned short vlan_tag);
 553         DECLARE_NAPI_STRUCT
 554         DECLARE_NET_DEVICE_STATS
 555 };
 556
 557 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
 558 static struct net_device_stats *
 559 jme_get_stats(struct net_device *netdev)
 560 {
 561         struct jme_adapter *jme = netdev_priv(netdev);
 562         return &jme->stats;
 563 }
 564 #endif
 565
 566 enum jme_flags_bits {
 567         JME_FLAG_MSI            = 1,
 568         JME_FLAG_SSET           = 2,
 569         JME_FLAG_TXCSUM         = 3,
 570         JME_FLAG_TSO            = 4,
 571         JME_FLAG_POLL           = 5,
 572         JME_FLAG_SHUTDOWN       = 6,
 573 };
 574
 575 #define TX_TIMEOUT              (5 * HZ)
 576 #define JME_REG_LEN             0x500
 577 #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
 578
 579 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
 580 static inline struct jme_adapter*
 581 jme_napi_priv(struct net_device *holder)
 582 {
 583         struct jme_adapter *jme;
 584         jme = netdev_priv(holder);
 585         return jme;
 586 }
 587 #else
 588 static inline struct jme_adapter*
 589 jme_napi_priv(struct napi_struct *napi)
 590 {
 591         struct jme_adapter *jme;
 592         jme = container_of(napi, struct jme_adapter, napi);
 593         return jme;
 594 }
 595 #endif
 596
 597 /*
 598  * MMaped I/O Resters
 599  */
 600 enum jme_iomap_offsets {
 601         JME_MAC         = 0x0000,
 602         JME_PHY         = 0x0400,
 603         JME_MISC        = 0x0800,
 604         JME_RSS         = 0x0C00,
 605 };
 606
 607 enum jme_iomap_lens {
 608         JME_MAC_LEN     = 0x80,
 609         JME_PHY_LEN     = 0x58,
 610         JME_MISC_LEN    = 0x98,
 611         JME_RSS_LEN     = 0xFF,
 612 };
 613
 614 enum jme_iomap_regs {
 615         JME_TXCS        = JME_MAC | 0x00, /* Transmit Control and Status */
 616         JME_TXDBA_LO    = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
 617         JME_TXDBA_HI    = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
 618         JME_TXQDC       = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
 619         JME_TXNDA       = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
 620         JME_TXMCS       = JME_MAC | 0x14, /* Transmit MAC Control Status */
 621         JME_TXPFC       = JME_MAC | 0x18, /* Transmit Pause Frame Control */
 622         JME_TXTRHD      = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
 623
 624         JME_RXCS        = JME_MAC | 0x20, /* Receive Control and Status */
 625         JME_RXDBA_LO    = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
 626         JME_RXDBA_HI    = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
 627         JME_RXQDC       = JME_MAC | 0x2C, /* Receive Queue Desc Count */
 628         JME_RXNDA       = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
 629         JME_RXMCS       = JME_MAC | 0x34, /* Receive MAC Control Status */
 630         JME_RXUMA_LO    = JME_MAC | 0x38, /* Receive Unicast MAC Address */
 631         JME_RXUMA_HI    = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
 632         JME_RXMCHT_LO   = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
 633         JME_RXMCHT_HI   = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
 634         JME_WFODP       = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
 635         JME_WFOI        = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
 636
 637         JME_SMI         = JME_MAC | 0x50, /* Station Management Interface */
 638         JME_GHC         = JME_MAC | 0x54, /* Global Host Control */
 639         JME_PMCS        = JME_MAC | 0x60, /* Power Management Control/Stat */
 640
 641
 642         JME_PHY_CS      = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
 643         JME_PHY_LINK    = JME_PHY | 0x30, /* PHY Link Status Register */
 644         JME_SMBCSR      = JME_PHY | 0x40, /* SMB Control and Status */
 645         JME_SMBINTF     = JME_PHY | 0x44, /* SMB Interface */
 646
 647
 648         JME_TMCSR       = JME_MISC | 0x00, /* Timer Control/Status Register */
 649         JME_GPREG0      = JME_MISC | 0x08, /* General purpose REG-0 */
 650         JME_GPREG1      = JME_MISC | 0x0C, /* General purpose REG-1 */
 651         JME_IEVE        = JME_MISC | 0x20, /* Interrupt Event Status */
 652         JME_IREQ        = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
 653         JME_IENS        = JME_MISC | 0x28, /* Intr Enable - Setting Port */
 654         JME_IENC        = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
 655         JME_PCCRX0      = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
 656         JME_PCCTX       = JME_MISC | 0x40, /* PCC Control for TX Queues */
 657         JME_CHIPMODE    = JME_MISC | 0x44, /* Identify FPGA Version */
 658         JME_SHBA_HI     = JME_MISC | 0x48, /* Shadow Register Base HI */
 659         JME_SHBA_LO     = JME_MISC | 0x4C, /* Shadow Register Base LO */
 660         JME_TIMER1      = JME_MISC | 0x70, /* Timer1 */
 661         JME_TIMER2      = JME_MISC | 0x74, /* Timer2 */
 662         JME_APMC        = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
 663         JME_PCCSRX0     = JME_MISC | 0x80, /* PCC Status of RX0 */
 664 };
 665
 666 /*
 667  * TX Control/Status Bits
 668  */
 669 enum jme_txcs_bits {
 670         TXCS_QUEUE7S    = 0x00008000,
 671         TXCS_QUEUE6S    = 0x00004000,
 672         TXCS_QUEUE5S    = 0x00002000,
 673         TXCS_QUEUE4S    = 0x00001000,
 674         TXCS_QUEUE3S    = 0x00000800,
 675         TXCS_QUEUE2S    = 0x00000400,
 676         TXCS_QUEUE1S    = 0x00000200,
 677         TXCS_QUEUE0S    = 0x00000100,
 678         TXCS_FIFOTH     = 0x000000C0,
 679         TXCS_DMASIZE    = 0x00000030,
 680         TXCS_BURST      = 0x00000004,
 681         TXCS_ENABLE     = 0x00000001,
 682 };
 683
 684 enum jme_txcs_value {
 685         TXCS_FIFOTH_16QW        = 0x000000C0,
 686         TXCS_FIFOTH_12QW        = 0x00000080,
 687         TXCS_FIFOTH_8QW         = 0x00000040,
 688         TXCS_FIFOTH_4QW         = 0x00000000,
 689
 690         TXCS_DMASIZE_64B        = 0x00000000,
 691         TXCS_DMASIZE_128B       = 0x00000010,
 692         TXCS_DMASIZE_256B       = 0x00000020,
 693         TXCS_DMASIZE_512B       = 0x00000030,
 694
 695         TXCS_SELECT_QUEUE0      = 0x00000000,
 696         TXCS_SELECT_QUEUE1      = 0x00010000,
 697         TXCS_SELECT_QUEUE2      = 0x00020000,
 698         TXCS_SELECT_QUEUE3      = 0x00030000,
 699         TXCS_SELECT_QUEUE4      = 0x00040000,
 700         TXCS_SELECT_QUEUE5      = 0x00050000,
 701         TXCS_SELECT_QUEUE6      = 0x00060000,
 702         TXCS_SELECT_QUEUE7      = 0x00070000,
 703
 704         TXCS_DEFAULT            = TXCS_FIFOTH_4QW |
 705                                   TXCS_BURST,
 706 };
 707
 708 #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
 709
 710 /*
 711  * TX MAC Control/Status Bits
 712  */
 713 enum jme_txmcs_bit_masks {
 714         TXMCS_IFG2              = 0xC0000000,
 715         TXMCS_IFG1              = 0x30000000,
 716         TXMCS_TTHOLD            = 0x00000300,
 717         TXMCS_FBURST            = 0x00000080,
 718         TXMCS_CARRIEREXT        = 0x00000040,
 719         TXMCS_DEFER             = 0x00000020,
 720         TXMCS_BACKOFF           = 0x00000010,
 721         TXMCS_CARRIERSENSE      = 0x00000008,
 722         TXMCS_COLLISION         = 0x00000004,
 723         TXMCS_CRC               = 0x00000002,
 724         TXMCS_PADDING           = 0x00000001,
 725 };
 726
 727 enum jme_txmcs_values {
 728         TXMCS_IFG2_6_4          = 0x00000000,
 729         TXMCS_IFG2_8_5          = 0x40000000,
 730         TXMCS_IFG2_10_6         = 0x80000000,
 731         TXMCS_IFG2_12_7         = 0xC0000000,
 732
 733         TXMCS_IFG1_8_4          = 0x00000000,
 734         TXMCS_IFG1_12_6         = 0x10000000,
 735         TXMCS_IFG1_16_8         = 0x20000000,
 736         TXMCS_IFG1_20_10        = 0x30000000,
 737
 738         TXMCS_TTHOLD_1_8        = 0x00000000,
 739         TXMCS_TTHOLD_1_4        = 0x00000100,
 740         TXMCS_TTHOLD_1_2        = 0x00000200,
 741         TXMCS_TTHOLD_FULL       = 0x00000300,
 742
 743         TXMCS_DEFAULT           = TXMCS_IFG2_8_5 |
 744                                   TXMCS_IFG1_16_8 |
 745                                   TXMCS_TTHOLD_FULL |
 746                                   TXMCS_DEFER |
 747                                   TXMCS_CRC |
 748                                   TXMCS_PADDING,
 749 };
 750
 751 enum jme_txpfc_bits_masks {
 752         TXPFC_VLAN_TAG          = 0xFFFF0000,
 753         TXPFC_VLAN_EN           = 0x00008000,
 754         TXPFC_PF_EN             = 0x00000001,
 755 };
 756
 757 enum jme_txtrhd_bits_masks {
 758         TXTRHD_TXPEN            = 0x80000000,
 759         TXTRHD_TXP              = 0x7FFFFF00,
 760         TXTRHD_TXREN            = 0x00000080,
 761         TXTRHD_TXRL             = 0x0000007F,
 762 };
 763
 764 enum jme_txtrhd_shifts {
 765         TXTRHD_TXP_SHIFT        = 8,
 766         TXTRHD_TXRL_SHIFT       = 0,
 767 };
 768
 769 /*
 770  * RX Control/Status Bits
 771  */
 772 enum jme_rxcs_bit_masks {
 773         /* FIFO full threshold for transmitting Tx Pause Packet */
 774         RXCS_FIFOTHTP   = 0x30000000,
 775         /* FIFO threshold for processing next packet */
 776         RXCS_FIFOTHNP   = 0x0C000000,
 777         RXCS_DMAREQSZ   = 0x03000000, /* DMA Request Size */
 778         RXCS_QUEUESEL   = 0x00030000, /* Queue selection */
 779         RXCS_RETRYGAP   = 0x0000F000, /* RX Desc full retry gap */
 780         RXCS_RETRYCNT   = 0x00000F00, /* RX Desc full retry counter */
 781         RXCS_WAKEUP     = 0x00000040, /* Enable receive wakeup packet */
 782         RXCS_MAGIC      = 0x00000020, /* Enable receive magic packet */
 783         RXCS_SHORT      = 0x00000010, /* Enable receive short packet */
 784         RXCS_ABORT      = 0x00000008, /* Enable receive errorr packet */
 785         RXCS_QST        = 0x00000004, /* Receive queue start */
 786         RXCS_SUSPEND    = 0x00000002,
 787         RXCS_ENABLE     = 0x00000001,
 788 };
 789
 790 enum jme_rxcs_values {
 791         RXCS_FIFOTHTP_16T       = 0x00000000,
 792         RXCS_FIFOTHTP_32T       = 0x10000000,
 793         RXCS_FIFOTHTP_64T       = 0x20000000,
 794         RXCS_FIFOTHTP_128T      = 0x30000000,
 795
 796         RXCS_FIFOTHNP_16QW      = 0x00000000,
 797         RXCS_FIFOTHNP_32QW      = 0x04000000,
 798         RXCS_FIFOTHNP_64QW      = 0x08000000,
 799         RXCS_FIFOTHNP_128QW     = 0x0C000000,
 800
 801         RXCS_DMAREQSZ_16B       = 0x00000000,
 802         RXCS_DMAREQSZ_32B       = 0x01000000,
 803         RXCS_DMAREQSZ_64B       = 0x02000000,
 804         RXCS_DMAREQSZ_128B      = 0x03000000,
 805
 806         RXCS_QUEUESEL_Q0        = 0x00000000,
 807         RXCS_QUEUESEL_Q1        = 0x00010000,
 808         RXCS_QUEUESEL_Q2        = 0x00020000,
 809         RXCS_QUEUESEL_Q3        = 0x00030000,
 810
 811         RXCS_RETRYGAP_256ns     = 0x00000000,
 812         RXCS_RETRYGAP_512ns     = 0x00001000,
 813         RXCS_RETRYGAP_1024ns    = 0x00002000,
 814         RXCS_RETRYGAP_2048ns    = 0x00003000,
 815         RXCS_RETRYGAP_4096ns    = 0x00004000,
 816         RXCS_RETRYGAP_8192ns    = 0x00005000,
 817         RXCS_RETRYGAP_16384ns   = 0x00006000,
 818         RXCS_RETRYGAP_32768ns   = 0x00007000,
 819
 820         RXCS_RETRYCNT_0         = 0x00000000,
 821         RXCS_RETRYCNT_4         = 0x00000100,
 822         RXCS_RETRYCNT_8         = 0x00000200,
 823         RXCS_RETRYCNT_12        = 0x00000300,
 824         RXCS_RETRYCNT_16        = 0x00000400,
 825         RXCS_RETRYCNT_20        = 0x00000500,
 826         RXCS_RETRYCNT_24        = 0x00000600,
 827         RXCS_RETRYCNT_28        = 0x00000700,
 828         RXCS_RETRYCNT_32        = 0x00000800,
 829         RXCS_RETRYCNT_36        = 0x00000900,
 830         RXCS_RETRYCNT_40        = 0x00000A00,
 831         RXCS_RETRYCNT_44        = 0x00000B00,
 832         RXCS_RETRYCNT_48        = 0x00000C00,
 833         RXCS_RETRYCNT_52        = 0x00000D00,
 834         RXCS_RETRYCNT_56        = 0x00000E00,
 835         RXCS_RETRYCNT_60        = 0x00000F00,
 836
 837         RXCS_DEFAULT            = RXCS_FIFOTHTP_128T |
 838                                   RXCS_FIFOTHNP_128QW |
 839                                   RXCS_DMAREQSZ_128B |
 840                                   RXCS_RETRYGAP_256ns |
 841                                   RXCS_RETRYCNT_32,
 842 };
 843
 844 #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
 845
 846 /*
 847  * RX MAC Control/Status Bits
 848  */
 849 enum jme_rxmcs_bits {
 850         RXMCS_ALLFRAME          = 0x00000800,
 851         RXMCS_BRDFRAME          = 0x00000400,
 852         RXMCS_MULFRAME          = 0x00000200,
 853         RXMCS_UNIFRAME          = 0x00000100,
 854         RXMCS_ALLMULFRAME       = 0x00000080,
 855         RXMCS_MULFILTERED       = 0x00000040,
 856         RXMCS_RXCOLLDEC         = 0x00000020,
 857         RXMCS_FLOWCTRL          = 0x00000008,
 858         RXMCS_VTAGRM            = 0x00000004,
 859         RXMCS_PREPAD            = 0x00000002,
 860         RXMCS_CHECKSUM          = 0x00000001,
 861
 862         RXMCS_DEFAULT           = RXMCS_VTAGRM |
 863                                   RXMCS_PREPAD |
 864                                   RXMCS_FLOWCTRL |
 865                                   RXMCS_CHECKSUM,
 866 };
 867
 868 /*
 869  * Wakeup Frame setup interface registers
 870  */
 871 #define WAKEUP_FRAME_NR 8
 872 #define WAKEUP_FRAME_MASK_DWNR  4
 873
 874 enum jme_wfoi_bit_masks {
 875         WFOI_MASK_SEL           = 0x00000070,
 876         WFOI_CRC_SEL            = 0x00000008,
 877         WFOI_FRAME_SEL          = 0x00000007,
 878 };
 879
 880 enum jme_wfoi_shifts {
 881         WFOI_MASK_SHIFT         = 4,
 882 };
 883
 884 /*
 885  * SMI Related definitions
 886  */
 887 enum jme_smi_bit_mask {
 888         SMI_DATA_MASK           = 0xFFFF0000,
 889         SMI_REG_ADDR_MASK       = 0x0000F800,
 890         SMI_PHY_ADDR_MASK       = 0x000007C0,
 891         SMI_OP_WRITE            = 0x00000020,
 892         /* Set to 1, after req done it'll be cleared to 0 */
 893         SMI_OP_REQ              = 0x00000010,
 894         SMI_OP_MDIO             = 0x00000008, /* Software assess In/Out */
 895         SMI_OP_MDOE             = 0x00000004, /* Software Output Enable */
 896         SMI_OP_MDC              = 0x00000002, /* Software CLK Control */
 897         SMI_OP_MDEN             = 0x00000001, /* Software access Enable */
 898 };
 899
 900 enum jme_smi_bit_shift {
 901         SMI_DATA_SHIFT          = 16,
 902         SMI_REG_ADDR_SHIFT      = 11,
 903         SMI_PHY_ADDR_SHIFT      = 6,
 904 };
 905
 906 static inline u32 smi_reg_addr(int x)
 907 {
 908         return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
 909 }
 910
 911 static inline u32 smi_phy_addr(int x)
 912 {
 913         return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
 914 }
 915
 916 #define JME_PHY_TIMEOUT 100 /* 100 msec */
 917 #define JME_PHY_REG_NR 32
 918
 919 /*
 920  * Global Host Control
 921  */
 922 enum jme_ghc_bit_mask {
 923         GHC_SWRST               = 0x40000000,
 924         GHC_DPX                 = 0x00000040,
 925         GHC_SPEED               = 0x00000030,
 926         GHC_LINK_POLL           = 0x00000001,
 927 };
 928
 929 enum jme_ghc_speed_val {
 930         GHC_SPEED_10M           = 0x00000010,
 931         GHC_SPEED_100M          = 0x00000020,
 932         GHC_SPEED_1000M         = 0x00000030,
 933 };
 934
 935 enum jme_ghc_to_clk {
 936         GHC_TO_CLK_OFF          = 0x00000000,
 937         GHC_TO_CLK_GPHY         = 0x00400000,
 938         GHC_TO_CLK_PCIE         = 0x00800000,
 939         GHC_TO_CLK_INVALID      = 0x00C00000,
 940 };
 941
 942 enum jme_ghc_txmac_clk {
 943         GHC_TXMAC_CLK_OFF       = 0x00000000,
 944         GHC_TXMAC_CLK_GPHY      = 0x00100000,
 945         GHC_TXMAC_CLK_PCIE      = 0x00200000,
 946         GHC_TXMAC_CLK_INVALID   = 0x00300000,
 947 };
 948
 949 /*
 950  * Power management control and status register
 951  */
 952 enum jme_pmcs_bit_masks {
 953         PMCS_WF7DET     = 0x80000000,
 954         PMCS_WF6DET     = 0x40000000,
 955         PMCS_WF5DET     = 0x20000000,
 956         PMCS_WF4DET     = 0x10000000,
 957         PMCS_WF3DET     = 0x08000000,
 958         PMCS_WF2DET     = 0x04000000,
 959         PMCS_WF1DET     = 0x02000000,
 960         PMCS_WF0DET     = 0x01000000,
 961         PMCS_LFDET      = 0x00040000,
 962         PMCS_LRDET      = 0x00020000,
 963         PMCS_MFDET      = 0x00010000,
 964         PMCS_WF7EN      = 0x00008000,
 965         PMCS_WF6EN      = 0x00004000,
 966         PMCS_WF5EN      = 0x00002000,
 967         PMCS_WF4EN      = 0x00001000,
 968         PMCS_WF3EN      = 0x00000800,
 969         PMCS_WF2EN      = 0x00000400,
 970         PMCS_WF1EN      = 0x00000200,
 971         PMCS_WF0EN      = 0x00000100,
 972         PMCS_LFEN       = 0x00000004,
 973         PMCS_LREN       = 0x00000002,
 974         PMCS_MFEN       = 0x00000001,
 975 };
 976
 977 /*
 978  * Giga PHY Status Registers
 979  */
 980 enum jme_phy_link_bit_mask {
 981         PHY_LINK_SPEED_MASK             = 0x0000C000,
 982         PHY_LINK_DUPLEX                 = 0x00002000,
 983         PHY_LINK_SPEEDDPU_RESOLVED      = 0x00000800,
 984         PHY_LINK_UP                     = 0x00000400,
 985         PHY_LINK_AUTONEG_COMPLETE       = 0x00000200,
 986         PHY_LINK_MDI_STAT               = 0x00000040,
 987 };
 988
 989 enum jme_phy_link_speed_val {
 990         PHY_LINK_SPEED_10M              = 0x00000000,
 991         PHY_LINK_SPEED_100M             = 0x00004000,
 992         PHY_LINK_SPEED_1000M            = 0x00008000,
 993 };
 994
 995 #define JME_SPDRSV_TIMEOUT      500     /* 500 us */
 996
 997 /*
 998  * SMB Control and Status
 999  */
1000 enum jme_smbcsr_bit_mask {
1001         SMBCSR_CNACK    = 0x00020000,
1002         SMBCSR_RELOAD   = 0x00010000,
1003         SMBCSR_EEPROMD  = 0x00000020,
1004         SMBCSR_INITDONE = 0x00000010,
1005         SMBCSR_BUSY     = 0x0000000F,
1006 };
1007
1008 enum jme_smbintf_bit_mask {
1009         SMBINTF_HWDATR  = 0xFF000000,
1010         SMBINTF_HWDATW  = 0x00FF0000,
1011         SMBINTF_HWADDR  = 0x0000FF00,
1012         SMBINTF_HWRWN   = 0x00000020,
1013         SMBINTF_HWCMD   = 0x00000010,
1014         SMBINTF_FASTM   = 0x00000008,
1015         SMBINTF_GPIOSCL = 0x00000004,
1016         SMBINTF_GPIOSDA = 0x00000002,
1017         SMBINTF_GPIOEN  = 0x00000001,
1018 };
1019
1020 enum jme_smbintf_vals {
1021         SMBINTF_HWRWN_READ      = 0x00000020,
1022         SMBINTF_HWRWN_WRITE     = 0x00000000,
1023 };
1024
1025 enum jme_smbintf_shifts {
1026         SMBINTF_HWDATR_SHIFT    = 24,
1027         SMBINTF_HWDATW_SHIFT    = 16,
1028         SMBINTF_HWADDR_SHIFT    = 8,
1029 };
1030
1031 #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
1032 #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
1033 #define JME_SMB_LEN 256
1034 #define JME_EEPROM_MAGIC 0x250
1035
1036 /*
1037  * Timer Control/Status Register
1038  */
1039 enum jme_tmcsr_bit_masks {
1040         TMCSR_SWIT      = 0x80000000,
1041         TMCSR_EN        = 0x01000000,
1042         TMCSR_CNT       = 0x00FFFFFF,
1043 };
1044
1045 /*
1046  * General Purpose REG-0
1047  */
1048 enum jme_gpreg0_masks {
1049         GPREG0_DISSH            = 0xFF000000,
1050         GPREG0_PCIRLMT          = 0x00300000,
1051         GPREG0_PCCNOMUTCLR      = 0x00040000,
1052         GPREG0_LNKINTPOLL       = 0x00001000,
1053         GPREG0_PCCTMR           = 0x00000300,
1054         GPREG0_PHYADDR          = 0x0000001F,
1055 };
1056
1057 enum jme_gpreg0_vals {
1058         GPREG0_DISSH_DW7        = 0x80000000,
1059         GPREG0_DISSH_DW6        = 0x40000000,
1060         GPREG0_DISSH_DW5        = 0x20000000,
1061         GPREG0_DISSH_DW4        = 0x10000000,
1062         GPREG0_DISSH_DW3        = 0x08000000,
1063         GPREG0_DISSH_DW2        = 0x04000000,
1064         GPREG0_DISSH_DW1        = 0x02000000,
1065         GPREG0_DISSH_DW0        = 0x01000000,
1066         GPREG0_DISSH_ALL        = 0xFF000000,
1067
1068         GPREG0_PCIRLMT_8        = 0x00000000,
1069         GPREG0_PCIRLMT_6        = 0x00100000,
1070         GPREG0_PCIRLMT_5        = 0x00200000,
1071         GPREG0_PCIRLMT_4        = 0x00300000,
1072
1073         GPREG0_PCCTMR_16ns      = 0x00000000,
1074         GPREG0_PCCTMR_256ns     = 0x00000100,
1075         GPREG0_PCCTMR_1us       = 0x00000200,
1076         GPREG0_PCCTMR_1ms       = 0x00000300,
1077
1078         GPREG0_PHYADDR_1        = 0x00000001,
1079
1080         GPREG0_DEFAULT          = GPREG0_PCIRLMT_4 |
1081                                   GPREG0_PCCTMR_1us |
1082                                   GPREG0_PHYADDR_1,
1083 };
1084
1085 /*
1086  * General Purpose REG-1
1087  * Note: All theses bits defined here are for
1088  *       Chip mode revision 0x11 only
1089  */
1090 enum jme_gpreg1_masks {
1091         GPREG1_INTRDELAYUNIT    = 0x00000018,
1092         GPREG1_INTRDELAYENABLE  = 0x00000007,
1093 };
1094
1095 enum jme_gpreg1_vals {
1096         GPREG1_RSSPATCH         = 0x00000040,
1097         GPREG1_HALFMODEPATCH    = 0x00000020,
1098
1099         GPREG1_INTDLYUNIT_16NS  = 0x00000000,
1100         GPREG1_INTDLYUNIT_256NS = 0x00000008,
1101         GPREG1_INTDLYUNIT_1US   = 0x00000010,
1102         GPREG1_INTDLYUNIT_16US  = 0x00000018,
1103
1104         GPREG1_INTDLYEN_1U      = 0x00000001,
1105         GPREG1_INTDLYEN_2U      = 0x00000002,
1106         GPREG1_INTDLYEN_3U      = 0x00000003,
1107         GPREG1_INTDLYEN_4U      = 0x00000004,
1108         GPREG1_INTDLYEN_5U      = 0x00000005,
1109         GPREG1_INTDLYEN_6U      = 0x00000006,
1110         GPREG1_INTDLYEN_7U      = 0x00000007,
1111
1112         GPREG1_DEFAULT          = 0x00000000,
1113 };
1114
1115 /*
1116  * Interrupt Status Bits
1117  */
1118 enum jme_interrupt_bits {
1119         INTR_SWINTR     = 0x80000000,
1120         INTR_TMINTR     = 0x40000000,
1121         INTR_LINKCH     = 0x20000000,
1122         INTR_PAUSERCV   = 0x10000000,
1123         INTR_MAGICRCV   = 0x08000000,
1124         INTR_WAKERCV    = 0x04000000,
1125         INTR_PCCRX0TO   = 0x02000000,
1126         INTR_PCCRX1TO   = 0x01000000,
1127         INTR_PCCRX2TO   = 0x00800000,
1128         INTR_PCCRX3TO   = 0x00400000,
1129         INTR_PCCTXTO    = 0x00200000,
1130         INTR_PCCRX0     = 0x00100000,
1131         INTR_PCCRX1     = 0x00080000,
1132         INTR_PCCRX2     = 0x00040000,
1133         INTR_PCCRX3     = 0x00020000,
1134         INTR_PCCTX      = 0x00010000,
1135         INTR_RX3EMP     = 0x00008000,
1136         INTR_RX2EMP     = 0x00004000,
1137         INTR_RX1EMP     = 0x00002000,
1138         INTR_RX0EMP     = 0x00001000,
1139         INTR_RX3        = 0x00000800,
1140         INTR_RX2        = 0x00000400,
1141         INTR_RX1        = 0x00000200,
1142         INTR_RX0        = 0x00000100,
1143         INTR_TX7        = 0x00000080,
1144         INTR_TX6        = 0x00000040,
1145         INTR_TX5        = 0x00000020,
1146         INTR_TX4        = 0x00000010,
1147         INTR_TX3        = 0x00000008,
1148         INTR_TX2        = 0x00000004,
1149         INTR_TX1        = 0x00000002,
1150         INTR_TX0        = 0x00000001,
1151 };
1152
1153 static const u32 INTR_ENABLE = INTR_SWINTR |
1154                                  INTR_TMINTR |
1155                                  INTR_LINKCH |
1156                                  INTR_PCCRX0TO |
1157                                  INTR_PCCRX0 |
1158                                  INTR_PCCTXTO |
1159                                  INTR_PCCTX |
1160                                  INTR_RX0EMP;
1161
1162 /*
1163  * PCC Control Registers
1164  */
1165 enum jme_pccrx_masks {
1166         PCCRXTO_MASK    = 0xFFFF0000,
1167         PCCRX_MASK      = 0x0000FF00,
1168 };
1169
1170 enum jme_pcctx_masks {
1171         PCCTXTO_MASK    = 0xFFFF0000,
1172         PCCTX_MASK      = 0x0000FF00,
1173         PCCTX_QS_MASK   = 0x000000FF,
1174 };
1175
1176 enum jme_pccrx_shifts {
1177         PCCRXTO_SHIFT   = 16,
1178         PCCRX_SHIFT     = 8,
1179 };
1180
1181 enum jme_pcctx_shifts {
1182         PCCTXTO_SHIFT   = 16,
1183         PCCTX_SHIFT     = 8,
1184 };
1185
1186 enum jme_pcctx_bits {
1187         PCCTXQ0_EN      = 0x00000001,
1188         PCCTXQ1_EN      = 0x00000002,
1189         PCCTXQ2_EN      = 0x00000004,
1190         PCCTXQ3_EN      = 0x00000008,
1191         PCCTXQ4_EN      = 0x00000010,
1192         PCCTXQ5_EN      = 0x00000020,
1193         PCCTXQ6_EN      = 0x00000040,
1194         PCCTXQ7_EN      = 0x00000080,
1195 };
1196
1197 /*
1198  * Chip Mode Register
1199  */
1200 enum jme_chipmode_bit_masks {
1201         CM_FPGAVER_MASK         = 0xFFFF0000,
1202         CM_CHIPREV_MASK         = 0x0000FF00,
1203         CM_CHIPMODE_MASK        = 0x0000000F,
1204 };
1205
1206 enum jme_chipmode_shifts {
1207         CM_FPGAVER_SHIFT        = 16,
1208         CM_CHIPREV_SHIFT        = 8,
1209 };
1210
1211 /*
1212  * Aggressive Power Mode Control
1213  */
1214 enum jme_apmc_bits {
1215         JME_APMC_PCIE_SD_EN     = 0x40000000,
1216         JME_APMC_PSEUDO_HP_EN   = 0x20000000,
1217         JME_APMC_EPIEN          = 0x04000000,
1218         JME_APMC_EPIEN_CTRL     = 0x03000000,
1219 };
1220
1221 enum jme_apmc_values {
1222         JME_APMC_EPIEN_CTRL_EN  = 0x02000000,
1223         JME_APMC_EPIEN_CTRL_DIS = 0x01000000,
1224 };
1225
1226 #define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000)
1227
1228 #ifdef REG_DEBUG
1229 static char *MAC_REG_NAME[] = {
1230         "JME_TXCS",      "JME_TXDBA_LO",  "JME_TXDBA_HI", "JME_TXQDC",
1231         "JME_TXNDA",     "JME_TXMCS",     "JME_TXPFC",    "JME_TXTRHD",
1232         "JME_RXCS",      "JME_RXDBA_LO",  "JME_RXDBA_HI", "JME_RXQDC",
1233         "JME_RXNDA",     "JME_RXMCS",     "JME_RXUMA_LO", "JME_RXUMA_HI",
1234         "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP",    "JME_WFOI",
1235         "JME_SMI",       "JME_GHC",       "UNKNOWN",      "UNKNOWN",
1236         "JME_PMCS"};
1237
1238 static char *PE_REG_NAME[] = {
1239         "UNKNOWN",      "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1240         "UNKNOWN",      "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1241         "UNKNOWN",      "UNKNOWN",     "JME_PHY_CS", "UNKNOWN",
1242         "JME_PHY_LINK", "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1243         "JME_SMBCSR",   "JME_SMBINTF"};
1244
1245 static char *MISC_REG_NAME[] = {
1246         "JME_TMCSR",  "JME_GPIO",     "JME_GPREG0",  "JME_GPREG1",
1247         "JME_IEVE",   "JME_IREQ",     "JME_IENS",    "JME_IENC",
1248         "JME_PCCRX0", "JME_PCCRX1",   "JME_PCCRX2",  "JME_PCCRX3",
1249         "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO",
1250         "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1251         "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1252         "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1253         "JME_TIMER1", "JME_TIMER2",   "UNKNOWN",     "JME_APMC",
1254         "JME_PCCSRX0"};
1255
1256 static inline void reg_dbg(const struct jme_adapter *jme,
1257                 const char *msg, u32 val, u32 reg)
1258 {
1259         const char *regname;
1260         switch (reg & 0xF00) {
1261         case 0x000:
1262                 regname = MAC_REG_NAME[(reg & 0xFF) >> 2];
1263                 break;
1264         case 0x400:
1265                 regname = PE_REG_NAME[(reg & 0xFF) >> 2];
1266                 break;
1267         case 0x800:
1268                 regname = MISC_REG_NAME[(reg & 0xFF) >> 2];
1269                 break;
1270         default:
1271                 regname = PE_REG_NAME[0];
1272         }
1273         printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name,
1274                         msg, val, regname);
1275 }
1276 #else
1277 static inline void reg_dbg(const struct jme_adapter *jme,
1278                 const char *msg, u32 val, u32 reg) {}
1279 #endif
1280
1281 /*
1282  * Read/Write MMaped I/O Registers
1283  */
1284 static inline u32 jread32(struct jme_adapter *jme, u32 reg)
1285 {
1286         return readl(jme->regs + reg);
1287 }
1288
1289 static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val)
1290 {
1291         reg_dbg(jme, "REG WRITE", val, reg);
1292         writel(val, jme->regs + reg);
1293         reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1294 }
1295
1296 static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val)
1297 {
1298         /*
1299          * Read after write should cause flush
1300          */
1301         reg_dbg(jme, "REG WRITE FLUSH", val, reg);
1302         writel(val, jme->regs + reg);
1303         readl(jme->regs + reg);
1304         reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1305 }
1306
1307 /*
1308  * PHY Regs
1309  */
1310 enum jme_phy_reg17_bit_masks {
1311         PREG17_SPEED            = 0xC000,
1312         PREG17_DUPLEX           = 0x2000,
1313         PREG17_SPDRSV           = 0x0800,
1314         PREG17_LNKUP            = 0x0400,
1315         PREG17_MDI              = 0x0040,
1316 };
1317
1318 enum jme_phy_reg17_vals {
1319         PREG17_SPEED_10M        = 0x0000,
1320         PREG17_SPEED_100M       = 0x4000,
1321         PREG17_SPEED_1000M      = 0x8000,
1322 };
1323
1324 #define BMSR_ANCOMP               0x0020
1325
1326 /*
1327  * Workaround
1328  */
1329 static inline int is_buggy250(unsigned short device, u8 chiprev)
1330 {
1331         return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
1332 }
1333
1334 /*
1335  * Function prototypes
1336  */
1337 static int jme_set_settings(struct net_device *netdev,
1338                                 struct ethtool_cmd *ecmd);
1339 static void jme_set_multi(struct net_device *netdev);
1340
1341 #endif
1342