jme.h

   1 /*
   2  * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
   3  *
   4  * Copyright 2008 JMicron Technology Corporation
   5  * http://www.jmicron.com/
   6  *
   7  * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  *
  22  */
  23
  24 #include <linux/version.h>
  25
  26 #define DRV_NAME        "jme"
  27 #define DRV_VERSION     "0.5"
  28 #define PFX DRV_NAME    ": "
  29
  30 #ifdef DEBUG
  31 #define dprintk(devname, fmt, args...) \
  32         printk(KERN_DEBUG "%s: " fmt, devname, ## args)
  33 #else
  34 #define dprintk(devname, fmt, args...)
  35 #endif
  36
  37 #ifdef TX_DEBUG
  38 #define tx_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
  39 #else
  40 #define tx_dbg(args...)
  41 #endif
  42
  43 #ifdef RX_DEBUG
  44 #define rx_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
  45 #else
  46 #define rx_dbg(args...)
  47 #endif
  48
  49 #define jprintk(devname, fmt, args...) \
  50         printk(KERN_INFO "%s: " fmt, devname, ## args)
  51
  52 #define jeprintk(devname, fmt, args...) \
  53         printk(KERN_ERR "%s: " fmt, devname, ## args)
  54
  55 #define USE_IEVE_SHADOW 0
  56
  57 #define DEFAULT_MSG_ENABLE        \
  58         (NETIF_MSG_DRV          | \
  59          NETIF_MSG_PROBE        | \
  60          NETIF_MSG_LINK         | \
  61          NETIF_MSG_TIMER        | \
  62          NETIF_MSG_RX_ERR       | \
  63          NETIF_MSG_TX_ERR)
  64
  65 #define PCI_CONF_DCSR_MRRS      0x59
  66 #define PCI_CONF_DCSR_MRRS_MASK 0x70
  67 enum pci_conf_dcsr_mrrs_vals {
  68         MRRS_128B       = 0x00,
  69         MRRS_256B       = 0x10,
  70         MRRS_512B       = 0x20,
  71         MRRS_1024B      = 0x30,
  72         MRRS_2048B      = 0x40,
  73         MRRS_4096B      = 0x50,
  74 };
  75
  76 enum dynamic_pcc_values {
  77         PCC_P1          = 1,
  78         PCC_P2          = 2,
  79         PCC_P3          = 3,
  80
  81         PCC_P1_TO       = 1,
  82         PCC_P2_TO       = 250,
  83         PCC_P3_TO       = 1000,
  84
  85         PCC_P1_CNT      = 1,
  86         PCC_P2_CNT      = 64,
  87         PCC_P3_CNT      = 255,
  88 };
  89 struct dynpcc_info {
  90         unsigned long   check_point;
  91         unsigned long   last_bytes;
  92         unsigned long   last_pkts;
  93         unsigned char   cur;
  94         unsigned char   attempt;
  95         unsigned char   cnt;
  96 };
  97 #define PCC_INTERVAL (HZ / 10)
  98 #define PCC_P3_THRESHOLD 3*1024*1024
  99 #define PCC_P2_THRESHOLD 1000
 100 #define PCC_TX_TO 60000
 101 #define PCC_TX_CNT 8
 102
 103 /*
 104  * TX/RX Descriptors
 105  *
 106  * TX/RX Ring DESC Count Must be multiple of 16
 107  * RX Ring DESC Count Must be <= 1024
 108  */
 109 #define RING_DESC_NR            512     /* Must be power of 2 */
 110 #define RING_DESC_ALIGN         16      /* Descriptor alignment */
 111
 112 #define TX_DESC_SIZE            16
 113 #define TX_RING_NR              8
 114 #define TX_RING_ALLOC_SIZE      (RING_DESC_NR * TX_DESC_SIZE) + TX_DESC_SIZE
 115 #define TX_RING_SIZE            (RING_DESC_NR * TX_DESC_SIZE)
 116
 117 struct txdesc {
 118         union {
 119                 __u8  all[16];
 120                 __u32 dw[4];
 121                 struct {
 122                         /* DW0 */
 123                         __u16 vlan;
 124                         __u8 rsv1;
 125                         __u8 flags;
 126
 127                         /* DW1 */
 128                         __u16 datalen;
 129                         __u16 mss;
 130
 131                         /* DW2 */
 132                         __u16 pktsize;
 133                         __u16 rsv2;
 134
 135                         /* DW3 */
 136                         __u32 bufaddr;
 137                 } desc1;
 138                 struct {
 139                         /* DW0 */
 140                         __u16 rsv1;
 141                         __u8 rsv2;
 142                         __u8 flags;
 143
 144                         /* DW1 */
 145                         __u16 datalen;
 146                         __u16 rsv3;
 147
 148                         /* DW2 */
 149                         __u32 bufaddrh;
 150
 151                         /* DW3 */
 152                         __u32 bufaddrl;
 153                 } desc2;
 154                 struct {
 155                         /* DW0 */
 156                         __u8 ehdrsz;
 157                         __u8 rsv1;
 158                         __u8 rsv2;
 159                         __u8 flags;
 160
 161                         /* DW1 */
 162                         __u16 trycnt;
 163                         __u16 segcnt;
 164
 165                         /* DW2 */
 166                         __u16 pktsz;
 167                         __u16 rsv3;
 168
 169                         /* DW3 */
 170                         __u32 bufaddrl;
 171                 } descwb;
 172         };
 173 };
 174 enum jme_txdesc_flags_bits {
 175         TXFLAG_OWN      = 0x80,
 176         TXFLAG_INT      = 0x40,
 177         TXFLAG_64BIT    = 0x20,
 178         TXFLAG_TCPCS    = 0x10,
 179         TXFLAG_UDPCS    = 0x08,
 180         TXFLAG_IPCS     = 0x04,
 181         TXFLAG_LSEN     = 0x02,
 182         TXFLAG_TAGON    = 0x01,
 183 };
 184 enum jme_rxdescwb_flags_bits {
 185         TXWBFLAG_OWN    = 0x80,
 186         TXWBFLAG_INT    = 0x40,
 187         TXWBFLAG_TMOUT  = 0x20,
 188         TXWBFLAG_TRYOUT = 0x10,
 189         TXWBFLAG_COL    = 0x08,
 190
 191         TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
 192                           TXWBFLAG_TRYOUT |
 193                           TXWBFLAG_COL,
 194 };
 195
 196
 197 #define RX_DESC_SIZE            16
 198 #define RX_RING_NR              4
 199 #define RX_RING_ALLOC_SIZE      (RING_DESC_NR * RX_DESC_SIZE) + RX_DESC_SIZE
 200 #define RX_RING_SIZE            (RING_DESC_NR * RX_DESC_SIZE)
 201
 202 #define RX_BUF_DMA_ALIGN        8
 203 #define RX_BUF_SIZE             9216
 204 #define RX_PREPAD_SIZE          10
 205
 206 /*
 207  * Will use mtu in the future
 208  */
 209 #define RX_BUF_ALLOC_SIZE       RX_BUF_SIZE + RX_BUF_DMA_ALIGN
 210
 211 struct rxdesc {
 212         union {
 213                 __u8   all[16];
 214                 __le32 dw[4];
 215                 struct {
 216                         /* DW0 */
 217                         __le16 rsv2;
 218                         __u8 rsv1;
 219                         __u8 flags;
 220
 221                         /* DW1 */
 222                         __le16 datalen;
 223                         __le16 wbcpl;
 224
 225                         /* DW2 */
 226                         __le32 bufaddrh;
 227
 228                         /* DW3 */
 229                         __le32 bufaddrl;
 230                 } desc1;
 231                 struct {
 232                         /* DW0 */
 233                         __le16 vlan;
 234                         __le16 flags;
 235
 236                         /* DW1 */
 237                         __le16 framesize;
 238                         __u8 errstat;
 239                         __u8 desccnt;
 240
 241                         /* DW2 */
 242                         __le32 rsshash;
 243
 244                         /* DW3 */
 245                         __u8   hashfun;
 246                         __u8   hashtype;
 247                         __le16 resrv;
 248                 } descwb;
 249         };
 250 };
 251 enum jme_rxdesc_flags_bits {
 252         RXFLAG_OWN      = 0x80,
 253         RXFLAG_INT      = 0x40,
 254         RXFLAG_64BIT    = 0x20,
 255 };
 256 enum jme_rxwbdesc_flags_bits {
 257         RXWBFLAG_OWN            = 0x8000,
 258         RXWBFLAG_INT            = 0x4000,
 259         RXWBFLAG_MF             = 0x2000,
 260         RXWBFLAG_64BIT          = 0x2000,
 261         RXWBFLAG_TCPON          = 0x1000,
 262         RXWBFLAG_UDPON          = 0x0800,
 263         RXWBFLAG_IPCS           = 0x0400,
 264         RXWBFLAG_TCPCS          = 0x0200,
 265         RXWBFLAG_UDPCS          = 0x0100,
 266         RXWBFLAG_TAGON          = 0x0080,
 267         RXWBFLAG_IPV4           = 0x0040,
 268         RXWBFLAG_IPV6           = 0x0020,
 269         RXWBFLAG_PAUSE          = 0x0010,
 270         RXWBFLAG_MAGIC          = 0x0008,
 271         RXWBFLAG_WAKEUP         = 0x0004,
 272         RXWBFLAG_DEST           = 0x0003,
 273         RXWBFLAG_DEST_UNI       = 0x0001,
 274         RXWBFLAG_DEST_MUL       = 0x0002,
 275         RXWBFLAG_DEST_BRO       = 0x0003,
 276 };
 277 enum jme_rxwbdesc_desccnt_mask {
 278         RXWBDCNT_WBCPL  = 0x80,
 279         RXWBDCNT_DCNT   = 0x7F,
 280 };
 281 enum jme_rxwbdesc_errstat_bits {
 282         RXWBERR_LIMIT   = 0x80,
 283         RXWBERR_MIIER   = 0x40,
 284         RXWBERR_NIBON   = 0x20,
 285         RXWBERR_COLON   = 0x10,
 286         RXWBERR_ABORT   = 0x08,
 287         RXWBERR_SHORT   = 0x04,
 288         RXWBERR_OVERUN  = 0x02,
 289         RXWBERR_CRCERR  = 0x01,
 290         RXWBERR_ALLERR  = 0xFF,
 291 };
 292
 293 struct jme_buffer_info {
 294         struct sk_buff *skb;
 295         dma_addr_t mapping;
 296         int len;
 297         int nr_desc;
 298 };
 299
 300 struct jme_ring {
 301         void* alloc;            /* pointer to allocated memory */
 302         volatile void* desc;    /* pointer to ring memory  */
 303         dma_addr_t dmaalloc;    /* phys address of ring alloc */
 304         dma_addr_t dma;         /* phys address for ring dma */
 305
 306         /* Buffer information corresponding to each descriptor */
 307         struct jme_buffer_info bufinf[RING_DESC_NR];
 308
 309         u16 next_to_use;
 310         u16 next_to_clean;
 311
 312         u16 nr_free;
 313 };
 314
 315 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
 316 #define NET_STAT(priv) priv->stats
 317 #define NETDEV_GET_STATS(netdev, fun_ptr) \
 318         netdev->get_stats = fun_ptr
 319 #define DECLARE_NET_DEVICE_STATS struct net_device_stats stats;
 320 #else
 321 #define NET_STAT(priv) priv->dev->stats
 322 #define NETDEV_GET_STATS(netdev, fun_ptr)
 323 #define DECLARE_NET_DEVICE_STATS
 324 #endif
 325
 326 /*
 327  * Jmac Adapter Private data
 328  */
 329 #define SHADOW_REG_NR 8
 330 struct jme_adapter {
 331         struct pci_dev          *pdev;
 332         struct net_device       *dev;
 333         void __iomem            *regs;
 334         dma_addr_t              shadow_dma;
 335         __u32                   *shadow_regs;
 336         struct mii_if_info      mii_if;
 337         struct jme_ring         rxring[RX_RING_NR];
 338         struct jme_ring         txring[TX_RING_NR];
 339         spinlock_t              tx_lock;
 340         spinlock_t              phy_lock;
 341         spinlock_t              macaddr_lock;
 342         spinlock_t              rxmcs_lock;
 343         struct tasklet_struct   rxempty_task;
 344         struct tasklet_struct   rxclean_task;
 345         struct tasklet_struct   txclean_task;
 346         struct tasklet_struct   linkch_task;
 347         __u32                   features;
 348         __u32                   reg_txcs;
 349         __u32                   reg_txpfc;
 350         __u32                   reg_rxmcs;
 351         __u32                   reg_ghc;
 352         __u32                   phylink;
 353         __u8                    mrrs;
 354         struct dynpcc_info      dpi;
 355         atomic_t                intr_sem;
 356         atomic_t                link_changing;
 357         atomic_t                tx_cleaning;
 358         atomic_t                rx_cleaning;
 359         DECLARE_NET_DEVICE_STATS
 360 };
 361 enum shadow_reg_val {
 362         SHADOW_IEVE = 0,
 363 };
 364 enum jme_features_bits {
 365         JME_FEATURE_LALALA      = 0x00000001,
 366 };
 367 #define WAIT_TASKLET_TIMEOUT    500 /* 500 ms */
 368 #define TX_TIMEOUT              (5*HZ)
 369
 370
 371 /*
 372  * MMaped I/O Resters
 373  */
 374 enum jme_iomap_offsets {
 375         JME_MAC         = 0x0000,
 376         JME_PHY         = 0x0400,
 377         JME_MISC        = 0x0800,
 378         JME_RSS         = 0x0C00,
 379 };
 380
 381 enum jme_iomap_lens {
 382         JME_MAC_LEN     = 0x80,
 383         JME_PHY_LEN     = 0x58,
 384         JME_MISC_LEN    = 0x98,
 385         JME_RSS_LEN     = 0xFF,
 386 };
 387
 388 enum jme_iomap_regs {
 389         JME_TXCS        = JME_MAC | 0x00, /* Transmit Control and Status */
 390         JME_TXDBA_LO    = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
 391         JME_TXDBA_HI    = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
 392         JME_TXQDC       = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
 393         JME_TXNDA       = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
 394         JME_TXMCS       = JME_MAC | 0x14, /* Transmit MAC Control Status */
 395         JME_TXPFC       = JME_MAC | 0x18, /* Transmit Pause Frame Control */
 396         JME_TXTRHD      = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
 397
 398         JME_RXCS        = JME_MAC | 0x20, /* Receive Control and Status */
 399         JME_RXDBA_LO    = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
 400         JME_RXDBA_HI    = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
 401         JME_RXQDC       = JME_MAC | 0x2C, /* Receive Queue Desc Count */
 402         JME_RXNDA       = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
 403         JME_RXMCS       = JME_MAC | 0x34, /* Receive MAC Control Status */
 404         JME_RXUMA_LO    = JME_MAC | 0x38, /* Receive Unicast MAC Address */
 405         JME_RXUMA_HI    = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
 406         JME_RXMCHT_LO   = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
 407         JME_RXMCHT_HI   = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
 408         JME_WFODP       = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
 409         JME_WFOI        = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
 410
 411         JME_SMI         = JME_MAC | 0x50, /* Station Management Interface */
 412         JME_GHC         = JME_MAC | 0x54, /* Global Host Control */
 413         JME_PMCS        = JME_MAC | 0x60, /* Power Management Control/Stat */
 414
 415
 416         JME_PHY_CS      = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
 417         JME_PHY_LINK    = JME_PHY | 0x30, /* PHY Link Status Register */
 418         JME_SMBCSR      = JME_PHY | 0x40, /* SMB Control and Status */
 419
 420
 421         JME_GPREG0      = JME_MISC| 0x08, /* General purpose REG-0 */
 422         JME_GPREG1      = JME_MISC| 0x0C, /* General purpose REG-1 */
 423         JME_IEVE        = JME_MISC| 0x20, /* Interrupt Event Status */
 424         JME_IREQ        = JME_MISC| 0x24, /* Interrupt Req Status(For Debug) */
 425         JME_IENS        = JME_MISC| 0x28, /* Interrupt Enable - Setting Port */
 426         JME_IENC        = JME_MISC| 0x2C, /* Interrupt Enable - Clear Port */
 427         JME_PCCRX0      = JME_MISC| 0x30, /* PCC Control for RX Queue 0 */
 428         JME_PCCTX       = JME_MISC| 0x40, /* PCC Control for TX Queues */
 429         JME_SHBA_HI     = JME_MISC| 0x48, /* Shadow Register Base HI */
 430         JME_SHBA_LO     = JME_MISC| 0x4C, /* Shadow Register Base LO */
 431         JME_PCCSRX0     = JME_MISC| 0x80, /* PCC Status of RX0 */
 432 };
 433
 434 /*
 435  * TX Control/Status Bits
 436  */
 437 enum jme_txcs_bits {
 438         TXCS_QUEUE7S    = 0x00008000,
 439         TXCS_QUEUE6S    = 0x00004000,
 440         TXCS_QUEUE5S    = 0x00002000,
 441         TXCS_QUEUE4S    = 0x00001000,
 442         TXCS_QUEUE3S    = 0x00000800,
 443         TXCS_QUEUE2S    = 0x00000400,
 444         TXCS_QUEUE1S    = 0x00000200,
 445         TXCS_QUEUE0S    = 0x00000100,
 446         TXCS_FIFOTH     = 0x000000C0,
 447         TXCS_DMASIZE    = 0x00000030,
 448         TXCS_BURST      = 0x00000004,
 449         TXCS_ENABLE     = 0x00000001,
 450 };
 451 enum jme_txcs_value {
 452         TXCS_FIFOTH_16QW        = 0x000000C0,
 453         TXCS_FIFOTH_12QW        = 0x00000080,
 454         TXCS_FIFOTH_8QW         = 0x00000040,
 455         TXCS_FIFOTH_4QW         = 0x00000000,
 456
 457         TXCS_DMASIZE_64B        = 0x00000000,
 458         TXCS_DMASIZE_128B       = 0x00000010,
 459         TXCS_DMASIZE_256B       = 0x00000020,
 460         TXCS_DMASIZE_512B       = 0x00000030,
 461
 462         TXCS_SELECT_QUEUE0      = 0x00000000,
 463         TXCS_SELECT_QUEUE1      = 0x00010000,
 464         TXCS_SELECT_QUEUE2      = 0x00020000,
 465         TXCS_SELECT_QUEUE3      = 0x00030000,
 466         TXCS_SELECT_QUEUE4      = 0x00040000,
 467         TXCS_SELECT_QUEUE5      = 0x00050000,
 468         TXCS_SELECT_QUEUE6      = 0x00060000,
 469         TXCS_SELECT_QUEUE7      = 0x00070000,
 470
 471         TXCS_DEFAULT            = TXCS_FIFOTH_4QW |
 472                                   TXCS_BURST,
 473 };
 474 #define JME_TX_DISABLE_TIMEOUT 5 /* 5 msec */
 475
 476 /*
 477  * TX MAC Control/Status Bits
 478  */
 479 enum jme_txmcs_bit_masks {
 480         TXMCS_IFG2              = 0xC0000000,
 481         TXMCS_IFG1              = 0x30000000,
 482         TXMCS_TTHOLD            = 0x00000300,
 483         TXMCS_FBURST            = 0x00000080,
 484         TXMCS_CARRIEREXT        = 0x00000040,
 485         TXMCS_DEFER             = 0x00000020,
 486         TXMCS_BACKOFF           = 0x00000010,
 487         TXMCS_CARRIERSENSE      = 0x00000008,
 488         TXMCS_COLLISION         = 0x00000004,
 489         TXMCS_CRC               = 0x00000002,
 490         TXMCS_PADDING           = 0x00000001,
 491 };
 492 enum jme_txmcs_values {
 493         TXMCS_IFG2_6_4          = 0x00000000,
 494         TXMCS_IFG2_8_5          = 0x40000000,
 495         TXMCS_IFG2_10_6         = 0x80000000,
 496         TXMCS_IFG2_12_7         = 0xC0000000,
 497
 498         TXMCS_IFG1_8_4          = 0x00000000,
 499         TXMCS_IFG1_12_6         = 0x10000000,
 500         TXMCS_IFG1_16_8         = 0x20000000,
 501         TXMCS_IFG1_20_10        = 0x30000000,
 502
 503         TXMCS_TTHOLD_1_8        = 0x00000000,
 504         TXMCS_TTHOLD_1_4        = 0x00000100,
 505         TXMCS_TTHOLD_1_2        = 0x00000200,
 506         TXMCS_TTHOLD_FULL       = 0x00000300,
 507
 508         TXMCS_DEFAULT           = TXMCS_IFG2_8_5 |
 509                                   TXMCS_IFG1_16_8 |
 510                                   TXMCS_TTHOLD_FULL |
 511                                   TXMCS_DEFER |
 512                                   TXMCS_CRC |
 513                                   TXMCS_PADDING,
 514 };
 515
 516 enum jme_txpfc_bits_masks {
 517         TXPFC_VLAN_TAG          = 0xFFFF0000,
 518         TXPFC_VLAN_EN           = 0x00008000,
 519         TXPFC_PF_EN             = 0x00000001,
 520 };
 521
 522 enum jme_txtrhd_bits_masks {
 523         TXTRHD_TXPEN            = 0x80000000,
 524         TXTRHD_TXP              = 0x7FFFFF00,
 525         TXTRHD_TXREN            = 0x00000080,
 526         TXTRHD_TXRL             = 0x0000007F,
 527 };
 528 enum jme_txtrhd_shifts {
 529         TXTRHD_TXP_SHIFT        = 8,
 530         TXTRHD_TXRL_SHIFT       = 0,
 531 };
 532
 533
 534 /*
 535  * RX Control/Status Bits
 536  */
 537 enum jme_rxcs_bit_masks {
 538         /* FIFO full threshold for transmitting Tx Pause Packet */
 539         RXCS_FIFOTHTP   = 0x30000000,
 540         /* FIFO threshold for processing next packet */
 541         RXCS_FIFOTHNP   = 0x0C000000,
 542         RXCS_DMAREQSZ   = 0x03000000, /* DMA Request Size */
 543         RXCS_QUEUESEL   = 0x00030000, /* Queue selection */
 544         RXCS_RETRYGAP   = 0x0000F000, /* RX Desc full retry gap */
 545         RXCS_RETRYCNT   = 0x00000F00, /* RX Desc full retry counter */
 546         RXCS_WAKEUP     = 0x00000040, /* Enable receive wakeup packet */
 547         RXCS_MAGIC      = 0x00000020, /* Enable receive magic packet */
 548         RXCS_SHORT      = 0x00000010, /* Enable receive short packet */
 549         RXCS_ABORT      = 0x00000008, /* Enable receive errorr packet */
 550         RXCS_QST        = 0x00000004, /* Receive queue start */
 551         RXCS_SUSPEND    = 0x00000002,
 552         RXCS_ENABLE     = 0x00000001,
 553 };
 554 enum jme_rxcs_values {
 555         RXCS_FIFOTHTP_16T       = 0x00000000,
 556         RXCS_FIFOTHTP_32T       = 0x10000000,
 557         RXCS_FIFOTHTP_64T       = 0x20000000,
 558         RXCS_FIFOTHTP_128T      = 0x30000000,
 559
 560         RXCS_FIFOTHNP_16QW      = 0x00000000,
 561         RXCS_FIFOTHNP_32QW      = 0x04000000,
 562         RXCS_FIFOTHNP_64QW      = 0x08000000,
 563         RXCS_FIFOTHNP_128QW     = 0x0C000000,
 564
 565         RXCS_DMAREQSZ_16B       = 0x00000000,
 566         RXCS_DMAREQSZ_32B       = 0x01000000,
 567         RXCS_DMAREQSZ_64B       = 0x02000000,
 568         RXCS_DMAREQSZ_128B      = 0x03000000,
 569
 570         RXCS_QUEUESEL_Q0        = 0x00000000,
 571         RXCS_QUEUESEL_Q1        = 0x00010000,
 572         RXCS_QUEUESEL_Q2        = 0x00020000,
 573         RXCS_QUEUESEL_Q3        = 0x00030000,
 574
 575         RXCS_RETRYGAP_256ns     = 0x00000000,
 576         RXCS_RETRYGAP_512ns     = 0x00001000,
 577         RXCS_RETRYGAP_1024ns    = 0x00002000,
 578         RXCS_RETRYGAP_2048ns    = 0x00003000,
 579         RXCS_RETRYGAP_4096ns    = 0x00004000,
 580         RXCS_RETRYGAP_8192ns    = 0x00005000,
 581         RXCS_RETRYGAP_16384ns   = 0x00006000,
 582         RXCS_RETRYGAP_32768ns   = 0x00007000,
 583
 584         RXCS_RETRYCNT_0         = 0x00000000,
 585         RXCS_RETRYCNT_4         = 0x00000100,
 586         RXCS_RETRYCNT_8         = 0x00000200,
 587         RXCS_RETRYCNT_12        = 0x00000300,
 588         RXCS_RETRYCNT_16        = 0x00000400,
 589         RXCS_RETRYCNT_20        = 0x00000500,
 590         RXCS_RETRYCNT_24        = 0x00000600,
 591         RXCS_RETRYCNT_28        = 0x00000700,
 592         RXCS_RETRYCNT_32        = 0x00000800,
 593         RXCS_RETRYCNT_36        = 0x00000900,
 594         RXCS_RETRYCNT_40        = 0x00000A00,
 595         RXCS_RETRYCNT_44        = 0x00000B00,
 596         RXCS_RETRYCNT_48        = 0x00000C00,
 597         RXCS_RETRYCNT_52        = 0x00000D00,
 598         RXCS_RETRYCNT_56        = 0x00000E00,
 599         RXCS_RETRYCNT_60        = 0x00000F00,
 600
 601         RXCS_DEFAULT            = RXCS_FIFOTHTP_128T |
 602                                   //RXCS_FIFOTHNP_128QW |
 603                                   RXCS_FIFOTHNP_32QW |
 604                                   RXCS_DMAREQSZ_128B |
 605                                   RXCS_RETRYGAP_256ns |
 606                                   RXCS_RETRYCNT_32,
 607 };
 608 #define JME_RX_DISABLE_TIMEOUT 5 /* 5 msec */
 609
 610 /*
 611  * RX MAC Control/Status Bits
 612  */
 613 enum jme_rxmcs_bits {
 614         RXMCS_ALLFRAME          = 0x00000800,
 615         RXMCS_BRDFRAME          = 0x00000400,
 616         RXMCS_MULFRAME          = 0x00000200,
 617         RXMCS_UNIFRAME          = 0x00000100,
 618         RXMCS_ALLMULFRAME       = 0x00000080,
 619         RXMCS_MULFILTERED       = 0x00000040,
 620         RXMCS_RXCOLLDEC         = 0x00000020,
 621         RXMCS_FLOWCTRL          = 0x00000008,
 622         RXMCS_VTAGRM            = 0x00000004,
 623         RXMCS_PREPAD            = 0x00000002,
 624         RXMCS_CHECKSUM          = 0x00000001,
 625
 626         RXMCS_DEFAULT           = RXMCS_VTAGRM |
 627                                   RXMCS_PREPAD |
 628                                   RXMCS_FLOWCTRL |
 629                                   RXMCS_CHECKSUM,
 630 };
 631
 632 /*
 633  * SMI Related definitions
 634  */
 635 enum jme_smi_bit_mask
 636 {
 637         SMI_DATA_MASK           = 0xFFFF0000,
 638         SMI_REG_ADDR_MASK       = 0x0000F800,
 639         SMI_PHY_ADDR_MASK       = 0x000007C0,
 640         SMI_OP_WRITE            = 0x00000020,
 641         /* Set to 1, after req done it'll be cleared to 0 */
 642         SMI_OP_REQ              = 0x00000010,
 643         SMI_OP_MDIO             = 0x00000008, /* Software assess In/Out */
 644         SMI_OP_MDOE             = 0x00000004, /* Software Output Enable */
 645         SMI_OP_MDC              = 0x00000002, /* Software CLK Control */
 646         SMI_OP_MDEN             = 0x00000001, /* Software access Enable */
 647 };
 648 enum jme_smi_bit_shift
 649 {
 650         SMI_DATA_SHIFT          = 16,
 651         SMI_REG_ADDR_SHIFT      = 11,
 652         SMI_PHY_ADDR_SHIFT      = 6,
 653 };
 654 __always_inline __u32 smi_reg_addr(int x)
 655 {
 656         return (((x) << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK);
 657 }
 658 __always_inline __u32 smi_phy_addr(int x)
 659 {
 660         return (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK);
 661 }
 662 #define JME_PHY_TIMEOUT 1000 /* 1000 usec */
 663
 664 /*
 665  * Global Host Control
 666  */
 667 enum jme_ghc_bit_mask {
 668         GHC_SWRST       = 0x40000000,
 669         GHC_DPX         = 0x00000040,
 670         GHC_SPEED       = 0x00000030,
 671         GHC_LINK_POLL   = 0x00000001,
 672 };
 673 enum jme_ghc_speed_val {
 674         GHC_SPEED_10M   = 0x00000010,
 675         GHC_SPEED_100M  = 0x00000020,
 676         GHC_SPEED_1000M = 0x00000030,
 677 };
 678
 679 /*
 680  * Giga PHY Status Registers
 681  */
 682 enum jme_phy_link_bit_mask {
 683         PHY_LINK_SPEED_MASK             = 0x0000C000,
 684         PHY_LINK_DUPLEX                 = 0x00002000,
 685         PHY_LINK_SPEEDDPU_RESOLVED      = 0x00000800,
 686         PHY_LINK_UP                     = 0x00000400,
 687         PHY_LINK_AUTONEG_COMPLETE       = 0x00000200,
 688         PHY_LINK_MDI_STAT               = 0x00000040,
 689 };
 690 enum jme_phy_link_speed_val {
 691         PHY_LINK_SPEED_10M              = 0x00000000,
 692         PHY_LINK_SPEED_100M             = 0x00004000,
 693         PHY_LINK_SPEED_1000M            = 0x00008000,
 694 };
 695 #define JME_SPDRSV_TIMEOUT      500     /* 500 us */
 696
 697 /*
 698  * SMB Control and Status
 699  */
 700 enum jme_smbcsr_bit_mask
 701 {
 702         SMBCSR_CNACK    = 0x00020000,
 703         SMBCSR_RELOAD   = 0x00010000,
 704         SMBCSR_EEPROMD  = 0x00000020,
 705 };
 706 #define JME_SMB_TIMEOUT 10 /* 10 msec */
 707
 708
 709 /*
 710  * General Purpost REG-0
 711  */
 712 enum jme_gpreg0_masks {
 713         GPREG0_DISSH            = 0xFF000000,
 714         GPREG0_PCIRLMT          = 0x00300000,
 715         GPREG0_PCCNOMUTCLR      = 0x00040000,
 716         GPREG0_PCCTMR           = 0x00000300,
 717         GPREG0_PHYADDR          = 0x0000001F,
 718 };
 719 enum jme_gpreg0_vals {
 720         GPREG0_DISSH_DW7        = 0x80000000,
 721         GPREG0_DISSH_DW6        = 0x40000000,
 722         GPREG0_DISSH_DW5        = 0x20000000,
 723         GPREG0_DISSH_DW4        = 0x10000000,
 724         GPREG0_DISSH_DW3        = 0x08000000,
 725         GPREG0_DISSH_DW2        = 0x04000000,
 726         GPREG0_DISSH_DW1        = 0x02000000,
 727         GPREG0_DISSH_DW0        = 0x01000000,
 728         GPREG0_DISSH_ALL        = 0xFF000000,
 729
 730         GPREG0_PCIRLMT_8        = 0x00000000,
 731         GPREG0_PCIRLMT_6        = 0x00100000,
 732         GPREG0_PCIRLMT_5        = 0x00200000,
 733         GPREG0_PCIRLMT_4        = 0x00300000,
 734
 735         GPREG0_PCCTMR_16ns      = 0x00000000,
 736         GPREG0_PCCTMR_256ns     = 0x00000100,
 737         GPREG0_PCCTMR_1us       = 0x00000200,
 738         GPREG0_PCCTMR_1ms       = 0x00000300,
 739
 740         GPREG0_PHYADDR_1        = 0x00000001,
 741
 742         GPREG0_DEFAULT          = GPREG0_PCIRLMT_4 |
 743                                   GPREG0_PCCNOMUTCLR |
 744                                   GPREG0_PCCTMR_1us |
 745                                   GPREG0_PHYADDR_1,
 746 };
 747
 748 /*
 749  * Interrupt Status Bits
 750  */
 751 enum jme_interrupt_bits
 752 {
 753         INTR_SWINTR     = 0x80000000,
 754         INTR_TMINTR     = 0x40000000,
 755         INTR_LINKCH     = 0x20000000,
 756         INTR_PAUSERCV   = 0x10000000,
 757         INTR_MAGICRCV   = 0x08000000,
 758         INTR_WAKERCV    = 0x04000000,
 759         INTR_PCCRX0TO   = 0x02000000,
 760         INTR_PCCRX1TO   = 0x01000000,
 761         INTR_PCCRX2TO   = 0x00800000,
 762         INTR_PCCRX3TO   = 0x00400000,
 763         INTR_PCCTXTO    = 0x00200000,
 764         INTR_PCCRX0     = 0x00100000,
 765         INTR_PCCRX1     = 0x00080000,
 766         INTR_PCCRX2     = 0x00040000,
 767         INTR_PCCRX3     = 0x00020000,
 768         INTR_PCCTX      = 0x00010000,
 769         INTR_RX3EMP     = 0x00008000,
 770         INTR_RX2EMP     = 0x00004000,
 771         INTR_RX1EMP     = 0x00002000,
 772         INTR_RX0EMP     = 0x00001000,
 773         INTR_RX3        = 0x00000800,
 774         INTR_RX2        = 0x00000400,
 775         INTR_RX1        = 0x00000200,
 776         INTR_RX0        = 0x00000100,
 777         INTR_TX7        = 0x00000080,
 778         INTR_TX6        = 0x00000040,
 779         INTR_TX5        = 0x00000020,
 780         INTR_TX4        = 0x00000010,
 781         INTR_TX3        = 0x00000008,
 782         INTR_TX2        = 0x00000004,
 783         INTR_TX1        = 0x00000002,
 784         INTR_TX0        = 0x00000001,
 785 };
 786 static const __u32 INTR_ENABLE = INTR_LINKCH |
 787                                  INTR_RX0EMP |
 788                                  INTR_PCCRX0TO |
 789                                  INTR_PCCRX0 |
 790                                  INTR_PCCTXTO |
 791                                  INTR_PCCTX;
 792
 793 /*
 794  * PCC Control Registers
 795  */
 796 enum jme_pccrx_masks {
 797         PCCRXTO_MASK    = 0xFFFF0000,
 798         PCCRX_MASK      = 0x0000FF00,
 799 };
 800 enum jme_pcctx_masks {
 801         PCCTXTO_MASK    = 0xFFFF0000,
 802         PCCTX_MASK      = 0x0000FF00,
 803         PCCTX_QS_MASK   = 0x000000FF,
 804 };
 805 enum jme_pccrx_shifts {
 806         PCCRXTO_SHIFT   = 16,
 807         PCCRX_SHIFT     = 8,
 808 };
 809 enum jme_pcctx_shifts {
 810         PCCTXTO_SHIFT   = 16,
 811         PCCTX_SHIFT     = 8,
 812 };
 813 enum jme_pcctx_bits {
 814         PCCTXQ0_EN      = 0x00000001,
 815         PCCTXQ1_EN      = 0x00000002,
 816         PCCTXQ2_EN      = 0x00000004,
 817         PCCTXQ3_EN      = 0x00000008,
 818         PCCTXQ4_EN      = 0x00000010,
 819         PCCTXQ5_EN      = 0x00000020,
 820         PCCTXQ6_EN      = 0x00000040,
 821         PCCTXQ7_EN      = 0x00000080,
 822 };
 823
 824
 825 /*
 826  * Shadow base address register bits
 827  */
 828 enum jme_shadow_base_address_bits {
 829         SHBA_POSTEN     = 0x1,
 830 };
 831
 832 /*
 833  * Read/Write MMaped I/O Registers
 834  */
 835 __always_inline __u32 jread32(struct jme_adapter *jme, __u32 reg)
 836 {
 837         return le32_to_cpu(readl(jme->regs + reg));
 838 }
 839 __always_inline void jwrite32(struct jme_adapter *jme, __u32 reg, __u32 val)
 840 {
 841         writel(cpu_to_le32(val), jme->regs + reg);
 842 }
 843 __always_inline void jwrite32f(struct jme_adapter *jme, __u32 reg, __u32 val)
 844 {
 845         /*
 846          * Read after write should cause flush
 847          */
 848         writel(cpu_to_le32(val), jme->regs + reg);
 849         readl(jme->regs + reg);
 850 }
 851
 852 /*
 853  * Function prototypes for ethtool
 854  */
 855 static void jme_get_drvinfo(struct net_device *netdev,
 856                              struct ethtool_drvinfo *info);
 857 static int jme_get_settings(struct net_device *netdev,
 858                              struct ethtool_cmd *ecmd);
 859 static int jme_set_settings(struct net_device *netdev,
 860                              struct ethtool_cmd *ecmd);
 861 static u32 jme_get_link(struct net_device *netdev);
 862
 863
 864 /*
 865  * Function prototypes for netdev
 866  */
 867 static int jme_open(struct net_device *netdev);
 868 static int jme_close(struct net_device *netdev);
 869 static int jme_start_xmit(struct sk_buff *skb, struct net_device *netdev);
 870 static int jme_set_macaddr(struct net_device *netdev, void *p);
 871 static void jme_set_multi(struct net_device *netdev);
 872
 873