jme.h

   1 /*
   2  * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
   3  *
   4  * Copyright 2008 JMicron Technology Corporation
   5  * http://www.jmicron.com/
   6  * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
   7  *
   8  * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22  *
  23  */
  24
  25 #ifndef __JME_H_INCLUDED__
  26 #define __JME_H_INCLUDED__
  27
  28 #define DRV_NAME        "jme"
  29 #define DRV_VERSION     "1.0.7-jmmod"
  30 #define PFX             DRV_NAME ": "
  31
  32 #define PCI_DEVICE_ID_JMICRON_JMC250    0x0250
  33 #define PCI_DEVICE_ID_JMICRON_JMC260    0x0260
  34
  35 /*
  36  * Message related definitions
  37  */
  38 #define JME_DEF_MSG_ENABLE \
  39         (NETIF_MSG_PROBE | \
  40         NETIF_MSG_LINK | \
  41         NETIF_MSG_RX_ERR | \
  42         NETIF_MSG_TX_ERR | \
  43         NETIF_MSG_HW)
  44
  45 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
  46 #define pr_err(fmt, arg...) \
  47         printk(KERN_ERR fmt, ##arg)
  48 #endif
  49 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
  50 #define netdev_err(netdev, fmt, arg...) \
  51         pr_err(fmt, ##arg)
  52 #endif
  53
  54 #ifdef TX_DEBUG
  55 #define tx_dbg(priv, fmt, args...)                                      \
  56         printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args)
  57 #else
  58 #define tx_dbg(priv, fmt, args...)                                      \
  59 do {                                                                    \
  60         if (0)                                                          \
  61                 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args); \
  62 } while (0)
  63 #endif
  64
  65 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
  66 #define jme_msg(msglvl, type, priv, fmt, args...) \
  67         if (netif_msg_##type(priv)) \
  68                 printk(msglvl "%s: " fmt, (priv)->dev->name, ## args)
  69
  70 #define msg_probe(priv, fmt, args...) \
  71         jme_msg(KERN_INFO, probe, priv, fmt, ## args)
  72
  73 #define msg_link(priv, fmt, args...) \
  74         jme_msg(KERN_INFO, link, priv, fmt, ## args)
  75
  76 #define msg_intr(priv, fmt, args...) \
  77         jme_msg(KERN_INFO, intr, priv, fmt, ## args)
  78
  79 #define msg_rx_err(priv, fmt, args...) \
  80         jme_msg(KERN_ERR, rx_err, priv, fmt, ## args)
  81
  82 #define msg_rx_status(priv, fmt, args...) \
  83         jme_msg(KERN_INFO, rx_status, priv, fmt, ## args)
  84
  85 #define msg_tx_err(priv, fmt, args...) \
  86         jme_msg(KERN_ERR, tx_err, priv, fmt, ## args)
  87
  88 #define msg_tx_done(priv, fmt, args...) \
  89         jme_msg(KERN_INFO, tx_done, priv, fmt, ## args)
  90
  91 #define msg_tx_queued(priv, fmt, args...) \
  92         jme_msg(KERN_INFO, tx_queued, priv, fmt, ## args)
  93
  94 #define msg_hw(priv, fmt, args...) \
  95         jme_msg(KERN_ERR, hw, priv, fmt, ## args)
  96
  97 #define netif_info(priv, type, dev, fmt, args...) \
  98         msg_ ## type(priv, fmt, ## args)
  99 #define netif_err(priv, type, dev, fmt, args...) \
 100         msg_ ## type(priv, fmt, ## args)
 101 #endif
 102
 103 #ifndef NETIF_F_TSO6
 104 #define NETIF_F_TSO6 0
 105 #endif
 106 #ifndef NETIF_F_IPV6_CSUM
 107 #define NETIF_F_IPV6_CSUM 0
 108 #endif
 109
 110 /*
 111  * Extra PCI Configuration space interface
 112  */
 113 #define PCI_DCSR_MRRS           0x59
 114 #define PCI_DCSR_MRRS_MASK      0x70
 115
 116 enum pci_dcsr_mrrs_vals {
 117         MRRS_128B       = 0x00,
 118         MRRS_256B       = 0x10,
 119         MRRS_512B       = 0x20,
 120         MRRS_1024B      = 0x30,
 121         MRRS_2048B      = 0x40,
 122         MRRS_4096B      = 0x50,
 123 };
 124
 125 #define PCI_SPI                 0xB0
 126
 127 enum pci_spi_bits {
 128         SPI_EN          = 0x10,
 129         SPI_MISO        = 0x08,
 130         SPI_MOSI        = 0x04,
 131         SPI_SCLK        = 0x02,
 132         SPI_CS          = 0x01,
 133 };
 134
 135 struct jme_spi_op {
 136         void __user *uwbuf;
 137         void __user *urbuf;
 138         __u8    wn;     /* Number of write actions */
 139         __u8    rn;     /* Number of read actions */
 140         __u8    bitn;   /* Number of bits per action */
 141         __u8    spd;    /* The maxim acceptable speed of controller, in MHz.*/
 142         __u8    mode;   /* CPOL, CPHA, and Duplex mode of SPI */
 143
 144         /* Internal use only */
 145         u8      *kwbuf;
 146         u8      *krbuf;
 147         u8      sr;
 148         u16     halfclk; /* Half of clock cycle calculated from spd, in ns */
 149 };
 150
 151 enum jme_spi_op_bits {
 152         SPI_MODE_CPHA   = 0x01,
 153         SPI_MODE_CPOL   = 0x02,
 154         SPI_MODE_DUP    = 0x80,
 155 };
 156
 157 #define HALF_US 500     /* 500 ns */
 158 #define JMESPIIOCTL     SIOCDEVPRIVATE
 159
 160 #define PCI_PRIV_PE1            0xE4
 161
 162 enum pci_priv_pe1_bit_masks {
 163         PE1_ASPMSUPRT   = 0x00000003, /*
 164                                        * RW:
 165                                        * Aspm_support[1:0]
 166                                        * (R/W Port of 5C[11:10])
 167                                        */
 168         PE1_MULTIFUN    = 0x00000004, /* RW: Multi_fun_bit */
 169         PE1_RDYDMA      = 0x00000008, /* RO: ~link.rdy_for_dma */
 170         PE1_ASPMOPTL    = 0x00000030, /* RW: link.rx10s_option[1:0] */
 171         PE1_ASPMOPTH    = 0x000000C0, /* RW: 10_req=[3]?HW:[2] */
 172         PE1_GPREG0      = 0x0000FF00, /*
 173                                        * SRW:
 174                                        * Cfg_gp_reg0
 175                                        * [7:6] phy_giga BG control
 176                                        * [5] CREQ_N as CREQ_N1 (CPPE# as CREQ#)
 177                                        * [4:0] Reserved
 178                                        */
 179         PE1_GPREG0_PBG  = 0x0000C000, /* phy_giga BG control */
 180         PE1_GPREG1      = 0x00FF0000, /* RW: Cfg_gp_reg1 */
 181         PE1_REVID       = 0xFF000000, /* RO: Rev ID */
 182 };
 183
 184 enum pci_priv_pe1_values {
 185         PE1_GPREG0_ENBG         = 0x00000000, /* en BG */
 186         PE1_GPREG0_PDD3COLD     = 0x00004000, /* giga_PD + d3cold */
 187         PE1_GPREG0_PDPCIESD     = 0x00008000, /* giga_PD + pcie_shutdown */
 188         PE1_GPREG0_PDPCIEIDDQ   = 0x0000C000, /* giga_PD + pcie_iddq */
 189 };
 190
 191 /*
 192  * Dynamic(adaptive)/Static PCC values
 193  */
 194 enum dynamic_pcc_values {
 195         PCC_OFF         = 0,
 196         PCC_P1          = 1,
 197         PCC_P2          = 2,
 198         PCC_P3          = 3,
 199
 200         PCC_OFF_TO      = 0,
 201         PCC_P1_TO       = 1,
 202         PCC_P2_TO       = 64,
 203         PCC_P3_TO       = 128,
 204
 205         PCC_OFF_CNT     = 0,
 206         PCC_P1_CNT      = 1,
 207         PCC_P2_CNT      = 16,
 208         PCC_P3_CNT      = 32,
 209 };
 210 struct dynpcc_info {
 211         unsigned long   last_bytes;
 212         unsigned long   last_pkts;
 213         unsigned long   intr_cnt;
 214         unsigned char   cur;
 215         unsigned char   attempt;
 216         unsigned char   cnt;
 217 };
 218 #define PCC_INTERVAL_US 100000
 219 #define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
 220 #define PCC_P3_THRESHOLD (2 * 1024 * 1024)
 221 #define PCC_P2_THRESHOLD 800
 222 #define PCC_INTR_THRESHOLD 800
 223 #define PCC_TX_TO 1000
 224 #define PCC_TX_CNT 8
 225
 226 /*
 227  * TX/RX Descriptors
 228  *
 229  * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
 230  */
 231 #define RING_DESC_ALIGN         16      /* Descriptor alignment */
 232 #define TX_DESC_SIZE            16
 233 #define TX_RING_NR              8
 234 #define TX_RING_ALLOC_SIZE(s)   ((s * TX_DESC_SIZE) + RING_DESC_ALIGN)
 235
 236 struct txdesc {
 237         union {
 238                 __u8    all[16];
 239                 __le32  dw[4];
 240                 struct {
 241                         /* DW0 */
 242                         __le16  vlan;
 243                         __u8    rsv1;
 244                         __u8    flags;
 245
 246                         /* DW1 */
 247                         __le16  datalen;
 248                         __le16  mss;
 249
 250                         /* DW2 */
 251                         __le16  pktsize;
 252                         __le16  rsv2;
 253
 254                         /* DW3 */
 255                         __le32  bufaddr;
 256                 } desc1;
 257                 struct {
 258                         /* DW0 */
 259                         __le16  rsv1;
 260                         __u8    rsv2;
 261                         __u8    flags;
 262
 263                         /* DW1 */
 264                         __le16  datalen;
 265                         __le16  rsv3;
 266
 267                         /* DW2 */
 268                         __le32  bufaddrh;
 269
 270                         /* DW3 */
 271                         __le32  bufaddrl;
 272                 } desc2;
 273                 struct {
 274                         /* DW0 */
 275                         __u8    ehdrsz;
 276                         __u8    rsv1;
 277                         __u8    rsv2;
 278                         __u8    flags;
 279
 280                         /* DW1 */
 281                         __le16  trycnt;
 282                         __le16  segcnt;
 283
 284                         /* DW2 */
 285                         __le16  pktsz;
 286                         __le16  rsv3;
 287
 288                         /* DW3 */
 289                         __le32  bufaddrl;
 290                 } descwb;
 291         };
 292 };
 293
 294 enum jme_txdesc_flags_bits {
 295         TXFLAG_OWN      = 0x80,
 296         TXFLAG_INT      = 0x40,
 297         TXFLAG_64BIT    = 0x20,
 298         TXFLAG_TCPCS    = 0x10,
 299         TXFLAG_UDPCS    = 0x08,
 300         TXFLAG_IPCS     = 0x04,
 301         TXFLAG_LSEN     = 0x02,
 302         TXFLAG_TAGON    = 0x01,
 303 };
 304
 305 #define TXDESC_MSS_SHIFT        2
 306 enum jme_txwbdesc_flags_bits {
 307         TXWBFLAG_OWN    = 0x80,
 308         TXWBFLAG_INT    = 0x40,
 309         TXWBFLAG_TMOUT  = 0x20,
 310         TXWBFLAG_TRYOUT = 0x10,
 311         TXWBFLAG_COL    = 0x08,
 312
 313         TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
 314                           TXWBFLAG_TRYOUT |
 315                           TXWBFLAG_COL,
 316 };
 317
 318 #define RX_DESC_SIZE            16
 319 #define RX_RING_NR              4
 320 #define RX_RING_ALLOC_SIZE(s)   ((s * RX_DESC_SIZE) + RING_DESC_ALIGN)
 321 #define RX_BUF_DMA_ALIGN        8
 322 #define RX_PREPAD_SIZE          10
 323 #define ETH_CRC_LEN             2
 324 #define RX_VLANHDR_LEN          2
 325 #define RX_EXTRA_LEN            (RX_PREPAD_SIZE + \
 326                                 ETH_HLEN + \
 327                                 ETH_CRC_LEN + \
 328                                 RX_VLANHDR_LEN + \
 329                                 RX_BUF_DMA_ALIGN)
 330
 331 struct rxdesc {
 332         union {
 333                 __u8    all[16];
 334                 __le32  dw[4];
 335                 struct {
 336                         /* DW0 */
 337                         __le16  rsv2;
 338                         __u8    rsv1;
 339                         __u8    flags;
 340
 341                         /* DW1 */
 342                         __le16  datalen;
 343                         __le16  wbcpl;
 344
 345                         /* DW2 */
 346                         __le32  bufaddrh;
 347
 348                         /* DW3 */
 349                         __le32  bufaddrl;
 350                 } desc1;
 351                 struct {
 352                         /* DW0 */
 353                         __le16  vlan;
 354                         __le16  flags;
 355
 356                         /* DW1 */
 357                         __le16  framesize;
 358                         __u8    errstat;
 359                         __u8    desccnt;
 360
 361                         /* DW2 */
 362                         __le32  rsshash;
 363
 364                         /* DW3 */
 365                         __u8    hashfun;
 366                         __u8    hashtype;
 367                         __le16  resrv;
 368                 } descwb;
 369         };
 370 };
 371
 372 enum jme_rxdesc_flags_bits {
 373         RXFLAG_OWN      = 0x80,
 374         RXFLAG_INT      = 0x40,
 375         RXFLAG_64BIT    = 0x20,
 376 };
 377
 378 enum jme_rxwbdesc_flags_bits {
 379         RXWBFLAG_OWN            = 0x8000,
 380         RXWBFLAG_INT            = 0x4000,
 381         RXWBFLAG_MF             = 0x2000,
 382         RXWBFLAG_64BIT          = 0x2000,
 383         RXWBFLAG_TCPON          = 0x1000,
 384         RXWBFLAG_UDPON          = 0x0800,
 385         RXWBFLAG_IPCS           = 0x0400,
 386         RXWBFLAG_TCPCS          = 0x0200,
 387         RXWBFLAG_UDPCS          = 0x0100,
 388         RXWBFLAG_TAGON          = 0x0080,
 389         RXWBFLAG_IPV4           = 0x0040,
 390         RXWBFLAG_IPV6           = 0x0020,
 391         RXWBFLAG_PAUSE          = 0x0010,
 392         RXWBFLAG_MAGIC          = 0x0008,
 393         RXWBFLAG_WAKEUP         = 0x0004,
 394         RXWBFLAG_DEST           = 0x0003,
 395         RXWBFLAG_DEST_UNI       = 0x0001,
 396         RXWBFLAG_DEST_MUL       = 0x0002,
 397         RXWBFLAG_DEST_BRO       = 0x0003,
 398 };
 399
 400 enum jme_rxwbdesc_desccnt_mask {
 401         RXWBDCNT_WBCPL  = 0x80,
 402         RXWBDCNT_DCNT   = 0x7F,
 403 };
 404
 405 enum jme_rxwbdesc_errstat_bits {
 406         RXWBERR_LIMIT   = 0x80,
 407         RXWBERR_MIIER   = 0x40,
 408         RXWBERR_NIBON   = 0x20,
 409         RXWBERR_COLON   = 0x10,
 410         RXWBERR_ABORT   = 0x08,
 411         RXWBERR_SHORT   = 0x04,
 412         RXWBERR_OVERUN  = 0x02,
 413         RXWBERR_CRCERR  = 0x01,
 414         RXWBERR_ALLERR  = 0xFF,
 415 };
 416
 417 /*
 418  * Buffer information corresponding to ring descriptors.
 419  */
 420 struct jme_buffer_info {
 421         struct sk_buff *skb;
 422         dma_addr_t mapping;
 423         int len;
 424         int nr_desc;
 425         unsigned long start_xmit;
 426 };
 427
 428 /*
 429  * The structure holding buffer information and ring descriptors all together.
 430  */
 431 struct jme_ring {
 432         void *alloc;            /* pointer to allocated memory */
 433         void *desc;             /* pointer to ring memory  */
 434         dma_addr_t dmaalloc;    /* phys address of ring alloc */
 435         dma_addr_t dma;         /* phys address for ring dma */
 436
 437         /* Buffer information corresponding to each descriptor */
 438         struct jme_buffer_info *bufinf;
 439
 440         int next_to_use;
 441         atomic_t next_to_clean;
 442         atomic_t nr_free;
 443 };
 444
 445 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
 446 #define false 0
 447 #define true 0
 448 #define netdev_alloc_skb(dev, len) dev_alloc_skb(len)
 449 #define PCI_VENDOR_ID_JMICRON           0x197B
 450 #endif
 451
 452 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,19)
 453 #define PCI_VDEVICE(vendor, device)             \
 454         PCI_VENDOR_ID_##vendor, (device),       \
 455         PCI_ANY_ID, PCI_ANY_ID, 0, 0
 456 #endif
 457
 458 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
 459 #define NET_STAT(priv) priv->stats
 460 #define NETDEV_GET_STATS(netdev, fun_ptr) \
 461         netdev->get_stats = fun_ptr
 462 #define DECLARE_NET_DEVICE_STATS struct net_device_stats stats;
 463 /*
 464  * CentOS 5.5 have *_hdr helpers back-ported
 465  */
 466 #ifdef RHEL_RELEASE_CODE
 467 #if RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,5)
 468 #define __DEFINE_IPHDR_HELPERS__
 469 #endif
 470 #else
 471 #define __DEFINE_IPHDR_HELPERS__
 472 #endif
 473 #else
 474 #define NET_STAT(priv) (priv->dev->stats)
 475 #define NETDEV_GET_STATS(netdev, fun_ptr)
 476 #define DECLARE_NET_DEVICE_STATS
 477 #endif
 478
 479 #ifdef __DEFINE_IPHDR_HELPERS__
 480 static inline struct iphdr *ip_hdr(const struct sk_buff *skb)
 481 {
 482         return skb->nh.iph;
 483 }
 484
 485 static inline struct ipv6hdr *ipv6_hdr(const struct sk_buff *skb)
 486 {
 487         return skb->nh.ipv6h;
 488 }
 489
 490 static inline struct tcphdr *tcp_hdr(const struct sk_buff *skb)
 491 {
 492         return skb->h.th;
 493 }
 494 #endif
 495
 496 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
 497 #define DECLARE_NAPI_STRUCT
 498 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
 499         dev->poll = pollfn; \
 500         dev->weight = q;
 501 #define JME_NAPI_HOLDER(holder) struct net_device *holder
 502 #define JME_NAPI_WEIGHT(w) int *w
 503 #define JME_NAPI_WEIGHT_VAL(w) *w
 504 #define JME_NAPI_WEIGHT_SET(w, r) *w = r
 505 #define DECLARE_NETDEV struct net_device *netdev = jme->dev;
 506 #define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev)
 507 #define JME_NAPI_ENABLE(priv) netif_poll_enable(priv->dev);
 508 #define JME_NAPI_DISABLE(priv) netif_poll_disable(priv->dev);
 509 #define JME_RX_SCHEDULE_PREP(priv) \
 510         netif_rx_schedule_prep(priv->dev)
 511 #define JME_RX_SCHEDULE(priv) \
 512         __netif_rx_schedule(priv->dev);
 513 #else
 514 #define DECLARE_NAPI_STRUCT struct napi_struct napi;
 515 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
 516         netif_napi_add(dev, napis, pollfn, q);
 517 #define JME_NAPI_HOLDER(holder) struct napi_struct *holder
 518 #define JME_NAPI_WEIGHT(w) int w
 519 #define JME_NAPI_WEIGHT_VAL(w) w
 520 #define JME_NAPI_WEIGHT_SET(w, r)
 521 #define DECLARE_NETDEV
 522 #define JME_RX_COMPLETE(dev, napis) napi_complete(napis)
 523 #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
 524 #define JME_NAPI_DISABLE(priv) \
 525         if (!napi_disable_pending(&priv->napi)) \
 526                 napi_disable(&priv->napi);
 527 #define JME_RX_SCHEDULE_PREP(priv) \
 528         napi_schedule_prep(&priv->napi)
 529 #define JME_RX_SCHEDULE(priv) \
 530         __napi_schedule(&priv->napi);
 531 #endif
 532
 533 /*
 534  * Jmac Adapter Private data
 535  */
 536 struct jme_adapter {
 537         struct pci_dev          *pdev;
 538         struct net_device       *dev;
 539         void __iomem            *regs;
 540         struct mii_if_info      mii_if;
 541         struct jme_ring         rxring[RX_RING_NR];
 542         struct jme_ring         txring[TX_RING_NR];
 543         spinlock_t              phy_lock;
 544         spinlock_t              macaddr_lock;
 545         spinlock_t              rxmcs_lock;
 546         struct tasklet_struct   rxempty_task;
 547         struct tasklet_struct   rxclean_task;
 548         struct tasklet_struct   txclean_task;
 549         struct tasklet_struct   linkch_task;
 550         struct tasklet_struct   pcc_task;
 551         unsigned long           flags;
 552         u32                     reg_txcs;
 553         u32                     reg_txpfc;
 554         u32                     reg_rxcs;
 555         u32                     reg_rxmcs;
 556         u32                     reg_ghc;
 557         u32                     reg_pmcs;
 558         u32                     phylink;
 559         u32                     tx_ring_size;
 560         u32                     tx_ring_mask;
 561         u32                     tx_wake_threshold;
 562         u32                     rx_ring_size;
 563         u32                     rx_ring_mask;
 564         u8                      mrrs;
 565         unsigned int            fpgaver;
 566         u8                      chiprev;
 567         u8                      chip_main_rev;
 568         u8                      chip_sub_rev;
 569         u8                      pcirev;
 570         u32                     msg_enable;
 571         struct ethtool_cmd      old_ecmd;
 572         unsigned int            old_mtu;
 573         struct vlan_group       *vlgrp;
 574         struct dynpcc_info      dpi;
 575         atomic_t                intr_sem;
 576         atomic_t                link_changing;
 577         atomic_t                tx_cleaning;
 578         atomic_t                rx_cleaning;
 579         atomic_t                rx_empty;
 580         int                     (*jme_rx)(struct sk_buff *skb);
 581         int                     (*jme_vlan_rx)(struct sk_buff *skb,
 582                                           struct vlan_group *grp,
 583                                           unsigned short vlan_tag);
 584         DECLARE_NAPI_STRUCT
 585         DECLARE_NET_DEVICE_STATS
 586 };
 587
 588 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
 589 static struct net_device_stats *
 590 jme_get_stats(struct net_device *netdev)
 591 {
 592         struct jme_adapter *jme = netdev_priv(netdev);
 593         return &jme->stats;
 594 }
 595 #endif
 596
 597 enum jme_flags_bits {
 598         JME_FLAG_MSI            = 1,
 599         JME_FLAG_SSET           = 2,
 600         JME_FLAG_TXCSUM         = 3,
 601         JME_FLAG_TSO            = 4,
 602         JME_FLAG_POLL           = 5,
 603         JME_FLAG_SHUTDOWN       = 6,
 604 };
 605
 606 #define TX_TIMEOUT              (5 * HZ)
 607 #define JME_REG_LEN             0x500
 608 #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
 609
 610 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
 611 static inline struct jme_adapter*
 612 jme_napi_priv(struct net_device *holder)
 613 {
 614         struct jme_adapter *jme;
 615         jme = netdev_priv(holder);
 616         return jme;
 617 }
 618 #else
 619 static inline struct jme_adapter*
 620 jme_napi_priv(struct napi_struct *napi)
 621 {
 622         struct jme_adapter *jme;
 623         jme = container_of(napi, struct jme_adapter, napi);
 624         return jme;
 625 }
 626 #endif
 627
 628 /*
 629  * MMaped I/O Resters
 630  */
 631 enum jme_iomap_offsets {
 632         JME_MAC         = 0x0000,
 633         JME_PHY         = 0x0400,
 634         JME_MISC        = 0x0800,
 635         JME_RSS         = 0x0C00,
 636 };
 637
 638 enum jme_iomap_lens {
 639         JME_MAC_LEN     = 0x80,
 640         JME_PHY_LEN     = 0x58,
 641         JME_MISC_LEN    = 0x98,
 642         JME_RSS_LEN     = 0xFF,
 643 };
 644
 645 enum jme_iomap_regs {
 646         JME_TXCS        = JME_MAC | 0x00, /* Transmit Control and Status */
 647         JME_TXDBA_LO    = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
 648         JME_TXDBA_HI    = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
 649         JME_TXQDC       = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
 650         JME_TXNDA       = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
 651         JME_TXMCS       = JME_MAC | 0x14, /* Transmit MAC Control Status */
 652         JME_TXPFC       = JME_MAC | 0x18, /* Transmit Pause Frame Control */
 653         JME_TXTRHD      = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
 654
 655         JME_RXCS        = JME_MAC | 0x20, /* Receive Control and Status */
 656         JME_RXDBA_LO    = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
 657         JME_RXDBA_HI    = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
 658         JME_RXQDC       = JME_MAC | 0x2C, /* Receive Queue Desc Count */
 659         JME_RXNDA       = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
 660         JME_RXMCS       = JME_MAC | 0x34, /* Receive MAC Control Status */
 661         JME_RXUMA_LO    = JME_MAC | 0x38, /* Receive Unicast MAC Address */
 662         JME_RXUMA_HI    = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
 663         JME_RXMCHT_LO   = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
 664         JME_RXMCHT_HI   = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
 665         JME_WFODP       = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
 666         JME_WFOI        = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
 667
 668         JME_SMI         = JME_MAC | 0x50, /* Station Management Interface */
 669         JME_GHC         = JME_MAC | 0x54, /* Global Host Control */
 670         JME_PMCS        = JME_MAC | 0x60, /* Power Management Control/Stat */
 671
 672
 673         JME_PHY_PWR     = JME_PHY | 0x24, /* New PHY Power Ctrl Register */
 674         JME_PHY_CS      = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
 675         JME_PHY_LINK    = JME_PHY | 0x30, /* PHY Link Status Register */
 676         JME_SMBCSR      = JME_PHY | 0x40, /* SMB Control and Status */
 677         JME_SMBINTF     = JME_PHY | 0x44, /* SMB Interface */
 678
 679
 680         JME_TMCSR       = JME_MISC | 0x00, /* Timer Control/Status Register */
 681         JME_GPREG0      = JME_MISC | 0x08, /* General purpose REG-0 */
 682         JME_GPREG1      = JME_MISC | 0x0C, /* General purpose REG-1 */
 683         JME_IEVE        = JME_MISC | 0x20, /* Interrupt Event Status */
 684         JME_IREQ        = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
 685         JME_IENS        = JME_MISC | 0x28, /* Intr Enable - Setting Port */
 686         JME_IENC        = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
 687         JME_PCCRX0      = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
 688         JME_PCCTX       = JME_MISC | 0x40, /* PCC Control for TX Queues */
 689         JME_CHIPMODE    = JME_MISC | 0x44, /* Identify FPGA Version */
 690         JME_SHBA_HI     = JME_MISC | 0x48, /* Shadow Register Base HI */
 691         JME_SHBA_LO     = JME_MISC | 0x4C, /* Shadow Register Base LO */
 692         JME_TIMER1      = JME_MISC | 0x70, /* Timer1 */
 693         JME_TIMER2      = JME_MISC | 0x74, /* Timer2 */
 694         JME_APMC        = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
 695         JME_PCCSRX0     = JME_MISC | 0x80, /* PCC Status of RX0 */
 696 };
 697
 698 /*
 699  * TX Control/Status Bits
 700  */
 701 enum jme_txcs_bits {
 702         TXCS_QUEUE7S    = 0x00008000,
 703         TXCS_QUEUE6S    = 0x00004000,
 704         TXCS_QUEUE5S    = 0x00002000,
 705         TXCS_QUEUE4S    = 0x00001000,
 706         TXCS_QUEUE3S    = 0x00000800,
 707         TXCS_QUEUE2S    = 0x00000400,
 708         TXCS_QUEUE1S    = 0x00000200,
 709         TXCS_QUEUE0S    = 0x00000100,
 710         TXCS_FIFOTH     = 0x000000C0,
 711         TXCS_DMASIZE    = 0x00000030,
 712         TXCS_BURST      = 0x00000004,
 713         TXCS_ENABLE     = 0x00000001,
 714 };
 715
 716 enum jme_txcs_value {
 717         TXCS_FIFOTH_16QW        = 0x000000C0,
 718         TXCS_FIFOTH_12QW        = 0x00000080,
 719         TXCS_FIFOTH_8QW         = 0x00000040,
 720         TXCS_FIFOTH_4QW         = 0x00000000,
 721
 722         TXCS_DMASIZE_64B        = 0x00000000,
 723         TXCS_DMASIZE_128B       = 0x00000010,
 724         TXCS_DMASIZE_256B       = 0x00000020,
 725         TXCS_DMASIZE_512B       = 0x00000030,
 726
 727         TXCS_SELECT_QUEUE0      = 0x00000000,
 728         TXCS_SELECT_QUEUE1      = 0x00010000,
 729         TXCS_SELECT_QUEUE2      = 0x00020000,
 730         TXCS_SELECT_QUEUE3      = 0x00030000,
 731         TXCS_SELECT_QUEUE4      = 0x00040000,
 732         TXCS_SELECT_QUEUE5      = 0x00050000,
 733         TXCS_SELECT_QUEUE6      = 0x00060000,
 734         TXCS_SELECT_QUEUE7      = 0x00070000,
 735
 736         TXCS_DEFAULT            = TXCS_FIFOTH_4QW |
 737                                   TXCS_BURST,
 738 };
 739
 740 #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
 741
 742 /*
 743  * TX MAC Control/Status Bits
 744  */
 745 enum jme_txmcs_bit_masks {
 746         TXMCS_IFG2              = 0xC0000000,
 747         TXMCS_IFG1              = 0x30000000,
 748         TXMCS_TTHOLD            = 0x00000300,
 749         TXMCS_FBURST            = 0x00000080,
 750         TXMCS_CARRIEREXT        = 0x00000040,
 751         TXMCS_DEFER             = 0x00000020,
 752         TXMCS_BACKOFF           = 0x00000010,
 753         TXMCS_CARRIERSENSE      = 0x00000008,
 754         TXMCS_COLLISION         = 0x00000004,
 755         TXMCS_CRC               = 0x00000002,
 756         TXMCS_PADDING           = 0x00000001,
 757 };
 758
 759 enum jme_txmcs_values {
 760         TXMCS_IFG2_6_4          = 0x00000000,
 761         TXMCS_IFG2_8_5          = 0x40000000,
 762         TXMCS_IFG2_10_6         = 0x80000000,
 763         TXMCS_IFG2_12_7         = 0xC0000000,
 764
 765         TXMCS_IFG1_8_4          = 0x00000000,
 766         TXMCS_IFG1_12_6         = 0x10000000,
 767         TXMCS_IFG1_16_8         = 0x20000000,
 768         TXMCS_IFG1_20_10        = 0x30000000,
 769
 770         TXMCS_TTHOLD_1_8        = 0x00000000,
 771         TXMCS_TTHOLD_1_4        = 0x00000100,
 772         TXMCS_TTHOLD_1_2        = 0x00000200,
 773         TXMCS_TTHOLD_FULL       = 0x00000300,
 774
 775         TXMCS_DEFAULT           = TXMCS_IFG2_8_5 |
 776                                   TXMCS_IFG1_16_8 |
 777                                   TXMCS_TTHOLD_FULL |
 778                                   TXMCS_DEFER |
 779                                   TXMCS_CRC |
 780                                   TXMCS_PADDING,
 781 };
 782
 783 enum jme_txpfc_bits_masks {
 784         TXPFC_VLAN_TAG          = 0xFFFF0000,
 785         TXPFC_VLAN_EN           = 0x00008000,
 786         TXPFC_PF_EN             = 0x00000001,
 787 };
 788
 789 enum jme_txtrhd_bits_masks {
 790         TXTRHD_TXPEN            = 0x80000000,
 791         TXTRHD_TXP              = 0x7FFFFF00,
 792         TXTRHD_TXREN            = 0x00000080,
 793         TXTRHD_TXRL             = 0x0000007F,
 794 };
 795
 796 enum jme_txtrhd_shifts {
 797         TXTRHD_TXP_SHIFT        = 8,
 798         TXTRHD_TXRL_SHIFT       = 0,
 799 };
 800
 801 /*
 802  * RX Control/Status Bits
 803  */
 804 enum jme_rxcs_bit_masks {
 805         /* FIFO full threshold for transmitting Tx Pause Packet */
 806         RXCS_FIFOTHTP   = 0x30000000,
 807         /* FIFO threshold for processing next packet */
 808         RXCS_FIFOTHNP   = 0x0C000000,
 809         RXCS_DMAREQSZ   = 0x03000000, /* DMA Request Size */
 810         RXCS_QUEUESEL   = 0x00030000, /* Queue selection */
 811         RXCS_RETRYGAP   = 0x0000F000, /* RX Desc full retry gap */
 812         RXCS_RETRYCNT   = 0x00000F00, /* RX Desc full retry counter */
 813         RXCS_WAKEUP     = 0x00000040, /* Enable receive wakeup packet */
 814         RXCS_MAGIC      = 0x00000020, /* Enable receive magic packet */
 815         RXCS_SHORT      = 0x00000010, /* Enable receive short packet */
 816         RXCS_ABORT      = 0x00000008, /* Enable receive errorr packet */
 817         RXCS_QST        = 0x00000004, /* Receive queue start */
 818         RXCS_SUSPEND    = 0x00000002,
 819         RXCS_ENABLE     = 0x00000001,
 820 };
 821
 822 enum jme_rxcs_values {
 823         RXCS_FIFOTHTP_16T       = 0x00000000,
 824         RXCS_FIFOTHTP_32T       = 0x10000000,
 825         RXCS_FIFOTHTP_64T       = 0x20000000,
 826         RXCS_FIFOTHTP_128T      = 0x30000000,
 827
 828         RXCS_FIFOTHNP_16QW      = 0x00000000,
 829         RXCS_FIFOTHNP_32QW      = 0x04000000,
 830         RXCS_FIFOTHNP_64QW      = 0x08000000,
 831         RXCS_FIFOTHNP_128QW     = 0x0C000000,
 832
 833         RXCS_DMAREQSZ_16B       = 0x00000000,
 834         RXCS_DMAREQSZ_32B       = 0x01000000,
 835         RXCS_DMAREQSZ_64B       = 0x02000000,
 836         RXCS_DMAREQSZ_128B      = 0x03000000,
 837
 838         RXCS_QUEUESEL_Q0        = 0x00000000,
 839         RXCS_QUEUESEL_Q1        = 0x00010000,
 840         RXCS_QUEUESEL_Q2        = 0x00020000,
 841         RXCS_QUEUESEL_Q3        = 0x00030000,
 842
 843         RXCS_RETRYGAP_256ns     = 0x00000000,
 844         RXCS_RETRYGAP_512ns     = 0x00001000,
 845         RXCS_RETRYGAP_1024ns    = 0x00002000,
 846         RXCS_RETRYGAP_2048ns    = 0x00003000,
 847         RXCS_RETRYGAP_4096ns    = 0x00004000,
 848         RXCS_RETRYGAP_8192ns    = 0x00005000,
 849         RXCS_RETRYGAP_16384ns   = 0x00006000,
 850         RXCS_RETRYGAP_32768ns   = 0x00007000,
 851
 852         RXCS_RETRYCNT_0         = 0x00000000,
 853         RXCS_RETRYCNT_4         = 0x00000100,
 854         RXCS_RETRYCNT_8         = 0x00000200,
 855         RXCS_RETRYCNT_12        = 0x00000300,
 856         RXCS_RETRYCNT_16        = 0x00000400,
 857         RXCS_RETRYCNT_20        = 0x00000500,
 858         RXCS_RETRYCNT_24        = 0x00000600,
 859         RXCS_RETRYCNT_28        = 0x00000700,
 860         RXCS_RETRYCNT_32        = 0x00000800,
 861         RXCS_RETRYCNT_36        = 0x00000900,
 862         RXCS_RETRYCNT_40        = 0x00000A00,
 863         RXCS_RETRYCNT_44        = 0x00000B00,
 864         RXCS_RETRYCNT_48        = 0x00000C00,
 865         RXCS_RETRYCNT_52        = 0x00000D00,
 866         RXCS_RETRYCNT_56        = 0x00000E00,
 867         RXCS_RETRYCNT_60        = 0x00000F00,
 868
 869         RXCS_DEFAULT            = RXCS_FIFOTHTP_128T |
 870                                   RXCS_FIFOTHNP_128QW |
 871                                   RXCS_DMAREQSZ_128B |
 872                                   RXCS_RETRYGAP_256ns |
 873                                   RXCS_RETRYCNT_32,
 874 };
 875
 876 #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
 877
 878 /*
 879  * RX MAC Control/Status Bits
 880  */
 881 enum jme_rxmcs_bits {
 882         RXMCS_ALLFRAME          = 0x00000800,
 883         RXMCS_BRDFRAME          = 0x00000400,
 884         RXMCS_MULFRAME          = 0x00000200,
 885         RXMCS_UNIFRAME          = 0x00000100,
 886         RXMCS_ALLMULFRAME       = 0x00000080,
 887         RXMCS_MULFILTERED       = 0x00000040,
 888         RXMCS_RXCOLLDEC         = 0x00000020,
 889         RXMCS_FLOWCTRL          = 0x00000008,
 890         RXMCS_VTAGRM            = 0x00000004,
 891         RXMCS_PREPAD            = 0x00000002,
 892         RXMCS_CHECKSUM          = 0x00000001,
 893
 894         RXMCS_DEFAULT           = RXMCS_VTAGRM |
 895                                   RXMCS_PREPAD |
 896                                   RXMCS_FLOWCTRL |
 897                                   RXMCS_CHECKSUM,
 898 };
 899
 900 /*
 901  * Wakeup Frame setup interface registers
 902  */
 903 #define WAKEUP_FRAME_NR 8
 904 #define WAKEUP_FRAME_MASK_DWNR  4
 905
 906 enum jme_wfoi_bit_masks {
 907         WFOI_MASK_SEL           = 0x00000070,
 908         WFOI_CRC_SEL            = 0x00000008,
 909         WFOI_FRAME_SEL          = 0x00000007,
 910 };
 911
 912 enum jme_wfoi_shifts {
 913         WFOI_MASK_SHIFT         = 4,
 914 };
 915
 916 /*
 917  * SMI Related definitions
 918  */
 919 enum jme_smi_bit_mask {
 920         SMI_DATA_MASK           = 0xFFFF0000,
 921         SMI_REG_ADDR_MASK       = 0x0000F800,
 922         SMI_PHY_ADDR_MASK       = 0x000007C0,
 923         SMI_OP_WRITE            = 0x00000020,
 924         /* Set to 1, after req done it'll be cleared to 0 */
 925         SMI_OP_REQ              = 0x00000010,
 926         SMI_OP_MDIO             = 0x00000008, /* Software assess In/Out */
 927         SMI_OP_MDOE             = 0x00000004, /* Software Output Enable */
 928         SMI_OP_MDC              = 0x00000002, /* Software CLK Control */
 929         SMI_OP_MDEN             = 0x00000001, /* Software access Enable */
 930 };
 931
 932 enum jme_smi_bit_shift {
 933         SMI_DATA_SHIFT          = 16,
 934         SMI_REG_ADDR_SHIFT      = 11,
 935         SMI_PHY_ADDR_SHIFT      = 6,
 936 };
 937
 938 static inline u32 smi_reg_addr(int x)
 939 {
 940         return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
 941 }
 942
 943 static inline u32 smi_phy_addr(int x)
 944 {
 945         return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
 946 }
 947
 948 #define JME_PHY_TIMEOUT 100 /* 100 msec */
 949 #define JME_PHY_REG_NR 32
 950
 951 /*
 952  * Global Host Control
 953  */
 954 enum jme_ghc_bit_mask {
 955         GHC_SWRST               = 0x40000000,
 956         GHC_DPX                 = 0x00000040,
 957         GHC_SPEED               = 0x00000030,
 958         GHC_LINK_POLL           = 0x00000001,
 959 };
 960
 961 enum jme_ghc_speed_val {
 962         GHC_SPEED_10M           = 0x00000010,
 963         GHC_SPEED_100M          = 0x00000020,
 964         GHC_SPEED_1000M         = 0x00000030,
 965 };
 966
 967 enum jme_ghc_to_clk {
 968         GHC_TO_CLK_OFF          = 0x00000000,
 969         GHC_TO_CLK_GPHY         = 0x00400000,
 970         GHC_TO_CLK_PCIE         = 0x00800000,
 971         GHC_TO_CLK_INVALID      = 0x00C00000,
 972 };
 973
 974 enum jme_ghc_txmac_clk {
 975         GHC_TXMAC_CLK_OFF       = 0x00000000,
 976         GHC_TXMAC_CLK_GPHY      = 0x00100000,
 977         GHC_TXMAC_CLK_PCIE      = 0x00200000,
 978         GHC_TXMAC_CLK_INVALID   = 0x00300000,
 979 };
 980
 981 /*
 982  * Power management control and status register
 983  */
 984 enum jme_pmcs_bit_masks {
 985         PMCS_WF7DET     = 0x80000000,
 986         PMCS_WF6DET     = 0x40000000,
 987         PMCS_WF5DET     = 0x20000000,
 988         PMCS_WF4DET     = 0x10000000,
 989         PMCS_WF3DET     = 0x08000000,
 990         PMCS_WF2DET     = 0x04000000,
 991         PMCS_WF1DET     = 0x02000000,
 992         PMCS_WF0DET     = 0x01000000,
 993         PMCS_LFDET      = 0x00040000,
 994         PMCS_LRDET      = 0x00020000,
 995         PMCS_MFDET      = 0x00010000,
 996         PMCS_WF7EN      = 0x00008000,
 997         PMCS_WF6EN      = 0x00004000,
 998         PMCS_WF5EN      = 0x00002000,
 999         PMCS_WF4EN      = 0x00001000,
1000         PMCS_WF3EN      = 0x00000800,
1001         PMCS_WF2EN      = 0x00000400,
1002         PMCS_WF1EN      = 0x00000200,
1003         PMCS_WF0EN      = 0x00000100,
1004         PMCS_LFEN       = 0x00000004,
1005         PMCS_LREN       = 0x00000002,
1006         PMCS_MFEN       = 0x00000001,
1007 };
1008
1009 /*
1010  * New PHY Power Control Register
1011  */
1012 enum jme_phy_pwr_bit_masks {
1013         PHY_PWR_DWN1SEL = 0x01000000, /* Phy_giga.p_PWR_DOWN1_SEL */
1014         PHY_PWR_DWN1SW  = 0x02000000, /* Phy_giga.p_PWR_DOWN1_SW */
1015         PHY_PWR_DWN2    = 0x04000000, /* Phy_giga.p_PWR_DOWN2 */
1016         PHY_PWR_CLKSEL  = 0x08000000, /*
1017                                        * XTL_OUT Clock select
1018                                        * (an internal free-running clock)
1019                                        * 0: xtl_out = phy_giga.A_XTL25_O
1020                                        * 1: xtl_out = phy_giga.PD_OSC
1021                                        */
1022 };
1023
1024 /*
1025  * Giga PHY Status Registers
1026  */
1027 enum jme_phy_link_bit_mask {
1028         PHY_LINK_SPEED_MASK             = 0x0000C000,
1029         PHY_LINK_DUPLEX                 = 0x00002000,
1030         PHY_LINK_SPEEDDPU_RESOLVED      = 0x00000800,
1031         PHY_LINK_UP                     = 0x00000400,
1032         PHY_LINK_AUTONEG_COMPLETE       = 0x00000200,
1033         PHY_LINK_MDI_STAT               = 0x00000040,
1034 };
1035
1036 enum jme_phy_link_speed_val {
1037         PHY_LINK_SPEED_10M              = 0x00000000,
1038         PHY_LINK_SPEED_100M             = 0x00004000,
1039         PHY_LINK_SPEED_1000M            = 0x00008000,
1040 };
1041
1042 #define JME_SPDRSV_TIMEOUT      500     /* 500 us */
1043
1044 /*
1045  * SMB Control and Status
1046  */
1047 enum jme_smbcsr_bit_mask {
1048         SMBCSR_CNACK    = 0x00020000,
1049         SMBCSR_RELOAD   = 0x00010000,
1050         SMBCSR_EEPROMD  = 0x00000020,
1051         SMBCSR_INITDONE = 0x00000010,
1052         SMBCSR_BUSY     = 0x0000000F,
1053 };
1054
1055 enum jme_smbintf_bit_mask {
1056         SMBINTF_HWDATR  = 0xFF000000,
1057         SMBINTF_HWDATW  = 0x00FF0000,
1058         SMBINTF_HWADDR  = 0x0000FF00,
1059         SMBINTF_HWRWN   = 0x00000020,
1060         SMBINTF_HWCMD   = 0x00000010,
1061         SMBINTF_FASTM   = 0x00000008,
1062         SMBINTF_GPIOSCL = 0x00000004,
1063         SMBINTF_GPIOSDA = 0x00000002,
1064         SMBINTF_GPIOEN  = 0x00000001,
1065 };
1066
1067 enum jme_smbintf_vals {
1068         SMBINTF_HWRWN_READ      = 0x00000020,
1069         SMBINTF_HWRWN_WRITE     = 0x00000000,
1070 };
1071
1072 enum jme_smbintf_shifts {
1073         SMBINTF_HWDATR_SHIFT    = 24,
1074         SMBINTF_HWDATW_SHIFT    = 16,
1075         SMBINTF_HWADDR_SHIFT    = 8,
1076 };
1077
1078 #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
1079 #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
1080 #define JME_SMB_LEN 256
1081 #define JME_EEPROM_MAGIC 0x250
1082
1083 /*
1084  * Timer Control/Status Register
1085  */
1086 enum jme_tmcsr_bit_masks {
1087         TMCSR_SWIT      = 0x80000000,
1088         TMCSR_EN        = 0x01000000,
1089         TMCSR_CNT       = 0x00FFFFFF,
1090 };
1091
1092 /*
1093  * General Purpose REG-0
1094  */
1095 enum jme_gpreg0_masks {
1096         GPREG0_DISSH            = 0xFF000000,
1097         GPREG0_PCIRLMT          = 0x00300000,
1098         GPREG0_PCCNOMUTCLR      = 0x00040000,
1099         GPREG0_LNKINTPOLL       = 0x00001000,
1100         GPREG0_PCCTMR           = 0x00000300,
1101         GPREG0_PHYADDR          = 0x0000001F,
1102 };
1103
1104 enum jme_gpreg0_vals {
1105         GPREG0_DISSH_DW7        = 0x80000000,
1106         GPREG0_DISSH_DW6        = 0x40000000,
1107         GPREG0_DISSH_DW5        = 0x20000000,
1108         GPREG0_DISSH_DW4        = 0x10000000,
1109         GPREG0_DISSH_DW3        = 0x08000000,
1110         GPREG0_DISSH_DW2        = 0x04000000,
1111         GPREG0_DISSH_DW1        = 0x02000000,
1112         GPREG0_DISSH_DW0        = 0x01000000,
1113         GPREG0_DISSH_ALL        = 0xFF000000,
1114
1115         GPREG0_PCIRLMT_8        = 0x00000000,
1116         GPREG0_PCIRLMT_6        = 0x00100000,
1117         GPREG0_PCIRLMT_5        = 0x00200000,
1118         GPREG0_PCIRLMT_4        = 0x00300000,
1119
1120         GPREG0_PCCTMR_16ns      = 0x00000000,
1121         GPREG0_PCCTMR_256ns     = 0x00000100,
1122         GPREG0_PCCTMR_1us       = 0x00000200,
1123         GPREG0_PCCTMR_1ms       = 0x00000300,
1124
1125         GPREG0_PHYADDR_1        = 0x00000001,
1126
1127         GPREG0_DEFAULT          = GPREG0_PCIRLMT_4 |
1128                                   GPREG0_PCCTMR_1us |
1129                                   GPREG0_PHYADDR_1,
1130 };
1131
1132 /*
1133  * General Purpose REG-1
1134  * Note: All theses bits defined here are for
1135  *       Chip mode revision 0x11 only
1136  */
1137 enum jme_gpreg1_masks {
1138         GPREG1_INTRDELAYUNIT    = 0x00000018,
1139         GPREG1_INTRDELAYENABLE  = 0x00000007,
1140 };
1141
1142 enum jme_gpreg1_vals {
1143         GPREG1_HALFMODEPATCH    = 0x00000040,
1144         GPREG1_RSSPATCH         = 0x00000020,
1145
1146         GPREG1_INTDLYUNIT_16NS  = 0x00000000,
1147         GPREG1_INTDLYUNIT_256NS = 0x00000008,
1148         GPREG1_INTDLYUNIT_1US   = 0x00000010,
1149         GPREG1_INTDLYUNIT_16US  = 0x00000018,
1150
1151         GPREG1_INTDLYEN_1U      = 0x00000001,
1152         GPREG1_INTDLYEN_2U      = 0x00000002,
1153         GPREG1_INTDLYEN_3U      = 0x00000003,
1154         GPREG1_INTDLYEN_4U      = 0x00000004,
1155         GPREG1_INTDLYEN_5U      = 0x00000005,
1156         GPREG1_INTDLYEN_6U      = 0x00000006,
1157         GPREG1_INTDLYEN_7U      = 0x00000007,
1158
1159         GPREG1_DEFAULT          = 0x00000000,
1160 };
1161
1162 /*
1163  * Interrupt Status Bits
1164  */
1165 enum jme_interrupt_bits {
1166         INTR_SWINTR     = 0x80000000,
1167         INTR_TMINTR     = 0x40000000,
1168         INTR_LINKCH     = 0x20000000,
1169         INTR_PAUSERCV   = 0x10000000,
1170         INTR_MAGICRCV   = 0x08000000,
1171         INTR_WAKERCV    = 0x04000000,
1172         INTR_PCCRX0TO   = 0x02000000,
1173         INTR_PCCRX1TO   = 0x01000000,
1174         INTR_PCCRX2TO   = 0x00800000,
1175         INTR_PCCRX3TO   = 0x00400000,
1176         INTR_PCCTXTO    = 0x00200000,
1177         INTR_PCCRX0     = 0x00100000,
1178         INTR_PCCRX1     = 0x00080000,
1179         INTR_PCCRX2     = 0x00040000,
1180         INTR_PCCRX3     = 0x00020000,
1181         INTR_PCCTX      = 0x00010000,
1182         INTR_RX3EMP     = 0x00008000,
1183         INTR_RX2EMP     = 0x00004000,
1184         INTR_RX1EMP     = 0x00002000,
1185         INTR_RX0EMP     = 0x00001000,
1186         INTR_RX3        = 0x00000800,
1187         INTR_RX2        = 0x00000400,
1188         INTR_RX1        = 0x00000200,
1189         INTR_RX0        = 0x00000100,
1190         INTR_TX7        = 0x00000080,
1191         INTR_TX6        = 0x00000040,
1192         INTR_TX5        = 0x00000020,
1193         INTR_TX4        = 0x00000010,
1194         INTR_TX3        = 0x00000008,
1195         INTR_TX2        = 0x00000004,
1196         INTR_TX1        = 0x00000002,
1197         INTR_TX0        = 0x00000001,
1198 };
1199
1200 static const u32 INTR_ENABLE = INTR_SWINTR |
1201                                  INTR_TMINTR |
1202                                  INTR_LINKCH |
1203                                  INTR_PCCRX0TO |
1204                                  INTR_PCCRX0 |
1205                                  INTR_PCCTXTO |
1206                                  INTR_PCCTX |
1207                                  INTR_RX0EMP;
1208
1209 /*
1210  * PCC Control Registers
1211  */
1212 enum jme_pccrx_masks {
1213         PCCRXTO_MASK    = 0xFFFF0000,
1214         PCCRX_MASK      = 0x0000FF00,
1215 };
1216
1217 enum jme_pcctx_masks {
1218         PCCTXTO_MASK    = 0xFFFF0000,
1219         PCCTX_MASK      = 0x0000FF00,
1220         PCCTX_QS_MASK   = 0x000000FF,
1221 };
1222
1223 enum jme_pccrx_shifts {
1224         PCCRXTO_SHIFT   = 16,
1225         PCCRX_SHIFT     = 8,
1226 };
1227
1228 enum jme_pcctx_shifts {
1229         PCCTXTO_SHIFT   = 16,
1230         PCCTX_SHIFT     = 8,
1231 };
1232
1233 enum jme_pcctx_bits {
1234         PCCTXQ0_EN      = 0x00000001,
1235         PCCTXQ1_EN      = 0x00000002,
1236         PCCTXQ2_EN      = 0x00000004,
1237         PCCTXQ3_EN      = 0x00000008,
1238         PCCTXQ4_EN      = 0x00000010,
1239         PCCTXQ5_EN      = 0x00000020,
1240         PCCTXQ6_EN      = 0x00000040,
1241         PCCTXQ7_EN      = 0x00000080,
1242 };
1243
1244 /*
1245  * Chip Mode Register
1246  */
1247 enum jme_chipmode_bit_masks {
1248         CM_FPGAVER_MASK         = 0xFFFF0000,
1249         CM_CHIPREV_MASK         = 0x0000FF00,
1250         CM_CHIPMODE_MASK        = 0x0000000F,
1251 };
1252
1253 enum jme_chipmode_shifts {
1254         CM_FPGAVER_SHIFT        = 16,
1255         CM_CHIPREV_SHIFT        = 8,
1256 };
1257
1258 /*
1259  * Aggressive Power Mode Control
1260  */
1261 enum jme_apmc_bits {
1262         JME_APMC_PCIE_SD_EN     = 0x40000000,
1263         JME_APMC_PSEUDO_HP_EN   = 0x20000000,
1264         JME_APMC_EPIEN          = 0x04000000,
1265         JME_APMC_EPIEN_CTRL     = 0x03000000,
1266 };
1267
1268 enum jme_apmc_values {
1269         JME_APMC_EPIEN_CTRL_EN  = 0x02000000,
1270         JME_APMC_EPIEN_CTRL_DIS = 0x01000000,
1271 };
1272
1273 #define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000)
1274
1275 #ifdef REG_DEBUG
1276 static char *MAC_REG_NAME[] = {
1277         "JME_TXCS",      "JME_TXDBA_LO",  "JME_TXDBA_HI", "JME_TXQDC",
1278         "JME_TXNDA",     "JME_TXMCS",     "JME_TXPFC",    "JME_TXTRHD",
1279         "JME_RXCS",      "JME_RXDBA_LO",  "JME_RXDBA_HI", "JME_RXQDC",
1280         "JME_RXNDA",     "JME_RXMCS",     "JME_RXUMA_LO", "JME_RXUMA_HI",
1281         "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP",    "JME_WFOI",
1282         "JME_SMI",       "JME_GHC",       "UNKNOWN",      "UNKNOWN",
1283         "JME_PMCS"};
1284
1285 static char *PE_REG_NAME[] = {
1286         "UNKNOWN",      "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1287         "UNKNOWN",      "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1288         "UNKNOWN",      "UNKNOWN",     "JME_PHY_CS", "UNKNOWN",
1289         "JME_PHY_LINK", "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1290         "JME_SMBCSR",   "JME_SMBINTF"};
1291
1292 static char *MISC_REG_NAME[] = {
1293         "JME_TMCSR",  "JME_GPIO",     "JME_GPREG0",  "JME_GPREG1",
1294         "JME_IEVE",   "JME_IREQ",     "JME_IENS",    "JME_IENC",
1295         "JME_PCCRX0", "JME_PCCRX1",   "JME_PCCRX2",  "JME_PCCRX3",
1296         "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO",
1297         "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1298         "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1299         "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1300         "JME_TIMER1", "JME_TIMER2",   "UNKNOWN",     "JME_APMC",
1301         "JME_PCCSRX0"};
1302
1303 static inline void reg_dbg(const struct jme_adapter *jme,
1304                 const char *msg, u32 val, u32 reg)
1305 {
1306         const char *regname;
1307         switch (reg & 0xF00) {
1308         case 0x000:
1309                 regname = MAC_REG_NAME[(reg & 0xFF) >> 2];
1310                 break;
1311         case 0x400:
1312                 regname = PE_REG_NAME[(reg & 0xFF) >> 2];
1313                 break;
1314         case 0x800:
1315                 regname = MISC_REG_NAME[(reg & 0xFF) >> 2];
1316                 break;
1317         default:
1318                 regname = PE_REG_NAME[0];
1319         }
1320         printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name,
1321                         msg, val, regname);
1322 }
1323 #else
1324 static inline void reg_dbg(const struct jme_adapter *jme,
1325                 const char *msg, u32 val, u32 reg) {}
1326 #endif
1327
1328 /*
1329  * Read/Write MMaped I/O Registers
1330  */
1331 static inline u32 jread32(struct jme_adapter *jme, u32 reg)
1332 {
1333         return readl(jme->regs + reg);
1334 }
1335
1336 static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val)
1337 {
1338         reg_dbg(jme, "REG WRITE", val, reg);
1339         writel(val, jme->regs + reg);
1340         reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1341 }
1342
1343 static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val)
1344 {
1345         /*
1346          * Read after write should cause flush
1347          */
1348         reg_dbg(jme, "REG WRITE FLUSH", val, reg);
1349         writel(val, jme->regs + reg);
1350         readl(jme->regs + reg);
1351         reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1352 }
1353
1354 /*
1355  * PHY Regs
1356  */
1357 enum jme_phy_reg17_bit_masks {
1358         PREG17_SPEED            = 0xC000,
1359         PREG17_DUPLEX           = 0x2000,
1360         PREG17_SPDRSV           = 0x0800,
1361         PREG17_LNKUP            = 0x0400,
1362         PREG17_MDI              = 0x0040,
1363 };
1364
1365 enum jme_phy_reg17_vals {
1366         PREG17_SPEED_10M        = 0x0000,
1367         PREG17_SPEED_100M       = 0x4000,
1368         PREG17_SPEED_1000M      = 0x8000,
1369 };
1370
1371 #define BMSR_ANCOMP               0x0020
1372
1373 /*
1374  * Workaround
1375  */
1376 static inline int is_buggy250(unsigned short device, u8 chiprev)
1377 {
1378         return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
1379 }
1380
1381 static inline int new_phy_power_ctrl(u8 chip_main_rev)
1382 {
1383         return chip_main_rev >= 5;
1384 }
1385
1386 /*
1387  * Function prototypes
1388  */
1389 static int jme_set_settings(struct net_device *netdev,
1390                                 struct ethtool_cmd *ecmd);
1391 static void jme_set_multi(struct net_device *netdev);
1392
1393 #endif
1394