Import jme 0.2 source
[jme.git] / jme.h
1 /*
2  * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3  *
4  * Copyright 2008 JMicron Technology Corporation
5  * http://www.jmicron.com/
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19  *
20  */
21
22 #include <linux/version.h>
23
24 #define DRV_NAME        "jme"
25 #define DRV_VERSION     "0.2"
26 #define PFX DRV_NAME    ": "
27
28 #ifdef DEBUG
29 #define dprintk(devname, fmt, args...) \
30         printk(KERN_DEBUG PFX "%s: " fmt, devname, ## args);
31 #else
32 #define dprintk(devname, fmt, args...)
33 #endif
34
35 #define jprintk(devname, fmt, args...) \
36         printk(KERN_INFO PFX "%s: " fmt, devname, ## args);
37
38 #define jeprintk(devname, fmt, args...) \
39         printk(KERN_ERR PFX "%s: " fmt, devname, ## args);
40
41 #undef RX_QUEUE_DEBUG
42 #undef RX_PKT_DEBUG
43 #undef RX_ERR_DEBUG
44 #undef TX_QUEUE_DEBUG
45 #undef TX_PKT_DEBUG
46 #undef TX_BUSY_DEBUG
47 #undef INTERRUPT_DEBUG
48 #undef SET_MULTI_DEBUG
49 #undef TX_TASKLET_DEBUG
50
51 #define USE_IEVE_SHADOW 0
52
53 #define DEFAULT_MSG_ENABLE        \
54         (NETIF_MSG_DRV          | \
55          NETIF_MSG_PROBE        | \
56          NETIF_MSG_LINK         | \
57          NETIF_MSG_TIMER        | \
58          NETIF_MSG_RX_ERR       | \
59          NETIF_MSG_TX_ERR)
60
61 #define PCI_CONF_DCSR_MRRS      0x59
62 #define PCI_CONF_DCSR_MRRS_MASK 0x70
63 enum pci_conf_dcsr_mrrs_vals {
64         MRRS_128B       = 0x00,
65         MRRS_256B       = 0x10,
66         MRRS_512B       = 0x20,
67         MRRS_1024B      = 0x30,
68         MRRS_2048B      = 0x40,
69         MRRS_4096B      = 0x50,
70 };
71
72 /*
73  * TX/RX Descriptors
74  *
75  * TX/RX Ring DESC Count Must be multiple of 16
76  * RX Ring DESC Count Must be <= 1024
77  */
78 #define RING_DESC_NR            512     /* Must be power of 2 */
79 #define RING_DESC_ALIGN         16      /* Descriptor alignment */
80
81 #define TX_DESC_SIZE            16
82 #define TX_RING_NR              8
83 #define TX_RING_ALLOC_SIZE      (RING_DESC_NR * TX_DESC_SIZE) + TX_DESC_SIZE
84 #define TX_RING_SIZE            (RING_DESC_NR * TX_DESC_SIZE)
85
86 struct TxDesc {
87         union {
88                 __u8  all[16];
89                 __u32 dw[4];
90                 struct {
91                         /* DW0 */
92                         __u16 vlan;
93                         __u8 rsv1;
94                         __u8 flags;
95
96                         /* DW1 */
97                         __u16 datalen;
98                         __u16 mss;
99
100                         /* DW2 */
101                         __u16 pktsize;
102                         __u16 rsv2;
103
104                         /* DW3 */
105                         __u32 bufaddr;
106                 } desc1;
107         };
108 };
109 enum jme_txdesc_flag_bits {
110         TXFLAG_OWN      = 0x80,
111         TXFLAG_INT      = 0x40,
112         TXFLAG_TCPCS    = 0x10,
113         TXFLAG_UDPCS    = 0x08,
114         TXFLAG_IPCS     = 0x04,
115         TXFLAG_LSEN     = 0x02,
116         TXFLAG_TAGON    = 0x01,
117 };
118
119
120 #define RX_DESC_SIZE            16
121 #define RX_RING_NR              4
122 #define RX_RING_ALLOC_SIZE      (RING_DESC_NR * RX_DESC_SIZE) + RX_DESC_SIZE
123 #define RX_RING_SIZE            (RING_DESC_NR * RX_DESC_SIZE)
124
125 #define RX_BUF_DMA_ALIGN        8
126 //#define RX_BUF_SIZE           1600
127 #define RX_BUF_SIZE             9216
128 /*
129  * Will use mtu in the future
130  */
131 #define RX_BUF_ALLOC_SIZE       RX_BUF_SIZE + RX_BUF_DMA_ALIGN
132
133 struct RxDesc {
134         union {
135                 __u8   all[16];
136                 __le32 dw[4];
137                 struct {
138                         /* DW0 */
139                         __le16 rsv2;
140                         __u8 rsv1;
141                         __u8 flags;
142
143                         /* DW1 */
144                         __le16 datalen;
145                         __le16 wbcpl;
146
147                         /* DW2 */
148                         __le32 bufaddrh;
149
150                         /* DW3 */
151                         __le32 bufaddrl;
152                 } desc1;
153                 struct {
154                         /* DW0 */
155                         __le16 vlan;
156                         __le16 flags;
157
158                         /* DW1 */
159                         __le16 framesize;
160                         __u8 errstat;
161                         __u8 desccnt;
162
163                         /* DW2 */
164                         __le32 rsshash;
165
166                         /* DW3 */
167                         __u8   hashfun; 
168                         __u8   hashtype; 
169                         __le16 resrv;
170                 } descwb;
171         };
172 };
173 enum jme_rxdesc_flags_bits {
174         RXFLAG_OWN      = 0x80,
175         RXFLAG_INT      = 0x40,
176         RXFLAG_64BIT    = 0x20,
177 };
178 enum jme_rxwbdesc_flags_bits {
179         RXWBFLAG_OWN            = 0x8000,
180         RXWBFLAG_INT            = 0x4000,
181         RXWBFLAG_MF             = 0x2000,
182         RXWBFLAG_64BIT          = 0x2000,
183         RXWBFLAG_TCPON          = 0x1000,
184         RXWBFLAG_UDPON          = 0x0800,
185         RXWBFLAG_IPCS           = 0x0400,
186         RXWBFLAG_TCPCS          = 0x0200,
187         RXWBFLAG_UDPCS          = 0x0100,
188         RXWBFLAG_TAGON          = 0x0080,
189         RXWBFLAG_IPV4           = 0x0040,
190         RXWBFLAG_IPV6           = 0x0020,
191         RXWBFLAG_PAUSE          = 0x0010,
192         RXWBFLAG_MAGIC          = 0x0008,
193         RXWBFLAG_WAKEUP         = 0x0004,
194         RXWBFLAG_DEST           = 0x0003,
195         RXWBFLAG_DEST_UNI       = 0x0001,
196         RXWBFLAG_DEST_MUL       = 0x0002,
197         RXWBFLAG_DEST_BRO       = 0x0003,
198 };
199 enum jme_rxwbdesc_desccnt_mask {
200         RXWBDCNT_WBCPL  = 0x80,
201         RXWBDCNT_DCNT   = 0x7F,
202 };
203 enum jme_rxwbdesc_errstat_bits {
204         RXWBERR_LIMIT   = 0x80,
205         RXWBERR_MIIER   = 0x40,
206         RXWBERR_NIBON   = 0x20,
207         RXWBERR_COLON   = 0x10,
208         RXWBERR_ABORT   = 0x08,
209         RXWBERR_SHORT   = 0x04,
210         RXWBERR_OVERUN  = 0x02,
211         RXWBERR_CRCERR  = 0x01,
212         RXWBERR_ALLERR  = 0xFF,
213 };
214
215 struct jme_buffer_info {
216         struct sk_buff *skb;
217         dma_addr_t mapping;
218         int len;
219 };
220
221 struct jme_ring {
222         void* alloc;            /* pointer to allocated memory */
223         void* desc;             /* pointer to ring memory  */
224         dma_addr_t dmaalloc;    /* phys address of ring alloc */
225         dma_addr_t dma;         /* phys address for ring dma */
226
227         /* Buffer information corresponding to each descriptor */
228         struct jme_buffer_info bufinf[RING_DESC_NR];
229
230         u16 next_to_use;
231         u16 next_to_clean;
232 };
233
234 /*
235  * Jmac Adapter Private data
236  */
237 #define SHADOW_REG_NR 8
238 struct jme_adapter {
239         struct pci_dev          *pdev;
240         struct net_device       *dev;
241         void __iomem            *regs;
242         dma_addr_t              shadow_dma;
243         __u32                   *shadow_regs;
244         struct mii_if_info      mii_if;
245         struct jme_ring         rxring[RX_RING_NR];
246         struct jme_ring         txring[TX_RING_NR];
247         spinlock_t              xmit_lock;
248         spinlock_t              recv_lock;
249         spinlock_t              macaddr_lock;
250         spinlock_t              phy_lock;
251         struct tasklet_struct   rxclean_task;
252         struct tasklet_struct   txclean_task;
253         struct tasklet_struct   linkch_task;
254         __u32                   flags;
255         __u32                   reg_txcs;
256 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
257         struct net_device_stats stats;
258 #endif
259 };
260 enum shadow_reg_val {
261         SHADOW_IEVE = 0,
262 };
263
264 #define JME_FLAG_RXQ0_EMPTY     0x00000001
265 #define JME_FLAG_RXQ1_EMPTY     0x00000002
266 #define JME_FLAG_RXQ2_EMPTY     0x00000004
267 #define JME_FLAG_RXQ3_EMPTY     0x00000008
268
269 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
270 #define NET_STAT jme->stats
271 #else
272 #define NET_STAT netdev->stats
273 #endif
274
275 /*
276  * MMaped I/O Resters
277  */
278 enum jme_iomap_offsets {
279         JME_MAC         = 0x0000,
280         JME_PHY         = 0x0400,
281         JME_MISC        = 0x0800,
282         JME_RSS         = 0x0C00,
283 };
284
285 enum jme_iomap_regs {
286         JME_TXCS        = JME_MAC | 0x00, /* Transmit Control and Status */
287         JME_TXDBA       = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
288         JME_TXQDC       = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
289         JME_TXNDA       = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
290         JME_TXMCS       = JME_MAC | 0x14, /* Transmit MAC Control Status */
291         JME_TXPFC       = JME_MAC | 0x18, /* Transmit Pause Frame Control */
292         JME_TXTRHD      = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
293
294         JME_RXCS        = JME_MAC | 0x20, /* Receive Control and Status */
295         JME_RXDBA       = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
296         JME_RXQDC       = JME_MAC | 0x2C, /* Receive Queue Desc Count */
297         JME_RXNDA       = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
298         JME_RXMCS       = JME_MAC | 0x34, /* Receive MAC Control Status */
299         JME_RXUMA_LO    = JME_MAC | 0x38, /* Receive Unicast MAC Address */
300         JME_RXUMA_HI    = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
301         JME_RXMCHT_LO   = JME_MAC | 0x40, /* Receive Multicast Addr HashTable */
302         JME_RXMCHT_HI   = JME_MAC | 0x44, /* Receive Multicast Addr HashTable */
303         JME_WFODP       = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
304         JME_WFOI        = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
305
306         JME_SMI         = JME_MAC | 0x50, /* Station Management Interface */
307         JME_GHC         = JME_MAC | 0x54, /* Global Host Control */
308         JME_PMCS        = JME_MAC | 0x60, /* Power Management Control/Stat */
309
310
311         JME_PHY_CS      = JME_PHY | 0x28, /* PHY Control and Status Register */
312         JME_PHY_LINK    = JME_PHY | 0x30, /* PHY Link Status Register */
313         JME_SMBCSR      = JME_PHY | 0x40, /* SMB Control and Status */
314
315
316         JME_GPREG0      = JME_MISC| 0x08, /* General purpose REG-0 */
317         JME_GPREG1      = JME_MISC| 0x0C, /* General purpose REG-1 */
318         JME_IEVE        = JME_MISC| 0x20, /* Interrupt Event Status */
319         JME_IREQ        = JME_MISC| 0x24, /* Interrupt Req Status (For Debug) */
320         JME_IENS        = JME_MISC| 0x28, /* Interrupt Enable - Setting Port */
321         JME_IENC        = JME_MISC| 0x2C, /* Interrupt Enable - Clearing Port */
322         JME_SHBA_HI     = JME_MISC| 0x48, /* Shadow Register Base HI */
323         JME_SHBA_LO     = JME_MISC| 0x4C, /* Shadow Register Base LO */
324 };
325
326 /*
327  * TX Control/Status Bits
328  */
329 enum jme_txcs_bits {
330         TXCS_QUEUE7S    = 0x00008000,
331         TXCS_QUEUE6S    = 0x00004000,
332         TXCS_QUEUE5S    = 0x00002000,
333         TXCS_QUEUE4S    = 0x00001000,
334         TXCS_QUEUE3S    = 0x00000800,
335         TXCS_QUEUE2S    = 0x00000400,
336         TXCS_QUEUE1S    = 0x00000200,
337         TXCS_QUEUE0S    = 0x00000100,
338         TXCS_FIFOTH     = 0x000000C0,
339         TXCS_DMASIZE    = 0x00000030,
340         TXCS_BURST      = 0x00000004,
341         TXCS_ENABLE     = 0x00000001,
342 };
343 enum jme_txcs_value {
344         TXCS_FIFOTH_16QW        = 0x000000C0,
345         TXCS_FIFOTH_12QW        = 0x00000080,
346         TXCS_FIFOTH_8QW         = 0x00000040,
347         TXCS_FIFOTH_4QW         = 0x00000000,
348
349         TXCS_DMASIZE_64B        = 0x00000000,
350         TXCS_DMASIZE_128B       = 0x00000010,
351         TXCS_DMASIZE_256B       = 0x00000020,
352         TXCS_DMASIZE_512B       = 0x00000030,
353
354         TXCS_SELECT_QUEUE0      = 0x00000000,
355         TXCS_SELECT_QUEUE1      = 0x00010000,
356         TXCS_SELECT_QUEUE2      = 0x00020000,
357         TXCS_SELECT_QUEUE3      = 0x00030000,
358         TXCS_SELECT_QUEUE4      = 0x00040000,
359         TXCS_SELECT_QUEUE5      = 0x00050000,
360         TXCS_SELECT_QUEUE6      = 0x00060000,
361         TXCS_SELECT_QUEUE7      = 0x00070000,
362
363         TXCS_DEFAULT            = TXCS_FIFOTH_4QW |
364                                   TXCS_BURST,
365 };
366 #define JME_TX_DISABLE_TIMEOUT 200 /* 200 usec */
367
368 /*
369  * TX MAC Control/Status Bits
370  */
371 enum jme_txmcs_bit_masks {
372         TXMCS_IFG2              = 0xC0000000,
373         TXMCS_IFG1              = 0x30000000,
374         TXMCS_TTHOLD            = 0x00000300,
375         TXMCS_FBURST            = 0x00000080,
376         TXMCS_CARRIEREXT        = 0x00000040,
377         TXMCS_DEFER             = 0x00000020,
378         TXMCS_BACKOFF           = 0x00000010,
379         TXMCS_CARRIERSENSE      = 0x00000008,
380         TXMCS_COLLISION         = 0x00000004,
381         TXMCS_CRC               = 0x00000002,
382         TXMCS_PADDING           = 0x00000001,
383 };
384 enum jme_txmcs_values {
385         TXMCS_IFG2_6_4          = 0x00000000,
386         TXMCS_IFG2_8_5          = 0x40000000,
387         TXMCS_IFG2_10_6         = 0x80000000,
388         TXMCS_IFG2_12_7         = 0xC0000000,
389
390         TXMCS_IFG1_8_4          = 0x00000000,
391         TXMCS_IFG1_12_6         = 0x10000000,
392         TXMCS_IFG1_16_8         = 0x20000000,
393         TXMCS_IFG1_20_10        = 0x30000000,
394
395         TXMCS_TTHOLD_1_8        = 0x00000000,
396         TXMCS_TTHOLD_1_4        = 0x00000100,
397         TXMCS_TTHOLD_1_2        = 0x00000200,
398         TXMCS_TTHOLD_FULL       = 0x00000300,
399
400         TXMCS_DEFAULT           = TXMCS_IFG2_8_5 |
401                                   TXMCS_IFG1_16_8 |
402                                   TXMCS_TTHOLD_FULL |
403                                   TXMCS_DEFER |
404                                   TXMCS_CRC |
405                                   TXMCS_PADDING,
406 };
407
408
409 /*
410  * RX Control/Status Bits
411  */
412 enum jme_rxcs_bit_masks {
413         RXCS_FIFOTHTP   = 0x30000000, /* FIFO full threshold for transmitting Tx Pause Packet */
414         RXCS_FIFOTHNP   = 0x0C000000, /* FIFO threshold for processing next packet */
415         RXCS_DMAREQSZ   = 0x03000000, /* DMA Request Size */
416         RXCS_QUEUESEL   = 0x00030000, /* Queue selection */
417         RXCS_RETRYGAP   = 0x0000F000, /* RX Desc full retry gap */
418         RXCS_RETRYCNT   = 0x00000F00, /* RX Desc full retry counter */
419         RXCS_WAKEUP     = 0x00000040, /* Enable receive wakeup packet */
420         RXCS_MAGIC      = 0x00000020, /* Enable receive magic packet */
421         RXCS_SHORT      = 0x00000010, /* Enable receive short packet */
422         RXCS_ABORT      = 0x00000008, /* Enable receive errorr packet */
423         RXCS_QST        = 0x00000004, /* Receive queue start */
424         RXCS_SUSPEND    = 0x00000002,
425         RXCS_ENABLE     = 0x00000001,
426 };
427 enum jme_rxcs_values {
428         RXCS_FIFOTHTP_16T       = 0x00000000,
429         RXCS_FIFOTHTP_32T       = 0x10000000,
430         RXCS_FIFOTHTP_64T       = 0x20000000,
431         RXCS_FIFOTHTP_128T      = 0x30000000,
432
433         RXCS_FIFOTHNP_16QW      = 0x00000000,
434         RXCS_FIFOTHNP_32QW      = 0x04000000,
435         RXCS_FIFOTHNP_64QW      = 0x08000000,
436         RXCS_FIFOTHNP_128QW     = 0x0C000000,
437
438         RXCS_DMAREQSZ_16B       = 0x00000000,
439         RXCS_DMAREQSZ_32B       = 0x01000000,
440         RXCS_DMAREQSZ_64B       = 0x02000000,
441         RXCS_DMAREQSZ_128B      = 0x03000000,
442
443         RXCS_QUEUESEL_Q0        = 0x00000000,
444         RXCS_QUEUESEL_Q1        = 0x00010000,
445         RXCS_QUEUESEL_Q2        = 0x00020000,
446         RXCS_QUEUESEL_Q3        = 0x00030000,
447
448         RXCS_RETRYGAP_256ns     = 0x00000000,
449         RXCS_RETRYGAP_512ns     = 0x00001000,
450         RXCS_RETRYGAP_1024ns    = 0x00002000,
451         RXCS_RETRYGAP_2048ns    = 0x00003000,
452         RXCS_RETRYGAP_4096ns    = 0x00004000,
453         RXCS_RETRYGAP_8192ns    = 0x00005000,
454         RXCS_RETRYGAP_16384ns   = 0x00006000,
455         RXCS_RETRYGAP_32768ns   = 0x00007000,
456
457         RXCS_RETRYCNT_0         = 0x00000000,
458         RXCS_RETRYCNT_4         = 0x00000100,
459         RXCS_RETRYCNT_8         = 0x00000200,
460         RXCS_RETRYCNT_12        = 0x00000300,
461         RXCS_RETRYCNT_16        = 0x00000400,
462         RXCS_RETRYCNT_20        = 0x00000500,
463         RXCS_RETRYCNT_24        = 0x00000600,
464         RXCS_RETRYCNT_28        = 0x00000700,
465         RXCS_RETRYCNT_32        = 0x00000800,
466         RXCS_RETRYCNT_36        = 0x00000900,
467         RXCS_RETRYCNT_40        = 0x00000A00,
468         RXCS_RETRYCNT_44        = 0x00000B00,
469         RXCS_RETRYCNT_48        = 0x00000C00,
470         RXCS_RETRYCNT_52        = 0x00000D00,
471         RXCS_RETRYCNT_56        = 0x00000E00,
472         RXCS_RETRYCNT_60        = 0x00000F00,
473
474         RXCS_DEFAULT            = RXCS_FIFOTHTP_128T |
475                                   RXCS_FIFOTHNP_128QW |
476                                   RXCS_DMAREQSZ_128B |
477                                   RXCS_RETRYGAP_256ns |
478                                   RXCS_RETRYCNT_32,
479 };
480 #define JME_RX_DISABLE_TIMEOUT 200 /* 200 usec */
481
482 /*
483  * RX MAC Control/Status Bits
484  */
485 enum jme_rxmcs_bits {
486         RXMCS_ALLFRAME          = 0x00000800,
487         RXMCS_BRDFRAME          = 0x00000400,
488         RXMCS_MULFRAME          = 0x00000200,
489         RXMCS_UNIFRAME          = 0x00000100,
490         RXMCS_ALLMULFRAME       = 0x00000080,
491         RXMCS_MULFILTERED       = 0x00000040,
492 };
493
494 /*
495  * SMI Related definitions
496  */
497 enum jme_smi_bit_mask
498 {
499         SMI_DATA_MASK           = 0xFFFF0000,
500         SMI_REG_ADDR_MASK       = 0x0000F800,
501         SMI_PHY_ADDR_MASK       = 0x000007C0,
502         SMI_OP_WRITE            = 0x00000020,
503         SMI_OP_REQ              = 0x00000010, /* Set to 1, after req done it'll be cleared to 0 */
504         SMI_OP_MDIO             = 0x00000008, /* Software assess In/Out */
505         SMI_OP_MDOE             = 0x00000004, /* Software Output Enable */
506         SMI_OP_MDC              = 0x00000002, /* Software CLK Control */
507         SMI_OP_MDEN             = 0x00000001, /* Software access Enable */
508 };
509 enum jme_smi_bit_shift
510 {
511         SMI_DATA_SHIFT          = 16,
512         SMI_REG_ADDR_SHIFT      = 11,
513         SMI_PHY_ADDR_SHIFT      = 6,
514 };
515 __always_inline __u32 smi_reg_addr(int x)
516 {
517         return (((x) << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK);
518 }
519 __always_inline __u32 smi_phy_addr(int x)
520 {
521         return (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK);
522 }
523 #define JME_PHY_TIMEOUT 1000 /* 1000 usec */
524
525 /*
526  * Global Host Control
527  */
528 enum jme_ghc_bit_mask {
529         GHC_SWRST       = 0x40000000,
530         GHC_DPX         = 0x00000040,
531         GHC_SPEED       = 0x00000030,
532         GHC_LINK_POLL   = 0x00000001,
533 };
534 enum jme_ghc_speed_val {
535         GHC_SPEED_10M   = 0x00000010,
536         GHC_SPEED_100M  = 0x00000020,
537         GHC_SPEED_1000M = 0x00000030,
538 };
539
540 /*
541  * Giga PHY Status Registers 
542  */
543 enum jme_phy_link_bit_mask {
544         PHY_LINK_SPEED_MASK             = 0x0000C000,
545         PHY_LINK_DUPLEX                 = 0x00002000,
546         PHY_LINK_SPEEDDPU_RESOLVED      = 0x00000800,
547         PHY_LINK_UP                     = 0x00000400,
548         PHY_LINK_AUTONEG_COMPLETE       = 0x00000200,
549 };
550 enum jme_phy_link_speed_val {
551         PHY_LINK_SPEED_10M              = 0x00000000,
552         PHY_LINK_SPEED_100M             = 0x00004000,
553         PHY_LINK_SPEED_1000M            = 0x00008000,
554 };
555 #define JME_AUTONEG_TIMEOUT     500     /* 500 ms */
556
557 /*
558  * SMB Control and Status
559  */
560 enum jme_smbcsr_bit_mask
561 {
562         SMBCSR_CNACK    = 0x00020000,
563         SMBCSR_RELOAD   = 0x00010000,
564         SMBCSR_EEPROMD  = 0x00000020,
565 };
566 #define JME_SMB_TIMEOUT 10 /* 10 msec */
567
568
569 /*
570  * General Purpost REG-0
571  */
572 enum jme_gpreg0_masks {
573         GPREG0_DISSH    = 0xFF000000,
574         GPREG0_PCIRLMT  = 0x00300000,
575         GPREG0_PCCTMR   = 0x00000300,
576         GPREG0_PHYADDR  = 0x0000001F,
577 };
578 enum jme_gpreg0_vals {
579         GPREG0_DISSH_DW7        = 0x80000000,
580         GPREG0_DISSH_DW6        = 0x40000000,
581         GPREG0_DISSH_DW5        = 0x20000000,
582         GPREG0_DISSH_DW4        = 0x10000000,
583         GPREG0_DISSH_DW3        = 0x08000000,
584         GPREG0_DISSH_DW2        = 0x04000000,
585         GPREG0_DISSH_DW1        = 0x02000000,
586         GPREG0_DISSH_DW0        = 0x01000000,
587         GPREG0_DISSH_ALL        = 0xFF000000,
588
589         GPREG0_PCIRLMT_8        = 0x00000000,
590         GPREG0_PCIRLMT_6        = 0x00100000,
591         GPREG0_PCIRLMT_5        = 0x00200000,
592         GPREG0_PCIRLMT_4        = 0x00300000,
593
594         GPREG0_PCCTMR_16ns      = 0x00000000,
595         GPREG0_PCCTMR_256ns     = 0x00000010,
596         GPREG0_PCCTMR_1us       = 0x00000020,
597         GPREG0_PCCTMR_1ms       = 0x00000030,
598
599         GPREG0_PHYADDR_1        = 0x00000001,
600
601         GPREG0_DEFAULT          = GPREG0_PCIRLMT_4 |
602                                   GPREG0_PHYADDR_1,     
603 };
604
605 /*
606  * Interrupt Status Bits
607  */
608 enum jme_interrupt_bits
609 {
610         INTR_SWINTR     = 0x80000000,
611         INTR_TMINTR     = 0x40000000,
612         INTR_LINKCH     = 0x20000000,
613         INTR_PAUSERCV   = 0x10000000,
614         INTR_MAGICRCV   = 0x08000000,
615         INTR_WAKERCV    = 0x04000000,
616         INTR_PCCRX0TO   = 0x02000000,
617         INTR_PCCRX1TO   = 0x01000000,
618         INTR_PCCRX2TO   = 0x00800000,
619         INTR_PCCRX3TO   = 0x00400000,
620         INTR_PCCTXTO    = 0x00200000,
621         INTR_PCCRX0     = 0x00100000,
622         INTR_PCCRX1     = 0x00080000,
623         INTR_PCCRX2     = 0x00040000,
624         INTR_PCCRX3     = 0x00020000,
625         INTR_PCCTX      = 0x00010000,
626         INTR_RX3EMP     = 0x00008000,
627         INTR_RX2EMP     = 0x00004000,
628         INTR_RX1EMP     = 0x00002000,
629         INTR_RX0EMP     = 0x00001000,
630         INTR_RX3        = 0x00000800,
631         INTR_RX2        = 0x00000400,
632         INTR_RX1        = 0x00000200,
633         INTR_RX0        = 0x00000100,
634         INTR_TX7        = 0x00000080,
635         INTR_TX6        = 0x00000040,
636         INTR_TX5        = 0x00000020,
637         INTR_TX4        = 0x00000010,
638         INTR_TX3        = 0x00000008,
639         INTR_TX2        = 0x00000004,
640         INTR_TX1        = 0x00000002,
641         INTR_TX0        = 0x00000001,
642 };
643 static const __u32 INTR_ENABLE = INTR_LINKCH |
644                                  INTR_RX0EMP |
645                                  INTR_RX0 |
646                                  INTR_TX0;
647
648 /*
649  * Shadow base address register bits
650  */
651 enum jme_shadow_base_address_bits {
652         SHBA_POSTEN     = 0x1,
653 };
654
655 /*
656  * Read/Write MMaped I/O Registers
657  */
658 __always_inline __u32 jread32(struct jme_adapter *jme, __u32 reg)
659 {
660         return le32_to_cpu(readl(jme->regs + reg));
661 }
662 __always_inline void jwrite32(struct jme_adapter *jme, __u32 reg, __u32 val)
663 {
664         writel(cpu_to_le32(val), jme->regs + reg);
665 }
666 __always_inline void jwrite32f(struct jme_adapter *jme, __u32 reg, __u32 val)
667 {
668         /*
669          * Read after write should cause flush
670          */
671         writel(cpu_to_le32(val), jme->regs + reg);
672         readl(jme->regs + reg);
673 }
674
675 /*
676  * Function prototypes for ethtool
677  */
678 static void jme_get_drvinfo(struct net_device *netdev,
679                              struct ethtool_drvinfo *info);
680 static int jme_get_settings(struct net_device *netdev,
681                              struct ethtool_cmd *ecmd);
682 static int jme_set_settings(struct net_device *netdev,
683                              struct ethtool_cmd *ecmd);
684 static u32 jme_get_link(struct net_device *netdev);
685
686
687 /*
688  * Function prototypes for netdev
689  */
690 static int jme_open(struct net_device *netdev);
691 static int jme_close(struct net_device *netdev);
692 static int jme_start_xmit(struct sk_buff *skb, struct net_device *netdev);
693 static int jme_set_macaddr(struct net_device *netdev, void *p);
694 static void jme_set_multi(struct net_device *netdev);
695