jme.h

   1 /*
   2  * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
   3  *
   4  * Copyright 2008 JMicron Technology Corporation
   5  * http://www.jmicron.com/
   6  *
   7  * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  *
  22  */
  23
  24 #include <linux/version.h>
  25
  26 #define DRV_NAME        "jme"
  27 #define DRV_VERSION     "0.3"
  28 #define PFX DRV_NAME    ": "
  29
  30 #ifdef DEBUG
  31 #define dprintk(devname, fmt, args...) \
  32         printk(KERN_DEBUG PFX "%s: " fmt, devname, ## args)
  33 #else
  34 #define dprintk(devname, fmt, args...)
  35 #endif
  36
  37 #ifdef TX_DEBUG
  38 #define tx_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
  39 #else
  40 #define tx_dbg(args...)
  41 #endif
  42
  43 #ifdef RX_DEBUG
  44 #define rx_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
  45 #else
  46 #define rx_dbg(args...)
  47 #endif
  48
  49 #define jprintk(devname, fmt, args...) \
  50         printk(KERN_INFO PFX "%s: " fmt, devname, ## args)
  51
  52 #define jeprintk(devname, fmt, args...) \
  53         printk(KERN_ERR PFX "%s: " fmt, devname, ## args)
  54
  55 #define USE_IEVE_SHADOW 0
  56
  57 #define DEFAULT_MSG_ENABLE        \
  58         (NETIF_MSG_DRV          | \
  59          NETIF_MSG_PROBE        | \
  60          NETIF_MSG_LINK         | \
  61          NETIF_MSG_TIMER        | \
  62          NETIF_MSG_RX_ERR       | \
  63          NETIF_MSG_TX_ERR)
  64
  65 #define PCI_CONF_DCSR_MRRS      0x59
  66 #define PCI_CONF_DCSR_MRRS_MASK 0x70
  67 enum pci_conf_dcsr_mrrs_vals {
  68         MRRS_128B       = 0x00,
  69         MRRS_256B       = 0x10,
  70         MRRS_512B       = 0x20,
  71         MRRS_1024B      = 0x30,
  72         MRRS_2048B      = 0x40,
  73         MRRS_4096B      = 0x50,
  74 };
  75
  76 enum dynamic_pcc_values {
  77         PCC_P1          = 1,
  78         PCC_P2          = 2,
  79         PCC_P3          = 3,
  80
  81         PCC_P1_TO       = 1,
  82         PCC_P2_TO       = 250,
  83         PCC_P3_TO       = 1000,
  84
  85         PCC_P1_CNT      = 1,
  86         PCC_P2_CNT      = 64,
  87         PCC_P3_CNT      = 255,
  88 };
  89 struct dynpcc_info {
  90         unsigned long   check_point;
  91         unsigned long   last_bytes;
  92         unsigned long   last_pkts;
  93         unsigned char   cur;
  94         unsigned char   attempt;
  95         unsigned char   cnt;
  96 };
  97 #define PCC_INTERVAL (HZ / 10)
  98 #define PCC_P3_THRESHOLD 3*1024*1024
  99 #define PCC_P2_THRESHOLD 1000
 100
 101 /*
 102  * TX/RX Descriptors
 103  *
 104  * TX/RX Ring DESC Count Must be multiple of 16
 105  * RX Ring DESC Count Must be <= 1024
 106  */
 107 #define RING_DESC_NR            512     /* Must be power of 2 */
 108 #define RING_DESC_ALIGN         16      /* Descriptor alignment */
 109
 110 #define TX_DESC_SIZE            16
 111 #define TX_RING_NR              8
 112 #define TX_RING_ALLOC_SIZE      (RING_DESC_NR * TX_DESC_SIZE) + TX_DESC_SIZE
 113 #define TX_RING_SIZE            (RING_DESC_NR * TX_DESC_SIZE)
 114
 115 struct txdesc {
 116         union {
 117                 __u8  all[16];
 118                 __u32 dw[4];
 119                 struct {
 120                         /* DW0 */
 121                         __u16 vlan;
 122                         __u8 rsv1;
 123                         __u8 flags;
 124
 125                         /* DW1 */
 126                         __u16 datalen;
 127                         __u16 mss;
 128
 129                         /* DW2 */
 130                         __u16 pktsize;
 131                         __u16 rsv2;
 132
 133                         /* DW3 */
 134                         __u32 bufaddr;
 135                 } desc1;
 136                 struct {
 137                         /* DW0 */
 138                         __u16 rsv1;
 139                         __u8 rsv2;
 140                         __u8 flags;
 141
 142                         /* DW1 */
 143                         __u16 datalen;
 144                         __u16 rsv3;
 145
 146                         /* DW2 */
 147                         __u32 bufaddrh;
 148
 149                         /* DW3 */
 150                         __u32 bufaddrl;
 151                 } desc2;
 152         };
 153 };
 154 enum jme_txdesc_flag_bits {
 155         TXFLAG_OWN      = 0x80,
 156         TXFLAG_INT      = 0x40,
 157         TXFLAG_64BIT    = 0x20,
 158         TXFLAG_TCPCS    = 0x10,
 159         TXFLAG_UDPCS    = 0x08,
 160         TXFLAG_IPCS     = 0x04,
 161         TXFLAG_LSEN     = 0x02,
 162         TXFLAG_TAGON    = 0x01,
 163 };
 164
 165
 166 #define RX_DESC_SIZE            16
 167 #define RX_RING_NR              4
 168 #define RX_RING_ALLOC_SIZE      (RING_DESC_NR * RX_DESC_SIZE) + RX_DESC_SIZE
 169 #define RX_RING_SIZE            (RING_DESC_NR * RX_DESC_SIZE)
 170
 171 #define RX_BUF_DMA_ALIGN        8
 172 //#define RX_BUF_SIZE           1600
 173 #define RX_BUF_SIZE             9200
 174 //#define RX_BUF_SIZE           4000
 175 #define RX_PREPAD_SIZE          10
 176
 177 /*
 178  * Will use mtu in the future
 179  */
 180 #define RX_BUF_ALLOC_SIZE       RX_BUF_SIZE + RX_BUF_DMA_ALIGN
 181
 182 struct rxdesc {
 183         union {
 184                 __u8   all[16];
 185                 __le32 dw[4];
 186                 struct {
 187                         /* DW0 */
 188                         __le16 rsv2;
 189                         __u8 rsv1;
 190                         __u8 flags;
 191
 192                         /* DW1 */
 193                         __le16 datalen;
 194                         __le16 wbcpl;
 195
 196                         /* DW2 */
 197                         __le32 bufaddrh;
 198
 199                         /* DW3 */
 200                         __le32 bufaddrl;
 201                 } desc1;
 202                 struct {
 203                         /* DW0 */
 204                         __le16 vlan;
 205                         __le16 flags;
 206
 207                         /* DW1 */
 208                         __le16 framesize;
 209                         __u8 errstat;
 210                         __u8 desccnt;
 211
 212                         /* DW2 */
 213                         __le32 rsshash;
 214
 215                         /* DW3 */
 216                         __u8   hashfun;
 217                         __u8   hashtype;
 218                         __le16 resrv;
 219                 } descwb;
 220         };
 221 };
 222 enum jme_rxdesc_flags_bits {
 223         RXFLAG_OWN      = 0x80,
 224         RXFLAG_INT      = 0x40,
 225         RXFLAG_64BIT    = 0x20,
 226 };
 227 enum jme_rxwbdesc_flags_bits {
 228         RXWBFLAG_OWN            = 0x8000,
 229         RXWBFLAG_INT            = 0x4000,
 230         RXWBFLAG_MF             = 0x2000,
 231         RXWBFLAG_64BIT          = 0x2000,
 232         RXWBFLAG_TCPON          = 0x1000,
 233         RXWBFLAG_UDPON          = 0x0800,
 234         RXWBFLAG_IPCS           = 0x0400,
 235         RXWBFLAG_TCPCS          = 0x0200,
 236         RXWBFLAG_UDPCS          = 0x0100,
 237         RXWBFLAG_TAGON          = 0x0080,
 238         RXWBFLAG_IPV4           = 0x0040,
 239         RXWBFLAG_IPV6           = 0x0020,
 240         RXWBFLAG_PAUSE          = 0x0010,
 241         RXWBFLAG_MAGIC          = 0x0008,
 242         RXWBFLAG_WAKEUP         = 0x0004,
 243         RXWBFLAG_DEST           = 0x0003,
 244         RXWBFLAG_DEST_UNI       = 0x0001,
 245         RXWBFLAG_DEST_MUL       = 0x0002,
 246         RXWBFLAG_DEST_BRO       = 0x0003,
 247 };
 248 enum jme_rxwbdesc_desccnt_mask {
 249         RXWBDCNT_WBCPL  = 0x80,
 250         RXWBDCNT_DCNT   = 0x7F,
 251 };
 252 enum jme_rxwbdesc_errstat_bits {
 253         RXWBERR_LIMIT   = 0x80,
 254         RXWBERR_MIIER   = 0x40,
 255         RXWBERR_NIBON   = 0x20,
 256         RXWBERR_COLON   = 0x10,
 257         RXWBERR_ABORT   = 0x08,
 258         RXWBERR_SHORT   = 0x04,
 259         RXWBERR_OVERUN  = 0x02,
 260         RXWBERR_CRCERR  = 0x01,
 261         RXWBERR_ALLERR  = 0xFF,
 262 };
 263
 264 struct jme_buffer_info {
 265         struct sk_buff *skb;
 266         dma_addr_t mapping;
 267         int len;
 268         int nr_desc;
 269 };
 270
 271 struct jme_ring {
 272         void* alloc;            /* pointer to allocated memory */
 273         volatile void* desc;    /* pointer to ring memory  */
 274         dma_addr_t dmaalloc;    /* phys address of ring alloc */
 275         dma_addr_t dma;         /* phys address for ring dma */
 276
 277         /* Buffer information corresponding to each descriptor */
 278         struct jme_buffer_info bufinf[RING_DESC_NR];
 279
 280         u16 next_to_use;
 281         u16 next_to_clean;
 282
 283         u16 nr_free;
 284 };
 285
 286 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
 287 #define NET_STAT(priv) priv->stats
 288 #define NETDEV_GET_STATS(netdev, fun_ptr) \
 289         netdev->get_stats = fun_ptr
 290 #define DECLARE_NET_DEVICE_STATS struct net_device_stats stats;
 291 #else
 292 #define NET_STAT(priv) priv->dev->stats
 293 #define NETDEV_GET_STATS(netdev, fun_ptr)
 294 #define DECLARE_NET_DEVICE_STATS
 295 #endif
 296
 297 /*
 298  * Jmac Adapter Private data
 299  */
 300 #define SHADOW_REG_NR 8
 301 struct jme_adapter {
 302         struct pci_dev          *pdev;
 303         struct net_device       *dev;
 304         void __iomem            *regs;
 305         dma_addr_t              shadow_dma;
 306         __u32                   *shadow_regs;
 307         struct mii_if_info      mii_if;
 308         struct jme_ring         rxring[RX_RING_NR];
 309         struct jme_ring         txring[TX_RING_NR];
 310         spinlock_t              rx_lock;
 311         spinlock_t              tx_lock;
 312         spinlock_t              phy_lock;
 313         struct tasklet_struct   rxclean_task;
 314         struct tasklet_struct   txclean_task;
 315         struct tasklet_struct   linkch_task;
 316         __u32                   flags;
 317         __u32                   reg_txcs;
 318         __u32                   reg_rxmcs;
 319         __u32                   reg_ghc;
 320         struct dynpcc_info      dpi;
 321         atomic_t                intr_sem;
 322         DECLARE_NET_DEVICE_STATS
 323 };
 324 enum shadow_reg_val {
 325         SHADOW_IEVE = 0,
 326 };
 327
 328 #define JME_FLAG_RXQ0_EMPTY    0x00000001
 329 #define JME_FLAG_RXQ1_EMPTY    0x00000002
 330 #define JME_FLAG_RXQ2_EMPTY    0x00000004
 331 #define JME_FLAG_RXQ3_EMPTY    0x00000008
 332
 333 /*
 334  * MMaped I/O Resters
 335  */
 336 enum jme_iomap_offsets {
 337         JME_MAC         = 0x0000,
 338         JME_PHY         = 0x0400,
 339         JME_MISC        = 0x0800,
 340         JME_RSS         = 0x0C00,
 341 };
 342
 343 enum jme_iomap_regs {
 344         JME_TXCS        = JME_MAC | 0x00, /* Transmit Control and Status */
 345         JME_TXDBA_LO    = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
 346         JME_TXDBA_HI    = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
 347         JME_TXQDC       = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
 348         JME_TXNDA       = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
 349         JME_TXMCS       = JME_MAC | 0x14, /* Transmit MAC Control Status */
 350         JME_TXPFC       = JME_MAC | 0x18, /* Transmit Pause Frame Control */
 351         JME_TXTRHD      = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
 352
 353         JME_RXCS        = JME_MAC | 0x20, /* Receive Control and Status */
 354         JME_RXDBA_LO    = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
 355         JME_RXDBA_HI    = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
 356         JME_RXQDC       = JME_MAC | 0x2C, /* Receive Queue Desc Count */
 357         JME_RXNDA       = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
 358         JME_RXMCS       = JME_MAC | 0x34, /* Receive MAC Control Status */
 359         JME_RXUMA_LO    = JME_MAC | 0x38, /* Receive Unicast MAC Address */
 360         JME_RXUMA_HI    = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
 361         JME_RXMCHT_LO   = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
 362         JME_RXMCHT_HI   = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
 363         JME_WFODP       = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
 364         JME_WFOI        = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
 365
 366         JME_SMI         = JME_MAC | 0x50, /* Station Management Interface */
 367         JME_GHC         = JME_MAC | 0x54, /* Global Host Control */
 368         JME_PMCS        = JME_MAC | 0x60, /* Power Management Control/Stat */
 369
 370
 371         JME_PHY_CS      = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
 372         JME_PHY_LINK    = JME_PHY | 0x30, /* PHY Link Status Register */
 373         JME_SMBCSR      = JME_PHY | 0x40, /* SMB Control and Status */
 374
 375
 376         JME_GPREG0      = JME_MISC| 0x08, /* General purpose REG-0 */
 377         JME_GPREG1      = JME_MISC| 0x0C, /* General purpose REG-1 */
 378         JME_IEVE        = JME_MISC| 0x20, /* Interrupt Event Status */
 379         JME_IREQ        = JME_MISC| 0x24, /* Interrupt Req Status(For Debug) */
 380         JME_IENS        = JME_MISC| 0x28, /* Interrupt Enable - Setting Port */
 381         JME_IENC        = JME_MISC| 0x2C, /* Interrupt Enable - Clear Port */
 382         JME_PCCRX0      = JME_MISC| 0x30, /* PCC Control for RX Queue 0 */
 383         JME_PCCTX       = JME_MISC| 0x40, /* PCC Control for TX Queues */
 384         JME_SHBA_HI     = JME_MISC| 0x48, /* Shadow Register Base HI */
 385         JME_SHBA_LO     = JME_MISC| 0x4C, /* Shadow Register Base LO */
 386         JME_PCCSRX0     = JME_MISC| 0x80, /* PCC Status of RX0 */
 387 };
 388
 389 /*
 390  * TX Control/Status Bits
 391  */
 392 enum jme_txcs_bits {
 393         TXCS_QUEUE7S    = 0x00008000,
 394         TXCS_QUEUE6S    = 0x00004000,
 395         TXCS_QUEUE5S    = 0x00002000,
 396         TXCS_QUEUE4S    = 0x00001000,
 397         TXCS_QUEUE3S    = 0x00000800,
 398         TXCS_QUEUE2S    = 0x00000400,
 399         TXCS_QUEUE1S    = 0x00000200,
 400         TXCS_QUEUE0S    = 0x00000100,
 401         TXCS_FIFOTH     = 0x000000C0,
 402         TXCS_DMASIZE    = 0x00000030,
 403         TXCS_BURST      = 0x00000004,
 404         TXCS_ENABLE     = 0x00000001,
 405 };
 406 enum jme_txcs_value {
 407         TXCS_FIFOTH_16QW        = 0x000000C0,
 408         TXCS_FIFOTH_12QW        = 0x00000080,
 409         TXCS_FIFOTH_8QW         = 0x00000040,
 410         TXCS_FIFOTH_4QW         = 0x00000000,
 411
 412         TXCS_DMASIZE_64B        = 0x00000000,
 413         TXCS_DMASIZE_128B       = 0x00000010,
 414         TXCS_DMASIZE_256B       = 0x00000020,
 415         TXCS_DMASIZE_512B       = 0x00000030,
 416
 417         TXCS_SELECT_QUEUE0      = 0x00000000,
 418         TXCS_SELECT_QUEUE1      = 0x00010000,
 419         TXCS_SELECT_QUEUE2      = 0x00020000,
 420         TXCS_SELECT_QUEUE3      = 0x00030000,
 421         TXCS_SELECT_QUEUE4      = 0x00040000,
 422         TXCS_SELECT_QUEUE5      = 0x00050000,
 423         TXCS_SELECT_QUEUE6      = 0x00060000,
 424         TXCS_SELECT_QUEUE7      = 0x00070000,
 425
 426         TXCS_DEFAULT            = TXCS_FIFOTH_4QW |
 427                                   TXCS_BURST,
 428 };
 429 #define JME_TX_DISABLE_TIMEOUT 200 /* 200 usec */
 430
 431 /*
 432  * TX MAC Control/Status Bits
 433  */
 434 enum jme_txmcs_bit_masks {
 435         TXMCS_IFG2              = 0xC0000000,
 436         TXMCS_IFG1              = 0x30000000,
 437         TXMCS_TTHOLD            = 0x00000300,
 438         TXMCS_FBURST            = 0x00000080,
 439         TXMCS_CARRIEREXT        = 0x00000040,
 440         TXMCS_DEFER             = 0x00000020,
 441         TXMCS_BACKOFF           = 0x00000010,
 442         TXMCS_CARRIERSENSE      = 0x00000008,
 443         TXMCS_COLLISION         = 0x00000004,
 444         TXMCS_CRC               = 0x00000002,
 445         TXMCS_PADDING           = 0x00000001,
 446 };
 447 enum jme_txmcs_values {
 448         TXMCS_IFG2_6_4          = 0x00000000,
 449         TXMCS_IFG2_8_5          = 0x40000000,
 450         TXMCS_IFG2_10_6         = 0x80000000,
 451         TXMCS_IFG2_12_7         = 0xC0000000,
 452
 453         TXMCS_IFG1_8_4          = 0x00000000,
 454         TXMCS_IFG1_12_6         = 0x10000000,
 455         TXMCS_IFG1_16_8         = 0x20000000,
 456         TXMCS_IFG1_20_10        = 0x30000000,
 457
 458         TXMCS_TTHOLD_1_8        = 0x00000000,
 459         TXMCS_TTHOLD_1_4        = 0x00000100,
 460         TXMCS_TTHOLD_1_2        = 0x00000200,
 461         TXMCS_TTHOLD_FULL       = 0x00000300,
 462
 463         TXMCS_DEFAULT           = TXMCS_IFG2_8_5 |
 464                                   TXMCS_IFG1_16_8 |
 465                                   TXMCS_TTHOLD_FULL |
 466                                   TXMCS_DEFER |
 467                                   TXMCS_CRC |
 468                                   TXMCS_PADDING,
 469 };
 470
 471
 472 /*
 473  * RX Control/Status Bits
 474  */
 475 enum jme_rxcs_bit_masks {
 476         /* FIFO full threshold for transmitting Tx Pause Packet */
 477         RXCS_FIFOTHTP   = 0x30000000,
 478         /* FIFO threshold for processing next packet */
 479         RXCS_FIFOTHNP   = 0x0C000000,
 480         RXCS_DMAREQSZ   = 0x03000000, /* DMA Request Size */
 481         RXCS_QUEUESEL   = 0x00030000, /* Queue selection */
 482         RXCS_RETRYGAP   = 0x0000F000, /* RX Desc full retry gap */
 483         RXCS_RETRYCNT   = 0x00000F00, /* RX Desc full retry counter */
 484         RXCS_WAKEUP     = 0x00000040, /* Enable receive wakeup packet */
 485         RXCS_MAGIC      = 0x00000020, /* Enable receive magic packet */
 486         RXCS_SHORT      = 0x00000010, /* Enable receive short packet */
 487         RXCS_ABORT      = 0x00000008, /* Enable receive errorr packet */
 488         RXCS_QST        = 0x00000004, /* Receive queue start */
 489         RXCS_SUSPEND    = 0x00000002,
 490         RXCS_ENABLE     = 0x00000001,
 491 };
 492 enum jme_rxcs_values {
 493         RXCS_FIFOTHTP_16T       = 0x00000000,
 494         RXCS_FIFOTHTP_32T       = 0x10000000,
 495         RXCS_FIFOTHTP_64T       = 0x20000000,
 496         RXCS_FIFOTHTP_128T      = 0x30000000,
 497
 498         RXCS_FIFOTHNP_16QW      = 0x00000000,
 499         RXCS_FIFOTHNP_32QW      = 0x04000000,
 500         RXCS_FIFOTHNP_64QW      = 0x08000000,
 501         RXCS_FIFOTHNP_128QW     = 0x0C000000,
 502
 503         RXCS_DMAREQSZ_16B       = 0x00000000,
 504         RXCS_DMAREQSZ_32B       = 0x01000000,
 505         RXCS_DMAREQSZ_64B       = 0x02000000,
 506         RXCS_DMAREQSZ_128B      = 0x03000000,
 507
 508         RXCS_QUEUESEL_Q0        = 0x00000000,
 509         RXCS_QUEUESEL_Q1        = 0x00010000,
 510         RXCS_QUEUESEL_Q2        = 0x00020000,
 511         RXCS_QUEUESEL_Q3        = 0x00030000,
 512
 513         RXCS_RETRYGAP_256ns     = 0x00000000,
 514         RXCS_RETRYGAP_512ns     = 0x00001000,
 515         RXCS_RETRYGAP_1024ns    = 0x00002000,
 516         RXCS_RETRYGAP_2048ns    = 0x00003000,
 517         RXCS_RETRYGAP_4096ns    = 0x00004000,
 518         RXCS_RETRYGAP_8192ns    = 0x00005000,
 519         RXCS_RETRYGAP_16384ns   = 0x00006000,
 520         RXCS_RETRYGAP_32768ns   = 0x00007000,
 521
 522         RXCS_RETRYCNT_0         = 0x00000000,
 523         RXCS_RETRYCNT_4         = 0x00000100,
 524         RXCS_RETRYCNT_8         = 0x00000200,
 525         RXCS_RETRYCNT_12        = 0x00000300,
 526         RXCS_RETRYCNT_16        = 0x00000400,
 527         RXCS_RETRYCNT_20        = 0x00000500,
 528         RXCS_RETRYCNT_24        = 0x00000600,
 529         RXCS_RETRYCNT_28        = 0x00000700,
 530         RXCS_RETRYCNT_32        = 0x00000800,
 531         RXCS_RETRYCNT_36        = 0x00000900,
 532         RXCS_RETRYCNT_40        = 0x00000A00,
 533         RXCS_RETRYCNT_44        = 0x00000B00,
 534         RXCS_RETRYCNT_48        = 0x00000C00,
 535         RXCS_RETRYCNT_52        = 0x00000D00,
 536         RXCS_RETRYCNT_56        = 0x00000E00,
 537         RXCS_RETRYCNT_60        = 0x00000F00,
 538
 539         RXCS_DEFAULT            = RXCS_FIFOTHTP_128T |
 540                                   RXCS_FIFOTHNP_128QW |
 541                                   RXCS_DMAREQSZ_128B |
 542                                   RXCS_RETRYGAP_256ns |
 543                                   RXCS_RETRYCNT_32,
 544 };
 545 #define JME_RX_DISABLE_TIMEOUT 200 /* 200 usec */
 546
 547 /*
 548  * RX MAC Control/Status Bits
 549  */
 550 enum jme_rxmcs_bits {
 551         RXMCS_ALLFRAME          = 0x00000800,
 552         RXMCS_BRDFRAME          = 0x00000400,
 553         RXMCS_MULFRAME          = 0x00000200,
 554         RXMCS_UNIFRAME          = 0x00000100,
 555         RXMCS_ALLMULFRAME       = 0x00000080,
 556         RXMCS_MULFILTERED       = 0x00000040,
 557         RXMCS_RXCOLLDEC         = 0x00000020,
 558         RXMCS_FLOWCTRL          = 0x00000008,
 559         RXMCS_VTAGRM            = 0x00000004,
 560         RXMCS_PREPAD            = 0x00000002,
 561         RXMCS_CHECKSUM          = 0x00000001,
 562 };
 563
 564 /*
 565  * SMI Related definitions
 566  */
 567 enum jme_smi_bit_mask
 568 {
 569         SMI_DATA_MASK           = 0xFFFF0000,
 570         SMI_REG_ADDR_MASK       = 0x0000F800,
 571         SMI_PHY_ADDR_MASK       = 0x000007C0,
 572         SMI_OP_WRITE            = 0x00000020,
 573         /* Set to 1, after req done it'll be cleared to 0 */
 574         SMI_OP_REQ              = 0x00000010,
 575         SMI_OP_MDIO             = 0x00000008, /* Software assess In/Out */
 576         SMI_OP_MDOE             = 0x00000004, /* Software Output Enable */
 577         SMI_OP_MDC              = 0x00000002, /* Software CLK Control */
 578         SMI_OP_MDEN             = 0x00000001, /* Software access Enable */
 579 };
 580 enum jme_smi_bit_shift
 581 {
 582         SMI_DATA_SHIFT          = 16,
 583         SMI_REG_ADDR_SHIFT      = 11,
 584         SMI_PHY_ADDR_SHIFT      = 6,
 585 };
 586 __always_inline __u32 smi_reg_addr(int x)
 587 {
 588         return (((x) << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK);
 589 }
 590 __always_inline __u32 smi_phy_addr(int x)
 591 {
 592         return (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK);
 593 }
 594 #define JME_PHY_TIMEOUT 1000 /* 1000 usec */
 595 #define JME_PHY_RST_TIMEOUT 100 /* 100 usec */
 596
 597 /*
 598  * Global Host Control
 599  */
 600 enum jme_ghc_bit_mask {
 601         GHC_SWRST       = 0x40000000,
 602         GHC_DPX         = 0x00000040,
 603         GHC_SPEED       = 0x00000030,
 604         GHC_LINK_POLL   = 0x00000001,
 605 };
 606 enum jme_ghc_speed_val {
 607         GHC_SPEED_10M   = 0x00000010,
 608         GHC_SPEED_100M  = 0x00000020,
 609         GHC_SPEED_1000M = 0x00000030,
 610 };
 611
 612 /*
 613  * Giga PHY Status Registers
 614  */
 615 enum jme_phy_link_bit_mask {
 616         PHY_LINK_SPEED_MASK             = 0x0000C000,
 617         PHY_LINK_DUPLEX                 = 0x00002000,
 618         PHY_LINK_SPEEDDPU_RESOLVED      = 0x00000800,
 619         PHY_LINK_UP                     = 0x00000400,
 620         PHY_LINK_AUTONEG_COMPLETE       = 0x00000200,
 621 };
 622 enum jme_phy_link_speed_val {
 623         PHY_LINK_SPEED_10M              = 0x00000000,
 624         PHY_LINK_SPEED_100M             = 0x00004000,
 625         PHY_LINK_SPEED_1000M            = 0x00008000,
 626 };
 627 #define JME_AUTONEG_TIMEOUT     500     /* 500 ms */
 628
 629 /*
 630  * SMB Control and Status
 631  */
 632 enum jme_smbcsr_bit_mask
 633 {
 634         SMBCSR_CNACK    = 0x00020000,
 635         SMBCSR_RELOAD   = 0x00010000,
 636         SMBCSR_EEPROMD  = 0x00000020,
 637 };
 638 #define JME_SMB_TIMEOUT 10 /* 10 msec */
 639
 640
 641 /*
 642  * General Purpost REG-0
 643  */
 644 enum jme_gpreg0_masks {
 645         GPREG0_DISSH            = 0xFF000000,
 646         GPREG0_PCIRLMT          = 0x00300000,
 647         GPREG0_PCCNOMUTCLR      = 0x00040000,
 648         GPREG0_PCCTMR           = 0x00000300,
 649         GPREG0_PHYADDR          = 0x0000001F,
 650 };
 651 enum jme_gpreg0_vals {
 652         GPREG0_DISSH_DW7        = 0x80000000,
 653         GPREG0_DISSH_DW6        = 0x40000000,
 654         GPREG0_DISSH_DW5        = 0x20000000,
 655         GPREG0_DISSH_DW4        = 0x10000000,
 656         GPREG0_DISSH_DW3        = 0x08000000,
 657         GPREG0_DISSH_DW2        = 0x04000000,
 658         GPREG0_DISSH_DW1        = 0x02000000,
 659         GPREG0_DISSH_DW0        = 0x01000000,
 660         GPREG0_DISSH_ALL        = 0xFF000000,
 661
 662         GPREG0_PCIRLMT_8        = 0x00000000,
 663         GPREG0_PCIRLMT_6        = 0x00100000,
 664         GPREG0_PCIRLMT_5        = 0x00200000,
 665         GPREG0_PCIRLMT_4        = 0x00300000,
 666
 667         GPREG0_PCCTMR_16ns      = 0x00000000,
 668         GPREG0_PCCTMR_256ns     = 0x00000100,
 669         GPREG0_PCCTMR_1us       = 0x00000200,
 670         GPREG0_PCCTMR_1ms       = 0x00000300,
 671
 672         GPREG0_PHYADDR_1        = 0x00000001,
 673
 674         GPREG0_DEFAULT          = GPREG0_PCIRLMT_4 |
 675                                   GPREG0_PCCNOMUTCLR |
 676                                   GPREG0_PCCTMR_1us |
 677                                   GPREG0_PHYADDR_1,
 678 };
 679
 680 /*
 681  * Interrupt Status Bits
 682  */
 683 enum jme_interrupt_bits
 684 {
 685         INTR_SWINTR     = 0x80000000,
 686         INTR_TMINTR     = 0x40000000,
 687         INTR_LINKCH     = 0x20000000,
 688         INTR_PAUSERCV   = 0x10000000,
 689         INTR_MAGICRCV   = 0x08000000,
 690         INTR_WAKERCV    = 0x04000000,
 691         INTR_PCCRX0TO   = 0x02000000,
 692         INTR_PCCRX1TO   = 0x01000000,
 693         INTR_PCCRX2TO   = 0x00800000,
 694         INTR_PCCRX3TO   = 0x00400000,
 695         INTR_PCCTXTO    = 0x00200000,
 696         INTR_PCCRX0     = 0x00100000,
 697         INTR_PCCRX1     = 0x00080000,
 698         INTR_PCCRX2     = 0x00040000,
 699         INTR_PCCRX3     = 0x00020000,
 700         INTR_PCCTX      = 0x00010000,
 701         INTR_RX3EMP     = 0x00008000,
 702         INTR_RX2EMP     = 0x00004000,
 703         INTR_RX1EMP     = 0x00002000,
 704         INTR_RX0EMP     = 0x00001000,
 705         INTR_RX3        = 0x00000800,
 706         INTR_RX2        = 0x00000400,
 707         INTR_RX1        = 0x00000200,
 708         INTR_RX0        = 0x00000100,
 709         INTR_TX7        = 0x00000080,
 710         INTR_TX6        = 0x00000040,
 711         INTR_TX5        = 0x00000020,
 712         INTR_TX4        = 0x00000010,
 713         INTR_TX3        = 0x00000008,
 714         INTR_TX2        = 0x00000004,
 715         INTR_TX1        = 0x00000002,
 716         INTR_TX0        = 0x00000001,
 717 };
 718 static const __u32 INTR_ENABLE = INTR_LINKCH |
 719                                  INTR_RX0EMP |
 720                                  INTR_PCCRX0TO |
 721                                  INTR_PCCRX0 |
 722                                  INTR_PCCTXTO |
 723                                  INTR_PCCTX;
 724
 725 /*
 726  * PCC Control Registers
 727  */
 728 enum jme_pccrx_masks {
 729         PCCRXTO_MASK    = 0xFFFF0000,
 730         PCCRX_MASK      = 0x0000FF00,
 731 };
 732 enum jme_pcctx_masks {
 733         PCCTXTO_MASK    = 0xFFFF0000,
 734         PCCTX_MASK      = 0x0000FF00,
 735         PCCTX_QS_MASK   = 0x000000FF,
 736 };
 737 enum jme_pccrx_shifts {
 738         PCCRXTO_SHIFT   = 16,
 739         PCCRX_SHIFT     = 8,
 740 };
 741 enum jme_pcctx_shifts {
 742         PCCTXTO_SHIFT   = 16,
 743         PCCTX_SHIFT     = 8,
 744 };
 745 enum jme_pcctx_bits {
 746         PCCTXQ0_EN      = 0x00000001,
 747         PCCTXQ1_EN      = 0x00000002,
 748         PCCTXQ2_EN      = 0x00000004,
 749         PCCTXQ3_EN      = 0x00000008,
 750         PCCTXQ4_EN      = 0x00000010,
 751         PCCTXQ5_EN      = 0x00000020,
 752         PCCTXQ6_EN      = 0x00000040,
 753         PCCTXQ7_EN      = 0x00000080,
 754 };
 755
 756
 757 /*
 758  * Shadow base address register bits
 759  */
 760 enum jme_shadow_base_address_bits {
 761         SHBA_POSTEN     = 0x1,
 762 };
 763
 764 /*
 765  * Read/Write MMaped I/O Registers
 766  */
 767 __always_inline __u32 jread32(struct jme_adapter *jme, __u32 reg)
 768 {
 769         return le32_to_cpu(readl(jme->regs + reg));
 770 }
 771 __always_inline void jwrite32(struct jme_adapter *jme, __u32 reg, __u32 val)
 772 {
 773         writel(cpu_to_le32(val), jme->regs + reg);
 774 }
 775 __always_inline void jwrite32f(struct jme_adapter *jme, __u32 reg, __u32 val)
 776 {
 777         /*
 778          * Read after write should cause flush
 779          */
 780         writel(cpu_to_le32(val), jme->regs + reg);
 781         readl(jme->regs + reg);
 782 }
 783
 784 /*
 785  * Function prototypes for ethtool
 786  */
 787 static void jme_get_drvinfo(struct net_device *netdev,
 788                              struct ethtool_drvinfo *info);
 789 static int jme_get_settings(struct net_device *netdev,
 790                              struct ethtool_cmd *ecmd);
 791 static int jme_set_settings(struct net_device *netdev,
 792                              struct ethtool_cmd *ecmd);
 793 static u32 jme_get_link(struct net_device *netdev);
 794
 795
 796 /*
 797  * Function prototypes for netdev
 798  */
 799 static int jme_open(struct net_device *netdev);
 800 static int jme_close(struct net_device *netdev);
 801 static int jme_start_xmit(struct sk_buff *skb, struct net_device *netdev);
 802 static int jme_set_macaddr(struct net_device *netdev, void *p);
 803 static void jme_set_multi(struct net_device *netdev);
 804