Import jme 1.0-backport source
[jme.git] / jme.h
1 /*
2  * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3  *
4  * Copyright 2008 JMicron Technology Corporation
5  * http://www.jmicron.com/
6  *
7  * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2 of the License.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21  *
22  */
23
24 #ifndef __JME_H_INCLUDED__
25 #define __JME_H_INCLUDEE__
26
27 #define DRV_NAME        "jme"
28 #define DRV_VERSION     "1.0"
29 #define PFX             DRV_NAME ": "
30
31 #define PCI_DEVICE_ID_JMICRON_JMC250    0x0250
32 #define PCI_DEVICE_ID_JMICRON_JMC260    0x0260
33
34 /*
35  * Message related definitions
36  */
37 #define JME_DEF_MSG_ENABLE \
38         (NETIF_MSG_PROBE | \
39         NETIF_MSG_LINK | \
40         NETIF_MSG_RX_ERR | \
41         NETIF_MSG_TX_ERR | \
42         NETIF_MSG_HW)
43
44 #define jeprintk(pdev, fmt, args...) \
45         printk(KERN_ERR PFX fmt, ## args)
46
47 #ifdef TX_DEBUG
48 #define tx_dbg(priv, fmt, args...) \
49         printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ## args)
50 #else
51 #define tx_dbg(priv, fmt, args...)
52 #endif
53
54 #define jme_msg(msglvl, type, priv, fmt, args...) \
55         if (netif_msg_##type(priv)) \
56                 printk(msglvl "%s: " fmt, (priv)->dev->name, ## args)
57
58 #define msg_probe(priv, fmt, args...) \
59         jme_msg(KERN_INFO, probe, priv, fmt, ## args)
60
61 #define msg_link(priv, fmt, args...) \
62         jme_msg(KERN_INFO, link, priv, fmt, ## args)
63
64 #define msg_intr(priv, fmt, args...) \
65         jme_msg(KERN_INFO, intr, priv, fmt, ## args)
66
67 #define msg_rx_err(priv, fmt, args...) \
68         jme_msg(KERN_ERR, rx_err, priv, fmt, ## args)
69
70 #define msg_rx_status(priv, fmt, args...) \
71         jme_msg(KERN_INFO, rx_status, priv, fmt, ## args)
72
73 #define msg_tx_err(priv, fmt, args...) \
74         jme_msg(KERN_ERR, tx_err, priv, fmt, ## args)
75
76 #define msg_tx_done(priv, fmt, args...) \
77         jme_msg(KERN_INFO, tx_done, priv, fmt, ## args)
78
79 #define msg_tx_queued(priv, fmt, args...) \
80         jme_msg(KERN_INFO, tx_queued, priv, fmt, ## args)
81
82 #define msg_hw(priv, fmt, args...) \
83         jme_msg(KERN_ERR, hw, priv, fmt, ## args)
84
85 /*
86  * Extra PCI Configuration space interface
87  */
88 #define PCI_DCSR_MRRS           0x59
89 #define PCI_DCSR_MRRS_MASK      0x70
90
91 enum pci_dcsr_mrrs_vals {
92         MRRS_128B       = 0x00,
93         MRRS_256B       = 0x10,
94         MRRS_512B       = 0x20,
95         MRRS_1024B      = 0x30,
96         MRRS_2048B      = 0x40,
97         MRRS_4096B      = 0x50,
98 };
99
100 #define PCI_SPI                 0xB0
101
102 enum pci_spi_bits {
103         SPI_EN          = 0x10,
104         SPI_MISO        = 0x08,
105         SPI_MOSI        = 0x04,
106         SPI_SCLK        = 0x02,
107         SPI_CS          = 0x01,
108 };
109
110 struct jme_spi_op {
111         void __user *uwbuf;
112         void __user *urbuf;
113         __u8    wn;     /* Number of write actions */
114         __u8    rn;     /* Number of read actions */
115         __u8    bitn;   /* Number of bits per action */
116         __u8    spd;    /* The maxim acceptable speed of controller, in MHz.*/
117         __u8    mode;   /* CPOL, CPHA, and Duplex mode of SPI */
118
119         /* Internal use only */
120         u8      *kwbuf;
121         u8      *krbuf;
122         u8      sr;
123         u16     halfclk; /* Half of clock cycle calculated from spd, in ns */
124 };
125
126 enum jme_spi_op_bits {
127         SPI_MODE_CPHA   = 0x01,
128         SPI_MODE_CPOL   = 0x02,
129         SPI_MODE_DUP    = 0x80,
130 };
131
132 #define HALF_US 500     /* 500 ns */
133 #define JMESPIIOCTL     SIOCDEVPRIVATE
134
135 /*
136  * Dynamic(adaptive)/Static PCC values
137  */
138 enum dynamic_pcc_values {
139         PCC_OFF         = 0,
140         PCC_P1          = 1,
141         PCC_P2          = 2,
142         PCC_P3          = 3,
143
144         PCC_OFF_TO      = 0,
145         PCC_P1_TO       = 1,
146         PCC_P2_TO       = 64,
147         PCC_P3_TO       = 128,
148
149         PCC_OFF_CNT     = 0,
150         PCC_P1_CNT      = 1,
151         PCC_P2_CNT      = 16,
152         PCC_P3_CNT      = 32,
153 };
154 struct dynpcc_info {
155         unsigned long   last_bytes;
156         unsigned long   last_pkts;
157         unsigned long   intr_cnt;
158         unsigned char   cur;
159         unsigned char   attempt;
160         unsigned char   cnt;
161 };
162 #define PCC_INTERVAL_US 100000
163 #define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
164 #define PCC_P3_THRESHOLD (2 * 1024 * 1024)
165 #define PCC_P2_THRESHOLD 800
166 #define PCC_INTR_THRESHOLD 800
167 #define PCC_TX_TO 1000
168 #define PCC_TX_CNT 8
169
170 /*
171  * TX/RX Descriptors
172  *
173  * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
174  */
175 #define RING_DESC_ALIGN         16      /* Descriptor alignment */
176 #define TX_DESC_SIZE            16
177 #define TX_RING_NR              8
178 #define TX_RING_ALLOC_SIZE(s)   ((s * TX_DESC_SIZE) + RING_DESC_ALIGN)
179
180 struct txdesc {
181         union {
182                 __u8    all[16];
183                 __le32  dw[4];
184                 struct {
185                         /* DW0 */
186                         __le16  vlan;
187                         __u8    rsv1;
188                         __u8    flags;
189
190                         /* DW1 */
191                         __le16  datalen;
192                         __le16  mss;
193
194                         /* DW2 */
195                         __le16  pktsize;
196                         __le16  rsv2;
197
198                         /* DW3 */
199                         __le32  bufaddr;
200                 } desc1;
201                 struct {
202                         /* DW0 */
203                         __le16  rsv1;
204                         __u8    rsv2;
205                         __u8    flags;
206
207                         /* DW1 */
208                         __le16  datalen;
209                         __le16  rsv3;
210
211                         /* DW2 */
212                         __le32  bufaddrh;
213
214                         /* DW3 */
215                         __le32  bufaddrl;
216                 } desc2;
217                 struct {
218                         /* DW0 */
219                         __u8    ehdrsz;
220                         __u8    rsv1;
221                         __u8    rsv2;
222                         __u8    flags;
223
224                         /* DW1 */
225                         __le16  trycnt;
226                         __le16  segcnt;
227
228                         /* DW2 */
229                         __le16  pktsz;
230                         __le16  rsv3;
231
232                         /* DW3 */
233                         __le32  bufaddrl;
234                 } descwb;
235         };
236 };
237
238 enum jme_txdesc_flags_bits {
239         TXFLAG_OWN      = 0x80,
240         TXFLAG_INT      = 0x40,
241         TXFLAG_64BIT    = 0x20,
242         TXFLAG_TCPCS    = 0x10,
243         TXFLAG_UDPCS    = 0x08,
244         TXFLAG_IPCS     = 0x04,
245         TXFLAG_LSEN     = 0x02,
246         TXFLAG_TAGON    = 0x01,
247 };
248
249 #define TXDESC_MSS_SHIFT        2
250 enum jme_rxdescwb_flags_bits {
251         TXWBFLAG_OWN    = 0x80,
252         TXWBFLAG_INT    = 0x40,
253         TXWBFLAG_TMOUT  = 0x20,
254         TXWBFLAG_TRYOUT = 0x10,
255         TXWBFLAG_COL    = 0x08,
256
257         TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
258                           TXWBFLAG_TRYOUT |
259                           TXWBFLAG_COL,
260 };
261
262 #define RX_DESC_SIZE            16
263 #define RX_RING_NR              4
264 #define RX_RING_ALLOC_SIZE(s)   ((s * RX_DESC_SIZE) + RING_DESC_ALIGN)
265 #define RX_BUF_DMA_ALIGN        8
266 #define RX_PREPAD_SIZE          10
267 #define ETH_CRC_LEN             2
268 #define RX_VLANHDR_LEN          2
269 #define RX_EXTRA_LEN            (RX_PREPAD_SIZE + \
270                                 ETH_HLEN + \
271                                 ETH_CRC_LEN + \
272                                 RX_VLANHDR_LEN + \
273                                 RX_BUF_DMA_ALIGN)
274
275 struct rxdesc {
276         union {
277                 __u8    all[16];
278                 __le32  dw[4];
279                 struct {
280                         /* DW0 */
281                         __le16  rsv2;
282                         __u8    rsv1;
283                         __u8    flags;
284
285                         /* DW1 */
286                         __le16  datalen;
287                         __le16  wbcpl;
288
289                         /* DW2 */
290                         __le32  bufaddrh;
291
292                         /* DW3 */
293                         __le32  bufaddrl;
294                 } desc1;
295                 struct {
296                         /* DW0 */
297                         __le16  vlan;
298                         __le16  flags;
299
300                         /* DW1 */
301                         __le16  framesize;
302                         __u8    errstat;
303                         __u8    desccnt;
304
305                         /* DW2 */
306                         __le32  rsshash;
307
308                         /* DW3 */
309                         __u8    hashfun;
310                         __u8    hashtype;
311                         __le16  resrv;
312                 } descwb;
313         };
314 };
315
316 enum jme_rxdesc_flags_bits {
317         RXFLAG_OWN      = 0x80,
318         RXFLAG_INT      = 0x40,
319         RXFLAG_64BIT    = 0x20,
320 };
321
322 enum jme_rxwbdesc_flags_bits {
323         RXWBFLAG_OWN            = 0x8000,
324         RXWBFLAG_INT            = 0x4000,
325         RXWBFLAG_MF             = 0x2000,
326         RXWBFLAG_64BIT          = 0x2000,
327         RXWBFLAG_TCPON          = 0x1000,
328         RXWBFLAG_UDPON          = 0x0800,
329         RXWBFLAG_IPCS           = 0x0400,
330         RXWBFLAG_TCPCS          = 0x0200,
331         RXWBFLAG_UDPCS          = 0x0100,
332         RXWBFLAG_TAGON          = 0x0080,
333         RXWBFLAG_IPV4           = 0x0040,
334         RXWBFLAG_IPV6           = 0x0020,
335         RXWBFLAG_PAUSE          = 0x0010,
336         RXWBFLAG_MAGIC          = 0x0008,
337         RXWBFLAG_WAKEUP         = 0x0004,
338         RXWBFLAG_DEST           = 0x0003,
339         RXWBFLAG_DEST_UNI       = 0x0001,
340         RXWBFLAG_DEST_MUL       = 0x0002,
341         RXWBFLAG_DEST_BRO       = 0x0003,
342 };
343
344 enum jme_rxwbdesc_desccnt_mask {
345         RXWBDCNT_WBCPL  = 0x80,
346         RXWBDCNT_DCNT   = 0x7F,
347 };
348
349 enum jme_rxwbdesc_errstat_bits {
350         RXWBERR_LIMIT   = 0x80,
351         RXWBERR_MIIER   = 0x40,
352         RXWBERR_NIBON   = 0x20,
353         RXWBERR_COLON   = 0x10,
354         RXWBERR_ABORT   = 0x08,
355         RXWBERR_SHORT   = 0x04,
356         RXWBERR_OVERUN  = 0x02,
357         RXWBERR_CRCERR  = 0x01,
358         RXWBERR_ALLERR  = 0xFF,
359 };
360
361 /*
362  * Buffer information corresponding to ring descriptors.
363  */
364 struct jme_buffer_info {
365         struct sk_buff *skb;
366         dma_addr_t mapping;
367         int len;
368         int nr_desc;
369         unsigned long start_xmit;
370 };
371
372 /*
373  * The structure holding buffer information and ring descriptors all together.
374  */
375 #define MAX_RING_DESC_NR        1024
376 struct jme_ring {
377         void *alloc;            /* pointer to allocated memory */
378         void *desc;             /* pointer to ring memory  */
379         dma_addr_t dmaalloc;    /* phys address of ring alloc */
380         dma_addr_t dma;         /* phys address for ring dma */
381
382         /* Buffer information corresponding to each descriptor */
383         struct jme_buffer_info bufinf[MAX_RING_DESC_NR];
384
385         int next_to_use;
386         atomic_t next_to_clean;
387         atomic_t nr_free;
388 };
389
390 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
391 #define NET_STAT(priv) priv->stats
392 #define NETDEV_GET_STATS(netdev, fun_ptr) \
393         netdev->get_stats = fun_ptr
394 #define DECLARE_NET_DEVICE_STATS struct net_device_stats stats;
395 #else
396 #define NET_STAT(priv) priv->dev->stats
397 #define NETDEV_GET_STATS(netdev, fun_ptr)
398 #define DECLARE_NET_DEVICE_STATS
399 #endif
400
401 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
402 #define DECLARE_NAPI_STRUCT
403 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
404         dev->poll = pollfn; \
405         dev->weight = q;
406 #define JME_NAPI_HOLDER(holder) struct net_device *holder
407 #define JME_NAPI_WEIGHT(w) int *w
408 #define JME_NAPI_WEIGHT_VAL(w) *w
409 #define JME_NAPI_WEIGHT_SET(w, r) *w = r
410 #define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev)
411 #define JME_NAPI_ENABLE(priv) netif_poll_enable(priv->dev);
412 #define JME_NAPI_DISABLE(priv) netif_poll_disable(priv->dev);
413 #define JME_RX_SCHEDULE_PREP(priv) \
414         netif_rx_schedule_prep(priv->dev)
415 #define JME_RX_SCHEDULE(priv) \
416         __netif_rx_schedule(priv->dev);
417 #else
418 #define DECLARE_NAPI_STRUCT struct napi_struct napi;
419 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
420         netif_napi_add(dev, napis, pollfn, q);
421 #define JME_NAPI_HOLDER(holder) struct napi_struct *holder
422 #define JME_NAPI_WEIGHT(w) int w
423 #define JME_NAPI_WEIGHT_VAL(w) w
424 #define JME_NAPI_WEIGHT_SET(w, r)
425 #define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev, napis)
426 #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
427 #define JME_NAPI_DISABLE(priv) \
428         if(!napi_disable_pending(&priv->napi)) \
429                 napi_disable(&priv->napi);
430 #define JME_RX_SCHEDULE_PREP(priv) \
431         netif_rx_schedule_prep(priv->dev, &priv->napi)
432 #define JME_RX_SCHEDULE(priv) \
433         __netif_rx_schedule(priv->dev, &priv->napi);
434 #endif
435
436 /*
437  * Jmac Adapter Private data
438  */
439 #define SHADOW_REG_NR 8
440 struct jme_adapter {
441         struct pci_dev          *pdev;
442         struct net_device       *dev;
443         void __iomem            *regs;
444         dma_addr_t              shadow_dma;
445         u32                     *shadow_regs;
446         struct mii_if_info      mii_if;
447         struct jme_ring         rxring[RX_RING_NR];
448         struct jme_ring         txring[TX_RING_NR];
449         spinlock_t              phy_lock;
450         spinlock_t              macaddr_lock;
451         spinlock_t              rxmcs_lock;
452         struct tasklet_struct   rxempty_task;
453         struct tasklet_struct   rxclean_task;
454         struct tasklet_struct   txclean_task;
455         struct tasklet_struct   linkch_task;
456         struct tasklet_struct   pcc_task;
457         unsigned long           flags;
458         u32                     reg_txcs;
459         u32                     reg_txpfc;
460         u32                     reg_rxcs;
461         u32                     reg_rxmcs;
462         u32                     reg_ghc;
463         u32                     reg_pmcs;
464         u32                     phylink;
465         u32                     tx_ring_size;
466         u32                     tx_ring_mask;
467         u32                     tx_wake_threshold;
468         u32                     rx_ring_size;
469         u32                     rx_ring_mask;
470         u8                      mrrs;
471         unsigned int            fpgaver;
472         unsigned int            chipver;
473         u8                      rev;
474         u32                     msg_enable;
475         struct ethtool_cmd      old_ecmd;
476         unsigned int            old_mtu;
477         struct vlan_group       *vlgrp;
478         struct dynpcc_info      dpi;
479         atomic_t                intr_sem;
480         atomic_t                link_changing;
481         atomic_t                tx_cleaning;
482         atomic_t                rx_cleaning;
483         atomic_t                rx_empty;
484         int                     (*jme_rx)(struct sk_buff *skb);
485         int                     (*jme_vlan_rx)(struct sk_buff *skb,
486                                           struct vlan_group *grp,
487                                           unsigned short vlan_tag);
488         DECLARE_NAPI_STRUCT
489         DECLARE_NET_DEVICE_STATS
490 };
491
492 enum shadow_reg_val {
493         SHADOW_IEVE = 0,
494 };
495
496 enum jme_flags_bits {
497         JME_FLAG_MSI            = 1,
498         JME_FLAG_SSET           = 2,
499         JME_FLAG_TXCSUM         = 3,
500         JME_FLAG_TSO            = 4,
501         JME_FLAG_POLL           = 5,
502         JME_FLAG_SHUTDOWN       = 6,
503 };
504
505 #define TX_TIMEOUT              (5 * HZ)
506 #define JME_REG_LEN             0x500
507 #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
508
509 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
510 __always_inline static struct jme_adapter*
511 jme_napi_priv(struct net_device *holder)
512 {
513         struct jme_adapter* jme;
514         jme = netdev_priv(holder);
515         return jme;
516 }
517 #else
518 __always_inline static struct jme_adapter*
519 jme_napi_priv(struct napi_struct *napi)
520 {
521         struct jme_adapter* jme;
522         jme = container_of(napi, struct jme_adapter, napi);
523         return jme;
524 }
525 #endif
526
527 /*
528  * MMaped I/O Resters
529  */
530 enum jme_iomap_offsets {
531         JME_MAC         = 0x0000,
532         JME_PHY         = 0x0400,
533         JME_MISC        = 0x0800,
534         JME_RSS         = 0x0C00,
535 };
536
537 enum jme_iomap_lens {
538         JME_MAC_LEN     = 0x80,
539         JME_PHY_LEN     = 0x58,
540         JME_MISC_LEN    = 0x98,
541         JME_RSS_LEN     = 0xFF,
542 };
543
544 enum jme_iomap_regs {
545         JME_TXCS        = JME_MAC | 0x00, /* Transmit Control and Status */
546         JME_TXDBA_LO    = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
547         JME_TXDBA_HI    = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
548         JME_TXQDC       = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
549         JME_TXNDA       = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
550         JME_TXMCS       = JME_MAC | 0x14, /* Transmit MAC Control Status */
551         JME_TXPFC       = JME_MAC | 0x18, /* Transmit Pause Frame Control */
552         JME_TXTRHD      = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
553
554         JME_RXCS        = JME_MAC | 0x20, /* Receive Control and Status */
555         JME_RXDBA_LO    = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
556         JME_RXDBA_HI    = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
557         JME_RXQDC       = JME_MAC | 0x2C, /* Receive Queue Desc Count */
558         JME_RXNDA       = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
559         JME_RXMCS       = JME_MAC | 0x34, /* Receive MAC Control Status */
560         JME_RXUMA_LO    = JME_MAC | 0x38, /* Receive Unicast MAC Address */
561         JME_RXUMA_HI    = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
562         JME_RXMCHT_LO   = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
563         JME_RXMCHT_HI   = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
564         JME_WFODP       = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
565         JME_WFOI        = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
566
567         JME_SMI         = JME_MAC | 0x50, /* Station Management Interface */
568         JME_GHC         = JME_MAC | 0x54, /* Global Host Control */
569         JME_PMCS        = JME_MAC | 0x60, /* Power Management Control/Stat */
570
571
572         JME_PHY_CS      = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
573         JME_PHY_LINK    = JME_PHY | 0x30, /* PHY Link Status Register */
574         JME_SMBCSR      = JME_PHY | 0x40, /* SMB Control and Status */
575         JME_SMBINTF     = JME_PHY | 0x44, /* SMB Interface */
576
577
578         JME_TMCSR       = JME_MISC | 0x00, /* Timer Control/Status Register */
579         JME_GPREG0      = JME_MISC | 0x08, /* General purpose REG-0 */
580         JME_GPREG1      = JME_MISC | 0x0C, /* General purpose REG-1 */
581         JME_IEVE        = JME_MISC | 0x20, /* Interrupt Event Status */
582         JME_IREQ        = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
583         JME_IENS        = JME_MISC | 0x28, /* Intr Enable - Setting Port */
584         JME_IENC        = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
585         JME_PCCRX0      = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
586         JME_PCCTX       = JME_MISC | 0x40, /* PCC Control for TX Queues */
587         JME_CHIPMODE    = JME_MISC | 0x44, /* Identify FPGA Version */
588         JME_SHBA_HI     = JME_MISC | 0x48, /* Shadow Register Base HI */
589         JME_SHBA_LO     = JME_MISC | 0x4C, /* Shadow Register Base LO */
590         JME_TIMER1      = JME_MISC | 0x70, /* Timer1 */
591         JME_TIMER2      = JME_MISC | 0x74, /* Timer2 */
592         JME_APMC        = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
593         JME_PCCSRX0     = JME_MISC | 0x80, /* PCC Status of RX0 */
594 };
595
596 /*
597  * TX Control/Status Bits
598  */
599 enum jme_txcs_bits {
600         TXCS_QUEUE7S    = 0x00008000,
601         TXCS_QUEUE6S    = 0x00004000,
602         TXCS_QUEUE5S    = 0x00002000,
603         TXCS_QUEUE4S    = 0x00001000,
604         TXCS_QUEUE3S    = 0x00000800,
605         TXCS_QUEUE2S    = 0x00000400,
606         TXCS_QUEUE1S    = 0x00000200,
607         TXCS_QUEUE0S    = 0x00000100,
608         TXCS_FIFOTH     = 0x000000C0,
609         TXCS_DMASIZE    = 0x00000030,
610         TXCS_BURST      = 0x00000004,
611         TXCS_ENABLE     = 0x00000001,
612 };
613
614 enum jme_txcs_value {
615         TXCS_FIFOTH_16QW        = 0x000000C0,
616         TXCS_FIFOTH_12QW        = 0x00000080,
617         TXCS_FIFOTH_8QW         = 0x00000040,
618         TXCS_FIFOTH_4QW         = 0x00000000,
619
620         TXCS_DMASIZE_64B        = 0x00000000,
621         TXCS_DMASIZE_128B       = 0x00000010,
622         TXCS_DMASIZE_256B       = 0x00000020,
623         TXCS_DMASIZE_512B       = 0x00000030,
624
625         TXCS_SELECT_QUEUE0      = 0x00000000,
626         TXCS_SELECT_QUEUE1      = 0x00010000,
627         TXCS_SELECT_QUEUE2      = 0x00020000,
628         TXCS_SELECT_QUEUE3      = 0x00030000,
629         TXCS_SELECT_QUEUE4      = 0x00040000,
630         TXCS_SELECT_QUEUE5      = 0x00050000,
631         TXCS_SELECT_QUEUE6      = 0x00060000,
632         TXCS_SELECT_QUEUE7      = 0x00070000,
633
634         TXCS_DEFAULT            = TXCS_FIFOTH_4QW |
635                                   TXCS_BURST,
636 };
637
638 #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
639
640 /*
641  * TX MAC Control/Status Bits
642  */
643 enum jme_txmcs_bit_masks {
644         TXMCS_IFG2              = 0xC0000000,
645         TXMCS_IFG1              = 0x30000000,
646         TXMCS_TTHOLD            = 0x00000300,
647         TXMCS_FBURST            = 0x00000080,
648         TXMCS_CARRIEREXT        = 0x00000040,
649         TXMCS_DEFER             = 0x00000020,
650         TXMCS_BACKOFF           = 0x00000010,
651         TXMCS_CARRIERSENSE      = 0x00000008,
652         TXMCS_COLLISION         = 0x00000004,
653         TXMCS_CRC               = 0x00000002,
654         TXMCS_PADDING           = 0x00000001,
655 };
656
657 enum jme_txmcs_values {
658         TXMCS_IFG2_6_4          = 0x00000000,
659         TXMCS_IFG2_8_5          = 0x40000000,
660         TXMCS_IFG2_10_6         = 0x80000000,
661         TXMCS_IFG2_12_7         = 0xC0000000,
662
663         TXMCS_IFG1_8_4          = 0x00000000,
664         TXMCS_IFG1_12_6         = 0x10000000,
665         TXMCS_IFG1_16_8         = 0x20000000,
666         TXMCS_IFG1_20_10        = 0x30000000,
667
668         TXMCS_TTHOLD_1_8        = 0x00000000,
669         TXMCS_TTHOLD_1_4        = 0x00000100,
670         TXMCS_TTHOLD_1_2        = 0x00000200,
671         TXMCS_TTHOLD_FULL       = 0x00000300,
672
673         TXMCS_DEFAULT           = TXMCS_IFG2_8_5 |
674                                   TXMCS_IFG1_16_8 |
675                                   TXMCS_TTHOLD_FULL |
676                                   TXMCS_DEFER |
677                                   TXMCS_CRC |
678                                   TXMCS_PADDING,
679 };
680
681 enum jme_txpfc_bits_masks {
682         TXPFC_VLAN_TAG          = 0xFFFF0000,
683         TXPFC_VLAN_EN           = 0x00008000,
684         TXPFC_PF_EN             = 0x00000001,
685 };
686
687 enum jme_txtrhd_bits_masks {
688         TXTRHD_TXPEN            = 0x80000000,
689         TXTRHD_TXP              = 0x7FFFFF00,
690         TXTRHD_TXREN            = 0x00000080,
691         TXTRHD_TXRL             = 0x0000007F,
692 };
693
694 enum jme_txtrhd_shifts {
695         TXTRHD_TXP_SHIFT        = 8,
696         TXTRHD_TXRL_SHIFT       = 0,
697 };
698
699 /*
700  * RX Control/Status Bits
701  */
702 enum jme_rxcs_bit_masks {
703         /* FIFO full threshold for transmitting Tx Pause Packet */
704         RXCS_FIFOTHTP   = 0x30000000,
705         /* FIFO threshold for processing next packet */
706         RXCS_FIFOTHNP   = 0x0C000000,
707         RXCS_DMAREQSZ   = 0x03000000, /* DMA Request Size */
708         RXCS_QUEUESEL   = 0x00030000, /* Queue selection */
709         RXCS_RETRYGAP   = 0x0000F000, /* RX Desc full retry gap */
710         RXCS_RETRYCNT   = 0x00000F00, /* RX Desc full retry counter */
711         RXCS_WAKEUP     = 0x00000040, /* Enable receive wakeup packet */
712         RXCS_MAGIC      = 0x00000020, /* Enable receive magic packet */
713         RXCS_SHORT      = 0x00000010, /* Enable receive short packet */
714         RXCS_ABORT      = 0x00000008, /* Enable receive errorr packet */
715         RXCS_QST        = 0x00000004, /* Receive queue start */
716         RXCS_SUSPEND    = 0x00000002,
717         RXCS_ENABLE     = 0x00000001,
718 };
719
720 enum jme_rxcs_values {
721         RXCS_FIFOTHTP_16T       = 0x00000000,
722         RXCS_FIFOTHTP_32T       = 0x10000000,
723         RXCS_FIFOTHTP_64T       = 0x20000000,
724         RXCS_FIFOTHTP_128T      = 0x30000000,
725
726         RXCS_FIFOTHNP_16QW      = 0x00000000,
727         RXCS_FIFOTHNP_32QW      = 0x04000000,
728         RXCS_FIFOTHNP_64QW      = 0x08000000,
729         RXCS_FIFOTHNP_128QW     = 0x0C000000,
730
731         RXCS_DMAREQSZ_16B       = 0x00000000,
732         RXCS_DMAREQSZ_32B       = 0x01000000,
733         RXCS_DMAREQSZ_64B       = 0x02000000,
734         RXCS_DMAREQSZ_128B      = 0x03000000,
735
736         RXCS_QUEUESEL_Q0        = 0x00000000,
737         RXCS_QUEUESEL_Q1        = 0x00010000,
738         RXCS_QUEUESEL_Q2        = 0x00020000,
739         RXCS_QUEUESEL_Q3        = 0x00030000,
740
741         RXCS_RETRYGAP_256ns     = 0x00000000,
742         RXCS_RETRYGAP_512ns     = 0x00001000,
743         RXCS_RETRYGAP_1024ns    = 0x00002000,
744         RXCS_RETRYGAP_2048ns    = 0x00003000,
745         RXCS_RETRYGAP_4096ns    = 0x00004000,
746         RXCS_RETRYGAP_8192ns    = 0x00005000,
747         RXCS_RETRYGAP_16384ns   = 0x00006000,
748         RXCS_RETRYGAP_32768ns   = 0x00007000,
749
750         RXCS_RETRYCNT_0         = 0x00000000,
751         RXCS_RETRYCNT_4         = 0x00000100,
752         RXCS_RETRYCNT_8         = 0x00000200,
753         RXCS_RETRYCNT_12        = 0x00000300,
754         RXCS_RETRYCNT_16        = 0x00000400,
755         RXCS_RETRYCNT_20        = 0x00000500,
756         RXCS_RETRYCNT_24        = 0x00000600,
757         RXCS_RETRYCNT_28        = 0x00000700,
758         RXCS_RETRYCNT_32        = 0x00000800,
759         RXCS_RETRYCNT_36        = 0x00000900,
760         RXCS_RETRYCNT_40        = 0x00000A00,
761         RXCS_RETRYCNT_44        = 0x00000B00,
762         RXCS_RETRYCNT_48        = 0x00000C00,
763         RXCS_RETRYCNT_52        = 0x00000D00,
764         RXCS_RETRYCNT_56        = 0x00000E00,
765         RXCS_RETRYCNT_60        = 0x00000F00,
766
767         RXCS_DEFAULT            = RXCS_FIFOTHTP_128T |
768                                   RXCS_FIFOTHNP_128QW |
769                                   RXCS_DMAREQSZ_128B |
770                                   RXCS_RETRYGAP_256ns |
771                                   RXCS_RETRYCNT_32,
772 };
773
774 #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
775
776 /*
777  * RX MAC Control/Status Bits
778  */
779 enum jme_rxmcs_bits {
780         RXMCS_ALLFRAME          = 0x00000800,
781         RXMCS_BRDFRAME          = 0x00000400,
782         RXMCS_MULFRAME          = 0x00000200,
783         RXMCS_UNIFRAME          = 0x00000100,
784         RXMCS_ALLMULFRAME       = 0x00000080,
785         RXMCS_MULFILTERED       = 0x00000040,
786         RXMCS_RXCOLLDEC         = 0x00000020,
787         RXMCS_FLOWCTRL          = 0x00000008,
788         RXMCS_VTAGRM            = 0x00000004,
789         RXMCS_PREPAD            = 0x00000002,
790         RXMCS_CHECKSUM          = 0x00000001,
791
792         RXMCS_DEFAULT           = RXMCS_VTAGRM |
793                                   RXMCS_PREPAD |
794                                   RXMCS_FLOWCTRL |
795                                   RXMCS_CHECKSUM,
796 };
797
798 /*
799  * Wakeup Frame setup interface registers
800  */
801 #define WAKEUP_FRAME_NR 8
802 #define WAKEUP_FRAME_MASK_DWNR  4
803
804 enum jme_wfoi_bit_masks {
805         WFOI_MASK_SEL           = 0x00000070,
806         WFOI_CRC_SEL            = 0x00000008,
807         WFOI_FRAME_SEL          = 0x00000007,
808 };
809
810 enum jme_wfoi_shifts {
811         WFOI_MASK_SHIFT         = 4,
812 };
813
814 /*
815  * SMI Related definitions
816  */
817 enum jme_smi_bit_mask {
818         SMI_DATA_MASK           = 0xFFFF0000,
819         SMI_REG_ADDR_MASK       = 0x0000F800,
820         SMI_PHY_ADDR_MASK       = 0x000007C0,
821         SMI_OP_WRITE            = 0x00000020,
822         /* Set to 1, after req done it'll be cleared to 0 */
823         SMI_OP_REQ              = 0x00000010,
824         SMI_OP_MDIO             = 0x00000008, /* Software assess In/Out */
825         SMI_OP_MDOE             = 0x00000004, /* Software Output Enable */
826         SMI_OP_MDC              = 0x00000002, /* Software CLK Control */
827         SMI_OP_MDEN             = 0x00000001, /* Software access Enable */
828 };
829
830 enum jme_smi_bit_shift {
831         SMI_DATA_SHIFT          = 16,
832         SMI_REG_ADDR_SHIFT      = 11,
833         SMI_PHY_ADDR_SHIFT      = 6,
834 };
835
836 static inline u32 smi_reg_addr(int x)
837 {
838         return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
839 }
840
841 static inline u32 smi_phy_addr(int x)
842 {
843         return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
844 }
845
846 #define JME_PHY_TIMEOUT 100 /* 100 msec */
847 #define JME_PHY_REG_NR 32
848
849 /*
850  * Global Host Control
851  */
852 enum jme_ghc_bit_mask {
853         GHC_SWRST       = 0x40000000,
854         GHC_DPX         = 0x00000040,
855         GHC_SPEED       = 0x00000030,
856         GHC_LINK_POLL   = 0x00000001,
857 };
858
859 enum jme_ghc_speed_val {
860         GHC_SPEED_10M   = 0x00000010,
861         GHC_SPEED_100M  = 0x00000020,
862         GHC_SPEED_1000M = 0x00000030,
863 };
864
865 /*
866  * Power management control and status register
867  */
868 enum jme_pmcs_bit_masks {
869         PMCS_WF7DET     = 0x80000000,
870         PMCS_WF6DET     = 0x40000000,
871         PMCS_WF5DET     = 0x20000000,
872         PMCS_WF4DET     = 0x10000000,
873         PMCS_WF3DET     = 0x08000000,
874         PMCS_WF2DET     = 0x04000000,
875         PMCS_WF1DET     = 0x02000000,
876         PMCS_WF0DET     = 0x01000000,
877         PMCS_LFDET      = 0x00040000,
878         PMCS_LRDET      = 0x00020000,
879         PMCS_MFDET      = 0x00010000,
880         PMCS_WF7EN      = 0x00008000,
881         PMCS_WF6EN      = 0x00004000,
882         PMCS_WF5EN      = 0x00002000,
883         PMCS_WF4EN      = 0x00001000,
884         PMCS_WF3EN      = 0x00000800,
885         PMCS_WF2EN      = 0x00000400,
886         PMCS_WF1EN      = 0x00000200,
887         PMCS_WF0EN      = 0x00000100,
888         PMCS_LFEN       = 0x00000004,
889         PMCS_LREN       = 0x00000002,
890         PMCS_MFEN       = 0x00000001,
891 };
892
893 /*
894  * Giga PHY Status Registers
895  */
896 enum jme_phy_link_bit_mask {
897         PHY_LINK_SPEED_MASK             = 0x0000C000,
898         PHY_LINK_DUPLEX                 = 0x00002000,
899         PHY_LINK_SPEEDDPU_RESOLVED      = 0x00000800,
900         PHY_LINK_UP                     = 0x00000400,
901         PHY_LINK_AUTONEG_COMPLETE       = 0x00000200,
902         PHY_LINK_MDI_STAT               = 0x00000040,
903 };
904
905 enum jme_phy_link_speed_val {
906         PHY_LINK_SPEED_10M              = 0x00000000,
907         PHY_LINK_SPEED_100M             = 0x00004000,
908         PHY_LINK_SPEED_1000M            = 0x00008000,
909 };
910
911 #define JME_SPDRSV_TIMEOUT      500     /* 500 us */
912
913 /*
914  * SMB Control and Status
915  */
916 enum jme_smbcsr_bit_mask {
917         SMBCSR_CNACK    = 0x00020000,
918         SMBCSR_RELOAD   = 0x00010000,
919         SMBCSR_EEPROMD  = 0x00000020,
920         SMBCSR_INITDONE = 0x00000010,
921         SMBCSR_BUSY     = 0x0000000F,
922 };
923
924 enum jme_smbintf_bit_mask {
925         SMBINTF_HWDATR  = 0xFF000000,
926         SMBINTF_HWDATW  = 0x00FF0000,
927         SMBINTF_HWADDR  = 0x0000FF00,
928         SMBINTF_HWRWN   = 0x00000020,
929         SMBINTF_HWCMD   = 0x00000010,
930         SMBINTF_FASTM   = 0x00000008,
931         SMBINTF_GPIOSCL = 0x00000004,
932         SMBINTF_GPIOSDA = 0x00000002,
933         SMBINTF_GPIOEN  = 0x00000001,
934 };
935
936 enum jme_smbintf_vals {
937         SMBINTF_HWRWN_READ      = 0x00000020,
938         SMBINTF_HWRWN_WRITE     = 0x00000000,
939 };
940
941 enum jme_smbintf_shifts {
942         SMBINTF_HWDATR_SHIFT    = 24,
943         SMBINTF_HWDATW_SHIFT    = 16,
944         SMBINTF_HWADDR_SHIFT    = 8,
945 };
946
947 #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
948 #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
949 #define JME_SMB_LEN 256
950 #define JME_EEPROM_MAGIC 0x250
951
952 /*
953  * Timer Control/Status Register
954  */
955 enum jme_tmcsr_bit_masks {
956         TMCSR_SWIT      = 0x80000000,
957         TMCSR_EN        = 0x01000000,
958         TMCSR_CNT       = 0x00FFFFFF,
959 };
960
961 /*
962  * General Purpose REG-0
963  */
964 enum jme_gpreg0_masks {
965         GPREG0_DISSH            = 0xFF000000,
966         GPREG0_PCIRLMT          = 0x00300000,
967         GPREG0_PCCNOMUTCLR      = 0x00040000,
968         GPREG0_LNKINTPOLL       = 0x00001000,
969         GPREG0_PCCTMR           = 0x00000300,
970         GPREG0_PHYADDR          = 0x0000001F,
971 };
972
973 enum jme_gpreg0_vals {
974         GPREG0_DISSH_DW7        = 0x80000000,
975         GPREG0_DISSH_DW6        = 0x40000000,
976         GPREG0_DISSH_DW5        = 0x20000000,
977         GPREG0_DISSH_DW4        = 0x10000000,
978         GPREG0_DISSH_DW3        = 0x08000000,
979         GPREG0_DISSH_DW2        = 0x04000000,
980         GPREG0_DISSH_DW1        = 0x02000000,
981         GPREG0_DISSH_DW0        = 0x01000000,
982         GPREG0_DISSH_ALL        = 0xFF000000,
983
984         GPREG0_PCIRLMT_8        = 0x00000000,
985         GPREG0_PCIRLMT_6        = 0x00100000,
986         GPREG0_PCIRLMT_5        = 0x00200000,
987         GPREG0_PCIRLMT_4        = 0x00300000,
988
989         GPREG0_PCCTMR_16ns      = 0x00000000,
990         GPREG0_PCCTMR_256ns     = 0x00000100,
991         GPREG0_PCCTMR_1us       = 0x00000200,
992         GPREG0_PCCTMR_1ms       = 0x00000300,
993
994         GPREG0_PHYADDR_1        = 0x00000001,
995
996         GPREG0_DEFAULT          = GPREG0_PCIRLMT_4 |
997                                   GPREG0_PCCTMR_1us |
998                                   GPREG0_PHYADDR_1,
999 };
1000
1001 /*
1002  * Interrupt Status Bits
1003  */
1004 enum jme_interrupt_bits {
1005         INTR_SWINTR     = 0x80000000,
1006         INTR_TMINTR     = 0x40000000,
1007         INTR_LINKCH     = 0x20000000,
1008         INTR_PAUSERCV   = 0x10000000,
1009         INTR_MAGICRCV   = 0x08000000,
1010         INTR_WAKERCV    = 0x04000000,
1011         INTR_PCCRX0TO   = 0x02000000,
1012         INTR_PCCRX1TO   = 0x01000000,
1013         INTR_PCCRX2TO   = 0x00800000,
1014         INTR_PCCRX3TO   = 0x00400000,
1015         INTR_PCCTXTO    = 0x00200000,
1016         INTR_PCCRX0     = 0x00100000,
1017         INTR_PCCRX1     = 0x00080000,
1018         INTR_PCCRX2     = 0x00040000,
1019         INTR_PCCRX3     = 0x00020000,
1020         INTR_PCCTX      = 0x00010000,
1021         INTR_RX3EMP     = 0x00008000,
1022         INTR_RX2EMP     = 0x00004000,
1023         INTR_RX1EMP     = 0x00002000,
1024         INTR_RX0EMP     = 0x00001000,
1025         INTR_RX3        = 0x00000800,
1026         INTR_RX2        = 0x00000400,
1027         INTR_RX1        = 0x00000200,
1028         INTR_RX0        = 0x00000100,
1029         INTR_TX7        = 0x00000080,
1030         INTR_TX6        = 0x00000040,
1031         INTR_TX5        = 0x00000020,
1032         INTR_TX4        = 0x00000010,
1033         INTR_TX3        = 0x00000008,
1034         INTR_TX2        = 0x00000004,
1035         INTR_TX1        = 0x00000002,
1036         INTR_TX0        = 0x00000001,
1037 };
1038
1039 static const u32 INTR_ENABLE = INTR_SWINTR |
1040                                  INTR_TMINTR |
1041                                  INTR_LINKCH |
1042                                  INTR_PCCRX0TO |
1043                                  INTR_PCCRX0 |
1044                                  INTR_PCCTXTO |
1045                                  INTR_PCCTX |
1046                                  INTR_RX0EMP;
1047
1048 /*
1049  * PCC Control Registers
1050  */
1051 enum jme_pccrx_masks {
1052         PCCRXTO_MASK    = 0xFFFF0000,
1053         PCCRX_MASK      = 0x0000FF00,
1054 };
1055
1056 enum jme_pcctx_masks {
1057         PCCTXTO_MASK    = 0xFFFF0000,
1058         PCCTX_MASK      = 0x0000FF00,
1059         PCCTX_QS_MASK   = 0x000000FF,
1060 };
1061
1062 enum jme_pccrx_shifts {
1063         PCCRXTO_SHIFT   = 16,
1064         PCCRX_SHIFT     = 8,
1065 };
1066
1067 enum jme_pcctx_shifts {
1068         PCCTXTO_SHIFT   = 16,
1069         PCCTX_SHIFT     = 8,
1070 };
1071
1072 enum jme_pcctx_bits {
1073         PCCTXQ0_EN      = 0x00000001,
1074         PCCTXQ1_EN      = 0x00000002,
1075         PCCTXQ2_EN      = 0x00000004,
1076         PCCTXQ3_EN      = 0x00000008,
1077         PCCTXQ4_EN      = 0x00000010,
1078         PCCTXQ5_EN      = 0x00000020,
1079         PCCTXQ6_EN      = 0x00000040,
1080         PCCTXQ7_EN      = 0x00000080,
1081 };
1082
1083 /*
1084  * Chip Mode Register
1085  */
1086 enum jme_chipmode_bit_masks {
1087         CM_FPGAVER_MASK         = 0xFFFF0000,
1088         CM_CHIPVER_MASK         = 0x0000FF00,
1089         CM_CHIPMODE_MASK        = 0x0000000F,
1090 };
1091
1092 enum jme_chipmode_shifts {
1093         CM_FPGAVER_SHIFT        = 16,
1094         CM_CHIPVER_SHIFT        = 8,
1095 };
1096
1097 /*
1098  * Shadow base address register bits
1099  */
1100 enum jme_shadow_base_address_bits {
1101         SHBA_POSTEN     = 0x1,
1102 };
1103
1104 /*
1105  * Aggressive Power Mode Control
1106  */
1107 enum jme_apmc_bits {
1108         JME_APMC_PCIE_SD_EN     = 0x40000000,
1109         JME_APMC_PSEUDO_HP_EN   = 0x20000000,
1110         JME_APMC_EPIEN          = 0x04000000,
1111         JME_APMC_EPIEN_CTRL     = 0x03000000,
1112 };
1113
1114 enum jme_apmc_values {
1115         JME_APMC_EPIEN_CTRL_EN  = 0x02000000,
1116         JME_APMC_EPIEN_CTRL_DIS = 0x01000000,
1117 };
1118
1119 #define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000)
1120
1121 #ifdef REG_DEBUG
1122 static char *MAC_REG_NAME[] = {
1123         "JME_TXCS",      "JME_TXDBA_LO",  "JME_TXDBA_HI", "JME_TXQDC",
1124         "JME_TXNDA",     "JME_TXMCS",     "JME_TXPFC",    "JME_TXTRHD",
1125         "JME_RXCS",      "JME_RXDBA_LO",  "JME_RXDBA_HI", "JME_RXQDC",
1126         "JME_RXNDA",     "JME_RXMCS",     "JME_RXUMA_LO", "JME_RXUMA_HI",
1127         "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP",    "JME_WFOI",
1128         "JME_SMI",       "JME_GHC",       "UNKNOWN",      "UNKNOWN",
1129         "JME_PMCS"};
1130 static char *PE_REG_NAME[] = {
1131         "UNKNOWN",      "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1132         "UNKNOWN",      "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1133         "UNKNOWN",      "UNKNOWN",     "JME_PHY_CS", "UNKNOWN",
1134         "JME_PHY_LINK", "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1135         "JME_SMBCSR",   "JME_SMBINTF"};
1136 static char *MISC_REG_NAME[] = {
1137         "JME_TMCSR",  "JME_GPIO",     "JME_GPREG0",  "JME_GPREG1",
1138         "JME_IEVE",   "JME_IREQ",     "JME_IENS",    "JME_IENC",
1139         "JME_PCCRX0", "JME_PCCRX1",   "JME_PCCRX2",  "JME_PCCRX3",
1140         "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO",
1141         "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1142         "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1143         "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1144         "JME_TIMER1", "JME_TIMER2",   "UNKNOWN",     "JME_APMC",
1145         "JME_PCCSRX0"};
1146 static inline void reg_dbg(const struct jme_adapter *jme,
1147                 const char *msg, u32 val, u32 reg)
1148 {
1149         const char *regname;
1150         switch(reg & 0xF00) {
1151         case 0x000:
1152                 regname = MAC_REG_NAME[(reg & 0xFF) >> 2];
1153                 break;
1154         case 0x400:
1155                 regname = PE_REG_NAME[(reg & 0xFF) >> 2];
1156                 break;
1157         case 0x800:
1158                 regname = MISC_REG_NAME[(reg & 0xFF) >>2];
1159                 break;
1160         default:
1161                 regname = PE_REG_NAME[0];
1162         }
1163         printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name,
1164                         msg, val, regname);
1165 }
1166 #else
1167 static inline void reg_dbg(const struct jme_adapter *jme,
1168                 const char *msg, u32 val, u32 reg) {}
1169 #endif
1170
1171 /*
1172  * Read/Write MMaped I/O Registers
1173  */
1174 static inline u32 jread32(struct jme_adapter *jme, u32 reg)
1175 {
1176         return readl(jme->regs + reg);
1177 }
1178
1179 static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val)
1180 {
1181         reg_dbg(jme, "REG WRITE", val, reg);
1182         writel(val, jme->regs + reg);
1183         reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1184 }
1185
1186 static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val)
1187 {
1188         /*
1189          * Read after write should cause flush
1190          */
1191         reg_dbg(jme, "REG WRITE FLUSH", val, reg);
1192         writel(val, jme->regs + reg);
1193         readl(jme->regs + reg);
1194         reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1195 }
1196
1197 /*
1198  * PHY Regs
1199  */
1200 enum jme_phy_reg17_bit_masks {
1201         PREG17_SPEED            = 0xC000,
1202         PREG17_DUPLEX           = 0x2000,
1203         PREG17_SPDRSV           = 0x0800,
1204         PREG17_LNKUP            = 0x0400,
1205         PREG17_MDI              = 0x0040,
1206 };
1207
1208 enum jme_phy_reg17_vals {
1209         PREG17_SPEED_10M        = 0x0000,
1210         PREG17_SPEED_100M       = 0x4000,
1211         PREG17_SPEED_1000M      = 0x8000,
1212 };
1213
1214 #define BMSR_ANCOMP               0x0020
1215
1216 /*
1217  * Function prototypes
1218  */
1219 static int jme_set_settings(struct net_device *netdev,
1220                                 struct ethtool_cmd *ecmd);
1221 static void jme_set_multi(struct net_device *netdev);
1222
1223 #endif