Import jme 0.9b source
[jme.git] / jme.h
1 /*
2  * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3  *
4  * Copyright 2008 JMicron Technology Corporation
5  * http://www.jmicron.com/
6  *
7  * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2 of the License.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21  *
22  */
23
24 #include <linux/version.h>
25
26 #define DRV_NAME        "jme"
27 #define DRV_VERSION     "0.9b"
28 #define PFX DRV_NAME    ": "
29
30 #ifdef DEBUG
31 #define dprintk(devname, fmt, args...) \
32         printk(KERN_DEBUG "%s: " fmt, devname, ## args)
33 #else
34 #define dprintk(devname, fmt, args...)
35 #endif
36
37 #ifdef TX_DEBUG
38 #define tx_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
39 #else
40 #define tx_dbg(args...)
41 #endif
42
43 #ifdef RX_DEBUG
44 #define rx_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
45 #else
46 #define rx_dbg(args...)
47 #endif
48
49 #ifdef QUEUE_DEBUG
50 #define queue_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
51 #else
52 #define queue_dbg(args...)
53 #endif
54
55 #ifdef CSUM_DEBUG
56 #define csum_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
57 #else
58 #define csum_dbg(args...)
59 #endif
60
61 #ifdef VLAN_DEBUG
62 #define vlan_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
63 #else
64 #define vlan_dbg(args...)
65 #endif
66
67 #define jprintk(devname, fmt, args...) \
68         printk(KERN_INFO "%s: " fmt, devname, ## args)
69
70 #define jeprintk(devname, fmt, args...) \
71         printk(KERN_ERR "%s: " fmt, devname, ## args)
72
73 #define DEFAULT_MSG_ENABLE        \
74         (NETIF_MSG_DRV          | \
75          NETIF_MSG_PROBE        | \
76          NETIF_MSG_LINK         | \
77          NETIF_MSG_TIMER        | \
78          NETIF_MSG_RX_ERR       | \
79          NETIF_MSG_TX_ERR)
80
81 #define PCI_CONF_DCSR_MRRS      0x59
82 #define PCI_CONF_DCSR_MRRS_MASK 0x70
83 enum pci_conf_dcsr_mrrs_vals {
84         MRRS_128B       = 0x00,
85         MRRS_256B       = 0x10,
86         MRRS_512B       = 0x20,
87         MRRS_1024B      = 0x30,
88         MRRS_2048B      = 0x40,
89         MRRS_4096B      = 0x50,
90 };
91
92 #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
93 #define MIN_ETHERNET_PACKET_SIZE 60
94
95 enum dynamic_pcc_values {
96         PCC_OFF         = 0,
97         PCC_P1          = 1,
98         PCC_P2          = 2,
99         PCC_P3          = 3,
100
101         PCC_OFF_TO      = 0,
102         PCC_P1_TO       = 1,
103         PCC_P2_TO       = 64,
104         PCC_P3_TO       = 128,
105
106         PCC_OFF_CNT     = 0,
107         PCC_P1_CNT      = 1,
108         PCC_P2_CNT      = 16,
109         PCC_P3_CNT      = 32,
110 };
111 struct dynpcc_info {
112         unsigned long   last_bytes;
113         unsigned long   last_pkts;
114         unsigned long   intr_cnt;
115         unsigned char   cur;
116         unsigned char   attempt;
117         unsigned char   cnt;
118 };
119 #define PCC_INTERVAL_US 100000
120 #define PCC_INTERVAL (HZ / (1000000/PCC_INTERVAL_US))
121 #define PCC_P3_THRESHOLD 2*1024*1024
122 #define PCC_P2_THRESHOLD 800
123 #define PCC_INTR_THRESHOLD 800
124 #define PCC_TX_TO 333
125 #define PCC_TX_CNT 8
126
127 /*
128  * TX/RX Descriptors
129  *
130  * TX/RX Ring DESC Count Must be multiple of 16
131  * RX Ring DESC Count Must be <= 1024
132  */
133 #define RING_DESC_ALIGN         16      /* Descriptor alignment */
134
135 #define TX_DESC_SIZE            16
136 #define TX_RING_NR              8
137 #define TX_RING_ALLOC_SIZE(s)   (s * TX_DESC_SIZE) + RING_DESC_ALIGN
138
139 struct txdesc {
140         union {
141                 __u8  all[16];
142                 __u32 dw[4];
143                 struct {
144                         /* DW0 */
145                         __u16 vlan;
146                         __u8 rsv1;
147                         __u8 flags;
148
149                         /* DW1 */
150                         __u16 datalen;
151                         __u16 mss;
152
153                         /* DW2 */
154                         __u16 pktsize;
155                         __u16 rsv2;
156
157                         /* DW3 */
158                         __u32 bufaddr;
159                 } desc1;
160                 struct {
161                         /* DW0 */
162                         __u16 rsv1;
163                         __u8 rsv2;
164                         __u8 flags;
165
166                         /* DW1 */
167                         __u16 datalen;
168                         __u16 rsv3;
169
170                         /* DW2 */
171                         __u32 bufaddrh;
172
173                         /* DW3 */
174                         __u32 bufaddrl;
175                 } desc2;
176                 struct {
177                         /* DW0 */
178                         __u8 ehdrsz;
179                         __u8 rsv1;
180                         __u8 rsv2;
181                         __u8 flags;
182
183                         /* DW1 */
184                         __u16 trycnt;
185                         __u16 segcnt;
186
187                         /* DW2 */
188                         __u16 pktsz;
189                         __u16 rsv3;
190
191                         /* DW3 */
192                         __u32 bufaddrl;
193                 } descwb;
194         };
195 };
196 enum jme_txdesc_flags_bits {
197         TXFLAG_OWN      = 0x80,
198         TXFLAG_INT      = 0x40,
199         TXFLAG_64BIT    = 0x20,
200         TXFLAG_TCPCS    = 0x10,
201         TXFLAG_UDPCS    = 0x08,
202         TXFLAG_IPCS     = 0x04,
203         TXFLAG_LSEN     = 0x02,
204         TXFLAG_TAGON    = 0x01,
205 };
206 #define TXDESC_MSS_SHIFT        2
207 enum jme_rxdescwb_flags_bits {
208         TXWBFLAG_OWN    = 0x80,
209         TXWBFLAG_INT    = 0x40,
210         TXWBFLAG_TMOUT  = 0x20,
211         TXWBFLAG_TRYOUT = 0x10,
212         TXWBFLAG_COL    = 0x08,
213
214         TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
215                           TXWBFLAG_TRYOUT |
216                           TXWBFLAG_COL,
217 };
218
219
220 #define RX_DESC_SIZE            16
221 #define RX_RING_NR              4
222 #define RX_RING_ALLOC_SIZE(s)   (s * RX_DESC_SIZE) + RING_DESC_ALIGN
223
224 #define RX_BUF_DMA_ALIGN        8
225 #define RX_PREPAD_SIZE          10
226 #define ETH_CRC_LEN             2
227 #define RX_VLANHDR_LEN          2
228 #define RX_EXTRA_LEN            (RX_PREPAD_SIZE + \
229                                 ETH_HLEN + \
230                                 ETH_CRC_LEN + \
231                                 RX_VLANHDR_LEN + \
232                                 RX_BUF_DMA_ALIGN)
233
234 struct rxdesc {
235         union {
236                 __u8   all[16];
237                 __le32 dw[4];
238                 struct {
239                         /* DW0 */
240                         __le16 rsv2;
241                         __u8 rsv1;
242                         __u8 flags;
243
244                         /* DW1 */
245                         __le16 datalen;
246                         __le16 wbcpl;
247
248                         /* DW2 */
249                         __le32 bufaddrh;
250
251                         /* DW3 */
252                         __le32 bufaddrl;
253                 } desc1;
254                 struct {
255                         /* DW0 */
256                         __le16 vlan;
257                         __le16 flags;
258
259                         /* DW1 */
260                         __le16 framesize;
261                         __u8 errstat;
262                         __u8 desccnt;
263
264                         /* DW2 */
265                         __le32 rsshash;
266
267                         /* DW3 */
268                         __u8   hashfun;
269                         __u8   hashtype;
270                         __le16 resrv;
271                 } descwb;
272         };
273 };
274 enum jme_rxdesc_flags_bits {
275         RXFLAG_OWN      = 0x80,
276         RXFLAG_INT      = 0x40,
277         RXFLAG_64BIT    = 0x20,
278 };
279 enum jme_rxwbdesc_flags_bits {
280         RXWBFLAG_OWN            = 0x8000,
281         RXWBFLAG_INT            = 0x4000,
282         RXWBFLAG_MF             = 0x2000,
283         RXWBFLAG_64BIT          = 0x2000,
284         RXWBFLAG_TCPON          = 0x1000,
285         RXWBFLAG_UDPON          = 0x0800,
286         RXWBFLAG_IPCS           = 0x0400,
287         RXWBFLAG_TCPCS          = 0x0200,
288         RXWBFLAG_UDPCS          = 0x0100,
289         RXWBFLAG_TAGON          = 0x0080,
290         RXWBFLAG_IPV4           = 0x0040,
291         RXWBFLAG_IPV6           = 0x0020,
292         RXWBFLAG_PAUSE          = 0x0010,
293         RXWBFLAG_MAGIC          = 0x0008,
294         RXWBFLAG_WAKEUP         = 0x0004,
295         RXWBFLAG_DEST           = 0x0003,
296         RXWBFLAG_DEST_UNI       = 0x0001,
297         RXWBFLAG_DEST_MUL       = 0x0002,
298         RXWBFLAG_DEST_BRO       = 0x0003,
299 };
300 enum jme_rxwbdesc_desccnt_mask {
301         RXWBDCNT_WBCPL  = 0x80,
302         RXWBDCNT_DCNT   = 0x7F,
303 };
304 enum jme_rxwbdesc_errstat_bits {
305         RXWBERR_LIMIT   = 0x80,
306         RXWBERR_MIIER   = 0x40,
307         RXWBERR_NIBON   = 0x20,
308         RXWBERR_COLON   = 0x10,
309         RXWBERR_ABORT   = 0x08,
310         RXWBERR_SHORT   = 0x04,
311         RXWBERR_OVERUN  = 0x02,
312         RXWBERR_CRCERR  = 0x01,
313         RXWBERR_ALLERR  = 0xFF,
314 };
315
316 struct jme_buffer_info {
317         struct sk_buff *skb;
318         dma_addr_t mapping;
319         int len;
320         int nr_desc;
321         unsigned long start_xmit;
322 };
323
324 #define MAX_RING_DESC_NR        1024
325 struct jme_ring {
326         void* alloc;            /* pointer to allocated memory */
327         volatile void* desc;    /* pointer to ring memory  */
328         dma_addr_t dmaalloc;    /* phys address of ring alloc */
329         dma_addr_t dma;         /* phys address for ring dma */
330
331         /* Buffer information corresponding to each descriptor */
332         struct jme_buffer_info bufinf[MAX_RING_DESC_NR];
333
334         int next_to_use;
335         atomic_t next_to_clean;
336         atomic_t nr_free;
337 };
338
339 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
340 #define NET_STAT(priv) priv->stats
341 #define NETDEV_GET_STATS(netdev, fun_ptr) \
342         netdev->get_stats = fun_ptr
343 #define DECLARE_NET_DEVICE_STATS struct net_device_stats stats;
344 #else
345 #define NET_STAT(priv) priv->dev->stats
346 #define NETDEV_GET_STATS(netdev, fun_ptr)
347 #define DECLARE_NET_DEVICE_STATS
348 #endif
349
350 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
351 #define DECLARE_NAPI_STRUCT
352 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
353         dev->poll = pollfn; \
354         dev->weight = q;
355 #define JME_NAPI_HOLDER(holder) struct net_device *holder
356 #define JME_NAPI_WEIGHT(w) int *w
357 #define JME_NAPI_WEIGHT_VAL(w) *w
358 #define JME_NAPI_WEIGHT_SET(w, r) *w = r
359 #define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev)
360 #define JME_NAPI_ENABLE(priv) netif_poll_enable(priv->dev);
361 #define JME_NAPI_DISABLE(priv) netif_poll_disable(priv->dev);
362 #define JME_RX_SCHEDULE_PREP(priv) \
363         netif_rx_schedule_prep(priv->dev)
364 #define JME_RX_SCHEDULE(priv) \
365         __netif_rx_schedule(priv->dev);
366 #else
367 #define DECLARE_NAPI_STRUCT struct napi_struct napi;
368 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
369         netif_napi_add(dev, napis, pollfn, q);
370 #define JME_NAPI_HOLDER(holder) struct napi_struct *holder
371 #define JME_NAPI_WEIGHT(w) int w
372 #define JME_NAPI_WEIGHT_VAL(w) w
373 #define JME_NAPI_WEIGHT_SET(w, r)
374 #define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev, napis)
375 #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
376 #define JME_NAPI_DISABLE(priv) \
377         if(!napi_disable_pending(&priv->napi)) \
378                 napi_disable(&priv->napi);
379 #define JME_RX_SCHEDULE_PREP(priv) \
380         netif_rx_schedule_prep(priv->dev, &priv->napi)
381 #define JME_RX_SCHEDULE(priv) \
382         __netif_rx_schedule(priv->dev, &priv->napi);
383 #endif
384
385 /*
386  * Jmac Adapter Private data
387  */
388 #define SHADOW_REG_NR 8
389 struct jme_adapter {
390         struct pci_dev          *pdev;
391         struct net_device       *dev;
392         void __iomem            *regs;
393         dma_addr_t              shadow_dma;
394         __u32                   *shadow_regs;
395         struct mii_if_info      mii_if;
396         struct jme_ring         rxring[RX_RING_NR];
397         struct jme_ring         txring[TX_RING_NR];
398         spinlock_t              phy_lock;
399         spinlock_t              macaddr_lock;
400         spinlock_t              rxmcs_lock;
401         struct tasklet_struct   rxempty_task;
402         struct tasklet_struct   rxclean_task;
403         struct tasklet_struct   txclean_task;
404         struct tasklet_struct   linkch_task;
405         struct tasklet_struct   pcc_task;
406         __u32                   flags;
407         __u32                   reg_txcs;
408         __u32                   reg_txpfc;
409         __u32                   reg_rxcs;
410         __u32                   reg_rxmcs;
411         __u32                   reg_ghc;
412         __u32                   reg_pmcs;
413         __u32                   phylink;
414         __u32                   tx_ring_size;
415         __u32                   tx_ring_mask;
416         __u32                   tx_wake_threshold;
417         __u32                   rx_ring_size;
418         __u32                   rx_ring_mask;
419         __u8                    mrrs;
420         __u32                   fpgaver;
421         __u32                   chipver;
422         struct ethtool_cmd      old_ecmd;
423         unsigned int            old_mtu;
424         struct vlan_group*      vlgrp;
425         struct dynpcc_info      dpi;
426         atomic_t                intr_sem;
427         atomic_t                link_changing;
428         atomic_t                tx_cleaning;
429         atomic_t                rx_cleaning;
430         atomic_t                rx_empty;
431         int                     (*jme_rx)(struct sk_buff *skb);
432         int                     (*jme_vlan_rx)(struct sk_buff *skb,
433                                           struct vlan_group *grp,
434                                           unsigned short vlan_tag);
435         DECLARE_NAPI_STRUCT
436         DECLARE_NET_DEVICE_STATS
437 };
438 enum shadow_reg_val {
439         SHADOW_IEVE = 0,
440 };
441 enum jme_flags_bits {
442         JME_FLAG_MSI            = 0x00000001,
443         JME_FLAG_SSET           = 0x00000002,
444         JME_FLAG_TXCSUM         = 0x00000004,
445         JME_FLAG_TSO            = 0x00000008,
446         JME_FLAG_POLL           = 0x00000010,
447 };
448 #define WAIT_TASKLET_TIMEOUT    500 /* 500 ms */
449 #define TX_TIMEOUT              (5*HZ)
450
451 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
452 __always_inline static struct jme_adapter*
453 jme_napi_priv(struct net_device *holder)
454 {
455         struct jme_adapter* jme;
456         jme = netdev_priv(holder);
457         return jme;
458 }
459 #else
460 __always_inline static struct jme_adapter*
461 jme_napi_priv(struct napi_struct *napi)
462 {
463         struct jme_adapter* jme;
464         jme = container_of(napi, struct jme_adapter, napi);
465         return jme;
466 }
467 #endif
468
469 /*
470  * MMaped I/O Resters
471  */
472 enum jme_iomap_offsets {
473         JME_MAC         = 0x0000,
474         JME_PHY         = 0x0400,
475         JME_MISC        = 0x0800,
476         JME_RSS         = 0x0C00,
477 };
478
479 enum jme_iomap_lens {
480         JME_MAC_LEN     = 0x80,
481         JME_PHY_LEN     = 0x58,
482         JME_MISC_LEN    = 0x98,
483         JME_RSS_LEN     = 0xFF,
484 };
485
486 enum jme_iomap_regs {
487         JME_TXCS        = JME_MAC | 0x00, /* Transmit Control and Status */
488         JME_TXDBA_LO    = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
489         JME_TXDBA_HI    = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
490         JME_TXQDC       = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
491         JME_TXNDA       = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
492         JME_TXMCS       = JME_MAC | 0x14, /* Transmit MAC Control Status */
493         JME_TXPFC       = JME_MAC | 0x18, /* Transmit Pause Frame Control */
494         JME_TXTRHD      = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
495
496         JME_RXCS        = JME_MAC | 0x20, /* Receive Control and Status */
497         JME_RXDBA_LO    = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
498         JME_RXDBA_HI    = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
499         JME_RXQDC       = JME_MAC | 0x2C, /* Receive Queue Desc Count */
500         JME_RXNDA       = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
501         JME_RXMCS       = JME_MAC | 0x34, /* Receive MAC Control Status */
502         JME_RXUMA_LO    = JME_MAC | 0x38, /* Receive Unicast MAC Address */
503         JME_RXUMA_HI    = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
504         JME_RXMCHT_LO   = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
505         JME_RXMCHT_HI   = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
506         JME_WFODP       = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
507         JME_WFOI        = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
508
509         JME_SMI         = JME_MAC | 0x50, /* Station Management Interface */
510         JME_GHC         = JME_MAC | 0x54, /* Global Host Control */
511         JME_PMCS        = JME_MAC | 0x60, /* Power Management Control/Stat */
512
513
514         JME_PHY_CS      = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
515         JME_PHY_LINK    = JME_PHY | 0x30, /* PHY Link Status Register */
516         JME_SMBCSR      = JME_PHY | 0x40, /* SMB Control and Status */
517
518
519         JME_TMCSR       = JME_MISC| 0x00, /* Timer Control/Status Register */
520         JME_GPREG0      = JME_MISC| 0x08, /* General purpose REG-0 */
521         JME_GPREG1      = JME_MISC| 0x0C, /* General purpose REG-1 */
522         JME_IEVE        = JME_MISC| 0x20, /* Interrupt Event Status */
523         JME_IREQ        = JME_MISC| 0x24, /* Interrupt Req Status(For Debug) */
524         JME_IENS        = JME_MISC| 0x28, /* Interrupt Enable - Setting Port */
525         JME_IENC        = JME_MISC| 0x2C, /* Interrupt Enable - Clear Port */
526         JME_PCCRX0      = JME_MISC| 0x30, /* PCC Control for RX Queue 0 */
527         JME_PCCTX       = JME_MISC| 0x40, /* PCC Control for TX Queues */
528         JME_CHIPMODE    = JME_MISC| 0x44, /* Identify FPGA Version */
529         JME_SHBA_HI     = JME_MISC| 0x48, /* Shadow Register Base HI */
530         JME_SHBA_LO     = JME_MISC| 0x4C, /* Shadow Register Base LO */
531         JME_PCCSRX0     = JME_MISC| 0x80, /* PCC Status of RX0 */
532 };
533
534 /*
535  * TX Control/Status Bits
536  */
537 enum jme_txcs_bits {
538         TXCS_QUEUE7S    = 0x00008000,
539         TXCS_QUEUE6S    = 0x00004000,
540         TXCS_QUEUE5S    = 0x00002000,
541         TXCS_QUEUE4S    = 0x00001000,
542         TXCS_QUEUE3S    = 0x00000800,
543         TXCS_QUEUE2S    = 0x00000400,
544         TXCS_QUEUE1S    = 0x00000200,
545         TXCS_QUEUE0S    = 0x00000100,
546         TXCS_FIFOTH     = 0x000000C0,
547         TXCS_DMASIZE    = 0x00000030,
548         TXCS_BURST      = 0x00000004,
549         TXCS_ENABLE     = 0x00000001,
550 };
551 enum jme_txcs_value {
552         TXCS_FIFOTH_16QW        = 0x000000C0,
553         TXCS_FIFOTH_12QW        = 0x00000080,
554         TXCS_FIFOTH_8QW         = 0x00000040,
555         TXCS_FIFOTH_4QW         = 0x00000000,
556
557         TXCS_DMASIZE_64B        = 0x00000000,
558         TXCS_DMASIZE_128B       = 0x00000010,
559         TXCS_DMASIZE_256B       = 0x00000020,
560         TXCS_DMASIZE_512B       = 0x00000030,
561
562         TXCS_SELECT_QUEUE0      = 0x00000000,
563         TXCS_SELECT_QUEUE1      = 0x00010000,
564         TXCS_SELECT_QUEUE2      = 0x00020000,
565         TXCS_SELECT_QUEUE3      = 0x00030000,
566         TXCS_SELECT_QUEUE4      = 0x00040000,
567         TXCS_SELECT_QUEUE5      = 0x00050000,
568         TXCS_SELECT_QUEUE6      = 0x00060000,
569         TXCS_SELECT_QUEUE7      = 0x00070000,
570
571         TXCS_DEFAULT            = TXCS_FIFOTH_4QW |
572                                   TXCS_BURST,
573 };
574 #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
575
576 /*
577  * TX MAC Control/Status Bits
578  */
579 enum jme_txmcs_bit_masks {
580         TXMCS_IFG2              = 0xC0000000,
581         TXMCS_IFG1              = 0x30000000,
582         TXMCS_TTHOLD            = 0x00000300,
583         TXMCS_FBURST            = 0x00000080,
584         TXMCS_CARRIEREXT        = 0x00000040,
585         TXMCS_DEFER             = 0x00000020,
586         TXMCS_BACKOFF           = 0x00000010,
587         TXMCS_CARRIERSENSE      = 0x00000008,
588         TXMCS_COLLISION         = 0x00000004,
589         TXMCS_CRC               = 0x00000002,
590         TXMCS_PADDING           = 0x00000001,
591 };
592 enum jme_txmcs_values {
593         TXMCS_IFG2_6_4          = 0x00000000,
594         TXMCS_IFG2_8_5          = 0x40000000,
595         TXMCS_IFG2_10_6         = 0x80000000,
596         TXMCS_IFG2_12_7         = 0xC0000000,
597
598         TXMCS_IFG1_8_4          = 0x00000000,
599         TXMCS_IFG1_12_6         = 0x10000000,
600         TXMCS_IFG1_16_8         = 0x20000000,
601         TXMCS_IFG1_20_10        = 0x30000000,
602
603         TXMCS_TTHOLD_1_8        = 0x00000000,
604         TXMCS_TTHOLD_1_4        = 0x00000100,
605         TXMCS_TTHOLD_1_2        = 0x00000200,
606         TXMCS_TTHOLD_FULL       = 0x00000300,
607
608         TXMCS_DEFAULT           = TXMCS_IFG2_8_5 |
609                                   TXMCS_IFG1_16_8 |
610                                   TXMCS_TTHOLD_FULL |
611                                   TXMCS_DEFER |
612                                   TXMCS_CRC |
613                                   TXMCS_PADDING,
614 };
615
616 enum jme_txpfc_bits_masks {
617         TXPFC_VLAN_TAG          = 0xFFFF0000,
618         TXPFC_VLAN_EN           = 0x00008000,
619         TXPFC_PF_EN             = 0x00000001,
620 };
621
622 enum jme_txtrhd_bits_masks {
623         TXTRHD_TXPEN            = 0x80000000,
624         TXTRHD_TXP              = 0x7FFFFF00,
625         TXTRHD_TXREN            = 0x00000080,
626         TXTRHD_TXRL             = 0x0000007F,
627 };
628 enum jme_txtrhd_shifts {
629         TXTRHD_TXP_SHIFT        = 8,
630         TXTRHD_TXRL_SHIFT       = 0,
631 };
632
633
634 /*
635  * RX Control/Status Bits
636  */
637 enum jme_rxcs_bit_masks {
638         /* FIFO full threshold for transmitting Tx Pause Packet */
639         RXCS_FIFOTHTP   = 0x30000000,
640         /* FIFO threshold for processing next packet */
641         RXCS_FIFOTHNP   = 0x0C000000,
642         RXCS_DMAREQSZ   = 0x03000000, /* DMA Request Size */
643         RXCS_QUEUESEL   = 0x00030000, /* Queue selection */
644         RXCS_RETRYGAP   = 0x0000F000, /* RX Desc full retry gap */
645         RXCS_RETRYCNT   = 0x00000F00, /* RX Desc full retry counter */
646         RXCS_WAKEUP     = 0x00000040, /* Enable receive wakeup packet */
647         RXCS_MAGIC      = 0x00000020, /* Enable receive magic packet */
648         RXCS_SHORT      = 0x00000010, /* Enable receive short packet */
649         RXCS_ABORT      = 0x00000008, /* Enable receive errorr packet */
650         RXCS_QST        = 0x00000004, /* Receive queue start */
651         RXCS_SUSPEND    = 0x00000002,
652         RXCS_ENABLE     = 0x00000001,
653 };
654 enum jme_rxcs_values {
655         RXCS_FIFOTHTP_16T       = 0x00000000,
656         RXCS_FIFOTHTP_32T       = 0x10000000,
657         RXCS_FIFOTHTP_64T       = 0x20000000,
658         RXCS_FIFOTHTP_128T      = 0x30000000,
659
660         RXCS_FIFOTHNP_16QW      = 0x00000000,
661         RXCS_FIFOTHNP_32QW      = 0x04000000,
662         RXCS_FIFOTHNP_64QW      = 0x08000000,
663         RXCS_FIFOTHNP_128QW     = 0x0C000000,
664
665         RXCS_DMAREQSZ_16B       = 0x00000000,
666         RXCS_DMAREQSZ_32B       = 0x01000000,
667         RXCS_DMAREQSZ_64B       = 0x02000000,
668         RXCS_DMAREQSZ_128B      = 0x03000000,
669
670         RXCS_QUEUESEL_Q0        = 0x00000000,
671         RXCS_QUEUESEL_Q1        = 0x00010000,
672         RXCS_QUEUESEL_Q2        = 0x00020000,
673         RXCS_QUEUESEL_Q3        = 0x00030000,
674
675         RXCS_RETRYGAP_256ns     = 0x00000000,
676         RXCS_RETRYGAP_512ns     = 0x00001000,
677         RXCS_RETRYGAP_1024ns    = 0x00002000,
678         RXCS_RETRYGAP_2048ns    = 0x00003000,
679         RXCS_RETRYGAP_4096ns    = 0x00004000,
680         RXCS_RETRYGAP_8192ns    = 0x00005000,
681         RXCS_RETRYGAP_16384ns   = 0x00006000,
682         RXCS_RETRYGAP_32768ns   = 0x00007000,
683
684         RXCS_RETRYCNT_0         = 0x00000000,
685         RXCS_RETRYCNT_4         = 0x00000100,
686         RXCS_RETRYCNT_8         = 0x00000200,
687         RXCS_RETRYCNT_12        = 0x00000300,
688         RXCS_RETRYCNT_16        = 0x00000400,
689         RXCS_RETRYCNT_20        = 0x00000500,
690         RXCS_RETRYCNT_24        = 0x00000600,
691         RXCS_RETRYCNT_28        = 0x00000700,
692         RXCS_RETRYCNT_32        = 0x00000800,
693         RXCS_RETRYCNT_36        = 0x00000900,
694         RXCS_RETRYCNT_40        = 0x00000A00,
695         RXCS_RETRYCNT_44        = 0x00000B00,
696         RXCS_RETRYCNT_48        = 0x00000C00,
697         RXCS_RETRYCNT_52        = 0x00000D00,
698         RXCS_RETRYCNT_56        = 0x00000E00,
699         RXCS_RETRYCNT_60        = 0x00000F00,
700
701         RXCS_DEFAULT            = RXCS_FIFOTHTP_128T |
702                                   RXCS_FIFOTHNP_128QW |
703                                   RXCS_DMAREQSZ_128B |
704                                   RXCS_RETRYGAP_256ns |
705                                   RXCS_RETRYCNT_32,
706 };
707 #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
708
709 /*
710  * RX MAC Control/Status Bits
711  */
712 enum jme_rxmcs_bits {
713         RXMCS_ALLFRAME          = 0x00000800,
714         RXMCS_BRDFRAME          = 0x00000400,
715         RXMCS_MULFRAME          = 0x00000200,
716         RXMCS_UNIFRAME          = 0x00000100,
717         RXMCS_ALLMULFRAME       = 0x00000080,
718         RXMCS_MULFILTERED       = 0x00000040,
719         RXMCS_RXCOLLDEC         = 0x00000020,
720         RXMCS_FLOWCTRL          = 0x00000008,
721         RXMCS_VTAGRM            = 0x00000004,
722         RXMCS_PREPAD            = 0x00000002,
723         RXMCS_CHECKSUM          = 0x00000001,
724
725         RXMCS_DEFAULT           = RXMCS_VTAGRM |
726                                   RXMCS_PREPAD |
727                                   RXMCS_FLOWCTRL |
728                                   RXMCS_CHECKSUM,
729 };
730
731 /*
732  * Wakeup Frame setup interface registers
733  */
734 #define WAKEUP_FRAME_NR 8
735 #define WAKEUP_FRAME_MASK_DWNR  4
736 enum jme_wfoi_bit_masks {
737         WFOI_MASK_SEL           = 0x00000070,
738         WFOI_CRC_SEL            = 0x00000008,
739         WFOI_FRAME_SEL          = 0x00000007,
740 };
741 enum jme_wfoi_shifts {
742         WFOI_MASK_SHIFT         = 4,
743 };
744
745 /*
746  * SMI Related definitions
747  */
748 enum jme_smi_bit_mask
749 {
750         SMI_DATA_MASK           = 0xFFFF0000,
751         SMI_REG_ADDR_MASK       = 0x0000F800,
752         SMI_PHY_ADDR_MASK       = 0x000007C0,
753         SMI_OP_WRITE            = 0x00000020,
754         /* Set to 1, after req done it'll be cleared to 0 */
755         SMI_OP_REQ              = 0x00000010,
756         SMI_OP_MDIO             = 0x00000008, /* Software assess In/Out */
757         SMI_OP_MDOE             = 0x00000004, /* Software Output Enable */
758         SMI_OP_MDC              = 0x00000002, /* Software CLK Control */
759         SMI_OP_MDEN             = 0x00000001, /* Software access Enable */
760 };
761 enum jme_smi_bit_shift
762 {
763         SMI_DATA_SHIFT          = 16,
764         SMI_REG_ADDR_SHIFT      = 11,
765         SMI_PHY_ADDR_SHIFT      = 6,
766 };
767 __always_inline __u32 smi_reg_addr(int x)
768 {
769         return (((x) << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK);
770 }
771 __always_inline __u32 smi_phy_addr(int x)
772 {
773         return (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK);
774 }
775 #define JME_PHY_TIMEOUT 1000 /* 1000 msec */
776
777 /*
778  * Global Host Control
779  */
780 enum jme_ghc_bit_mask {
781         GHC_SWRST       = 0x40000000,
782         GHC_DPX         = 0x00000040,
783         GHC_SPEED       = 0x00000030,
784         GHC_LINK_POLL   = 0x00000001,
785 };
786 enum jme_ghc_speed_val {
787         GHC_SPEED_10M   = 0x00000010,
788         GHC_SPEED_100M  = 0x00000020,
789         GHC_SPEED_1000M = 0x00000030,
790 };
791
792 /*
793  * Power management control and status register
794  */
795 enum jme_pmcs_bit_masks {
796         PMCS_WF7DET     = 0x80000000,
797         PMCS_WF6DET     = 0x40000000,
798         PMCS_WF5DET     = 0x20000000,
799         PMCS_WF4DET     = 0x10000000,
800         PMCS_WF3DET     = 0x08000000,
801         PMCS_WF2DET     = 0x04000000,
802         PMCS_WF1DET     = 0x02000000,
803         PMCS_WF0DET     = 0x01000000,
804         PMCS_LFDET      = 0x00040000,
805         PMCS_LRDET      = 0x00020000,
806         PMCS_MFDET      = 0x00010000,
807         PMCS_WF7EN      = 0x00008000,
808         PMCS_WF6EN      = 0x00004000,
809         PMCS_WF5EN      = 0x00002000,
810         PMCS_WF4EN      = 0x00001000,
811         PMCS_WF3EN      = 0x00000800,
812         PMCS_WF2EN      = 0x00000400,
813         PMCS_WF1EN      = 0x00000200,
814         PMCS_WF0EN      = 0x00000100,
815         PMCS_LFEN       = 0x00000004,
816         PMCS_LREN       = 0x00000002,
817         PMCS_MFEN       = 0x00000001,
818 };
819
820 /*
821  * Giga PHY Status Registers
822  */
823 enum jme_phy_link_bit_mask {
824         PHY_LINK_SPEED_MASK             = 0x0000C000,
825         PHY_LINK_DUPLEX                 = 0x00002000,
826         PHY_LINK_SPEEDDPU_RESOLVED      = 0x00000800,
827         PHY_LINK_UP                     = 0x00000400,
828         PHY_LINK_AUTONEG_COMPLETE       = 0x00000200,
829         PHY_LINK_MDI_STAT               = 0x00000040,
830 };
831 enum jme_phy_link_speed_val {
832         PHY_LINK_SPEED_10M              = 0x00000000,
833         PHY_LINK_SPEED_100M             = 0x00004000,
834         PHY_LINK_SPEED_1000M            = 0x00008000,
835 };
836 #define JME_SPDRSV_TIMEOUT      500     /* 500 us */
837
838 /*
839  * SMB Control and Status
840  */
841 enum jme_smbcsr_bit_mask {
842         SMBCSR_CNACK    = 0x00020000,
843         SMBCSR_RELOAD   = 0x00010000,
844         SMBCSR_EEPROMD  = 0x00000020,
845 };
846 #define JME_SMB_TIMEOUT 10 /* 10 msec */
847
848 /*
849  * Timer Control/Status Register
850  */
851 enum jme_tmcsr_bit_masks {
852         TMCSR_SWIT      = 0x80000000,
853         TMCSR_EN        = 0x01000000,
854         TMCSR_CNT       = 0x00FFFFFF,
855 };
856
857
858 /*
859  * General Purpost REG-0
860  */
861 enum jme_gpreg0_masks {
862         GPREG0_DISSH            = 0xFF000000,
863         GPREG0_PCIRLMT          = 0x00300000,
864         GPREG0_PCCNOMUTCLR      = 0x00040000,
865         GPREG0_LNKINTPOLL       = 0x00001000,
866         GPREG0_PCCTMR           = 0x00000300,
867         GPREG0_PHYADDR          = 0x0000001F,
868 };
869 enum jme_gpreg0_vals {
870         GPREG0_DISSH_DW7        = 0x80000000,
871         GPREG0_DISSH_DW6        = 0x40000000,
872         GPREG0_DISSH_DW5        = 0x20000000,
873         GPREG0_DISSH_DW4        = 0x10000000,
874         GPREG0_DISSH_DW3        = 0x08000000,
875         GPREG0_DISSH_DW2        = 0x04000000,
876         GPREG0_DISSH_DW1        = 0x02000000,
877         GPREG0_DISSH_DW0        = 0x01000000,
878         GPREG0_DISSH_ALL        = 0xFF000000,
879
880         GPREG0_PCIRLMT_8        = 0x00000000,
881         GPREG0_PCIRLMT_6        = 0x00100000,
882         GPREG0_PCIRLMT_5        = 0x00200000,
883         GPREG0_PCIRLMT_4        = 0x00300000,
884
885         GPREG0_PCCTMR_16ns      = 0x00000000,
886         GPREG0_PCCTMR_256ns     = 0x00000100,
887         GPREG0_PCCTMR_1us       = 0x00000200,
888         GPREG0_PCCTMR_1ms       = 0x00000300,
889
890         GPREG0_PHYADDR_1        = 0x00000001,
891
892         GPREG0_DEFAULT          = GPREG0_PCIRLMT_4 |
893                                   GPREG0_PCCNOMUTCLR |
894                                   GPREG0_PCCTMR_1us |
895                                   GPREG0_PHYADDR_1,
896 };
897
898 /*
899  * Interrupt Status Bits
900  */
901 enum jme_interrupt_bits
902 {
903         INTR_SWINTR     = 0x80000000,
904         INTR_TMINTR     = 0x40000000,
905         INTR_LINKCH     = 0x20000000,
906         INTR_PAUSERCV   = 0x10000000,
907         INTR_MAGICRCV   = 0x08000000,
908         INTR_WAKERCV    = 0x04000000,
909         INTR_PCCRX0TO   = 0x02000000,
910         INTR_PCCRX1TO   = 0x01000000,
911         INTR_PCCRX2TO   = 0x00800000,
912         INTR_PCCRX3TO   = 0x00400000,
913         INTR_PCCTXTO    = 0x00200000,
914         INTR_PCCRX0     = 0x00100000,
915         INTR_PCCRX1     = 0x00080000,
916         INTR_PCCRX2     = 0x00040000,
917         INTR_PCCRX3     = 0x00020000,
918         INTR_PCCTX      = 0x00010000,
919         INTR_RX3EMP     = 0x00008000,
920         INTR_RX2EMP     = 0x00004000,
921         INTR_RX1EMP     = 0x00002000,
922         INTR_RX0EMP     = 0x00001000,
923         INTR_RX3        = 0x00000800,
924         INTR_RX2        = 0x00000400,
925         INTR_RX1        = 0x00000200,
926         INTR_RX0        = 0x00000100,
927         INTR_TX7        = 0x00000080,
928         INTR_TX6        = 0x00000040,
929         INTR_TX5        = 0x00000020,
930         INTR_TX4        = 0x00000010,
931         INTR_TX3        = 0x00000008,
932         INTR_TX2        = 0x00000004,
933         INTR_TX1        = 0x00000002,
934         INTR_TX0        = 0x00000001,
935 };
936 static const __u32 INTR_ENABLE = INTR_SWINTR |
937                                  INTR_TMINTR |
938                                  INTR_LINKCH |
939                                  INTR_PCCRX0TO |
940                                  INTR_PCCRX0 |
941                                  INTR_PCCTXTO |
942                                  INTR_PCCTX |
943                                  INTR_RX0EMP;
944
945 /*
946  * PCC Control Registers
947  */
948 enum jme_pccrx_masks {
949         PCCRXTO_MASK    = 0xFFFF0000,
950         PCCRX_MASK      = 0x0000FF00,
951 };
952 enum jme_pcctx_masks {
953         PCCTXTO_MASK    = 0xFFFF0000,
954         PCCTX_MASK      = 0x0000FF00,
955         PCCTX_QS_MASK   = 0x000000FF,
956 };
957 enum jme_pccrx_shifts {
958         PCCRXTO_SHIFT   = 16,
959         PCCRX_SHIFT     = 8,
960 };
961 enum jme_pcctx_shifts {
962         PCCTXTO_SHIFT   = 16,
963         PCCTX_SHIFT     = 8,
964 };
965 enum jme_pcctx_bits {
966         PCCTXQ0_EN      = 0x00000001,
967         PCCTXQ1_EN      = 0x00000002,
968         PCCTXQ2_EN      = 0x00000004,
969         PCCTXQ3_EN      = 0x00000008,
970         PCCTXQ4_EN      = 0x00000010,
971         PCCTXQ5_EN      = 0x00000020,
972         PCCTXQ6_EN      = 0x00000040,
973         PCCTXQ7_EN      = 0x00000080,
974 };
975
976 /*
977  * Chip Mode Register
978  */
979 enum jme_chipmode_bit_masks {
980         CM_FPGAVER_MASK         = 0xFFFF0000,
981         CM_CHIPVER_MASK         = 0x0000FF00,
982         CM_CHIPMODE_MASK        = 0x0000000F,
983 };
984 enum jme_chipmode_shifts {
985         CM_FPGAVER_SHIFT        = 16,
986         CM_CHIPVER_SHIFT        = 8,
987 };
988
989 /*
990  * Shadow base address register bits
991  */
992 enum jme_shadow_base_address_bits {
993         SHBA_POSTEN     = 0x1,
994 };
995
996 /*
997  * Read/Write MMaped I/O Registers
998  */
999 __always_inline __u32 jread32(struct jme_adapter *jme, __u32 reg)
1000 {
1001         return le32_to_cpu(readl((__u8*)jme->regs + reg));
1002 }
1003 __always_inline void jwrite32(struct jme_adapter *jme, __u32 reg, __u32 val)
1004 {
1005         writel(cpu_to_le32(val), (__u8*)jme->regs + reg);
1006 }
1007 __always_inline void jwrite32f(struct jme_adapter *jme, __u32 reg, __u32 val)
1008 {
1009         /*
1010          * Read after write should cause flush
1011          */
1012         writel(cpu_to_le32(val), (__u8*)jme->regs + reg);
1013         readl((__u8*)jme->regs + reg);
1014 }
1015
1016 /*
1017  * PHY Regs
1018  */
1019 enum jme_phy_reg17_bit_masks {
1020         PREG17_SPEED            = 0xC000,
1021         PREG17_DUPLEX           = 0x2000,
1022         PREG17_SPDRSV           = 0x0800,
1023         PREG17_LNKUP            = 0x0400,
1024         PREG17_MDI              = 0x0040,
1025 };
1026 enum jme_phy_reg17_vals {
1027         PREG17_SPEED_10M        = 0x0000,
1028         PREG17_SPEED_100M       = 0x4000,
1029         PREG17_SPEED_1000M      = 0x8000,
1030 };
1031 #define BMCR_ANCOMP               0x0020
1032
1033 /*
1034  * Function prototypes for ethtool
1035  */
1036 static void jme_get_drvinfo(struct net_device *netdev,
1037                              struct ethtool_drvinfo *info);
1038 static int jme_get_settings(struct net_device *netdev,
1039                              struct ethtool_cmd *ecmd);
1040 static int jme_set_settings(struct net_device *netdev,
1041                              struct ethtool_cmd *ecmd);
1042 static u32 jme_get_link(struct net_device *netdev);
1043
1044
1045 /*
1046  * Function prototypes for netdev
1047  */
1048 static int jme_open(struct net_device *netdev);
1049 static int jme_close(struct net_device *netdev);
1050 static int jme_start_xmit(struct sk_buff *skb, struct net_device *netdev);
1051 static int jme_set_macaddr(struct net_device *netdev, void *p);
1052 static void jme_set_multi(struct net_device *netdev);
1053