jme.h

   1 /*
   2  * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
   3  *
   4  * Copyright 2008 JMicron Technology Corporation
   5  * http://www.jmicron.com/
   6  *
   7  * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  *
  22  */
  23
  24 #ifndef __JME_H_INCLUDED__
  25 #define __JME_H_INCLUDED__
  26
  27 #define DRV_NAME        "jme"
  28 #define DRV_VERSION     "1.0.6.1-jmmod"
  29 #define PFX             DRV_NAME ": "
  30
  31 #define PCI_DEVICE_ID_JMICRON_JMC250    0x0250
  32 #define PCI_DEVICE_ID_JMICRON_JMC260    0x0260
  33
  34 /*
  35  * Message related definitions
  36  */
  37 #define JME_DEF_MSG_ENABLE \
  38         (NETIF_MSG_PROBE | \
  39         NETIF_MSG_LINK | \
  40         NETIF_MSG_RX_ERR | \
  41         NETIF_MSG_TX_ERR | \
  42         NETIF_MSG_HW)
  43
  44 #define jeprintk(pdev, fmt, args...) \
  45         printk(KERN_ERR PFX fmt, ## args)
  46
  47 #ifdef TX_DEBUG
  48 #define tx_dbg(priv, fmt, args...)                                      \
  49         printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args)
  50 #else
  51 #define tx_dbg(priv, fmt, args...)                                      \
  52 do {                                                                    \
  53         if (0)                                                          \
  54                 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args); \
  55 } while (0)
  56 #endif
  57
  58 #include <linux/version.h>
  59 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
  60 #define jme_msg(msglvl, type, priv, fmt, args...) \
  61         if (netif_msg_##type(priv)) \
  62                 printk(msglvl "%s: " fmt, (priv)->dev->name, ## args)
  63
  64 #define msg_probe(priv, fmt, args...) \
  65         jme_msg(KERN_INFO, probe, priv, fmt, ## args)
  66
  67 #define msg_link(priv, fmt, args...) \
  68         jme_msg(KERN_INFO, link, priv, fmt, ## args)
  69
  70 #define msg_intr(priv, fmt, args...) \
  71         jme_msg(KERN_INFO, intr, priv, fmt, ## args)
  72
  73 #define msg_rx_err(priv, fmt, args...) \
  74         jme_msg(KERN_ERR, rx_err, priv, fmt, ## args)
  75
  76 #define msg_rx_status(priv, fmt, args...) \
  77         jme_msg(KERN_INFO, rx_status, priv, fmt, ## args)
  78
  79 #define msg_tx_err(priv, fmt, args...) \
  80         jme_msg(KERN_ERR, tx_err, priv, fmt, ## args)
  81
  82 #define msg_tx_done(priv, fmt, args...) \
  83         jme_msg(KERN_INFO, tx_done, priv, fmt, ## args)
  84
  85 #define msg_tx_queued(priv, fmt, args...) \
  86         jme_msg(KERN_INFO, tx_queued, priv, fmt, ## args)
  87
  88 #define msg_hw(priv, fmt, args...) \
  89         jme_msg(KERN_ERR, hw, priv, fmt, ## args)
  90 #endif
  91
  92 /*
  93  * Extra PCI Configuration space interface
  94  */
  95 #define PCI_DCSR_MRRS           0x59
  96 #define PCI_DCSR_MRRS_MASK      0x70
  97
  98 enum pci_dcsr_mrrs_vals {
  99         MRRS_128B       = 0x00,
 100         MRRS_256B       = 0x10,
 101         MRRS_512B       = 0x20,
 102         MRRS_1024B      = 0x30,
 103         MRRS_2048B      = 0x40,
 104         MRRS_4096B      = 0x50,
 105 };
 106
 107 #define PCI_SPI                 0xB0
 108
 109 enum pci_spi_bits {
 110         SPI_EN          = 0x10,
 111         SPI_MISO        = 0x08,
 112         SPI_MOSI        = 0x04,
 113         SPI_SCLK        = 0x02,
 114         SPI_CS          = 0x01,
 115 };
 116
 117 struct jme_spi_op {
 118         void __user *uwbuf;
 119         void __user *urbuf;
 120         __u8    wn;     /* Number of write actions */
 121         __u8    rn;     /* Number of read actions */
 122         __u8    bitn;   /* Number of bits per action */
 123         __u8    spd;    /* The maxim acceptable speed of controller, in MHz.*/
 124         __u8    mode;   /* CPOL, CPHA, and Duplex mode of SPI */
 125
 126         /* Internal use only */
 127         u8      *kwbuf;
 128         u8      *krbuf;
 129         u8      sr;
 130         u16     halfclk; /* Half of clock cycle calculated from spd, in ns */
 131 };
 132
 133 enum jme_spi_op_bits {
 134         SPI_MODE_CPHA   = 0x01,
 135         SPI_MODE_CPOL   = 0x02,
 136         SPI_MODE_DUP    = 0x80,
 137 };
 138
 139 #define HALF_US 500     /* 500 ns */
 140 #define JMESPIIOCTL     SIOCDEVPRIVATE
 141
 142 /*
 143  * Dynamic(adaptive)/Static PCC values
 144  */
 145 enum dynamic_pcc_values {
 146         PCC_OFF         = 0,
 147         PCC_P1          = 1,
 148         PCC_P2          = 2,
 149         PCC_P3          = 3,
 150
 151         PCC_OFF_TO      = 0,
 152         PCC_P1_TO       = 1,
 153         PCC_P2_TO       = 64,
 154         PCC_P3_TO       = 128,
 155
 156         PCC_OFF_CNT     = 0,
 157         PCC_P1_CNT      = 1,
 158         PCC_P2_CNT      = 16,
 159         PCC_P3_CNT      = 32,
 160 };
 161 struct dynpcc_info {
 162         unsigned long   last_bytes;
 163         unsigned long   last_pkts;
 164         unsigned long   intr_cnt;
 165         unsigned char   cur;
 166         unsigned char   attempt;
 167         unsigned char   cnt;
 168 };
 169 #define PCC_INTERVAL_US 100000
 170 #define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
 171 #define PCC_P3_THRESHOLD (2 * 1024 * 1024)
 172 #define PCC_P2_THRESHOLD 800
 173 #define PCC_INTR_THRESHOLD 800
 174 #define PCC_TX_TO 1000
 175 #define PCC_TX_CNT 8
 176
 177 /*
 178  * TX/RX Descriptors
 179  *
 180  * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
 181  */
 182 #define RING_DESC_ALIGN         16      /* Descriptor alignment */
 183 #define TX_DESC_SIZE            16
 184 #define TX_RING_NR              8
 185 #define TX_RING_ALLOC_SIZE(s)   ((s * TX_DESC_SIZE) + RING_DESC_ALIGN)
 186
 187 struct txdesc {
 188         union {
 189                 __u8    all[16];
 190                 __le32  dw[4];
 191                 struct {
 192                         /* DW0 */
 193                         __le16  vlan;
 194                         __u8    rsv1;
 195                         __u8    flags;
 196
 197                         /* DW1 */
 198                         __le16  datalen;
 199                         __le16  mss;
 200
 201                         /* DW2 */
 202                         __le16  pktsize;
 203                         __le16  rsv2;
 204
 205                         /* DW3 */
 206                         __le32  bufaddr;
 207                 } desc1;
 208                 struct {
 209                         /* DW0 */
 210                         __le16  rsv1;
 211                         __u8    rsv2;
 212                         __u8    flags;
 213
 214                         /* DW1 */
 215                         __le16  datalen;
 216                         __le16  rsv3;
 217
 218                         /* DW2 */
 219                         __le32  bufaddrh;
 220
 221                         /* DW3 */
 222                         __le32  bufaddrl;
 223                 } desc2;
 224                 struct {
 225                         /* DW0 */
 226                         __u8    ehdrsz;
 227                         __u8    rsv1;
 228                         __u8    rsv2;
 229                         __u8    flags;
 230
 231                         /* DW1 */
 232                         __le16  trycnt;
 233                         __le16  segcnt;
 234
 235                         /* DW2 */
 236                         __le16  pktsz;
 237                         __le16  rsv3;
 238
 239                         /* DW3 */
 240                         __le32  bufaddrl;
 241                 } descwb;
 242         };
 243 };
 244
 245 enum jme_txdesc_flags_bits {
 246         TXFLAG_OWN      = 0x80,
 247         TXFLAG_INT      = 0x40,
 248         TXFLAG_64BIT    = 0x20,
 249         TXFLAG_TCPCS    = 0x10,
 250         TXFLAG_UDPCS    = 0x08,
 251         TXFLAG_IPCS     = 0x04,
 252         TXFLAG_LSEN     = 0x02,
 253         TXFLAG_TAGON    = 0x01,
 254 };
 255
 256 #define TXDESC_MSS_SHIFT        2
 257 enum jme_txwbdesc_flags_bits {
 258         TXWBFLAG_OWN    = 0x80,
 259         TXWBFLAG_INT    = 0x40,
 260         TXWBFLAG_TMOUT  = 0x20,
 261         TXWBFLAG_TRYOUT = 0x10,
 262         TXWBFLAG_COL    = 0x08,
 263
 264         TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
 265                           TXWBFLAG_TRYOUT |
 266                           TXWBFLAG_COL,
 267 };
 268
 269 #define RX_DESC_SIZE            16
 270 #define RX_RING_NR              4
 271 #define RX_RING_ALLOC_SIZE(s)   ((s * RX_DESC_SIZE) + RING_DESC_ALIGN)
 272 #define RX_BUF_DMA_ALIGN        8
 273 #define RX_PREPAD_SIZE          10
 274 #define ETH_CRC_LEN             2
 275 #define RX_VLANHDR_LEN          2
 276 #define RX_EXTRA_LEN            (RX_PREPAD_SIZE + \
 277                                 ETH_HLEN + \
 278                                 ETH_CRC_LEN + \
 279                                 RX_VLANHDR_LEN + \
 280                                 RX_BUF_DMA_ALIGN)
 281
 282 struct rxdesc {
 283         union {
 284                 __u8    all[16];
 285                 __le32  dw[4];
 286                 struct {
 287                         /* DW0 */
 288                         __le16  rsv2;
 289                         __u8    rsv1;
 290                         __u8    flags;
 291
 292                         /* DW1 */
 293                         __le16  datalen;
 294                         __le16  wbcpl;
 295
 296                         /* DW2 */
 297                         __le32  bufaddrh;
 298
 299                         /* DW3 */
 300                         __le32  bufaddrl;
 301                 } desc1;
 302                 struct {
 303                         /* DW0 */
 304                         __le16  vlan;
 305                         __le16  flags;
 306
 307                         /* DW1 */
 308                         __le16  framesize;
 309                         __u8    errstat;
 310                         __u8    desccnt;
 311
 312                         /* DW2 */
 313                         __le32  rsshash;
 314
 315                         /* DW3 */
 316                         __u8    hashfun;
 317                         __u8    hashtype;
 318                         __le16  resrv;
 319                 } descwb;
 320         };
 321 };
 322
 323 enum jme_rxdesc_flags_bits {
 324         RXFLAG_OWN      = 0x80,
 325         RXFLAG_INT      = 0x40,
 326         RXFLAG_64BIT    = 0x20,
 327 };
 328
 329 enum jme_rxwbdesc_flags_bits {
 330         RXWBFLAG_OWN            = 0x8000,
 331         RXWBFLAG_INT            = 0x4000,
 332         RXWBFLAG_MF             = 0x2000,
 333         RXWBFLAG_64BIT          = 0x2000,
 334         RXWBFLAG_TCPON          = 0x1000,
 335         RXWBFLAG_UDPON          = 0x0800,
 336         RXWBFLAG_IPCS           = 0x0400,
 337         RXWBFLAG_TCPCS          = 0x0200,
 338         RXWBFLAG_UDPCS          = 0x0100,
 339         RXWBFLAG_TAGON          = 0x0080,
 340         RXWBFLAG_IPV4           = 0x0040,
 341         RXWBFLAG_IPV6           = 0x0020,
 342         RXWBFLAG_PAUSE          = 0x0010,
 343         RXWBFLAG_MAGIC          = 0x0008,
 344         RXWBFLAG_WAKEUP         = 0x0004,
 345         RXWBFLAG_DEST           = 0x0003,
 346         RXWBFLAG_DEST_UNI       = 0x0001,
 347         RXWBFLAG_DEST_MUL       = 0x0002,
 348         RXWBFLAG_DEST_BRO       = 0x0003,
 349 };
 350
 351 enum jme_rxwbdesc_desccnt_mask {
 352         RXWBDCNT_WBCPL  = 0x80,
 353         RXWBDCNT_DCNT   = 0x7F,
 354 };
 355
 356 enum jme_rxwbdesc_errstat_bits {
 357         RXWBERR_LIMIT   = 0x80,
 358         RXWBERR_MIIER   = 0x40,
 359         RXWBERR_NIBON   = 0x20,
 360         RXWBERR_COLON   = 0x10,
 361         RXWBERR_ABORT   = 0x08,
 362         RXWBERR_SHORT   = 0x04,
 363         RXWBERR_OVERUN  = 0x02,
 364         RXWBERR_CRCERR  = 0x01,
 365         RXWBERR_ALLERR  = 0xFF,
 366 };
 367
 368 /*
 369  * Buffer information corresponding to ring descriptors.
 370  */
 371 struct jme_buffer_info {
 372         struct sk_buff *skb;
 373         dma_addr_t mapping;
 374         int len;
 375         int nr_desc;
 376         unsigned long start_xmit;
 377 };
 378
 379 /*
 380  * The structure holding buffer information and ring descriptors all together.
 381  */
 382 struct jme_ring {
 383         void *alloc;            /* pointer to allocated memory */
 384         void *desc;             /* pointer to ring memory  */
 385         dma_addr_t dmaalloc;    /* phys address of ring alloc */
 386         dma_addr_t dma;         /* phys address for ring dma */
 387
 388         /* Buffer information corresponding to each descriptor */
 389         struct jme_buffer_info *bufinf;
 390
 391         int next_to_use;
 392         atomic_t next_to_clean;
 393         atomic_t nr_free;
 394 };
 395
 396 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
 397 #define false 0
 398 #define true 0
 399 #define netdev_alloc_skb(dev, len) dev_alloc_skb(len)
 400 #define PCI_VENDOR_ID_JMICRON           0x197B
 401 #endif
 402
 403 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,19)
 404 #define PCI_VDEVICE(vendor, device)             \
 405         PCI_VENDOR_ID_##vendor, (device),       \
 406         PCI_ANY_ID, PCI_ANY_ID, 0, 0
 407 #endif
 408
 409 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
 410 #define NET_STAT(priv) priv->stats
 411 #define NETDEV_GET_STATS(netdev, fun_ptr) \
 412         netdev->get_stats = fun_ptr
 413 #define DECLARE_NET_DEVICE_STATS struct net_device_stats stats;
 414 /*
 415  * CentOS 5.5 have *_hdr helpers back-ported
 416  */
 417 #ifdef RHEL_RELEASE_CODE
 418 #if RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,5)
 419 #define __DEFINE_IPHDR_HELPERS__
 420 #endif
 421 #else
 422 #define __DEFINE_IPHDR_HELPERS__
 423 #endif
 424 #else
 425 #define NET_STAT(priv) (priv->dev->stats)
 426 #define NETDEV_GET_STATS(netdev, fun_ptr)
 427 #define DECLARE_NET_DEVICE_STATS
 428 #endif
 429
 430 #ifdef __DEFINE_IPHDR_HELPERS__
 431 static inline struct iphdr *ip_hdr(const struct sk_buff *skb)
 432 {
 433         return skb->nh.iph;
 434 }
 435
 436 static inline struct ipv6hdr *ipv6_hdr(const struct sk_buff *skb)
 437 {
 438         return skb->nh.ipv6h;
 439 }
 440
 441 static inline struct tcphdr *tcp_hdr(const struct sk_buff *skb)
 442 {
 443         return skb->h.th;
 444 }
 445 #endif
 446
 447 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
 448 #define DECLARE_NAPI_STRUCT
 449 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
 450         dev->poll = pollfn; \
 451         dev->weight = q;
 452 #define JME_NAPI_HOLDER(holder) struct net_device *holder
 453 #define JME_NAPI_WEIGHT(w) int *w
 454 #define JME_NAPI_WEIGHT_VAL(w) *w
 455 #define JME_NAPI_WEIGHT_SET(w, r) *w = r
 456 #define DECLARE_NETDEV struct net_device *netdev = jme->dev;
 457 #define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev)
 458 #define JME_NAPI_ENABLE(priv) netif_poll_enable(priv->dev);
 459 #define JME_NAPI_DISABLE(priv) netif_poll_disable(priv->dev);
 460 #define JME_RX_SCHEDULE_PREP(priv) \
 461         netif_rx_schedule_prep(priv->dev)
 462 #define JME_RX_SCHEDULE(priv) \
 463         __netif_rx_schedule(priv->dev);
 464 #else
 465 #define DECLARE_NAPI_STRUCT struct napi_struct napi;
 466 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
 467         netif_napi_add(dev, napis, pollfn, q);
 468 #define JME_NAPI_HOLDER(holder) struct napi_struct *holder
 469 #define JME_NAPI_WEIGHT(w) int w
 470 #define JME_NAPI_WEIGHT_VAL(w) w
 471 #define JME_NAPI_WEIGHT_SET(w, r)
 472 #define DECLARE_NETDEV
 473 #define JME_RX_COMPLETE(dev, napis) napi_complete(napis)
 474 #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
 475 #define JME_NAPI_DISABLE(priv) \
 476         if (!napi_disable_pending(&priv->napi)) \
 477                 napi_disable(&priv->napi);
 478 #define JME_RX_SCHEDULE_PREP(priv) \
 479         napi_schedule_prep(&priv->napi)
 480 #define JME_RX_SCHEDULE(priv) \
 481         __napi_schedule(&priv->napi);
 482 #endif
 483
 484 /*
 485  * Jmac Adapter Private data
 486  */
 487 struct jme_adapter {
 488         struct pci_dev          *pdev;
 489         struct net_device       *dev;
 490         void __iomem            *regs;
 491         struct mii_if_info      mii_if;
 492         struct jme_ring         rxring[RX_RING_NR];
 493         struct jme_ring         txring[TX_RING_NR];
 494         spinlock_t              phy_lock;
 495         spinlock_t              macaddr_lock;
 496         spinlock_t              rxmcs_lock;
 497         struct tasklet_struct   rxempty_task;
 498         struct tasklet_struct   rxclean_task;
 499         struct tasklet_struct   txclean_task;
 500         struct tasklet_struct   linkch_task;
 501         struct tasklet_struct   pcc_task;
 502         unsigned long           flags;
 503         u32                     reg_txcs;
 504         u32                     reg_txpfc;
 505         u32                     reg_rxcs;
 506         u32                     reg_rxmcs;
 507         u32                     reg_ghc;
 508         u32                     reg_pmcs;
 509         u32                     phylink;
 510         u32                     tx_ring_size;
 511         u32                     tx_ring_mask;
 512         u32                     tx_wake_threshold;
 513         u32                     rx_ring_size;
 514         u32                     rx_ring_mask;
 515         u8                      mrrs;
 516         unsigned int            fpgaver;
 517         unsigned int            chiprev;
 518         u8                      rev;
 519         u32                     msg_enable;
 520         struct ethtool_cmd      old_ecmd;
 521         unsigned int            old_mtu;
 522         struct vlan_group       *vlgrp;
 523         struct dynpcc_info      dpi;
 524         atomic_t                intr_sem;
 525         atomic_t                link_changing;
 526         atomic_t                tx_cleaning;
 527         atomic_t                rx_cleaning;
 528         atomic_t                rx_empty;
 529         int                     (*jme_rx)(struct sk_buff *skb);
 530         int                     (*jme_vlan_rx)(struct sk_buff *skb,
 531                                           struct vlan_group *grp,
 532                                           unsigned short vlan_tag);
 533         DECLARE_NAPI_STRUCT
 534         DECLARE_NET_DEVICE_STATS
 535 };
 536
 537 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
 538 static struct net_device_stats *
 539 jme_get_stats(struct net_device *netdev)
 540 {
 541         struct jme_adapter *jme = netdev_priv(netdev);
 542         return &jme->stats;
 543 }
 544 #endif
 545
 546 enum jme_flags_bits {
 547         JME_FLAG_MSI            = 1,
 548         JME_FLAG_SSET           = 2,
 549         JME_FLAG_TXCSUM         = 3,
 550         JME_FLAG_TSO            = 4,
 551         JME_FLAG_POLL           = 5,
 552         JME_FLAG_SHUTDOWN       = 6,
 553 };
 554
 555 #define TX_TIMEOUT              (5 * HZ)
 556 #define JME_REG_LEN             0x500
 557 #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
 558
 559 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
 560 static inline struct jme_adapter*
 561 jme_napi_priv(struct net_device *holder)
 562 {
 563         struct jme_adapter *jme;
 564         jme = netdev_priv(holder);
 565         return jme;
 566 }
 567 #else
 568 static inline struct jme_adapter*
 569 jme_napi_priv(struct napi_struct *napi)
 570 {
 571         struct jme_adapter *jme;
 572         jme = container_of(napi, struct jme_adapter, napi);
 573         return jme;
 574 }
 575 #endif
 576
 577 /*
 578  * MMaped I/O Resters
 579  */
 580 enum jme_iomap_offsets {
 581         JME_MAC         = 0x0000,
 582         JME_PHY         = 0x0400,
 583         JME_MISC        = 0x0800,
 584         JME_RSS         = 0x0C00,
 585 };
 586
 587 enum jme_iomap_lens {
 588         JME_MAC_LEN     = 0x80,
 589         JME_PHY_LEN     = 0x58,
 590         JME_MISC_LEN    = 0x98,
 591         JME_RSS_LEN     = 0xFF,
 592 };
 593
 594 enum jme_iomap_regs {
 595         JME_TXCS        = JME_MAC | 0x00, /* Transmit Control and Status */
 596         JME_TXDBA_LO    = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
 597         JME_TXDBA_HI    = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
 598         JME_TXQDC       = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
 599         JME_TXNDA       = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
 600         JME_TXMCS       = JME_MAC | 0x14, /* Transmit MAC Control Status */
 601         JME_TXPFC       = JME_MAC | 0x18, /* Transmit Pause Frame Control */
 602         JME_TXTRHD      = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
 603
 604         JME_RXCS        = JME_MAC | 0x20, /* Receive Control and Status */
 605         JME_RXDBA_LO    = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
 606         JME_RXDBA_HI    = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
 607         JME_RXQDC       = JME_MAC | 0x2C, /* Receive Queue Desc Count */
 608         JME_RXNDA       = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
 609         JME_RXMCS       = JME_MAC | 0x34, /* Receive MAC Control Status */
 610         JME_RXUMA_LO    = JME_MAC | 0x38, /* Receive Unicast MAC Address */
 611         JME_RXUMA_HI    = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
 612         JME_RXMCHT_LO   = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
 613         JME_RXMCHT_HI   = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
 614         JME_WFODP       = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
 615         JME_WFOI        = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
 616
 617         JME_SMI         = JME_MAC | 0x50, /* Station Management Interface */
 618         JME_GHC         = JME_MAC | 0x54, /* Global Host Control */
 619         JME_PMCS        = JME_MAC | 0x60, /* Power Management Control/Stat */
 620
 621
 622         JME_PHY_CS      = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
 623         JME_PHY_LINK    = JME_PHY | 0x30, /* PHY Link Status Register */
 624         JME_SMBCSR      = JME_PHY | 0x40, /* SMB Control and Status */
 625         JME_SMBINTF     = JME_PHY | 0x44, /* SMB Interface */
 626
 627
 628         JME_TMCSR       = JME_MISC | 0x00, /* Timer Control/Status Register */
 629         JME_GPREG0      = JME_MISC | 0x08, /* General purpose REG-0 */
 630         JME_GPREG1      = JME_MISC | 0x0C, /* General purpose REG-1 */
 631         JME_IEVE        = JME_MISC | 0x20, /* Interrupt Event Status */
 632         JME_IREQ        = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
 633         JME_IENS        = JME_MISC | 0x28, /* Intr Enable - Setting Port */
 634         JME_IENC        = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
 635         JME_PCCRX0      = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
 636         JME_PCCTX       = JME_MISC | 0x40, /* PCC Control for TX Queues */
 637         JME_CHIPMODE    = JME_MISC | 0x44, /* Identify FPGA Version */
 638         JME_SHBA_HI     = JME_MISC | 0x48, /* Shadow Register Base HI */
 639         JME_SHBA_LO     = JME_MISC | 0x4C, /* Shadow Register Base LO */
 640         JME_TIMER1      = JME_MISC | 0x70, /* Timer1 */
 641         JME_TIMER2      = JME_MISC | 0x74, /* Timer2 */
 642         JME_APMC        = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
 643         JME_PCCSRX0     = JME_MISC | 0x80, /* PCC Status of RX0 */
 644 };
 645
 646 /*
 647  * TX Control/Status Bits
 648  */
 649 enum jme_txcs_bits {
 650         TXCS_QUEUE7S    = 0x00008000,
 651         TXCS_QUEUE6S    = 0x00004000,
 652         TXCS_QUEUE5S    = 0x00002000,
 653         TXCS_QUEUE4S    = 0x00001000,
 654         TXCS_QUEUE3S    = 0x00000800,
 655         TXCS_QUEUE2S    = 0x00000400,
 656         TXCS_QUEUE1S    = 0x00000200,
 657         TXCS_QUEUE0S    = 0x00000100,
 658         TXCS_FIFOTH     = 0x000000C0,
 659         TXCS_DMASIZE    = 0x00000030,
 660         TXCS_BURST      = 0x00000004,
 661         TXCS_ENABLE     = 0x00000001,
 662 };
 663
 664 enum jme_txcs_value {
 665         TXCS_FIFOTH_16QW        = 0x000000C0,
 666         TXCS_FIFOTH_12QW        = 0x00000080,
 667         TXCS_FIFOTH_8QW         = 0x00000040,
 668         TXCS_FIFOTH_4QW         = 0x00000000,
 669
 670         TXCS_DMASIZE_64B        = 0x00000000,
 671         TXCS_DMASIZE_128B       = 0x00000010,
 672         TXCS_DMASIZE_256B       = 0x00000020,
 673         TXCS_DMASIZE_512B       = 0x00000030,
 674
 675         TXCS_SELECT_QUEUE0      = 0x00000000,
 676         TXCS_SELECT_QUEUE1      = 0x00010000,
 677         TXCS_SELECT_QUEUE2      = 0x00020000,
 678         TXCS_SELECT_QUEUE3      = 0x00030000,
 679         TXCS_SELECT_QUEUE4      = 0x00040000,
 680         TXCS_SELECT_QUEUE5      = 0x00050000,
 681         TXCS_SELECT_QUEUE6      = 0x00060000,
 682         TXCS_SELECT_QUEUE7      = 0x00070000,
 683
 684         TXCS_DEFAULT            = TXCS_FIFOTH_4QW |
 685                                   TXCS_BURST,
 686 };
 687
 688 #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
 689
 690 /*
 691  * TX MAC Control/Status Bits
 692  */
 693 enum jme_txmcs_bit_masks {
 694         TXMCS_IFG2              = 0xC0000000,
 695         TXMCS_IFG1              = 0x30000000,
 696         TXMCS_TTHOLD            = 0x00000300,
 697         TXMCS_FBURST            = 0x00000080,
 698         TXMCS_CARRIEREXT        = 0x00000040,
 699         TXMCS_DEFER             = 0x00000020,
 700         TXMCS_BACKOFF           = 0x00000010,
 701         TXMCS_CARRIERSENSE      = 0x00000008,
 702         TXMCS_COLLISION         = 0x00000004,
 703         TXMCS_CRC               = 0x00000002,
 704         TXMCS_PADDING           = 0x00000001,
 705 };
 706
 707 enum jme_txmcs_values {
 708         TXMCS_IFG2_6_4          = 0x00000000,
 709         TXMCS_IFG2_8_5          = 0x40000000,
 710         TXMCS_IFG2_10_6         = 0x80000000,
 711         TXMCS_IFG2_12_7         = 0xC0000000,
 712
 713         TXMCS_IFG1_8_4          = 0x00000000,
 714         TXMCS_IFG1_12_6         = 0x10000000,
 715         TXMCS_IFG1_16_8         = 0x20000000,
 716         TXMCS_IFG1_20_10        = 0x30000000,
 717
 718         TXMCS_TTHOLD_1_8        = 0x00000000,
 719         TXMCS_TTHOLD_1_4        = 0x00000100,
 720         TXMCS_TTHOLD_1_2        = 0x00000200,
 721         TXMCS_TTHOLD_FULL       = 0x00000300,
 722
 723         TXMCS_DEFAULT           = TXMCS_IFG2_8_5 |
 724                                   TXMCS_IFG1_16_8 |
 725                                   TXMCS_TTHOLD_FULL |
 726                                   TXMCS_DEFER |
 727                                   TXMCS_CRC |
 728                                   TXMCS_PADDING,
 729 };
 730
 731 enum jme_txpfc_bits_masks {
 732         TXPFC_VLAN_TAG          = 0xFFFF0000,
 733         TXPFC_VLAN_EN           = 0x00008000,
 734         TXPFC_PF_EN             = 0x00000001,
 735 };
 736
 737 enum jme_txtrhd_bits_masks {
 738         TXTRHD_TXPEN            = 0x80000000,
 739         TXTRHD_TXP              = 0x7FFFFF00,
 740         TXTRHD_TXREN            = 0x00000080,
 741         TXTRHD_TXRL             = 0x0000007F,
 742 };
 743
 744 enum jme_txtrhd_shifts {
 745         TXTRHD_TXP_SHIFT        = 8,
 746         TXTRHD_TXRL_SHIFT       = 0,
 747 };
 748
 749 /*
 750  * RX Control/Status Bits
 751  */
 752 enum jme_rxcs_bit_masks {
 753         /* FIFO full threshold for transmitting Tx Pause Packet */
 754         RXCS_FIFOTHTP   = 0x30000000,
 755         /* FIFO threshold for processing next packet */
 756         RXCS_FIFOTHNP   = 0x0C000000,
 757         RXCS_DMAREQSZ   = 0x03000000, /* DMA Request Size */
 758         RXCS_QUEUESEL   = 0x00030000, /* Queue selection */
 759         RXCS_RETRYGAP   = 0x0000F000, /* RX Desc full retry gap */
 760         RXCS_RETRYCNT   = 0x00000F00, /* RX Desc full retry counter */
 761         RXCS_WAKEUP     = 0x00000040, /* Enable receive wakeup packet */
 762         RXCS_MAGIC      = 0x00000020, /* Enable receive magic packet */
 763         RXCS_SHORT      = 0x00000010, /* Enable receive short packet */
 764         RXCS_ABORT      = 0x00000008, /* Enable receive errorr packet */
 765         RXCS_QST        = 0x00000004, /* Receive queue start */
 766         RXCS_SUSPEND    = 0x00000002,
 767         RXCS_ENABLE     = 0x00000001,
 768 };
 769
 770 enum jme_rxcs_values {
 771         RXCS_FIFOTHTP_16T       = 0x00000000,
 772         RXCS_FIFOTHTP_32T       = 0x10000000,
 773         RXCS_FIFOTHTP_64T       = 0x20000000,
 774         RXCS_FIFOTHTP_128T      = 0x30000000,
 775
 776         RXCS_FIFOTHNP_16QW      = 0x00000000,
 777         RXCS_FIFOTHNP_32QW      = 0x04000000,
 778         RXCS_FIFOTHNP_64QW      = 0x08000000,
 779         RXCS_FIFOTHNP_128QW     = 0x0C000000,
 780
 781         RXCS_DMAREQSZ_16B       = 0x00000000,
 782         RXCS_DMAREQSZ_32B       = 0x01000000,
 783         RXCS_DMAREQSZ_64B       = 0x02000000,
 784         RXCS_DMAREQSZ_128B      = 0x03000000,
 785
 786         RXCS_QUEUESEL_Q0        = 0x00000000,
 787         RXCS_QUEUESEL_Q1        = 0x00010000,
 788         RXCS_QUEUESEL_Q2        = 0x00020000,
 789         RXCS_QUEUESEL_Q3        = 0x00030000,
 790
 791         RXCS_RETRYGAP_256ns     = 0x00000000,
 792         RXCS_RETRYGAP_512ns     = 0x00001000,
 793         RXCS_RETRYGAP_1024ns    = 0x00002000,
 794         RXCS_RETRYGAP_2048ns    = 0x00003000,
 795         RXCS_RETRYGAP_4096ns    = 0x00004000,
 796         RXCS_RETRYGAP_8192ns    = 0x00005000,
 797         RXCS_RETRYGAP_16384ns   = 0x00006000,
 798         RXCS_RETRYGAP_32768ns   = 0x00007000,
 799
 800         RXCS_RETRYCNT_0         = 0x00000000,
 801         RXCS_RETRYCNT_4         = 0x00000100,
 802         RXCS_RETRYCNT_8         = 0x00000200,
 803         RXCS_RETRYCNT_12        = 0x00000300,
 804         RXCS_RETRYCNT_16        = 0x00000400,
 805         RXCS_RETRYCNT_20        = 0x00000500,
 806         RXCS_RETRYCNT_24        = 0x00000600,
 807         RXCS_RETRYCNT_28        = 0x00000700,
 808         RXCS_RETRYCNT_32        = 0x00000800,
 809         RXCS_RETRYCNT_36        = 0x00000900,
 810         RXCS_RETRYCNT_40        = 0x00000A00,
 811         RXCS_RETRYCNT_44        = 0x00000B00,
 812         RXCS_RETRYCNT_48        = 0x00000C00,
 813         RXCS_RETRYCNT_52        = 0x00000D00,
 814         RXCS_RETRYCNT_56        = 0x00000E00,
 815         RXCS_RETRYCNT_60        = 0x00000F00,
 816
 817         RXCS_DEFAULT            = RXCS_FIFOTHTP_128T |
 818                                   RXCS_FIFOTHNP_128QW |
 819                                   RXCS_DMAREQSZ_128B |
 820                                   RXCS_RETRYGAP_256ns |
 821                                   RXCS_RETRYCNT_32,
 822 };
 823
 824 #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
 825
 826 /*
 827  * RX MAC Control/Status Bits
 828  */
 829 enum jme_rxmcs_bits {
 830         RXMCS_ALLFRAME          = 0x00000800,
 831         RXMCS_BRDFRAME          = 0x00000400,
 832         RXMCS_MULFRAME          = 0x00000200,
 833         RXMCS_UNIFRAME          = 0x00000100,
 834         RXMCS_ALLMULFRAME       = 0x00000080,
 835         RXMCS_MULFILTERED       = 0x00000040,
 836         RXMCS_RXCOLLDEC         = 0x00000020,
 837         RXMCS_FLOWCTRL          = 0x00000008,
 838         RXMCS_VTAGRM            = 0x00000004,
 839         RXMCS_PREPAD            = 0x00000002,
 840         RXMCS_CHECKSUM          = 0x00000001,
 841
 842         RXMCS_DEFAULT           = RXMCS_VTAGRM |
 843                                   RXMCS_PREPAD |
 844                                   RXMCS_FLOWCTRL |
 845                                   RXMCS_CHECKSUM,
 846 };
 847
 848 /*
 849  * Wakeup Frame setup interface registers
 850  */
 851 #define WAKEUP_FRAME_NR 8
 852 #define WAKEUP_FRAME_MASK_DWNR  4
 853
 854 enum jme_wfoi_bit_masks {
 855         WFOI_MASK_SEL           = 0x00000070,
 856         WFOI_CRC_SEL            = 0x00000008,
 857         WFOI_FRAME_SEL          = 0x00000007,
 858 };
 859
 860 enum jme_wfoi_shifts {
 861         WFOI_MASK_SHIFT         = 4,
 862 };
 863
 864 /*
 865  * SMI Related definitions
 866  */
 867 enum jme_smi_bit_mask {
 868         SMI_DATA_MASK           = 0xFFFF0000,
 869         SMI_REG_ADDR_MASK       = 0x0000F800,
 870         SMI_PHY_ADDR_MASK       = 0x000007C0,
 871         SMI_OP_WRITE            = 0x00000020,
 872         /* Set to 1, after req done it'll be cleared to 0 */
 873         SMI_OP_REQ              = 0x00000010,
 874         SMI_OP_MDIO             = 0x00000008, /* Software assess In/Out */
 875         SMI_OP_MDOE             = 0x00000004, /* Software Output Enable */
 876         SMI_OP_MDC              = 0x00000002, /* Software CLK Control */
 877         SMI_OP_MDEN             = 0x00000001, /* Software access Enable */
 878 };
 879
 880 enum jme_smi_bit_shift {
 881         SMI_DATA_SHIFT          = 16,
 882         SMI_REG_ADDR_SHIFT      = 11,
 883         SMI_PHY_ADDR_SHIFT      = 6,
 884 };
 885
 886 static inline u32 smi_reg_addr(int x)
 887 {
 888         return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
 889 }
 890
 891 static inline u32 smi_phy_addr(int x)
 892 {
 893         return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
 894 }
 895
 896 #define JME_PHY_TIMEOUT 100 /* 100 msec */
 897 #define JME_PHY_REG_NR 32
 898
 899 /*
 900  * Global Host Control
 901  */
 902 enum jme_ghc_bit_mask {
 903         GHC_SWRST               = 0x40000000,
 904         GHC_DPX                 = 0x00000040,
 905         GHC_SPEED               = 0x00000030,
 906         GHC_LINK_POLL           = 0x00000001,
 907 };
 908
 909 enum jme_ghc_speed_val {
 910         GHC_SPEED_10M           = 0x00000010,
 911         GHC_SPEED_100M          = 0x00000020,
 912         GHC_SPEED_1000M         = 0x00000030,
 913 };
 914
 915 enum jme_ghc_to_clk {
 916         GHC_TO_CLK_OFF          = 0x00000000,
 917         GHC_TO_CLK_GPHY         = 0x00400000,
 918         GHC_TO_CLK_PCIE         = 0x00800000,
 919         GHC_TO_CLK_INVALID      = 0x00C00000,
 920 };
 921
 922 enum jme_ghc_txmac_clk {
 923         GHC_TXMAC_CLK_OFF       = 0x00000000,
 924         GHC_TXMAC_CLK_GPHY      = 0x00100000,
 925         GHC_TXMAC_CLK_PCIE      = 0x00200000,
 926         GHC_TXMAC_CLK_INVALID   = 0x00300000,
 927 };
 928
 929 /*
 930  * Power management control and status register
 931  */
 932 enum jme_pmcs_bit_masks {
 933         PMCS_WF7DET     = 0x80000000,
 934         PMCS_WF6DET     = 0x40000000,
 935         PMCS_WF5DET     = 0x20000000,
 936         PMCS_WF4DET     = 0x10000000,
 937         PMCS_WF3DET     = 0x08000000,
 938         PMCS_WF2DET     = 0x04000000,
 939         PMCS_WF1DET     = 0x02000000,
 940         PMCS_WF0DET     = 0x01000000,
 941         PMCS_LFDET      = 0x00040000,
 942         PMCS_LRDET      = 0x00020000,
 943         PMCS_MFDET      = 0x00010000,
 944         PMCS_WF7EN      = 0x00008000,
 945         PMCS_WF6EN      = 0x00004000,
 946         PMCS_WF5EN      = 0x00002000,
 947         PMCS_WF4EN      = 0x00001000,
 948         PMCS_WF3EN      = 0x00000800,
 949         PMCS_WF2EN      = 0x00000400,
 950         PMCS_WF1EN      = 0x00000200,
 951         PMCS_WF0EN      = 0x00000100,
 952         PMCS_LFEN       = 0x00000004,
 953         PMCS_LREN       = 0x00000002,
 954         PMCS_MFEN       = 0x00000001,
 955 };
 956
 957 /*
 958  * Giga PHY Status Registers
 959  */
 960 enum jme_phy_link_bit_mask {
 961         PHY_LINK_SPEED_MASK             = 0x0000C000,
 962         PHY_LINK_DUPLEX                 = 0x00002000,
 963         PHY_LINK_SPEEDDPU_RESOLVED      = 0x00000800,
 964         PHY_LINK_UP                     = 0x00000400,
 965         PHY_LINK_AUTONEG_COMPLETE       = 0x00000200,
 966         PHY_LINK_MDI_STAT               = 0x00000040,
 967 };
 968
 969 enum jme_phy_link_speed_val {
 970         PHY_LINK_SPEED_10M              = 0x00000000,
 971         PHY_LINK_SPEED_100M             = 0x00004000,
 972         PHY_LINK_SPEED_1000M            = 0x00008000,
 973 };
 974
 975 #define JME_SPDRSV_TIMEOUT      500     /* 500 us */
 976
 977 /*
 978  * SMB Control and Status
 979  */
 980 enum jme_smbcsr_bit_mask {
 981         SMBCSR_CNACK    = 0x00020000,
 982         SMBCSR_RELOAD   = 0x00010000,
 983         SMBCSR_EEPROMD  = 0x00000020,
 984         SMBCSR_INITDONE = 0x00000010,
 985         SMBCSR_BUSY     = 0x0000000F,
 986 };
 987
 988 enum jme_smbintf_bit_mask {
 989         SMBINTF_HWDATR  = 0xFF000000,
 990         SMBINTF_HWDATW  = 0x00FF0000,
 991         SMBINTF_HWADDR  = 0x0000FF00,
 992         SMBINTF_HWRWN   = 0x00000020,
 993         SMBINTF_HWCMD   = 0x00000010,
 994         SMBINTF_FASTM   = 0x00000008,
 995         SMBINTF_GPIOSCL = 0x00000004,
 996         SMBINTF_GPIOSDA = 0x00000002,
 997         SMBINTF_GPIOEN  = 0x00000001,
 998 };
 999
1000 enum jme_smbintf_vals {
1001         SMBINTF_HWRWN_READ      = 0x00000020,
1002         SMBINTF_HWRWN_WRITE     = 0x00000000,
1003 };
1004
1005 enum jme_smbintf_shifts {
1006         SMBINTF_HWDATR_SHIFT    = 24,
1007         SMBINTF_HWDATW_SHIFT    = 16,
1008         SMBINTF_HWADDR_SHIFT    = 8,
1009 };
1010
1011 #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
1012 #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
1013 #define JME_SMB_LEN 256
1014 #define JME_EEPROM_MAGIC 0x250
1015
1016 /*
1017  * Timer Control/Status Register
1018  */
1019 enum jme_tmcsr_bit_masks {
1020         TMCSR_SWIT      = 0x80000000,
1021         TMCSR_EN        = 0x01000000,
1022         TMCSR_CNT       = 0x00FFFFFF,
1023 };
1024
1025 /*
1026  * General Purpose REG-0
1027  */
1028 enum jme_gpreg0_masks {
1029         GPREG0_DISSH            = 0xFF000000,
1030         GPREG0_PCIRLMT          = 0x00300000,
1031         GPREG0_PCCNOMUTCLR      = 0x00040000,
1032         GPREG0_LNKINTPOLL       = 0x00001000,
1033         GPREG0_PCCTMR           = 0x00000300,
1034         GPREG0_PHYADDR          = 0x0000001F,
1035 };
1036
1037 enum jme_gpreg0_vals {
1038         GPREG0_DISSH_DW7        = 0x80000000,
1039         GPREG0_DISSH_DW6        = 0x40000000,
1040         GPREG0_DISSH_DW5        = 0x20000000,
1041         GPREG0_DISSH_DW4        = 0x10000000,
1042         GPREG0_DISSH_DW3        = 0x08000000,
1043         GPREG0_DISSH_DW2        = 0x04000000,
1044         GPREG0_DISSH_DW1        = 0x02000000,
1045         GPREG0_DISSH_DW0        = 0x01000000,
1046         GPREG0_DISSH_ALL        = 0xFF000000,
1047
1048         GPREG0_PCIRLMT_8        = 0x00000000,
1049         GPREG0_PCIRLMT_6        = 0x00100000,
1050         GPREG0_PCIRLMT_5        = 0x00200000,
1051         GPREG0_PCIRLMT_4        = 0x00300000,
1052
1053         GPREG0_PCCTMR_16ns      = 0x00000000,
1054         GPREG0_PCCTMR_256ns     = 0x00000100,
1055         GPREG0_PCCTMR_1us       = 0x00000200,
1056         GPREG0_PCCTMR_1ms       = 0x00000300,
1057
1058         GPREG0_PHYADDR_1        = 0x00000001,
1059
1060         GPREG0_DEFAULT          = GPREG0_PCIRLMT_4 |
1061                                   GPREG0_PCCTMR_1us |
1062                                   GPREG0_PHYADDR_1,
1063 };
1064
1065 /*
1066  * General Purpose REG-1
1067  * Note: All theses bits defined here are for
1068  *       Chip mode revision 0x11 only
1069  */
1070 enum jme_gpreg1_masks {
1071         GPREG1_INTRDELAYUNIT    = 0x00000018,
1072         GPREG1_INTRDELAYENABLE  = 0x00000007,
1073 };
1074
1075 enum jme_gpreg1_vals {
1076         GPREG1_RSSPATCH         = 0x00000040,
1077         GPREG1_HALFMODEPATCH    = 0x00000020,
1078
1079         GPREG1_INTDLYUNIT_16NS  = 0x00000000,
1080         GPREG1_INTDLYUNIT_256NS = 0x00000008,
1081         GPREG1_INTDLYUNIT_1US   = 0x00000010,
1082         GPREG1_INTDLYUNIT_16US  = 0x00000018,
1083
1084         GPREG1_INTDLYEN_1U      = 0x00000001,
1085         GPREG1_INTDLYEN_2U      = 0x00000002,
1086         GPREG1_INTDLYEN_3U      = 0x00000003,
1087         GPREG1_INTDLYEN_4U      = 0x00000004,
1088         GPREG1_INTDLYEN_5U      = 0x00000005,
1089         GPREG1_INTDLYEN_6U      = 0x00000006,
1090         GPREG1_INTDLYEN_7U      = 0x00000007,
1091
1092         GPREG1_DEFAULT          = 0x00000000,
1093 };
1094
1095 /*
1096  * Interrupt Status Bits
1097  */
1098 enum jme_interrupt_bits {
1099         INTR_SWINTR     = 0x80000000,
1100         INTR_TMINTR     = 0x40000000,
1101         INTR_LINKCH     = 0x20000000,
1102         INTR_PAUSERCV   = 0x10000000,
1103         INTR_MAGICRCV   = 0x08000000,
1104         INTR_WAKERCV    = 0x04000000,
1105         INTR_PCCRX0TO   = 0x02000000,
1106         INTR_PCCRX1TO   = 0x01000000,
1107         INTR_PCCRX2TO   = 0x00800000,
1108         INTR_PCCRX3TO   = 0x00400000,
1109         INTR_PCCTXTO    = 0x00200000,
1110         INTR_PCCRX0     = 0x00100000,
1111         INTR_PCCRX1     = 0x00080000,
1112         INTR_PCCRX2     = 0x00040000,
1113         INTR_PCCRX3     = 0x00020000,
1114         INTR_PCCTX      = 0x00010000,
1115         INTR_RX3EMP     = 0x00008000,
1116         INTR_RX2EMP     = 0x00004000,
1117         INTR_RX1EMP     = 0x00002000,
1118         INTR_RX0EMP     = 0x00001000,
1119         INTR_RX3        = 0x00000800,
1120         INTR_RX2        = 0x00000400,
1121         INTR_RX1        = 0x00000200,
1122         INTR_RX0        = 0x00000100,
1123         INTR_TX7        = 0x00000080,
1124         INTR_TX6        = 0x00000040,
1125         INTR_TX5        = 0x00000020,
1126         INTR_TX4        = 0x00000010,
1127         INTR_TX3        = 0x00000008,
1128         INTR_TX2        = 0x00000004,
1129         INTR_TX1        = 0x00000002,
1130         INTR_TX0        = 0x00000001,
1131 };
1132
1133 static const u32 INTR_ENABLE = INTR_SWINTR |
1134                                  INTR_TMINTR |
1135                                  INTR_LINKCH |
1136                                  INTR_PCCRX0TO |
1137                                  INTR_PCCRX0 |
1138                                  INTR_PCCTXTO |
1139                                  INTR_PCCTX |
1140                                  INTR_RX0EMP;
1141
1142 /*
1143  * PCC Control Registers
1144  */
1145 enum jme_pccrx_masks {
1146         PCCRXTO_MASK    = 0xFFFF0000,
1147         PCCRX_MASK      = 0x0000FF00,
1148 };
1149
1150 enum jme_pcctx_masks {
1151         PCCTXTO_MASK    = 0xFFFF0000,
1152         PCCTX_MASK      = 0x0000FF00,
1153         PCCTX_QS_MASK   = 0x000000FF,
1154 };
1155
1156 enum jme_pccrx_shifts {
1157         PCCRXTO_SHIFT   = 16,
1158         PCCRX_SHIFT     = 8,
1159 };
1160
1161 enum jme_pcctx_shifts {
1162         PCCTXTO_SHIFT   = 16,
1163         PCCTX_SHIFT     = 8,
1164 };
1165
1166 enum jme_pcctx_bits {
1167         PCCTXQ0_EN      = 0x00000001,
1168         PCCTXQ1_EN      = 0x00000002,
1169         PCCTXQ2_EN      = 0x00000004,
1170         PCCTXQ3_EN      = 0x00000008,
1171         PCCTXQ4_EN      = 0x00000010,
1172         PCCTXQ5_EN      = 0x00000020,
1173         PCCTXQ6_EN      = 0x00000040,
1174         PCCTXQ7_EN      = 0x00000080,
1175 };
1176
1177 /*
1178  * Chip Mode Register
1179  */
1180 enum jme_chipmode_bit_masks {
1181         CM_FPGAVER_MASK         = 0xFFFF0000,
1182         CM_CHIPREV_MASK         = 0x0000FF00,
1183         CM_CHIPMODE_MASK        = 0x0000000F,
1184 };
1185
1186 enum jme_chipmode_shifts {
1187         CM_FPGAVER_SHIFT        = 16,
1188         CM_CHIPREV_SHIFT        = 8,
1189 };
1190
1191 /*
1192  * Aggressive Power Mode Control
1193  */
1194 enum jme_apmc_bits {
1195         JME_APMC_PCIE_SD_EN     = 0x40000000,
1196         JME_APMC_PSEUDO_HP_EN   = 0x20000000,
1197         JME_APMC_EPIEN          = 0x04000000,
1198         JME_APMC_EPIEN_CTRL     = 0x03000000,
1199 };
1200
1201 enum jme_apmc_values {
1202         JME_APMC_EPIEN_CTRL_EN  = 0x02000000,
1203         JME_APMC_EPIEN_CTRL_DIS = 0x01000000,
1204 };
1205
1206 #define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000)
1207
1208 #ifdef REG_DEBUG
1209 static char *MAC_REG_NAME[] = {
1210         "JME_TXCS",      "JME_TXDBA_LO",  "JME_TXDBA_HI", "JME_TXQDC",
1211         "JME_TXNDA",     "JME_TXMCS",     "JME_TXPFC",    "JME_TXTRHD",
1212         "JME_RXCS",      "JME_RXDBA_LO",  "JME_RXDBA_HI", "JME_RXQDC",
1213         "JME_RXNDA",     "JME_RXMCS",     "JME_RXUMA_LO", "JME_RXUMA_HI",
1214         "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP",    "JME_WFOI",
1215         "JME_SMI",       "JME_GHC",       "UNKNOWN",      "UNKNOWN",
1216         "JME_PMCS"};
1217
1218 static char *PE_REG_NAME[] = {
1219         "UNKNOWN",      "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1220         "UNKNOWN",      "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1221         "UNKNOWN",      "UNKNOWN",     "JME_PHY_CS", "UNKNOWN",
1222         "JME_PHY_LINK", "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1223         "JME_SMBCSR",   "JME_SMBINTF"};
1224
1225 static char *MISC_REG_NAME[] = {
1226         "JME_TMCSR",  "JME_GPIO",     "JME_GPREG0",  "JME_GPREG1",
1227         "JME_IEVE",   "JME_IREQ",     "JME_IENS",    "JME_IENC",
1228         "JME_PCCRX0", "JME_PCCRX1",   "JME_PCCRX2",  "JME_PCCRX3",
1229         "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO",
1230         "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1231         "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1232         "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1233         "JME_TIMER1", "JME_TIMER2",   "UNKNOWN",     "JME_APMC",
1234         "JME_PCCSRX0"};
1235
1236 static inline void reg_dbg(const struct jme_adapter *jme,
1237                 const char *msg, u32 val, u32 reg)
1238 {
1239         const char *regname;
1240         switch (reg & 0xF00) {
1241         case 0x000:
1242                 regname = MAC_REG_NAME[(reg & 0xFF) >> 2];
1243                 break;
1244         case 0x400:
1245                 regname = PE_REG_NAME[(reg & 0xFF) >> 2];
1246                 break;
1247         case 0x800:
1248                 regname = MISC_REG_NAME[(reg & 0xFF) >> 2];
1249                 break;
1250         default:
1251                 regname = PE_REG_NAME[0];
1252         }
1253         printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name,
1254                         msg, val, regname);
1255 }
1256 #else
1257 static inline void reg_dbg(const struct jme_adapter *jme,
1258                 const char *msg, u32 val, u32 reg) {}
1259 #endif
1260
1261 /*
1262  * Read/Write MMaped I/O Registers
1263  */
1264 static inline u32 jread32(struct jme_adapter *jme, u32 reg)
1265 {
1266         return readl(jme->regs + reg);
1267 }
1268
1269 static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val)
1270 {
1271         reg_dbg(jme, "REG WRITE", val, reg);
1272         writel(val, jme->regs + reg);
1273         reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1274 }
1275
1276 static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val)
1277 {
1278         /*
1279          * Read after write should cause flush
1280          */
1281         reg_dbg(jme, "REG WRITE FLUSH", val, reg);
1282         writel(val, jme->regs + reg);
1283         readl(jme->regs + reg);
1284         reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1285 }
1286
1287 /*
1288  * PHY Regs
1289  */
1290 enum jme_phy_reg17_bit_masks {
1291         PREG17_SPEED            = 0xC000,
1292         PREG17_DUPLEX           = 0x2000,
1293         PREG17_SPDRSV           = 0x0800,
1294         PREG17_LNKUP            = 0x0400,
1295         PREG17_MDI              = 0x0040,
1296 };
1297
1298 enum jme_phy_reg17_vals {
1299         PREG17_SPEED_10M        = 0x0000,
1300         PREG17_SPEED_100M       = 0x4000,
1301         PREG17_SPEED_1000M      = 0x8000,
1302 };
1303
1304 #define BMSR_ANCOMP               0x0020
1305
1306 /*
1307  * Workaround
1308  */
1309 static inline int is_buggy250(unsigned short device, unsigned int chiprev)
1310 {
1311         return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
1312 }
1313
1314 /*
1315  * Function prototypes
1316  */
1317 static int jme_set_settings(struct net_device *netdev,
1318                                 struct ethtool_cmd *ecmd);
1319 static void jme_set_multi(struct net_device *netdev);
1320
1321 #endif
1322