jme: Safer MAC processor reset sequence
[jme.git] / jme.h
1 /*
2  * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3  *
4  * Copyright 2008 JMicron Technology Corporation
5  * http://www.jmicron.com/
6  * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
7  *
8  * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation; either version 2 of the License.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22  *
23  */
24
25 #ifndef __JME_H_INCLUDED__
26 #define __JME_H_INCLUDED__
27
28 #define DRV_NAME        "jme"
29 #define DRV_VERSION     "1.0.7-jmmod"
30 #define PFX             DRV_NAME ": "
31
32 #define PCI_DEVICE_ID_JMICRON_JMC250    0x0250
33 #define PCI_DEVICE_ID_JMICRON_JMC260    0x0260
34
35 /*
36  * Message related definitions
37  */
38 #define JME_DEF_MSG_ENABLE \
39         (NETIF_MSG_PROBE | \
40         NETIF_MSG_LINK | \
41         NETIF_MSG_RX_ERR | \
42         NETIF_MSG_TX_ERR | \
43         NETIF_MSG_HW)
44
45 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
46 #define pr_err(fmt, arg...) \
47         printk(KERN_ERR fmt, ##arg)
48 #endif
49 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
50 #define netdev_err(netdev, fmt, arg...) \
51         pr_err(fmt, ##arg)
52 #endif
53
54 #ifdef TX_DEBUG
55 #define tx_dbg(priv, fmt, args...)                                      \
56         printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args)
57 #else
58 #define tx_dbg(priv, fmt, args...)                                      \
59 do {                                                                    \
60         if (0)                                                          \
61                 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args); \
62 } while (0)
63 #endif
64
65 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
66 #define jme_msg(msglvl, type, priv, fmt, args...) \
67         if (netif_msg_##type(priv)) \
68                 printk(msglvl "%s: " fmt, (priv)->dev->name, ## args)
69
70 #define msg_probe(priv, fmt, args...) \
71         jme_msg(KERN_INFO, probe, priv, fmt, ## args)
72
73 #define msg_link(priv, fmt, args...) \
74         jme_msg(KERN_INFO, link, priv, fmt, ## args)
75
76 #define msg_intr(priv, fmt, args...) \
77         jme_msg(KERN_INFO, intr, priv, fmt, ## args)
78
79 #define msg_rx_err(priv, fmt, args...) \
80         jme_msg(KERN_ERR, rx_err, priv, fmt, ## args)
81
82 #define msg_rx_status(priv, fmt, args...) \
83         jme_msg(KERN_INFO, rx_status, priv, fmt, ## args)
84
85 #define msg_tx_err(priv, fmt, args...) \
86         jme_msg(KERN_ERR, tx_err, priv, fmt, ## args)
87
88 #define msg_tx_done(priv, fmt, args...) \
89         jme_msg(KERN_INFO, tx_done, priv, fmt, ## args)
90
91 #define msg_tx_queued(priv, fmt, args...) \
92         jme_msg(KERN_INFO, tx_queued, priv, fmt, ## args)
93
94 #define msg_hw(priv, fmt, args...) \
95         jme_msg(KERN_ERR, hw, priv, fmt, ## args)
96
97 #define netif_info(priv, type, dev, fmt, args...) \
98         msg_ ## type(priv, fmt, ## args)
99 #define netif_err(priv, type, dev, fmt, args...) \
100         msg_ ## type(priv, fmt, ## args)
101 #endif
102
103 #ifndef NETIF_F_TSO6
104 #define NETIF_F_TSO6 0
105 #endif
106 #ifndef NETIF_F_IPV6_CSUM
107 #define NETIF_F_IPV6_CSUM 0
108 #endif
109
110 /*
111  * Extra PCI Configuration space interface
112  */
113 #define PCI_DCSR_MRRS           0x59
114 #define PCI_DCSR_MRRS_MASK      0x70
115
116 enum pci_dcsr_mrrs_vals {
117         MRRS_128B       = 0x00,
118         MRRS_256B       = 0x10,
119         MRRS_512B       = 0x20,
120         MRRS_1024B      = 0x30,
121         MRRS_2048B      = 0x40,
122         MRRS_4096B      = 0x50,
123 };
124
125 #define PCI_SPI                 0xB0
126
127 enum pci_spi_bits {
128         SPI_EN          = 0x10,
129         SPI_MISO        = 0x08,
130         SPI_MOSI        = 0x04,
131         SPI_SCLK        = 0x02,
132         SPI_CS          = 0x01,
133 };
134
135 struct jme_spi_op {
136         void __user *uwbuf;
137         void __user *urbuf;
138         __u8    wn;     /* Number of write actions */
139         __u8    rn;     /* Number of read actions */
140         __u8    bitn;   /* Number of bits per action */
141         __u8    spd;    /* The maxim acceptable speed of controller, in MHz.*/
142         __u8    mode;   /* CPOL, CPHA, and Duplex mode of SPI */
143
144         /* Internal use only */
145         u8      *kwbuf;
146         u8      *krbuf;
147         u8      sr;
148         u16     halfclk; /* Half of clock cycle calculated from spd, in ns */
149 };
150
151 enum jme_spi_op_bits {
152         SPI_MODE_CPHA   = 0x01,
153         SPI_MODE_CPOL   = 0x02,
154         SPI_MODE_DUP    = 0x80,
155 };
156
157 #define HALF_US 500     /* 500 ns */
158 #define JMESPIIOCTL     SIOCDEVPRIVATE
159
160 #define PCI_PRIV_PE1            0xE4
161
162 enum pci_priv_pe1_bit_masks {
163         PE1_ASPMSUPRT   = 0x00000003, /*
164                                        * RW:
165                                        * Aspm_support[1:0]
166                                        * (R/W Port of 5C[11:10])
167                                        */
168         PE1_MULTIFUN    = 0x00000004, /* RW: Multi_fun_bit */
169         PE1_RDYDMA      = 0x00000008, /* RO: ~link.rdy_for_dma */
170         PE1_ASPMOPTL    = 0x00000030, /* RW: link.rx10s_option[1:0] */
171         PE1_ASPMOPTH    = 0x000000C0, /* RW: 10_req=[3]?HW:[2] */
172         PE1_GPREG0      = 0x0000FF00, /*
173                                        * SRW:
174                                        * Cfg_gp_reg0
175                                        * [7:6] phy_giga BG control
176                                        * [5] CREQ_N as CREQ_N1 (CPPE# as CREQ#)
177                                        * [4:0] Reserved
178                                        */
179         PE1_GPREG0_PBG  = 0x0000C000, /* phy_giga BG control */
180         PE1_GPREG1      = 0x00FF0000, /* RW: Cfg_gp_reg1 */
181         PE1_REVID       = 0xFF000000, /* RO: Rev ID */
182 };
183
184 enum pci_priv_pe1_values {
185         PE1_GPREG0_ENBG         = 0x00000000, /* en BG */
186         PE1_GPREG0_PDD3COLD     = 0x00004000, /* giga_PD + d3cold */
187         PE1_GPREG0_PDPCIESD     = 0x00008000, /* giga_PD + pcie_shutdown */
188         PE1_GPREG0_PDPCIEIDDQ   = 0x0000C000, /* giga_PD + pcie_iddq */
189 };
190
191 /*
192  * Dynamic(adaptive)/Static PCC values
193  */
194 enum dynamic_pcc_values {
195         PCC_OFF         = 0,
196         PCC_P1          = 1,
197         PCC_P2          = 2,
198         PCC_P3          = 3,
199
200         PCC_OFF_TO      = 0,
201         PCC_P1_TO       = 1,
202         PCC_P2_TO       = 64,
203         PCC_P3_TO       = 128,
204
205         PCC_OFF_CNT     = 0,
206         PCC_P1_CNT      = 1,
207         PCC_P2_CNT      = 16,
208         PCC_P3_CNT      = 32,
209 };
210 struct dynpcc_info {
211         unsigned long   last_bytes;
212         unsigned long   last_pkts;
213         unsigned long   intr_cnt;
214         unsigned char   cur;
215         unsigned char   attempt;
216         unsigned char   cnt;
217 };
218 #define PCC_INTERVAL_US 100000
219 #define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
220 #define PCC_P3_THRESHOLD (2 * 1024 * 1024)
221 #define PCC_P2_THRESHOLD 800
222 #define PCC_INTR_THRESHOLD 800
223 #define PCC_TX_TO 1000
224 #define PCC_TX_CNT 8
225
226 /*
227  * TX/RX Descriptors
228  *
229  * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
230  */
231 #define RING_DESC_ALIGN         16      /* Descriptor alignment */
232 #define TX_DESC_SIZE            16
233 #define TX_RING_NR              8
234 #define TX_RING_ALLOC_SIZE(s)   ((s * TX_DESC_SIZE) + RING_DESC_ALIGN)
235
236 struct txdesc {
237         union {
238                 __u8    all[16];
239                 __le32  dw[4];
240                 struct {
241                         /* DW0 */
242                         __le16  vlan;
243                         __u8    rsv1;
244                         __u8    flags;
245
246                         /* DW1 */
247                         __le16  datalen;
248                         __le16  mss;
249
250                         /* DW2 */
251                         __le16  pktsize;
252                         __le16  rsv2;
253
254                         /* DW3 */
255                         __le32  bufaddr;
256                 } desc1;
257                 struct {
258                         /* DW0 */
259                         __le16  rsv1;
260                         __u8    rsv2;
261                         __u8    flags;
262
263                         /* DW1 */
264                         __le16  datalen;
265                         __le16  rsv3;
266
267                         /* DW2 */
268                         __le32  bufaddrh;
269
270                         /* DW3 */
271                         __le32  bufaddrl;
272                 } desc2;
273                 struct {
274                         /* DW0 */
275                         __u8    ehdrsz;
276                         __u8    rsv1;
277                         __u8    rsv2;
278                         __u8    flags;
279
280                         /* DW1 */
281                         __le16  trycnt;
282                         __le16  segcnt;
283
284                         /* DW2 */
285                         __le16  pktsz;
286                         __le16  rsv3;
287
288                         /* DW3 */
289                         __le32  bufaddrl;
290                 } descwb;
291         };
292 };
293
294 enum jme_txdesc_flags_bits {
295         TXFLAG_OWN      = 0x80,
296         TXFLAG_INT      = 0x40,
297         TXFLAG_64BIT    = 0x20,
298         TXFLAG_TCPCS    = 0x10,
299         TXFLAG_UDPCS    = 0x08,
300         TXFLAG_IPCS     = 0x04,
301         TXFLAG_LSEN     = 0x02,
302         TXFLAG_TAGON    = 0x01,
303 };
304
305 #define TXDESC_MSS_SHIFT        2
306 enum jme_txwbdesc_flags_bits {
307         TXWBFLAG_OWN    = 0x80,
308         TXWBFLAG_INT    = 0x40,
309         TXWBFLAG_TMOUT  = 0x20,
310         TXWBFLAG_TRYOUT = 0x10,
311         TXWBFLAG_COL    = 0x08,
312
313         TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
314                           TXWBFLAG_TRYOUT |
315                           TXWBFLAG_COL,
316 };
317
318 #define RX_DESC_SIZE            16
319 #define RX_RING_NR              4
320 #define RX_RING_ALLOC_SIZE(s)   ((s * RX_DESC_SIZE) + RING_DESC_ALIGN)
321 #define RX_BUF_DMA_ALIGN        8
322 #define RX_PREPAD_SIZE          10
323 #define ETH_CRC_LEN             2
324 #define RX_VLANHDR_LEN          2
325 #define RX_EXTRA_LEN            (RX_PREPAD_SIZE + \
326                                 ETH_HLEN + \
327                                 ETH_CRC_LEN + \
328                                 RX_VLANHDR_LEN + \
329                                 RX_BUF_DMA_ALIGN)
330
331 struct rxdesc {
332         union {
333                 __u8    all[16];
334                 __le32  dw[4];
335                 struct {
336                         /* DW0 */
337                         __le16  rsv2;
338                         __u8    rsv1;
339                         __u8    flags;
340
341                         /* DW1 */
342                         __le16  datalen;
343                         __le16  wbcpl;
344
345                         /* DW2 */
346                         __le32  bufaddrh;
347
348                         /* DW3 */
349                         __le32  bufaddrl;
350                 } desc1;
351                 struct {
352                         /* DW0 */
353                         __le16  vlan;
354                         __le16  flags;
355
356                         /* DW1 */
357                         __le16  framesize;
358                         __u8    errstat;
359                         __u8    desccnt;
360
361                         /* DW2 */
362                         __le32  rsshash;
363
364                         /* DW3 */
365                         __u8    hashfun;
366                         __u8    hashtype;
367                         __le16  resrv;
368                 } descwb;
369         };
370 };
371
372 enum jme_rxdesc_flags_bits {
373         RXFLAG_OWN      = 0x80,
374         RXFLAG_INT      = 0x40,
375         RXFLAG_64BIT    = 0x20,
376 };
377
378 enum jme_rxwbdesc_flags_bits {
379         RXWBFLAG_OWN            = 0x8000,
380         RXWBFLAG_INT            = 0x4000,
381         RXWBFLAG_MF             = 0x2000,
382         RXWBFLAG_64BIT          = 0x2000,
383         RXWBFLAG_TCPON          = 0x1000,
384         RXWBFLAG_UDPON          = 0x0800,
385         RXWBFLAG_IPCS           = 0x0400,
386         RXWBFLAG_TCPCS          = 0x0200,
387         RXWBFLAG_UDPCS          = 0x0100,
388         RXWBFLAG_TAGON          = 0x0080,
389         RXWBFLAG_IPV4           = 0x0040,
390         RXWBFLAG_IPV6           = 0x0020,
391         RXWBFLAG_PAUSE          = 0x0010,
392         RXWBFLAG_MAGIC          = 0x0008,
393         RXWBFLAG_WAKEUP         = 0x0004,
394         RXWBFLAG_DEST           = 0x0003,
395         RXWBFLAG_DEST_UNI       = 0x0001,
396         RXWBFLAG_DEST_MUL       = 0x0002,
397         RXWBFLAG_DEST_BRO       = 0x0003,
398 };
399
400 enum jme_rxwbdesc_desccnt_mask {
401         RXWBDCNT_WBCPL  = 0x80,
402         RXWBDCNT_DCNT   = 0x7F,
403 };
404
405 enum jme_rxwbdesc_errstat_bits {
406         RXWBERR_LIMIT   = 0x80,
407         RXWBERR_MIIER   = 0x40,
408         RXWBERR_NIBON   = 0x20,
409         RXWBERR_COLON   = 0x10,
410         RXWBERR_ABORT   = 0x08,
411         RXWBERR_SHORT   = 0x04,
412         RXWBERR_OVERUN  = 0x02,
413         RXWBERR_CRCERR  = 0x01,
414         RXWBERR_ALLERR  = 0xFF,
415 };
416
417 /*
418  * Buffer information corresponding to ring descriptors.
419  */
420 struct jme_buffer_info {
421         struct sk_buff *skb;
422         dma_addr_t mapping;
423         int len;
424         int nr_desc;
425         unsigned long start_xmit;
426 };
427
428 /*
429  * The structure holding buffer information and ring descriptors all together.
430  */
431 struct jme_ring {
432         void *alloc;            /* pointer to allocated memory */
433         void *desc;             /* pointer to ring memory  */
434         dma_addr_t dmaalloc;    /* phys address of ring alloc */
435         dma_addr_t dma;         /* phys address for ring dma */
436
437         /* Buffer information corresponding to each descriptor */
438         struct jme_buffer_info *bufinf;
439
440         int next_to_use;
441         atomic_t next_to_clean;
442         atomic_t nr_free;
443 };
444
445 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
446 #define false 0
447 #define true 0
448 #define netdev_alloc_skb(dev, len) dev_alloc_skb(len)
449 #define PCI_VENDOR_ID_JMICRON           0x197B
450 #endif
451
452 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,19)
453 #define PCI_VDEVICE(vendor, device)             \
454         PCI_VENDOR_ID_##vendor, (device),       \
455         PCI_ANY_ID, PCI_ANY_ID, 0, 0
456 #endif
457
458 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
459 #define NET_STAT(priv) priv->stats
460 #define NETDEV_GET_STATS(netdev, fun_ptr) \
461         netdev->get_stats = fun_ptr
462 #define DECLARE_NET_DEVICE_STATS struct net_device_stats stats;
463 /*
464  * CentOS 5.5 have *_hdr helpers back-ported
465  */
466 #ifdef RHEL_RELEASE_CODE
467 #if RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,5)
468 #define __DEFINE_IPHDR_HELPERS__
469 #endif
470 #else
471 #define __DEFINE_IPHDR_HELPERS__
472 #endif
473 #else
474 #define NET_STAT(priv) (priv->dev->stats)
475 #define NETDEV_GET_STATS(netdev, fun_ptr)
476 #define DECLARE_NET_DEVICE_STATS
477 #endif
478
479 #ifdef __DEFINE_IPHDR_HELPERS__
480 static inline struct iphdr *ip_hdr(const struct sk_buff *skb)
481 {
482         return skb->nh.iph;
483 }
484
485 static inline struct ipv6hdr *ipv6_hdr(const struct sk_buff *skb)
486 {
487         return skb->nh.ipv6h;
488 }
489
490 static inline struct tcphdr *tcp_hdr(const struct sk_buff *skb)
491 {
492         return skb->h.th;
493 }
494 #endif
495
496 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
497 #define DECLARE_NAPI_STRUCT
498 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
499         dev->poll = pollfn; \
500         dev->weight = q;
501 #define JME_NAPI_HOLDER(holder) struct net_device *holder
502 #define JME_NAPI_WEIGHT(w) int *w
503 #define JME_NAPI_WEIGHT_VAL(w) *w
504 #define JME_NAPI_WEIGHT_SET(w, r) *w = r
505 #define DECLARE_NETDEV struct net_device *netdev = jme->dev;
506 #define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev)
507 #define JME_NAPI_ENABLE(priv) netif_poll_enable(priv->dev);
508 #define JME_NAPI_DISABLE(priv) netif_poll_disable(priv->dev);
509 #define JME_RX_SCHEDULE_PREP(priv) \
510         netif_rx_schedule_prep(priv->dev)
511 #define JME_RX_SCHEDULE(priv) \
512         __netif_rx_schedule(priv->dev);
513 #else
514 #define DECLARE_NAPI_STRUCT struct napi_struct napi;
515 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
516         netif_napi_add(dev, napis, pollfn, q);
517 #define JME_NAPI_HOLDER(holder) struct napi_struct *holder
518 #define JME_NAPI_WEIGHT(w) int w
519 #define JME_NAPI_WEIGHT_VAL(w) w
520 #define JME_NAPI_WEIGHT_SET(w, r)
521 #define DECLARE_NETDEV
522 #define JME_RX_COMPLETE(dev, napis) napi_complete(napis)
523 #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
524 #define JME_NAPI_DISABLE(priv) \
525         if (!napi_disable_pending(&priv->napi)) \
526                 napi_disable(&priv->napi);
527 #define JME_RX_SCHEDULE_PREP(priv) \
528         napi_schedule_prep(&priv->napi)
529 #define JME_RX_SCHEDULE(priv) \
530         __napi_schedule(&priv->napi);
531 #endif
532
533 /*
534  * Jmac Adapter Private data
535  */
536 struct jme_adapter {
537         struct pci_dev          *pdev;
538         struct net_device       *dev;
539         void __iomem            *regs;
540         struct mii_if_info      mii_if;
541         struct jme_ring         rxring[RX_RING_NR];
542         struct jme_ring         txring[TX_RING_NR];
543         spinlock_t              phy_lock;
544         spinlock_t              macaddr_lock;
545         spinlock_t              rxmcs_lock;
546         struct tasklet_struct   rxempty_task;
547         struct tasklet_struct   rxclean_task;
548         struct tasklet_struct   txclean_task;
549         struct tasklet_struct   linkch_task;
550         struct tasklet_struct   pcc_task;
551         unsigned long           flags;
552         u32                     reg_txcs;
553         u32                     reg_txpfc;
554         u32                     reg_rxcs;
555         u32                     reg_rxmcs;
556         u32                     reg_ghc;
557         u32                     reg_pmcs;
558         u32                     reg_gpreg1;
559         u32                     phylink;
560         u32                     tx_ring_size;
561         u32                     tx_ring_mask;
562         u32                     tx_wake_threshold;
563         u32                     rx_ring_size;
564         u32                     rx_ring_mask;
565         u8                      mrrs;
566         unsigned int            fpgaver;
567         u8                      chiprev;
568         u8                      chip_main_rev;
569         u8                      chip_sub_rev;
570         u8                      pcirev;
571         u32                     msg_enable;
572         struct ethtool_cmd      old_ecmd;
573         unsigned int            old_mtu;
574         struct vlan_group       *vlgrp;
575         struct dynpcc_info      dpi;
576         atomic_t                intr_sem;
577         atomic_t                link_changing;
578         atomic_t                tx_cleaning;
579         atomic_t                rx_cleaning;
580         atomic_t                rx_empty;
581         int                     (*jme_rx)(struct sk_buff *skb);
582         int                     (*jme_vlan_rx)(struct sk_buff *skb,
583                                           struct vlan_group *grp,
584                                           unsigned short vlan_tag);
585         DECLARE_NAPI_STRUCT
586         DECLARE_NET_DEVICE_STATS
587 };
588
589 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
590 static struct net_device_stats *
591 jme_get_stats(struct net_device *netdev)
592 {
593         struct jme_adapter *jme = netdev_priv(netdev);
594         return &jme->stats;
595 }
596 #endif
597
598 enum jme_flags_bits {
599         JME_FLAG_MSI            = 1,
600         JME_FLAG_SSET           = 2,
601         JME_FLAG_TXCSUM         = 3,
602         JME_FLAG_TSO            = 4,
603         JME_FLAG_POLL           = 5,
604         JME_FLAG_SHUTDOWN       = 6,
605 };
606
607 #define TX_TIMEOUT              (5 * HZ)
608 #define JME_REG_LEN             0x500
609 #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
610
611 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
612 static inline struct jme_adapter*
613 jme_napi_priv(struct net_device *holder)
614 {
615         struct jme_adapter *jme;
616         jme = netdev_priv(holder);
617         return jme;
618 }
619 #else
620 static inline struct jme_adapter*
621 jme_napi_priv(struct napi_struct *napi)
622 {
623         struct jme_adapter *jme;
624         jme = container_of(napi, struct jme_adapter, napi);
625         return jme;
626 }
627 #endif
628
629 /*
630  * MMaped I/O Resters
631  */
632 enum jme_iomap_offsets {
633         JME_MAC         = 0x0000,
634         JME_PHY         = 0x0400,
635         JME_MISC        = 0x0800,
636         JME_RSS         = 0x0C00,
637 };
638
639 enum jme_iomap_lens {
640         JME_MAC_LEN     = 0x80,
641         JME_PHY_LEN     = 0x58,
642         JME_MISC_LEN    = 0x98,
643         JME_RSS_LEN     = 0xFF,
644 };
645
646 enum jme_iomap_regs {
647         JME_TXCS        = JME_MAC | 0x00, /* Transmit Control and Status */
648         JME_TXDBA_LO    = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
649         JME_TXDBA_HI    = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
650         JME_TXQDC       = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
651         JME_TXNDA       = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
652         JME_TXMCS       = JME_MAC | 0x14, /* Transmit MAC Control Status */
653         JME_TXPFC       = JME_MAC | 0x18, /* Transmit Pause Frame Control */
654         JME_TXTRHD      = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
655
656         JME_RXCS        = JME_MAC | 0x20, /* Receive Control and Status */
657         JME_RXDBA_LO    = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
658         JME_RXDBA_HI    = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
659         JME_RXQDC       = JME_MAC | 0x2C, /* Receive Queue Desc Count */
660         JME_RXNDA       = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
661         JME_RXMCS       = JME_MAC | 0x34, /* Receive MAC Control Status */
662         JME_RXUMA_LO    = JME_MAC | 0x38, /* Receive Unicast MAC Address */
663         JME_RXUMA_HI    = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
664         JME_RXMCHT_LO   = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
665         JME_RXMCHT_HI   = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
666         JME_WFODP       = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
667         JME_WFOI        = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
668
669         JME_SMI         = JME_MAC | 0x50, /* Station Management Interface */
670         JME_GHC         = JME_MAC | 0x54, /* Global Host Control */
671         JME_PMCS        = JME_MAC | 0x60, /* Power Management Control/Stat */
672
673
674         JME_PHY_PWR     = JME_PHY | 0x24, /* New PHY Power Ctrl Register */
675         JME_PHY_CS      = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
676         JME_PHY_LINK    = JME_PHY | 0x30, /* PHY Link Status Register */
677         JME_SMBCSR      = JME_PHY | 0x40, /* SMB Control and Status */
678         JME_SMBINTF     = JME_PHY | 0x44, /* SMB Interface */
679
680
681         JME_TMCSR       = JME_MISC | 0x00, /* Timer Control/Status Register */
682         JME_GPREG0      = JME_MISC | 0x08, /* General purpose REG-0 */
683         JME_GPREG1      = JME_MISC | 0x0C, /* General purpose REG-1 */
684         JME_IEVE        = JME_MISC | 0x20, /* Interrupt Event Status */
685         JME_IREQ        = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
686         JME_IENS        = JME_MISC | 0x28, /* Intr Enable - Setting Port */
687         JME_IENC        = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
688         JME_PCCRX0      = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
689         JME_PCCTX       = JME_MISC | 0x40, /* PCC Control for TX Queues */
690         JME_CHIPMODE    = JME_MISC | 0x44, /* Identify FPGA Version */
691         JME_SHBA_HI     = JME_MISC | 0x48, /* Shadow Register Base HI */
692         JME_SHBA_LO     = JME_MISC | 0x4C, /* Shadow Register Base LO */
693         JME_TIMER1      = JME_MISC | 0x70, /* Timer1 */
694         JME_TIMER2      = JME_MISC | 0x74, /* Timer2 */
695         JME_APMC        = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
696         JME_PCCSRX0     = JME_MISC | 0x80, /* PCC Status of RX0 */
697 };
698
699 /*
700  * TX Control/Status Bits
701  */
702 enum jme_txcs_bits {
703         TXCS_QUEUE7S    = 0x00008000,
704         TXCS_QUEUE6S    = 0x00004000,
705         TXCS_QUEUE5S    = 0x00002000,
706         TXCS_QUEUE4S    = 0x00001000,
707         TXCS_QUEUE3S    = 0x00000800,
708         TXCS_QUEUE2S    = 0x00000400,
709         TXCS_QUEUE1S    = 0x00000200,
710         TXCS_QUEUE0S    = 0x00000100,
711         TXCS_FIFOTH     = 0x000000C0,
712         TXCS_DMASIZE    = 0x00000030,
713         TXCS_BURST      = 0x00000004,
714         TXCS_ENABLE     = 0x00000001,
715 };
716
717 enum jme_txcs_value {
718         TXCS_FIFOTH_16QW        = 0x000000C0,
719         TXCS_FIFOTH_12QW        = 0x00000080,
720         TXCS_FIFOTH_8QW         = 0x00000040,
721         TXCS_FIFOTH_4QW         = 0x00000000,
722
723         TXCS_DMASIZE_64B        = 0x00000000,
724         TXCS_DMASIZE_128B       = 0x00000010,
725         TXCS_DMASIZE_256B       = 0x00000020,
726         TXCS_DMASIZE_512B       = 0x00000030,
727
728         TXCS_SELECT_QUEUE0      = 0x00000000,
729         TXCS_SELECT_QUEUE1      = 0x00010000,
730         TXCS_SELECT_QUEUE2      = 0x00020000,
731         TXCS_SELECT_QUEUE3      = 0x00030000,
732         TXCS_SELECT_QUEUE4      = 0x00040000,
733         TXCS_SELECT_QUEUE5      = 0x00050000,
734         TXCS_SELECT_QUEUE6      = 0x00060000,
735         TXCS_SELECT_QUEUE7      = 0x00070000,
736
737         TXCS_DEFAULT            = TXCS_FIFOTH_4QW |
738                                   TXCS_BURST,
739 };
740
741 #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
742
743 /*
744  * TX MAC Control/Status Bits
745  */
746 enum jme_txmcs_bit_masks {
747         TXMCS_IFG2              = 0xC0000000,
748         TXMCS_IFG1              = 0x30000000,
749         TXMCS_TTHOLD            = 0x00000300,
750         TXMCS_FBURST            = 0x00000080,
751         TXMCS_CARRIEREXT        = 0x00000040,
752         TXMCS_DEFER             = 0x00000020,
753         TXMCS_BACKOFF           = 0x00000010,
754         TXMCS_CARRIERSENSE      = 0x00000008,
755         TXMCS_COLLISION         = 0x00000004,
756         TXMCS_CRC               = 0x00000002,
757         TXMCS_PADDING           = 0x00000001,
758 };
759
760 enum jme_txmcs_values {
761         TXMCS_IFG2_6_4          = 0x00000000,
762         TXMCS_IFG2_8_5          = 0x40000000,
763         TXMCS_IFG2_10_6         = 0x80000000,
764         TXMCS_IFG2_12_7         = 0xC0000000,
765
766         TXMCS_IFG1_8_4          = 0x00000000,
767         TXMCS_IFG1_12_6         = 0x10000000,
768         TXMCS_IFG1_16_8         = 0x20000000,
769         TXMCS_IFG1_20_10        = 0x30000000,
770
771         TXMCS_TTHOLD_1_8        = 0x00000000,
772         TXMCS_TTHOLD_1_4        = 0x00000100,
773         TXMCS_TTHOLD_1_2        = 0x00000200,
774         TXMCS_TTHOLD_FULL       = 0x00000300,
775
776         TXMCS_DEFAULT           = TXMCS_IFG2_8_5 |
777                                   TXMCS_IFG1_16_8 |
778                                   TXMCS_TTHOLD_FULL |
779                                   TXMCS_DEFER |
780                                   TXMCS_CRC |
781                                   TXMCS_PADDING,
782 };
783
784 enum jme_txpfc_bits_masks {
785         TXPFC_VLAN_TAG          = 0xFFFF0000,
786         TXPFC_VLAN_EN           = 0x00008000,
787         TXPFC_PF_EN             = 0x00000001,
788 };
789
790 enum jme_txtrhd_bits_masks {
791         TXTRHD_TXPEN            = 0x80000000,
792         TXTRHD_TXP              = 0x7FFFFF00,
793         TXTRHD_TXREN            = 0x00000080,
794         TXTRHD_TXRL             = 0x0000007F,
795 };
796
797 enum jme_txtrhd_shifts {
798         TXTRHD_TXP_SHIFT        = 8,
799         TXTRHD_TXRL_SHIFT       = 0,
800 };
801
802 enum jme_txtrhd_values {
803         TXTRHD_FULLDUPLEX       = 0x00000000,
804         TXTRHD_HALFDUPLEX       = TXTRHD_TXPEN |
805                                   ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
806                                   TXTRHD_TXREN |
807                                   ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL),
808 };
809
810 /*
811  * RX Control/Status Bits
812  */
813 enum jme_rxcs_bit_masks {
814         /* FIFO full threshold for transmitting Tx Pause Packet */
815         RXCS_FIFOTHTP   = 0x30000000,
816         /* FIFO threshold for processing next packet */
817         RXCS_FIFOTHNP   = 0x0C000000,
818         RXCS_DMAREQSZ   = 0x03000000, /* DMA Request Size */
819         RXCS_QUEUESEL   = 0x00030000, /* Queue selection */
820         RXCS_RETRYGAP   = 0x0000F000, /* RX Desc full retry gap */
821         RXCS_RETRYCNT   = 0x00000F00, /* RX Desc full retry counter */
822         RXCS_WAKEUP     = 0x00000040, /* Enable receive wakeup packet */
823         RXCS_MAGIC      = 0x00000020, /* Enable receive magic packet */
824         RXCS_SHORT      = 0x00000010, /* Enable receive short packet */
825         RXCS_ABORT      = 0x00000008, /* Enable receive errorr packet */
826         RXCS_QST        = 0x00000004, /* Receive queue start */
827         RXCS_SUSPEND    = 0x00000002,
828         RXCS_ENABLE     = 0x00000001,
829 };
830
831 enum jme_rxcs_values {
832         RXCS_FIFOTHTP_16T       = 0x00000000,
833         RXCS_FIFOTHTP_32T       = 0x10000000,
834         RXCS_FIFOTHTP_64T       = 0x20000000,
835         RXCS_FIFOTHTP_128T      = 0x30000000,
836
837         RXCS_FIFOTHNP_16QW      = 0x00000000,
838         RXCS_FIFOTHNP_32QW      = 0x04000000,
839         RXCS_FIFOTHNP_64QW      = 0x08000000,
840         RXCS_FIFOTHNP_128QW     = 0x0C000000,
841
842         RXCS_DMAREQSZ_16B       = 0x00000000,
843         RXCS_DMAREQSZ_32B       = 0x01000000,
844         RXCS_DMAREQSZ_64B       = 0x02000000,
845         RXCS_DMAREQSZ_128B      = 0x03000000,
846
847         RXCS_QUEUESEL_Q0        = 0x00000000,
848         RXCS_QUEUESEL_Q1        = 0x00010000,
849         RXCS_QUEUESEL_Q2        = 0x00020000,
850         RXCS_QUEUESEL_Q3        = 0x00030000,
851
852         RXCS_RETRYGAP_256ns     = 0x00000000,
853         RXCS_RETRYGAP_512ns     = 0x00001000,
854         RXCS_RETRYGAP_1024ns    = 0x00002000,
855         RXCS_RETRYGAP_2048ns    = 0x00003000,
856         RXCS_RETRYGAP_4096ns    = 0x00004000,
857         RXCS_RETRYGAP_8192ns    = 0x00005000,
858         RXCS_RETRYGAP_16384ns   = 0x00006000,
859         RXCS_RETRYGAP_32768ns   = 0x00007000,
860
861         RXCS_RETRYCNT_0         = 0x00000000,
862         RXCS_RETRYCNT_4         = 0x00000100,
863         RXCS_RETRYCNT_8         = 0x00000200,
864         RXCS_RETRYCNT_12        = 0x00000300,
865         RXCS_RETRYCNT_16        = 0x00000400,
866         RXCS_RETRYCNT_20        = 0x00000500,
867         RXCS_RETRYCNT_24        = 0x00000600,
868         RXCS_RETRYCNT_28        = 0x00000700,
869         RXCS_RETRYCNT_32        = 0x00000800,
870         RXCS_RETRYCNT_36        = 0x00000900,
871         RXCS_RETRYCNT_40        = 0x00000A00,
872         RXCS_RETRYCNT_44        = 0x00000B00,
873         RXCS_RETRYCNT_48        = 0x00000C00,
874         RXCS_RETRYCNT_52        = 0x00000D00,
875         RXCS_RETRYCNT_56        = 0x00000E00,
876         RXCS_RETRYCNT_60        = 0x00000F00,
877
878         RXCS_DEFAULT            = RXCS_FIFOTHTP_128T |
879                                   RXCS_FIFOTHNP_128QW |
880                                   RXCS_DMAREQSZ_128B |
881                                   RXCS_RETRYGAP_256ns |
882                                   RXCS_RETRYCNT_32,
883 };
884
885 #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
886
887 /*
888  * RX MAC Control/Status Bits
889  */
890 enum jme_rxmcs_bits {
891         RXMCS_ALLFRAME          = 0x00000800,
892         RXMCS_BRDFRAME          = 0x00000400,
893         RXMCS_MULFRAME          = 0x00000200,
894         RXMCS_UNIFRAME          = 0x00000100,
895         RXMCS_ALLMULFRAME       = 0x00000080,
896         RXMCS_MULFILTERED       = 0x00000040,
897         RXMCS_RXCOLLDEC         = 0x00000020,
898         RXMCS_FLOWCTRL          = 0x00000008,
899         RXMCS_VTAGRM            = 0x00000004,
900         RXMCS_PREPAD            = 0x00000002,
901         RXMCS_CHECKSUM          = 0x00000001,
902
903         RXMCS_DEFAULT           = RXMCS_VTAGRM |
904                                   RXMCS_PREPAD |
905                                   RXMCS_FLOWCTRL |
906                                   RXMCS_CHECKSUM,
907 };
908
909 /*
910  * Wakeup Frame setup interface registers
911  */
912 #define WAKEUP_FRAME_NR 8
913 #define WAKEUP_FRAME_MASK_DWNR  4
914
915 enum jme_wfoi_bit_masks {
916         WFOI_MASK_SEL           = 0x00000070,
917         WFOI_CRC_SEL            = 0x00000008,
918         WFOI_FRAME_SEL          = 0x00000007,
919 };
920
921 enum jme_wfoi_shifts {
922         WFOI_MASK_SHIFT         = 4,
923 };
924
925 /*
926  * SMI Related definitions
927  */
928 enum jme_smi_bit_mask {
929         SMI_DATA_MASK           = 0xFFFF0000,
930         SMI_REG_ADDR_MASK       = 0x0000F800,
931         SMI_PHY_ADDR_MASK       = 0x000007C0,
932         SMI_OP_WRITE            = 0x00000020,
933         /* Set to 1, after req done it'll be cleared to 0 */
934         SMI_OP_REQ              = 0x00000010,
935         SMI_OP_MDIO             = 0x00000008, /* Software assess In/Out */
936         SMI_OP_MDOE             = 0x00000004, /* Software Output Enable */
937         SMI_OP_MDC              = 0x00000002, /* Software CLK Control */
938         SMI_OP_MDEN             = 0x00000001, /* Software access Enable */
939 };
940
941 enum jme_smi_bit_shift {
942         SMI_DATA_SHIFT          = 16,
943         SMI_REG_ADDR_SHIFT      = 11,
944         SMI_PHY_ADDR_SHIFT      = 6,
945 };
946
947 static inline u32 smi_reg_addr(int x)
948 {
949         return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
950 }
951
952 static inline u32 smi_phy_addr(int x)
953 {
954         return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
955 }
956
957 #define JME_PHY_TIMEOUT 100 /* 100 msec */
958 #define JME_PHY_REG_NR 32
959
960 /*
961  * Global Host Control
962  */
963 enum jme_ghc_bit_mask {
964         GHC_SWRST               = 0x40000000,
965         GHC_TO_CLK_SRC          = 0x00C00000,
966         GHC_TXMAC_CLK_SRC       = 0x00300000,
967         GHC_DPX                 = 0x00000040,
968         GHC_SPEED               = 0x00000030,
969         GHC_LINK_POLL           = 0x00000001,
970 };
971
972 enum jme_ghc_speed_val {
973         GHC_SPEED_10M           = 0x00000010,
974         GHC_SPEED_100M          = 0x00000020,
975         GHC_SPEED_1000M         = 0x00000030,
976 };
977
978 enum jme_ghc_to_clk {
979         GHC_TO_CLK_OFF          = 0x00000000,
980         GHC_TO_CLK_GPHY         = 0x00400000,
981         GHC_TO_CLK_PCIE         = 0x00800000,
982         GHC_TO_CLK_INVALID      = 0x00C00000,
983 };
984
985 enum jme_ghc_txmac_clk {
986         GHC_TXMAC_CLK_OFF       = 0x00000000,
987         GHC_TXMAC_CLK_GPHY      = 0x00100000,
988         GHC_TXMAC_CLK_PCIE      = 0x00200000,
989         GHC_TXMAC_CLK_INVALID   = 0x00300000,
990 };
991
992 /*
993  * Power management control and status register
994  */
995 enum jme_pmcs_bit_masks {
996         PMCS_WF7DET     = 0x80000000,
997         PMCS_WF6DET     = 0x40000000,
998         PMCS_WF5DET     = 0x20000000,
999         PMCS_WF4DET     = 0x10000000,
1000         PMCS_WF3DET     = 0x08000000,
1001         PMCS_WF2DET     = 0x04000000,
1002         PMCS_WF1DET     = 0x02000000,
1003         PMCS_WF0DET     = 0x01000000,
1004         PMCS_LFDET      = 0x00040000,
1005         PMCS_LRDET      = 0x00020000,
1006         PMCS_MFDET      = 0x00010000,
1007         PMCS_WF7EN      = 0x00008000,
1008         PMCS_WF6EN      = 0x00004000,
1009         PMCS_WF5EN      = 0x00002000,
1010         PMCS_WF4EN      = 0x00001000,
1011         PMCS_WF3EN      = 0x00000800,
1012         PMCS_WF2EN      = 0x00000400,
1013         PMCS_WF1EN      = 0x00000200,
1014         PMCS_WF0EN      = 0x00000100,
1015         PMCS_LFEN       = 0x00000004,
1016         PMCS_LREN       = 0x00000002,
1017         PMCS_MFEN       = 0x00000001,
1018 };
1019
1020 /*
1021  * New PHY Power Control Register
1022  */
1023 enum jme_phy_pwr_bit_masks {
1024         PHY_PWR_DWN1SEL = 0x01000000, /* Phy_giga.p_PWR_DOWN1_SEL */
1025         PHY_PWR_DWN1SW  = 0x02000000, /* Phy_giga.p_PWR_DOWN1_SW */
1026         PHY_PWR_DWN2    = 0x04000000, /* Phy_giga.p_PWR_DOWN2 */
1027         PHY_PWR_CLKSEL  = 0x08000000, /*
1028                                        * XTL_OUT Clock select
1029                                        * (an internal free-running clock)
1030                                        * 0: xtl_out = phy_giga.A_XTL25_O
1031                                        * 1: xtl_out = phy_giga.PD_OSC
1032                                        */
1033 };
1034
1035 /*
1036  * Giga PHY Status Registers
1037  */
1038 enum jme_phy_link_bit_mask {
1039         PHY_LINK_SPEED_MASK             = 0x0000C000,
1040         PHY_LINK_DUPLEX                 = 0x00002000,
1041         PHY_LINK_SPEEDDPU_RESOLVED      = 0x00000800,
1042         PHY_LINK_UP                     = 0x00000400,
1043         PHY_LINK_AUTONEG_COMPLETE       = 0x00000200,
1044         PHY_LINK_MDI_STAT               = 0x00000040,
1045 };
1046
1047 enum jme_phy_link_speed_val {
1048         PHY_LINK_SPEED_10M              = 0x00000000,
1049         PHY_LINK_SPEED_100M             = 0x00004000,
1050         PHY_LINK_SPEED_1000M            = 0x00008000,
1051 };
1052
1053 #define JME_SPDRSV_TIMEOUT      500     /* 500 us */
1054
1055 /*
1056  * SMB Control and Status
1057  */
1058 enum jme_smbcsr_bit_mask {
1059         SMBCSR_CNACK    = 0x00020000,
1060         SMBCSR_RELOAD   = 0x00010000,
1061         SMBCSR_EEPROMD  = 0x00000020,
1062         SMBCSR_INITDONE = 0x00000010,
1063         SMBCSR_BUSY     = 0x0000000F,
1064 };
1065
1066 enum jme_smbintf_bit_mask {
1067         SMBINTF_HWDATR  = 0xFF000000,
1068         SMBINTF_HWDATW  = 0x00FF0000,
1069         SMBINTF_HWADDR  = 0x0000FF00,
1070         SMBINTF_HWRWN   = 0x00000020,
1071         SMBINTF_HWCMD   = 0x00000010,
1072         SMBINTF_FASTM   = 0x00000008,
1073         SMBINTF_GPIOSCL = 0x00000004,
1074         SMBINTF_GPIOSDA = 0x00000002,
1075         SMBINTF_GPIOEN  = 0x00000001,
1076 };
1077
1078 enum jme_smbintf_vals {
1079         SMBINTF_HWRWN_READ      = 0x00000020,
1080         SMBINTF_HWRWN_WRITE     = 0x00000000,
1081 };
1082
1083 enum jme_smbintf_shifts {
1084         SMBINTF_HWDATR_SHIFT    = 24,
1085         SMBINTF_HWDATW_SHIFT    = 16,
1086         SMBINTF_HWADDR_SHIFT    = 8,
1087 };
1088
1089 #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
1090 #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
1091 #define JME_SMB_LEN 256
1092 #define JME_EEPROM_MAGIC 0x250
1093
1094 /*
1095  * Timer Control/Status Register
1096  */
1097 enum jme_tmcsr_bit_masks {
1098         TMCSR_SWIT      = 0x80000000,
1099         TMCSR_EN        = 0x01000000,
1100         TMCSR_CNT       = 0x00FFFFFF,
1101 };
1102
1103 /*
1104  * General Purpose REG-0
1105  */
1106 enum jme_gpreg0_masks {
1107         GPREG0_DISSH            = 0xFF000000,
1108         GPREG0_PCIRLMT          = 0x00300000,
1109         GPREG0_PCCNOMUTCLR      = 0x00040000,
1110         GPREG0_LNKINTPOLL       = 0x00001000,
1111         GPREG0_PCCTMR           = 0x00000300,
1112         GPREG0_PHYADDR          = 0x0000001F,
1113 };
1114
1115 enum jme_gpreg0_vals {
1116         GPREG0_DISSH_DW7        = 0x80000000,
1117         GPREG0_DISSH_DW6        = 0x40000000,
1118         GPREG0_DISSH_DW5        = 0x20000000,
1119         GPREG0_DISSH_DW4        = 0x10000000,
1120         GPREG0_DISSH_DW3        = 0x08000000,
1121         GPREG0_DISSH_DW2        = 0x04000000,
1122         GPREG0_DISSH_DW1        = 0x02000000,
1123         GPREG0_DISSH_DW0        = 0x01000000,
1124         GPREG0_DISSH_ALL        = 0xFF000000,
1125
1126         GPREG0_PCIRLMT_8        = 0x00000000,
1127         GPREG0_PCIRLMT_6        = 0x00100000,
1128         GPREG0_PCIRLMT_5        = 0x00200000,
1129         GPREG0_PCIRLMT_4        = 0x00300000,
1130
1131         GPREG0_PCCTMR_16ns      = 0x00000000,
1132         GPREG0_PCCTMR_256ns     = 0x00000100,
1133         GPREG0_PCCTMR_1us       = 0x00000200,
1134         GPREG0_PCCTMR_1ms       = 0x00000300,
1135
1136         GPREG0_PHYADDR_1        = 0x00000001,
1137
1138         GPREG0_DEFAULT          = GPREG0_PCIRLMT_4 |
1139                                   GPREG0_PCCTMR_1us |
1140                                   GPREG0_PHYADDR_1,
1141 };
1142
1143 /*
1144  * General Purpose REG-1
1145  */
1146 enum jme_gpreg1_bit_masks {
1147         GPREG1_RXCLKOFF         = 0x04000000,
1148         GPREG1_PCREQN           = 0x00020000,
1149         GPREG1_HALFMODEPATCH    = 0x00000040, /* For Chip revision 0x11 only */
1150         GPREG1_RSSPATCH         = 0x00000020, /* For Chip revision 0x11 only */
1151         GPREG1_INTRDELAYUNIT    = 0x00000018,
1152         GPREG1_INTRDELAYENABLE  = 0x00000007,
1153 };
1154
1155 enum jme_gpreg1_vals {
1156         GPREG1_INTDLYUNIT_16NS  = 0x00000000,
1157         GPREG1_INTDLYUNIT_256NS = 0x00000008,
1158         GPREG1_INTDLYUNIT_1US   = 0x00000010,
1159         GPREG1_INTDLYUNIT_16US  = 0x00000018,
1160
1161         GPREG1_INTDLYEN_1U      = 0x00000001,
1162         GPREG1_INTDLYEN_2U      = 0x00000002,
1163         GPREG1_INTDLYEN_3U      = 0x00000003,
1164         GPREG1_INTDLYEN_4U      = 0x00000004,
1165         GPREG1_INTDLYEN_5U      = 0x00000005,
1166         GPREG1_INTDLYEN_6U      = 0x00000006,
1167         GPREG1_INTDLYEN_7U      = 0x00000007,
1168
1169         GPREG1_DEFAULT          = GPREG1_PCREQN,
1170 };
1171
1172 /*
1173  * Interrupt Status Bits
1174  */
1175 enum jme_interrupt_bits {
1176         INTR_SWINTR     = 0x80000000,
1177         INTR_TMINTR     = 0x40000000,
1178         INTR_LINKCH     = 0x20000000,
1179         INTR_PAUSERCV   = 0x10000000,
1180         INTR_MAGICRCV   = 0x08000000,
1181         INTR_WAKERCV    = 0x04000000,
1182         INTR_PCCRX0TO   = 0x02000000,
1183         INTR_PCCRX1TO   = 0x01000000,
1184         INTR_PCCRX2TO   = 0x00800000,
1185         INTR_PCCRX3TO   = 0x00400000,
1186         INTR_PCCTXTO    = 0x00200000,
1187         INTR_PCCRX0     = 0x00100000,
1188         INTR_PCCRX1     = 0x00080000,
1189         INTR_PCCRX2     = 0x00040000,
1190         INTR_PCCRX3     = 0x00020000,
1191         INTR_PCCTX      = 0x00010000,
1192         INTR_RX3EMP     = 0x00008000,
1193         INTR_RX2EMP     = 0x00004000,
1194         INTR_RX1EMP     = 0x00002000,
1195         INTR_RX0EMP     = 0x00001000,
1196         INTR_RX3        = 0x00000800,
1197         INTR_RX2        = 0x00000400,
1198         INTR_RX1        = 0x00000200,
1199         INTR_RX0        = 0x00000100,
1200         INTR_TX7        = 0x00000080,
1201         INTR_TX6        = 0x00000040,
1202         INTR_TX5        = 0x00000020,
1203         INTR_TX4        = 0x00000010,
1204         INTR_TX3        = 0x00000008,
1205         INTR_TX2        = 0x00000004,
1206         INTR_TX1        = 0x00000002,
1207         INTR_TX0        = 0x00000001,
1208 };
1209
1210 static const u32 INTR_ENABLE = INTR_SWINTR |
1211                                  INTR_TMINTR |
1212                                  INTR_LINKCH |
1213                                  INTR_PCCRX0TO |
1214                                  INTR_PCCRX0 |
1215                                  INTR_PCCTXTO |
1216                                  INTR_PCCTX |
1217                                  INTR_RX0EMP;
1218
1219 /*
1220  * PCC Control Registers
1221  */
1222 enum jme_pccrx_masks {
1223         PCCRXTO_MASK    = 0xFFFF0000,
1224         PCCRX_MASK      = 0x0000FF00,
1225 };
1226
1227 enum jme_pcctx_masks {
1228         PCCTXTO_MASK    = 0xFFFF0000,
1229         PCCTX_MASK      = 0x0000FF00,
1230         PCCTX_QS_MASK   = 0x000000FF,
1231 };
1232
1233 enum jme_pccrx_shifts {
1234         PCCRXTO_SHIFT   = 16,
1235         PCCRX_SHIFT     = 8,
1236 };
1237
1238 enum jme_pcctx_shifts {
1239         PCCTXTO_SHIFT   = 16,
1240         PCCTX_SHIFT     = 8,
1241 };
1242
1243 enum jme_pcctx_bits {
1244         PCCTXQ0_EN      = 0x00000001,
1245         PCCTXQ1_EN      = 0x00000002,
1246         PCCTXQ2_EN      = 0x00000004,
1247         PCCTXQ3_EN      = 0x00000008,
1248         PCCTXQ4_EN      = 0x00000010,
1249         PCCTXQ5_EN      = 0x00000020,
1250         PCCTXQ6_EN      = 0x00000040,
1251         PCCTXQ7_EN      = 0x00000080,
1252 };
1253
1254 /*
1255  * Chip Mode Register
1256  */
1257 enum jme_chipmode_bit_masks {
1258         CM_FPGAVER_MASK         = 0xFFFF0000,
1259         CM_CHIPREV_MASK         = 0x0000FF00,
1260         CM_CHIPMODE_MASK        = 0x0000000F,
1261 };
1262
1263 enum jme_chipmode_shifts {
1264         CM_FPGAVER_SHIFT        = 16,
1265         CM_CHIPREV_SHIFT        = 8,
1266 };
1267
1268 /*
1269  * Aggressive Power Mode Control
1270  */
1271 enum jme_apmc_bits {
1272         JME_APMC_PCIE_SD_EN     = 0x40000000,
1273         JME_APMC_PSEUDO_HP_EN   = 0x20000000,
1274         JME_APMC_EPIEN          = 0x04000000,
1275         JME_APMC_EPIEN_CTRL     = 0x03000000,
1276 };
1277
1278 enum jme_apmc_values {
1279         JME_APMC_EPIEN_CTRL_EN  = 0x02000000,
1280         JME_APMC_EPIEN_CTRL_DIS = 0x01000000,
1281 };
1282
1283 #define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000)
1284
1285 #ifdef REG_DEBUG
1286 static char *MAC_REG_NAME[] = {
1287         "JME_TXCS",      "JME_TXDBA_LO",  "JME_TXDBA_HI", "JME_TXQDC",
1288         "JME_TXNDA",     "JME_TXMCS",     "JME_TXPFC",    "JME_TXTRHD",
1289         "JME_RXCS",      "JME_RXDBA_LO",  "JME_RXDBA_HI", "JME_RXQDC",
1290         "JME_RXNDA",     "JME_RXMCS",     "JME_RXUMA_LO", "JME_RXUMA_HI",
1291         "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP",    "JME_WFOI",
1292         "JME_SMI",       "JME_GHC",       "UNKNOWN",      "UNKNOWN",
1293         "JME_PMCS"};
1294
1295 static char *PE_REG_NAME[] = {
1296         "UNKNOWN",      "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1297         "UNKNOWN",      "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1298         "UNKNOWN",      "UNKNOWN",     "JME_PHY_CS", "UNKNOWN",
1299         "JME_PHY_LINK", "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1300         "JME_SMBCSR",   "JME_SMBINTF"};
1301
1302 static char *MISC_REG_NAME[] = {
1303         "JME_TMCSR",  "JME_GPIO",     "JME_GPREG0",  "JME_GPREG1",
1304         "JME_IEVE",   "JME_IREQ",     "JME_IENS",    "JME_IENC",
1305         "JME_PCCRX0", "JME_PCCRX1",   "JME_PCCRX2",  "JME_PCCRX3",
1306         "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO",
1307         "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1308         "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1309         "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1310         "JME_TIMER1", "JME_TIMER2",   "UNKNOWN",     "JME_APMC",
1311         "JME_PCCSRX0"};
1312
1313 static inline void reg_dbg(const struct jme_adapter *jme,
1314                 const char *msg, u32 val, u32 reg)
1315 {
1316         const char *regname;
1317         switch (reg & 0xF00) {
1318         case 0x000:
1319                 regname = MAC_REG_NAME[(reg & 0xFF) >> 2];
1320                 break;
1321         case 0x400:
1322                 regname = PE_REG_NAME[(reg & 0xFF) >> 2];
1323                 break;
1324         case 0x800:
1325                 regname = MISC_REG_NAME[(reg & 0xFF) >> 2];
1326                 break;
1327         default:
1328                 regname = PE_REG_NAME[0];
1329         }
1330         printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name,
1331                         msg, val, regname);
1332 }
1333 #else
1334 static inline void reg_dbg(const struct jme_adapter *jme,
1335                 const char *msg, u32 val, u32 reg) {}
1336 #endif
1337
1338 /*
1339  * Read/Write MMaped I/O Registers
1340  */
1341 static inline u32 jread32(struct jme_adapter *jme, u32 reg)
1342 {
1343         return readl(jme->regs + reg);
1344 }
1345
1346 static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val)
1347 {
1348         reg_dbg(jme, "REG WRITE", val, reg);
1349         writel(val, jme->regs + reg);
1350         reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1351 }
1352
1353 static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val)
1354 {
1355         /*
1356          * Read after write should cause flush
1357          */
1358         reg_dbg(jme, "REG WRITE FLUSH", val, reg);
1359         writel(val, jme->regs + reg);
1360         readl(jme->regs + reg);
1361         reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1362 }
1363
1364 /*
1365  * PHY Regs
1366  */
1367 enum jme_phy_reg17_bit_masks {
1368         PREG17_SPEED            = 0xC000,
1369         PREG17_DUPLEX           = 0x2000,
1370         PREG17_SPDRSV           = 0x0800,
1371         PREG17_LNKUP            = 0x0400,
1372         PREG17_MDI              = 0x0040,
1373 };
1374
1375 enum jme_phy_reg17_vals {
1376         PREG17_SPEED_10M        = 0x0000,
1377         PREG17_SPEED_100M       = 0x4000,
1378         PREG17_SPEED_1000M      = 0x8000,
1379 };
1380
1381 #define BMSR_ANCOMP               0x0020
1382
1383 /*
1384  * Workaround
1385  */
1386 static inline int is_buggy250(unsigned short device, u8 chiprev)
1387 {
1388         return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
1389 }
1390
1391 static inline int new_phy_power_ctrl(u8 chip_main_rev)
1392 {
1393         return chip_main_rev >= 5;
1394 }
1395
1396 /*
1397  * Function prototypes
1398  */
1399 static int jme_set_settings(struct net_device *netdev,
1400                                 struct ethtool_cmd *ecmd);
1401 static void jme_set_multi(struct net_device *netdev);
1402
1403 #endif
1404