2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #ifndef __JME_H_INCLUDED__
25 #define __JME_H_INCLUDED__
27 #define DRV_NAME "jme"
28 #define DRV_VERSION "1.0.6.1-jmmod"
29 #define PFX DRV_NAME ": "
31 #define PCI_DEVICE_ID_JMICRON_JMC250 0x0250
32 #define PCI_DEVICE_ID_JMICRON_JMC260 0x0260
35 * Message related definitions
37 #define JME_DEF_MSG_ENABLE \
44 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
45 #define pr_err(fmt, arg...) \
46 printk(KERN_ERR fmt, ##arg)
48 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
49 #define netdev_err(netdev, fmt, arg...) \
54 #define tx_dbg(priv, fmt, args...) \
55 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args)
57 #define tx_dbg(priv, fmt, args...) \
60 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args); \
64 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
65 #define jme_msg(msglvl, type, priv, fmt, args...) \
66 if (netif_msg_##type(priv)) \
67 printk(msglvl "%s: " fmt, (priv)->dev->name, ## args)
69 #define msg_probe(priv, fmt, args...) \
70 jme_msg(KERN_INFO, probe, priv, fmt, ## args)
72 #define msg_link(priv, fmt, args...) \
73 jme_msg(KERN_INFO, link, priv, fmt, ## args)
75 #define msg_intr(priv, fmt, args...) \
76 jme_msg(KERN_INFO, intr, priv, fmt, ## args)
78 #define msg_rx_err(priv, fmt, args...) \
79 jme_msg(KERN_ERR, rx_err, priv, fmt, ## args)
81 #define msg_rx_status(priv, fmt, args...) \
82 jme_msg(KERN_INFO, rx_status, priv, fmt, ## args)
84 #define msg_tx_err(priv, fmt, args...) \
85 jme_msg(KERN_ERR, tx_err, priv, fmt, ## args)
87 #define msg_tx_done(priv, fmt, args...) \
88 jme_msg(KERN_INFO, tx_done, priv, fmt, ## args)
90 #define msg_tx_queued(priv, fmt, args...) \
91 jme_msg(KERN_INFO, tx_queued, priv, fmt, ## args)
93 #define msg_hw(priv, fmt, args...) \
94 jme_msg(KERN_ERR, hw, priv, fmt, ## args)
96 #define netif_info(priv, type, dev, fmt, args...) \
97 msg_ ## type(priv, fmt, ## args)
98 #define netif_err(priv, type, dev, fmt, args...) \
99 msg_ ## type(priv, fmt, ## args)
103 * Extra PCI Configuration space interface
105 #define PCI_DCSR_MRRS 0x59
106 #define PCI_DCSR_MRRS_MASK 0x70
108 enum pci_dcsr_mrrs_vals {
130 __u8 wn; /* Number of write actions */
131 __u8 rn; /* Number of read actions */
132 __u8 bitn; /* Number of bits per action */
133 __u8 spd; /* The maxim acceptable speed of controller, in MHz.*/
134 __u8 mode; /* CPOL, CPHA, and Duplex mode of SPI */
136 /* Internal use only */
140 u16 halfclk; /* Half of clock cycle calculated from spd, in ns */
143 enum jme_spi_op_bits {
144 SPI_MODE_CPHA = 0x01,
145 SPI_MODE_CPOL = 0x02,
149 #define HALF_US 500 /* 500 ns */
150 #define JMESPIIOCTL SIOCDEVPRIVATE
153 * Dynamic(adaptive)/Static PCC values
155 enum dynamic_pcc_values {
172 unsigned long last_bytes;
173 unsigned long last_pkts;
174 unsigned long intr_cnt;
176 unsigned char attempt;
179 #define PCC_INTERVAL_US 100000
180 #define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
181 #define PCC_P3_THRESHOLD (2 * 1024 * 1024)
182 #define PCC_P2_THRESHOLD 800
183 #define PCC_INTR_THRESHOLD 800
184 #define PCC_TX_TO 1000
190 * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
192 #define RING_DESC_ALIGN 16 /* Descriptor alignment */
193 #define TX_DESC_SIZE 16
195 #define TX_RING_ALLOC_SIZE(s) ((s * TX_DESC_SIZE) + RING_DESC_ALIGN)
255 enum jme_txdesc_flags_bits {
266 #define TXDESC_MSS_SHIFT 2
267 enum jme_txwbdesc_flags_bits {
270 TXWBFLAG_TMOUT = 0x20,
271 TXWBFLAG_TRYOUT = 0x10,
274 TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
279 #define RX_DESC_SIZE 16
281 #define RX_RING_ALLOC_SIZE(s) ((s * RX_DESC_SIZE) + RING_DESC_ALIGN)
282 #define RX_BUF_DMA_ALIGN 8
283 #define RX_PREPAD_SIZE 10
284 #define ETH_CRC_LEN 2
285 #define RX_VLANHDR_LEN 2
286 #define RX_EXTRA_LEN (RX_PREPAD_SIZE + \
333 enum jme_rxdesc_flags_bits {
339 enum jme_rxwbdesc_flags_bits {
340 RXWBFLAG_OWN = 0x8000,
341 RXWBFLAG_INT = 0x4000,
342 RXWBFLAG_MF = 0x2000,
343 RXWBFLAG_64BIT = 0x2000,
344 RXWBFLAG_TCPON = 0x1000,
345 RXWBFLAG_UDPON = 0x0800,
346 RXWBFLAG_IPCS = 0x0400,
347 RXWBFLAG_TCPCS = 0x0200,
348 RXWBFLAG_UDPCS = 0x0100,
349 RXWBFLAG_TAGON = 0x0080,
350 RXWBFLAG_IPV4 = 0x0040,
351 RXWBFLAG_IPV6 = 0x0020,
352 RXWBFLAG_PAUSE = 0x0010,
353 RXWBFLAG_MAGIC = 0x0008,
354 RXWBFLAG_WAKEUP = 0x0004,
355 RXWBFLAG_DEST = 0x0003,
356 RXWBFLAG_DEST_UNI = 0x0001,
357 RXWBFLAG_DEST_MUL = 0x0002,
358 RXWBFLAG_DEST_BRO = 0x0003,
361 enum jme_rxwbdesc_desccnt_mask {
362 RXWBDCNT_WBCPL = 0x80,
363 RXWBDCNT_DCNT = 0x7F,
366 enum jme_rxwbdesc_errstat_bits {
367 RXWBERR_LIMIT = 0x80,
368 RXWBERR_MIIER = 0x40,
369 RXWBERR_NIBON = 0x20,
370 RXWBERR_COLON = 0x10,
371 RXWBERR_ABORT = 0x08,
372 RXWBERR_SHORT = 0x04,
373 RXWBERR_OVERUN = 0x02,
374 RXWBERR_CRCERR = 0x01,
375 RXWBERR_ALLERR = 0xFF,
379 * Buffer information corresponding to ring descriptors.
381 struct jme_buffer_info {
386 unsigned long start_xmit;
390 * The structure holding buffer information and ring descriptors all together.
393 void *alloc; /* pointer to allocated memory */
394 void *desc; /* pointer to ring memory */
395 dma_addr_t dmaalloc; /* phys address of ring alloc */
396 dma_addr_t dma; /* phys address for ring dma */
398 /* Buffer information corresponding to each descriptor */
399 struct jme_buffer_info *bufinf;
402 atomic_t next_to_clean;
406 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
409 #define netdev_alloc_skb(dev, len) dev_alloc_skb(len)
410 #define PCI_VENDOR_ID_JMICRON 0x197B
413 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,19)
414 #define PCI_VDEVICE(vendor, device) \
415 PCI_VENDOR_ID_##vendor, (device), \
416 PCI_ANY_ID, PCI_ANY_ID, 0, 0
419 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
420 #define NET_STAT(priv) priv->stats
421 #define NETDEV_GET_STATS(netdev, fun_ptr) \
422 netdev->get_stats = fun_ptr
423 #define DECLARE_NET_DEVICE_STATS struct net_device_stats stats;
425 * CentOS 5.5 have *_hdr helpers back-ported
427 #ifdef RHEL_RELEASE_CODE
428 #if RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,5)
429 #define __DEFINE_IPHDR_HELPERS__
432 #define __DEFINE_IPHDR_HELPERS__
435 #define NET_STAT(priv) (priv->dev->stats)
436 #define NETDEV_GET_STATS(netdev, fun_ptr)
437 #define DECLARE_NET_DEVICE_STATS
440 #ifdef __DEFINE_IPHDR_HELPERS__
441 static inline struct iphdr *ip_hdr(const struct sk_buff *skb)
446 static inline struct ipv6hdr *ipv6_hdr(const struct sk_buff *skb)
448 return skb->nh.ipv6h;
451 static inline struct tcphdr *tcp_hdr(const struct sk_buff *skb)
457 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
458 #define DECLARE_NAPI_STRUCT
459 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
460 dev->poll = pollfn; \
462 #define JME_NAPI_HOLDER(holder) struct net_device *holder
463 #define JME_NAPI_WEIGHT(w) int *w
464 #define JME_NAPI_WEIGHT_VAL(w) *w
465 #define JME_NAPI_WEIGHT_SET(w, r) *w = r
466 #define DECLARE_NETDEV struct net_device *netdev = jme->dev;
467 #define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev)
468 #define JME_NAPI_ENABLE(priv) netif_poll_enable(priv->dev);
469 #define JME_NAPI_DISABLE(priv) netif_poll_disable(priv->dev);
470 #define JME_RX_SCHEDULE_PREP(priv) \
471 netif_rx_schedule_prep(priv->dev)
472 #define JME_RX_SCHEDULE(priv) \
473 __netif_rx_schedule(priv->dev);
475 #define DECLARE_NAPI_STRUCT struct napi_struct napi;
476 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
477 netif_napi_add(dev, napis, pollfn, q);
478 #define JME_NAPI_HOLDER(holder) struct napi_struct *holder
479 #define JME_NAPI_WEIGHT(w) int w
480 #define JME_NAPI_WEIGHT_VAL(w) w
481 #define JME_NAPI_WEIGHT_SET(w, r)
482 #define DECLARE_NETDEV
483 #define JME_RX_COMPLETE(dev, napis) napi_complete(napis)
484 #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
485 #define JME_NAPI_DISABLE(priv) \
486 if (!napi_disable_pending(&priv->napi)) \
487 napi_disable(&priv->napi);
488 #define JME_RX_SCHEDULE_PREP(priv) \
489 napi_schedule_prep(&priv->napi)
490 #define JME_RX_SCHEDULE(priv) \
491 __napi_schedule(&priv->napi);
495 * Jmac Adapter Private data
498 struct pci_dev *pdev;
499 struct net_device *dev;
501 struct mii_if_info mii_if;
502 struct jme_ring rxring[RX_RING_NR];
503 struct jme_ring txring[TX_RING_NR];
505 spinlock_t macaddr_lock;
506 spinlock_t rxmcs_lock;
507 struct tasklet_struct rxempty_task;
508 struct tasklet_struct rxclean_task;
509 struct tasklet_struct txclean_task;
510 struct tasklet_struct linkch_task;
511 struct tasklet_struct pcc_task;
522 u32 tx_wake_threshold;
526 unsigned int fpgaver;
527 unsigned int chiprev;
530 struct ethtool_cmd old_ecmd;
531 unsigned int old_mtu;
532 struct vlan_group *vlgrp;
533 struct dynpcc_info dpi;
535 atomic_t link_changing;
536 atomic_t tx_cleaning;
537 atomic_t rx_cleaning;
539 int (*jme_rx)(struct sk_buff *skb);
540 int (*jme_vlan_rx)(struct sk_buff *skb,
541 struct vlan_group *grp,
542 unsigned short vlan_tag);
544 DECLARE_NET_DEVICE_STATS
547 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
548 static struct net_device_stats *
549 jme_get_stats(struct net_device *netdev)
551 struct jme_adapter *jme = netdev_priv(netdev);
556 enum jme_flags_bits {
562 JME_FLAG_SHUTDOWN = 6,
565 #define TX_TIMEOUT (5 * HZ)
566 #define JME_REG_LEN 0x500
567 #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
569 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
570 static inline struct jme_adapter*
571 jme_napi_priv(struct net_device *holder)
573 struct jme_adapter *jme;
574 jme = netdev_priv(holder);
578 static inline struct jme_adapter*
579 jme_napi_priv(struct napi_struct *napi)
581 struct jme_adapter *jme;
582 jme = container_of(napi, struct jme_adapter, napi);
590 enum jme_iomap_offsets {
597 enum jme_iomap_lens {
604 enum jme_iomap_regs {
605 JME_TXCS = JME_MAC | 0x00, /* Transmit Control and Status */
606 JME_TXDBA_LO = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
607 JME_TXDBA_HI = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
608 JME_TXQDC = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
609 JME_TXNDA = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
610 JME_TXMCS = JME_MAC | 0x14, /* Transmit MAC Control Status */
611 JME_TXPFC = JME_MAC | 0x18, /* Transmit Pause Frame Control */
612 JME_TXTRHD = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
614 JME_RXCS = JME_MAC | 0x20, /* Receive Control and Status */
615 JME_RXDBA_LO = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
616 JME_RXDBA_HI = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
617 JME_RXQDC = JME_MAC | 0x2C, /* Receive Queue Desc Count */
618 JME_RXNDA = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
619 JME_RXMCS = JME_MAC | 0x34, /* Receive MAC Control Status */
620 JME_RXUMA_LO = JME_MAC | 0x38, /* Receive Unicast MAC Address */
621 JME_RXUMA_HI = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
622 JME_RXMCHT_LO = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
623 JME_RXMCHT_HI = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
624 JME_WFODP = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
625 JME_WFOI = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
627 JME_SMI = JME_MAC | 0x50, /* Station Management Interface */
628 JME_GHC = JME_MAC | 0x54, /* Global Host Control */
629 JME_PMCS = JME_MAC | 0x60, /* Power Management Control/Stat */
632 JME_PHY_CS = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
633 JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */
634 JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */
635 JME_SMBINTF = JME_PHY | 0x44, /* SMB Interface */
638 JME_TMCSR = JME_MISC | 0x00, /* Timer Control/Status Register */
639 JME_GPREG0 = JME_MISC | 0x08, /* General purpose REG-0 */
640 JME_GPREG1 = JME_MISC | 0x0C, /* General purpose REG-1 */
641 JME_IEVE = JME_MISC | 0x20, /* Interrupt Event Status */
642 JME_IREQ = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
643 JME_IENS = JME_MISC | 0x28, /* Intr Enable - Setting Port */
644 JME_IENC = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
645 JME_PCCRX0 = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
646 JME_PCCTX = JME_MISC | 0x40, /* PCC Control for TX Queues */
647 JME_CHIPMODE = JME_MISC | 0x44, /* Identify FPGA Version */
648 JME_SHBA_HI = JME_MISC | 0x48, /* Shadow Register Base HI */
649 JME_SHBA_LO = JME_MISC | 0x4C, /* Shadow Register Base LO */
650 JME_TIMER1 = JME_MISC | 0x70, /* Timer1 */
651 JME_TIMER2 = JME_MISC | 0x74, /* Timer2 */
652 JME_APMC = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
653 JME_PCCSRX0 = JME_MISC | 0x80, /* PCC Status of RX0 */
657 * TX Control/Status Bits
660 TXCS_QUEUE7S = 0x00008000,
661 TXCS_QUEUE6S = 0x00004000,
662 TXCS_QUEUE5S = 0x00002000,
663 TXCS_QUEUE4S = 0x00001000,
664 TXCS_QUEUE3S = 0x00000800,
665 TXCS_QUEUE2S = 0x00000400,
666 TXCS_QUEUE1S = 0x00000200,
667 TXCS_QUEUE0S = 0x00000100,
668 TXCS_FIFOTH = 0x000000C0,
669 TXCS_DMASIZE = 0x00000030,
670 TXCS_BURST = 0x00000004,
671 TXCS_ENABLE = 0x00000001,
674 enum jme_txcs_value {
675 TXCS_FIFOTH_16QW = 0x000000C0,
676 TXCS_FIFOTH_12QW = 0x00000080,
677 TXCS_FIFOTH_8QW = 0x00000040,
678 TXCS_FIFOTH_4QW = 0x00000000,
680 TXCS_DMASIZE_64B = 0x00000000,
681 TXCS_DMASIZE_128B = 0x00000010,
682 TXCS_DMASIZE_256B = 0x00000020,
683 TXCS_DMASIZE_512B = 0x00000030,
685 TXCS_SELECT_QUEUE0 = 0x00000000,
686 TXCS_SELECT_QUEUE1 = 0x00010000,
687 TXCS_SELECT_QUEUE2 = 0x00020000,
688 TXCS_SELECT_QUEUE3 = 0x00030000,
689 TXCS_SELECT_QUEUE4 = 0x00040000,
690 TXCS_SELECT_QUEUE5 = 0x00050000,
691 TXCS_SELECT_QUEUE6 = 0x00060000,
692 TXCS_SELECT_QUEUE7 = 0x00070000,
694 TXCS_DEFAULT = TXCS_FIFOTH_4QW |
698 #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
701 * TX MAC Control/Status Bits
703 enum jme_txmcs_bit_masks {
704 TXMCS_IFG2 = 0xC0000000,
705 TXMCS_IFG1 = 0x30000000,
706 TXMCS_TTHOLD = 0x00000300,
707 TXMCS_FBURST = 0x00000080,
708 TXMCS_CARRIEREXT = 0x00000040,
709 TXMCS_DEFER = 0x00000020,
710 TXMCS_BACKOFF = 0x00000010,
711 TXMCS_CARRIERSENSE = 0x00000008,
712 TXMCS_COLLISION = 0x00000004,
713 TXMCS_CRC = 0x00000002,
714 TXMCS_PADDING = 0x00000001,
717 enum jme_txmcs_values {
718 TXMCS_IFG2_6_4 = 0x00000000,
719 TXMCS_IFG2_8_5 = 0x40000000,
720 TXMCS_IFG2_10_6 = 0x80000000,
721 TXMCS_IFG2_12_7 = 0xC0000000,
723 TXMCS_IFG1_8_4 = 0x00000000,
724 TXMCS_IFG1_12_6 = 0x10000000,
725 TXMCS_IFG1_16_8 = 0x20000000,
726 TXMCS_IFG1_20_10 = 0x30000000,
728 TXMCS_TTHOLD_1_8 = 0x00000000,
729 TXMCS_TTHOLD_1_4 = 0x00000100,
730 TXMCS_TTHOLD_1_2 = 0x00000200,
731 TXMCS_TTHOLD_FULL = 0x00000300,
733 TXMCS_DEFAULT = TXMCS_IFG2_8_5 |
741 enum jme_txpfc_bits_masks {
742 TXPFC_VLAN_TAG = 0xFFFF0000,
743 TXPFC_VLAN_EN = 0x00008000,
744 TXPFC_PF_EN = 0x00000001,
747 enum jme_txtrhd_bits_masks {
748 TXTRHD_TXPEN = 0x80000000,
749 TXTRHD_TXP = 0x7FFFFF00,
750 TXTRHD_TXREN = 0x00000080,
751 TXTRHD_TXRL = 0x0000007F,
754 enum jme_txtrhd_shifts {
755 TXTRHD_TXP_SHIFT = 8,
756 TXTRHD_TXRL_SHIFT = 0,
760 * RX Control/Status Bits
762 enum jme_rxcs_bit_masks {
763 /* FIFO full threshold for transmitting Tx Pause Packet */
764 RXCS_FIFOTHTP = 0x30000000,
765 /* FIFO threshold for processing next packet */
766 RXCS_FIFOTHNP = 0x0C000000,
767 RXCS_DMAREQSZ = 0x03000000, /* DMA Request Size */
768 RXCS_QUEUESEL = 0x00030000, /* Queue selection */
769 RXCS_RETRYGAP = 0x0000F000, /* RX Desc full retry gap */
770 RXCS_RETRYCNT = 0x00000F00, /* RX Desc full retry counter */
771 RXCS_WAKEUP = 0x00000040, /* Enable receive wakeup packet */
772 RXCS_MAGIC = 0x00000020, /* Enable receive magic packet */
773 RXCS_SHORT = 0x00000010, /* Enable receive short packet */
774 RXCS_ABORT = 0x00000008, /* Enable receive errorr packet */
775 RXCS_QST = 0x00000004, /* Receive queue start */
776 RXCS_SUSPEND = 0x00000002,
777 RXCS_ENABLE = 0x00000001,
780 enum jme_rxcs_values {
781 RXCS_FIFOTHTP_16T = 0x00000000,
782 RXCS_FIFOTHTP_32T = 0x10000000,
783 RXCS_FIFOTHTP_64T = 0x20000000,
784 RXCS_FIFOTHTP_128T = 0x30000000,
786 RXCS_FIFOTHNP_16QW = 0x00000000,
787 RXCS_FIFOTHNP_32QW = 0x04000000,
788 RXCS_FIFOTHNP_64QW = 0x08000000,
789 RXCS_FIFOTHNP_128QW = 0x0C000000,
791 RXCS_DMAREQSZ_16B = 0x00000000,
792 RXCS_DMAREQSZ_32B = 0x01000000,
793 RXCS_DMAREQSZ_64B = 0x02000000,
794 RXCS_DMAREQSZ_128B = 0x03000000,
796 RXCS_QUEUESEL_Q0 = 0x00000000,
797 RXCS_QUEUESEL_Q1 = 0x00010000,
798 RXCS_QUEUESEL_Q2 = 0x00020000,
799 RXCS_QUEUESEL_Q3 = 0x00030000,
801 RXCS_RETRYGAP_256ns = 0x00000000,
802 RXCS_RETRYGAP_512ns = 0x00001000,
803 RXCS_RETRYGAP_1024ns = 0x00002000,
804 RXCS_RETRYGAP_2048ns = 0x00003000,
805 RXCS_RETRYGAP_4096ns = 0x00004000,
806 RXCS_RETRYGAP_8192ns = 0x00005000,
807 RXCS_RETRYGAP_16384ns = 0x00006000,
808 RXCS_RETRYGAP_32768ns = 0x00007000,
810 RXCS_RETRYCNT_0 = 0x00000000,
811 RXCS_RETRYCNT_4 = 0x00000100,
812 RXCS_RETRYCNT_8 = 0x00000200,
813 RXCS_RETRYCNT_12 = 0x00000300,
814 RXCS_RETRYCNT_16 = 0x00000400,
815 RXCS_RETRYCNT_20 = 0x00000500,
816 RXCS_RETRYCNT_24 = 0x00000600,
817 RXCS_RETRYCNT_28 = 0x00000700,
818 RXCS_RETRYCNT_32 = 0x00000800,
819 RXCS_RETRYCNT_36 = 0x00000900,
820 RXCS_RETRYCNT_40 = 0x00000A00,
821 RXCS_RETRYCNT_44 = 0x00000B00,
822 RXCS_RETRYCNT_48 = 0x00000C00,
823 RXCS_RETRYCNT_52 = 0x00000D00,
824 RXCS_RETRYCNT_56 = 0x00000E00,
825 RXCS_RETRYCNT_60 = 0x00000F00,
827 RXCS_DEFAULT = RXCS_FIFOTHTP_128T |
828 RXCS_FIFOTHNP_128QW |
830 RXCS_RETRYGAP_256ns |
834 #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
837 * RX MAC Control/Status Bits
839 enum jme_rxmcs_bits {
840 RXMCS_ALLFRAME = 0x00000800,
841 RXMCS_BRDFRAME = 0x00000400,
842 RXMCS_MULFRAME = 0x00000200,
843 RXMCS_UNIFRAME = 0x00000100,
844 RXMCS_ALLMULFRAME = 0x00000080,
845 RXMCS_MULFILTERED = 0x00000040,
846 RXMCS_RXCOLLDEC = 0x00000020,
847 RXMCS_FLOWCTRL = 0x00000008,
848 RXMCS_VTAGRM = 0x00000004,
849 RXMCS_PREPAD = 0x00000002,
850 RXMCS_CHECKSUM = 0x00000001,
852 RXMCS_DEFAULT = RXMCS_VTAGRM |
859 * Wakeup Frame setup interface registers
861 #define WAKEUP_FRAME_NR 8
862 #define WAKEUP_FRAME_MASK_DWNR 4
864 enum jme_wfoi_bit_masks {
865 WFOI_MASK_SEL = 0x00000070,
866 WFOI_CRC_SEL = 0x00000008,
867 WFOI_FRAME_SEL = 0x00000007,
870 enum jme_wfoi_shifts {
875 * SMI Related definitions
877 enum jme_smi_bit_mask {
878 SMI_DATA_MASK = 0xFFFF0000,
879 SMI_REG_ADDR_MASK = 0x0000F800,
880 SMI_PHY_ADDR_MASK = 0x000007C0,
881 SMI_OP_WRITE = 0x00000020,
882 /* Set to 1, after req done it'll be cleared to 0 */
883 SMI_OP_REQ = 0x00000010,
884 SMI_OP_MDIO = 0x00000008, /* Software assess In/Out */
885 SMI_OP_MDOE = 0x00000004, /* Software Output Enable */
886 SMI_OP_MDC = 0x00000002, /* Software CLK Control */
887 SMI_OP_MDEN = 0x00000001, /* Software access Enable */
890 enum jme_smi_bit_shift {
892 SMI_REG_ADDR_SHIFT = 11,
893 SMI_PHY_ADDR_SHIFT = 6,
896 static inline u32 smi_reg_addr(int x)
898 return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
901 static inline u32 smi_phy_addr(int x)
903 return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
906 #define JME_PHY_TIMEOUT 100 /* 100 msec */
907 #define JME_PHY_REG_NR 32
910 * Global Host Control
912 enum jme_ghc_bit_mask {
913 GHC_SWRST = 0x40000000,
914 GHC_DPX = 0x00000040,
915 GHC_SPEED = 0x00000030,
916 GHC_LINK_POLL = 0x00000001,
919 enum jme_ghc_speed_val {
920 GHC_SPEED_10M = 0x00000010,
921 GHC_SPEED_100M = 0x00000020,
922 GHC_SPEED_1000M = 0x00000030,
925 enum jme_ghc_to_clk {
926 GHC_TO_CLK_OFF = 0x00000000,
927 GHC_TO_CLK_GPHY = 0x00400000,
928 GHC_TO_CLK_PCIE = 0x00800000,
929 GHC_TO_CLK_INVALID = 0x00C00000,
932 enum jme_ghc_txmac_clk {
933 GHC_TXMAC_CLK_OFF = 0x00000000,
934 GHC_TXMAC_CLK_GPHY = 0x00100000,
935 GHC_TXMAC_CLK_PCIE = 0x00200000,
936 GHC_TXMAC_CLK_INVALID = 0x00300000,
940 * Power management control and status register
942 enum jme_pmcs_bit_masks {
943 PMCS_WF7DET = 0x80000000,
944 PMCS_WF6DET = 0x40000000,
945 PMCS_WF5DET = 0x20000000,
946 PMCS_WF4DET = 0x10000000,
947 PMCS_WF3DET = 0x08000000,
948 PMCS_WF2DET = 0x04000000,
949 PMCS_WF1DET = 0x02000000,
950 PMCS_WF0DET = 0x01000000,
951 PMCS_LFDET = 0x00040000,
952 PMCS_LRDET = 0x00020000,
953 PMCS_MFDET = 0x00010000,
954 PMCS_WF7EN = 0x00008000,
955 PMCS_WF6EN = 0x00004000,
956 PMCS_WF5EN = 0x00002000,
957 PMCS_WF4EN = 0x00001000,
958 PMCS_WF3EN = 0x00000800,
959 PMCS_WF2EN = 0x00000400,
960 PMCS_WF1EN = 0x00000200,
961 PMCS_WF0EN = 0x00000100,
962 PMCS_LFEN = 0x00000004,
963 PMCS_LREN = 0x00000002,
964 PMCS_MFEN = 0x00000001,
968 * Giga PHY Status Registers
970 enum jme_phy_link_bit_mask {
971 PHY_LINK_SPEED_MASK = 0x0000C000,
972 PHY_LINK_DUPLEX = 0x00002000,
973 PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800,
974 PHY_LINK_UP = 0x00000400,
975 PHY_LINK_AUTONEG_COMPLETE = 0x00000200,
976 PHY_LINK_MDI_STAT = 0x00000040,
979 enum jme_phy_link_speed_val {
980 PHY_LINK_SPEED_10M = 0x00000000,
981 PHY_LINK_SPEED_100M = 0x00004000,
982 PHY_LINK_SPEED_1000M = 0x00008000,
985 #define JME_SPDRSV_TIMEOUT 500 /* 500 us */
988 * SMB Control and Status
990 enum jme_smbcsr_bit_mask {
991 SMBCSR_CNACK = 0x00020000,
992 SMBCSR_RELOAD = 0x00010000,
993 SMBCSR_EEPROMD = 0x00000020,
994 SMBCSR_INITDONE = 0x00000010,
995 SMBCSR_BUSY = 0x0000000F,
998 enum jme_smbintf_bit_mask {
999 SMBINTF_HWDATR = 0xFF000000,
1000 SMBINTF_HWDATW = 0x00FF0000,
1001 SMBINTF_HWADDR = 0x0000FF00,
1002 SMBINTF_HWRWN = 0x00000020,
1003 SMBINTF_HWCMD = 0x00000010,
1004 SMBINTF_FASTM = 0x00000008,
1005 SMBINTF_GPIOSCL = 0x00000004,
1006 SMBINTF_GPIOSDA = 0x00000002,
1007 SMBINTF_GPIOEN = 0x00000001,
1010 enum jme_smbintf_vals {
1011 SMBINTF_HWRWN_READ = 0x00000020,
1012 SMBINTF_HWRWN_WRITE = 0x00000000,
1015 enum jme_smbintf_shifts {
1016 SMBINTF_HWDATR_SHIFT = 24,
1017 SMBINTF_HWDATW_SHIFT = 16,
1018 SMBINTF_HWADDR_SHIFT = 8,
1021 #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
1022 #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
1023 #define JME_SMB_LEN 256
1024 #define JME_EEPROM_MAGIC 0x250
1027 * Timer Control/Status Register
1029 enum jme_tmcsr_bit_masks {
1030 TMCSR_SWIT = 0x80000000,
1031 TMCSR_EN = 0x01000000,
1032 TMCSR_CNT = 0x00FFFFFF,
1036 * General Purpose REG-0
1038 enum jme_gpreg0_masks {
1039 GPREG0_DISSH = 0xFF000000,
1040 GPREG0_PCIRLMT = 0x00300000,
1041 GPREG0_PCCNOMUTCLR = 0x00040000,
1042 GPREG0_LNKINTPOLL = 0x00001000,
1043 GPREG0_PCCTMR = 0x00000300,
1044 GPREG0_PHYADDR = 0x0000001F,
1047 enum jme_gpreg0_vals {
1048 GPREG0_DISSH_DW7 = 0x80000000,
1049 GPREG0_DISSH_DW6 = 0x40000000,
1050 GPREG0_DISSH_DW5 = 0x20000000,
1051 GPREG0_DISSH_DW4 = 0x10000000,
1052 GPREG0_DISSH_DW3 = 0x08000000,
1053 GPREG0_DISSH_DW2 = 0x04000000,
1054 GPREG0_DISSH_DW1 = 0x02000000,
1055 GPREG0_DISSH_DW0 = 0x01000000,
1056 GPREG0_DISSH_ALL = 0xFF000000,
1058 GPREG0_PCIRLMT_8 = 0x00000000,
1059 GPREG0_PCIRLMT_6 = 0x00100000,
1060 GPREG0_PCIRLMT_5 = 0x00200000,
1061 GPREG0_PCIRLMT_4 = 0x00300000,
1063 GPREG0_PCCTMR_16ns = 0x00000000,
1064 GPREG0_PCCTMR_256ns = 0x00000100,
1065 GPREG0_PCCTMR_1us = 0x00000200,
1066 GPREG0_PCCTMR_1ms = 0x00000300,
1068 GPREG0_PHYADDR_1 = 0x00000001,
1070 GPREG0_DEFAULT = GPREG0_PCIRLMT_4 |
1076 * General Purpose REG-1
1077 * Note: All theses bits defined here are for
1078 * Chip mode revision 0x11 only
1080 enum jme_gpreg1_masks {
1081 GPREG1_INTRDELAYUNIT = 0x00000018,
1082 GPREG1_INTRDELAYENABLE = 0x00000007,
1085 enum jme_gpreg1_vals {
1086 GPREG1_RSSPATCH = 0x00000040,
1087 GPREG1_HALFMODEPATCH = 0x00000020,
1089 GPREG1_INTDLYUNIT_16NS = 0x00000000,
1090 GPREG1_INTDLYUNIT_256NS = 0x00000008,
1091 GPREG1_INTDLYUNIT_1US = 0x00000010,
1092 GPREG1_INTDLYUNIT_16US = 0x00000018,
1094 GPREG1_INTDLYEN_1U = 0x00000001,
1095 GPREG1_INTDLYEN_2U = 0x00000002,
1096 GPREG1_INTDLYEN_3U = 0x00000003,
1097 GPREG1_INTDLYEN_4U = 0x00000004,
1098 GPREG1_INTDLYEN_5U = 0x00000005,
1099 GPREG1_INTDLYEN_6U = 0x00000006,
1100 GPREG1_INTDLYEN_7U = 0x00000007,
1102 GPREG1_DEFAULT = 0x00000000,
1106 * Interrupt Status Bits
1108 enum jme_interrupt_bits {
1109 INTR_SWINTR = 0x80000000,
1110 INTR_TMINTR = 0x40000000,
1111 INTR_LINKCH = 0x20000000,
1112 INTR_PAUSERCV = 0x10000000,
1113 INTR_MAGICRCV = 0x08000000,
1114 INTR_WAKERCV = 0x04000000,
1115 INTR_PCCRX0TO = 0x02000000,
1116 INTR_PCCRX1TO = 0x01000000,
1117 INTR_PCCRX2TO = 0x00800000,
1118 INTR_PCCRX3TO = 0x00400000,
1119 INTR_PCCTXTO = 0x00200000,
1120 INTR_PCCRX0 = 0x00100000,
1121 INTR_PCCRX1 = 0x00080000,
1122 INTR_PCCRX2 = 0x00040000,
1123 INTR_PCCRX3 = 0x00020000,
1124 INTR_PCCTX = 0x00010000,
1125 INTR_RX3EMP = 0x00008000,
1126 INTR_RX2EMP = 0x00004000,
1127 INTR_RX1EMP = 0x00002000,
1128 INTR_RX0EMP = 0x00001000,
1129 INTR_RX3 = 0x00000800,
1130 INTR_RX2 = 0x00000400,
1131 INTR_RX1 = 0x00000200,
1132 INTR_RX0 = 0x00000100,
1133 INTR_TX7 = 0x00000080,
1134 INTR_TX6 = 0x00000040,
1135 INTR_TX5 = 0x00000020,
1136 INTR_TX4 = 0x00000010,
1137 INTR_TX3 = 0x00000008,
1138 INTR_TX2 = 0x00000004,
1139 INTR_TX1 = 0x00000002,
1140 INTR_TX0 = 0x00000001,
1143 static const u32 INTR_ENABLE = INTR_SWINTR |
1153 * PCC Control Registers
1155 enum jme_pccrx_masks {
1156 PCCRXTO_MASK = 0xFFFF0000,
1157 PCCRX_MASK = 0x0000FF00,
1160 enum jme_pcctx_masks {
1161 PCCTXTO_MASK = 0xFFFF0000,
1162 PCCTX_MASK = 0x0000FF00,
1163 PCCTX_QS_MASK = 0x000000FF,
1166 enum jme_pccrx_shifts {
1171 enum jme_pcctx_shifts {
1176 enum jme_pcctx_bits {
1177 PCCTXQ0_EN = 0x00000001,
1178 PCCTXQ1_EN = 0x00000002,
1179 PCCTXQ2_EN = 0x00000004,
1180 PCCTXQ3_EN = 0x00000008,
1181 PCCTXQ4_EN = 0x00000010,
1182 PCCTXQ5_EN = 0x00000020,
1183 PCCTXQ6_EN = 0x00000040,
1184 PCCTXQ7_EN = 0x00000080,
1188 * Chip Mode Register
1190 enum jme_chipmode_bit_masks {
1191 CM_FPGAVER_MASK = 0xFFFF0000,
1192 CM_CHIPREV_MASK = 0x0000FF00,
1193 CM_CHIPMODE_MASK = 0x0000000F,
1196 enum jme_chipmode_shifts {
1197 CM_FPGAVER_SHIFT = 16,
1198 CM_CHIPREV_SHIFT = 8,
1202 * Aggressive Power Mode Control
1204 enum jme_apmc_bits {
1205 JME_APMC_PCIE_SD_EN = 0x40000000,
1206 JME_APMC_PSEUDO_HP_EN = 0x20000000,
1207 JME_APMC_EPIEN = 0x04000000,
1208 JME_APMC_EPIEN_CTRL = 0x03000000,
1211 enum jme_apmc_values {
1212 JME_APMC_EPIEN_CTRL_EN = 0x02000000,
1213 JME_APMC_EPIEN_CTRL_DIS = 0x01000000,
1216 #define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000)
1219 static char *MAC_REG_NAME[] = {
1220 "JME_TXCS", "JME_TXDBA_LO", "JME_TXDBA_HI", "JME_TXQDC",
1221 "JME_TXNDA", "JME_TXMCS", "JME_TXPFC", "JME_TXTRHD",
1222 "JME_RXCS", "JME_RXDBA_LO", "JME_RXDBA_HI", "JME_RXQDC",
1223 "JME_RXNDA", "JME_RXMCS", "JME_RXUMA_LO", "JME_RXUMA_HI",
1224 "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP", "JME_WFOI",
1225 "JME_SMI", "JME_GHC", "UNKNOWN", "UNKNOWN",
1228 static char *PE_REG_NAME[] = {
1229 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1230 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1231 "UNKNOWN", "UNKNOWN", "JME_PHY_CS", "UNKNOWN",
1232 "JME_PHY_LINK", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1233 "JME_SMBCSR", "JME_SMBINTF"};
1235 static char *MISC_REG_NAME[] = {
1236 "JME_TMCSR", "JME_GPIO", "JME_GPREG0", "JME_GPREG1",
1237 "JME_IEVE", "JME_IREQ", "JME_IENS", "JME_IENC",
1238 "JME_PCCRX0", "JME_PCCRX1", "JME_PCCRX2", "JME_PCCRX3",
1239 "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO",
1240 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1241 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1242 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1243 "JME_TIMER1", "JME_TIMER2", "UNKNOWN", "JME_APMC",
1246 static inline void reg_dbg(const struct jme_adapter *jme,
1247 const char *msg, u32 val, u32 reg)
1249 const char *regname;
1250 switch (reg & 0xF00) {
1252 regname = MAC_REG_NAME[(reg & 0xFF) >> 2];
1255 regname = PE_REG_NAME[(reg & 0xFF) >> 2];
1258 regname = MISC_REG_NAME[(reg & 0xFF) >> 2];
1261 regname = PE_REG_NAME[0];
1263 printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name,
1267 static inline void reg_dbg(const struct jme_adapter *jme,
1268 const char *msg, u32 val, u32 reg) {}
1272 * Read/Write MMaped I/O Registers
1274 static inline u32 jread32(struct jme_adapter *jme, u32 reg)
1276 return readl(jme->regs + reg);
1279 static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val)
1281 reg_dbg(jme, "REG WRITE", val, reg);
1282 writel(val, jme->regs + reg);
1283 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1286 static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val)
1289 * Read after write should cause flush
1291 reg_dbg(jme, "REG WRITE FLUSH", val, reg);
1292 writel(val, jme->regs + reg);
1293 readl(jme->regs + reg);
1294 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1300 enum jme_phy_reg17_bit_masks {
1301 PREG17_SPEED = 0xC000,
1302 PREG17_DUPLEX = 0x2000,
1303 PREG17_SPDRSV = 0x0800,
1304 PREG17_LNKUP = 0x0400,
1305 PREG17_MDI = 0x0040,
1308 enum jme_phy_reg17_vals {
1309 PREG17_SPEED_10M = 0x0000,
1310 PREG17_SPEED_100M = 0x4000,
1311 PREG17_SPEED_1000M = 0x8000,
1314 #define BMSR_ANCOMP 0x0020
1319 static inline int is_buggy250(unsigned short device, unsigned int chiprev)
1321 return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
1325 * Function prototypes
1327 static int jme_set_settings(struct net_device *netdev,
1328 struct ethtool_cmd *ecmd);
1329 static void jme_set_multi(struct net_device *netdev);