jme.c

   1 /*
   2  * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
   3  *
   4  * Copyright 2008 JMicron Technology Corporation
   5  * http://www.jmicron.com/
   6  *
   7  * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  *
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/pci.h>
  27 #include <linux/netdevice.h>
  28 #include <linux/etherdevice.h>
  29 #include <linux/ethtool.h>
  30 #include <linux/mii.h>
  31 #include <linux/crc32.h>
  32 #include <linux/delay.h>
  33 #include <linux/spinlock.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/ipv6.h>
  37 #include <linux/tcp.h>
  38 #include <linux/udp.h>
  39 #include <linux/if_vlan.h>
  40 #include <net/ip6_checksum.h>
  41 #include "jme.h"
  42
  43 static int force_pseudohp = -1;
  44 static int no_pseudohp = -1;
  45 static int no_extplug = -1;
  46 module_param(force_pseudohp, int, 0);
  47 MODULE_PARM_DESC(force_pseudohp,
  48         "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
  49 module_param(no_pseudohp, int, 0);
  50 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
  51 module_param(no_extplug, int, 0);
  52 MODULE_PARM_DESC(no_extplug,
  53         "Do not use external plug signal for pseudo hot-plug.");
  54
  55 static int
  56 jme_mdio_read(struct net_device *netdev, int phy, int reg)
  57 {
  58         struct jme_adapter *jme = netdev_priv(netdev);
  59         int i, val, again = (reg == MII_BMSR) ? 1 : 0;
  60
  61 read_again:
  62         jwrite32(jme, JME_SMI, SMI_OP_REQ |
  63                                 smi_phy_addr(phy) |
  64                                 smi_reg_addr(reg));
  65
  66         wmb();
  67         for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
  68                 udelay(20);
  69                 val = jread32(jme, JME_SMI);
  70                 if ((val & SMI_OP_REQ) == 0)
  71                         break;
  72         }
  73
  74         if (i == 0) {
  75                 jeprintk(jme->pdev, "phy(%d) read timeout : %d\n", phy, reg);
  76                 return 0;
  77         }
  78
  79         if (again--)
  80                 goto read_again;
  81
  82         return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
  83 }
  84
  85 static void
  86 jme_mdio_write(struct net_device *netdev,
  87                                 int phy, int reg, int val)
  88 {
  89         struct jme_adapter *jme = netdev_priv(netdev);
  90         int i;
  91
  92         jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
  93                 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
  94                 smi_phy_addr(phy) | smi_reg_addr(reg));
  95
  96         wmb();
  97         for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
  98                 udelay(20);
  99                 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
 100                         break;
 101         }
 102
 103         if (i == 0)
 104                 jeprintk(jme->pdev, "phy(%d) write timeout : %d\n", phy, reg);
 105
 106         return;
 107 }
 108
 109 static inline void
 110 jme_reset_phy_processor(struct jme_adapter *jme)
 111 {
 112         u32 val;
 113
 114         jme_mdio_write(jme->dev,
 115                         jme->mii_if.phy_id,
 116                         MII_ADVERTISE, ADVERTISE_ALL |
 117                         ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
 118
 119         if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
 120                 jme_mdio_write(jme->dev,
 121                                 jme->mii_if.phy_id,
 122                                 MII_CTRL1000,
 123                                 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 124
 125         val = jme_mdio_read(jme->dev,
 126                                 jme->mii_if.phy_id,
 127                                 MII_BMCR);
 128
 129         jme_mdio_write(jme->dev,
 130                         jme->mii_if.phy_id,
 131                         MII_BMCR, val | BMCR_RESET);
 132
 133         return;
 134 }
 135
 136 static void
 137 jme_setup_wakeup_frame(struct jme_adapter *jme,
 138                 u32 *mask, u32 crc, int fnr)
 139 {
 140         int i;
 141
 142         /*
 143          * Setup CRC pattern
 144          */
 145         jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
 146         wmb();
 147         jwrite32(jme, JME_WFODP, crc);
 148         wmb();
 149
 150         /*
 151          * Setup Mask
 152          */
 153         for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
 154                 jwrite32(jme, JME_WFOI,
 155                                 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
 156                                 (fnr & WFOI_FRAME_SEL));
 157                 wmb();
 158                 jwrite32(jme, JME_WFODP, mask[i]);
 159                 wmb();
 160         }
 161 }
 162
 163 static inline void
 164 jme_reset_mac_processor(struct jme_adapter *jme)
 165 {
 166         u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
 167         u32 crc = 0xCDCDCDCD;
 168         u32 gpreg0;
 169         int i;
 170
 171         jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
 172         udelay(2);
 173         jwrite32(jme, JME_GHC, jme->reg_ghc);
 174
 175         jwrite32(jme, JME_RXDBA_LO, 0x00000000);
 176         jwrite32(jme, JME_RXDBA_HI, 0x00000000);
 177         jwrite32(jme, JME_RXQDC, 0x00000000);
 178         jwrite32(jme, JME_RXNDA, 0x00000000);
 179         jwrite32(jme, JME_TXDBA_LO, 0x00000000);
 180         jwrite32(jme, JME_TXDBA_HI, 0x00000000);
 181         jwrite32(jme, JME_TXQDC, 0x00000000);
 182         jwrite32(jme, JME_TXNDA, 0x00000000);
 183
 184         jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
 185         jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
 186         for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
 187                 jme_setup_wakeup_frame(jme, mask, crc, i);
 188         if (jme->fpgaver)
 189                 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
 190         else
 191                 gpreg0 = GPREG0_DEFAULT;
 192         jwrite32(jme, JME_GPREG0, gpreg0);
 193         jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
 194 }
 195
 196 static inline void
 197 jme_reset_ghc_speed(struct jme_adapter *jme)
 198 {
 199         jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
 200         jwrite32(jme, JME_GHC, jme->reg_ghc);
 201 }
 202
 203 static inline void
 204 jme_clear_pm(struct jme_adapter *jme)
 205 {
 206         jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
 207         pci_set_power_state(jme->pdev, PCI_D0);
 208         pci_enable_wake(jme->pdev, PCI_D0, false);
 209 }
 210
 211 static int
 212 jme_reload_eeprom(struct jme_adapter *jme)
 213 {
 214         u32 val;
 215         int i;
 216
 217         val = jread32(jme, JME_SMBCSR);
 218
 219         if (val & SMBCSR_EEPROMD) {
 220                 val |= SMBCSR_CNACK;
 221                 jwrite32(jme, JME_SMBCSR, val);
 222                 val |= SMBCSR_RELOAD;
 223                 jwrite32(jme, JME_SMBCSR, val);
 224                 mdelay(12);
 225
 226                 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
 227                         mdelay(1);
 228                         if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
 229                                 break;
 230                 }
 231
 232                 if (i == 0) {
 233                         jeprintk(jme->pdev, "eeprom reload timeout\n");
 234                         return -EIO;
 235                 }
 236         }
 237
 238         return 0;
 239 }
 240
 241 static void
 242 jme_load_macaddr(struct net_device *netdev)
 243 {
 244         struct jme_adapter *jme = netdev_priv(netdev);
 245         unsigned char macaddr[6];
 246         u32 val;
 247
 248         spin_lock_bh(&jme->macaddr_lock);
 249         val = jread32(jme, JME_RXUMA_LO);
 250         macaddr[0] = (val >>  0) & 0xFF;
 251         macaddr[1] = (val >>  8) & 0xFF;
 252         macaddr[2] = (val >> 16) & 0xFF;
 253         macaddr[3] = (val >> 24) & 0xFF;
 254         val = jread32(jme, JME_RXUMA_HI);
 255         macaddr[4] = (val >>  0) & 0xFF;
 256         macaddr[5] = (val >>  8) & 0xFF;
 257         memcpy(netdev->dev_addr, macaddr, 6);
 258         spin_unlock_bh(&jme->macaddr_lock);
 259 }
 260
 261 static inline void
 262 jme_set_rx_pcc(struct jme_adapter *jme, int p)
 263 {
 264         switch (p) {
 265         case PCC_OFF:
 266                 jwrite32(jme, JME_PCCRX0,
 267                         ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
 268                         ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
 269                 break;
 270         case PCC_P1:
 271                 jwrite32(jme, JME_PCCRX0,
 272                         ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
 273                         ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
 274                 break;
 275         case PCC_P2:
 276                 jwrite32(jme, JME_PCCRX0,
 277                         ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
 278                         ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
 279                 break;
 280         case PCC_P3:
 281                 jwrite32(jme, JME_PCCRX0,
 282                         ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
 283                         ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
 284                 break;
 285         default:
 286                 break;
 287         }
 288         wmb();
 289
 290         if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
 291                 msg_rx_status(jme, "Switched to PCC_P%d\n", p);
 292 }
 293
 294 static void
 295 jme_start_irq(struct jme_adapter *jme)
 296 {
 297         register struct dynpcc_info *dpi = &(jme->dpi);
 298
 299         jme_set_rx_pcc(jme, PCC_P1);
 300         dpi->cur                = PCC_P1;
 301         dpi->attempt            = PCC_P1;
 302         dpi->cnt                = 0;
 303
 304         jwrite32(jme, JME_PCCTX,
 305                         ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
 306                         ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
 307                         PCCTXQ0_EN
 308                 );
 309
 310         /*
 311          * Enable Interrupts
 312          */
 313         jwrite32(jme, JME_IENS, INTR_ENABLE);
 314 }
 315
 316 static inline void
 317 jme_stop_irq(struct jme_adapter *jme)
 318 {
 319         /*
 320          * Disable Interrupts
 321          */
 322         jwrite32f(jme, JME_IENC, INTR_ENABLE);
 323 }
 324
 325 static inline void
 326 jme_enable_shadow(struct jme_adapter *jme)
 327 {
 328         jwrite32(jme,
 329                  JME_SHBA_LO,
 330                  ((u32)jme->shadow_dma & ~((u32)0x1F)) | SHBA_POSTEN);
 331 }
 332
 333 static inline void
 334 jme_disable_shadow(struct jme_adapter *jme)
 335 {
 336         jwrite32(jme, JME_SHBA_LO, 0x0);
 337 }
 338
 339 static u32
 340 jme_linkstat_from_phy(struct jme_adapter *jme)
 341 {
 342         u32 phylink, bmsr;
 343
 344         phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
 345         bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
 346         if (bmsr & BMSR_ANCOMP)
 347                 phylink |= PHY_LINK_AUTONEG_COMPLETE;
 348
 349         return phylink;
 350 }
 351
 352 static inline void
 353 jme_set_phyfifoa(struct jme_adapter *jme)
 354 {
 355         jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
 356 }
 357
 358 static inline void
 359 jme_set_phyfifob(struct jme_adapter *jme)
 360 {
 361         jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
 362 }
 363
 364 static int
 365 jme_check_link(struct net_device *netdev, int testonly)
 366 {
 367         struct jme_adapter *jme = netdev_priv(netdev);
 368         u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
 369         char linkmsg[64];
 370         int rc = 0;
 371
 372         linkmsg[0] = '\0';
 373
 374         if (jme->fpgaver)
 375                 phylink = jme_linkstat_from_phy(jme);
 376         else
 377                 phylink = jread32(jme, JME_PHY_LINK);
 378
 379         if (phylink & PHY_LINK_UP) {
 380                 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
 381                         /*
 382                          * If we did not enable AN
 383                          * Speed/Duplex Info should be obtained from SMI
 384                          */
 385                         phylink = PHY_LINK_UP;
 386
 387                         bmcr = jme_mdio_read(jme->dev,
 388                                                 jme->mii_if.phy_id,
 389                                                 MII_BMCR);
 390
 391                         phylink |= ((bmcr & BMCR_SPEED1000) &&
 392                                         (bmcr & BMCR_SPEED100) == 0) ?
 393                                         PHY_LINK_SPEED_1000M :
 394                                         (bmcr & BMCR_SPEED100) ?
 395                                         PHY_LINK_SPEED_100M :
 396                                         PHY_LINK_SPEED_10M;
 397
 398                         phylink |= (bmcr & BMCR_FULLDPLX) ?
 399                                          PHY_LINK_DUPLEX : 0;
 400
 401                         strcat(linkmsg, "Forced: ");
 402                 } else {
 403                         /*
 404                          * Keep polling for speed/duplex resolve complete
 405                          */
 406                         while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
 407                                 --cnt) {
 408
 409                                 udelay(1);
 410
 411                                 if (jme->fpgaver)
 412                                         phylink = jme_linkstat_from_phy(jme);
 413                                 else
 414                                         phylink = jread32(jme, JME_PHY_LINK);
 415                         }
 416                         if (!cnt)
 417                                 jeprintk(jme->pdev,
 418                                         "Waiting speed resolve timeout.\n");
 419
 420                         strcat(linkmsg, "ANed: ");
 421                 }
 422
 423                 if (jme->phylink == phylink) {
 424                         rc = 1;
 425                         goto out;
 426                 }
 427                 if (testonly)
 428                         goto out;
 429
 430                 jme->phylink = phylink;
 431
 432                 ghc = jme->reg_ghc & ~(GHC_SPEED | GHC_DPX |
 433                                 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE |
 434                                 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY);
 435                 switch (phylink & PHY_LINK_SPEED_MASK) {
 436                 case PHY_LINK_SPEED_10M:
 437                         ghc |= GHC_SPEED_10M |
 438                                 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
 439                         strcat(linkmsg, "10 Mbps, ");
 440                         break;
 441                 case PHY_LINK_SPEED_100M:
 442                         ghc |= GHC_SPEED_100M |
 443                                 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
 444                         strcat(linkmsg, "100 Mbps, ");
 445                         break;
 446                 case PHY_LINK_SPEED_1000M:
 447                         ghc |= GHC_SPEED_1000M |
 448                                 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
 449                         strcat(linkmsg, "1000 Mbps, ");
 450                         break;
 451                 default:
 452                         break;
 453                 }
 454
 455                 if (phylink & PHY_LINK_DUPLEX) {
 456                         jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
 457                         ghc |= GHC_DPX;
 458                 } else {
 459                         jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
 460                                                 TXMCS_BACKOFF |
 461                                                 TXMCS_CARRIERSENSE |
 462                                                 TXMCS_COLLISION);
 463                         jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
 464                                 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
 465                                 TXTRHD_TXREN |
 466                                 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
 467                 }
 468
 469                 gpreg1 = GPREG1_DEFAULT;
 470                 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
 471                         if (!(phylink & PHY_LINK_DUPLEX))
 472                                 gpreg1 |= GPREG1_HALFMODEPATCH;
 473                         switch (phylink & PHY_LINK_SPEED_MASK) {
 474                         case PHY_LINK_SPEED_10M:
 475                                 jme_set_phyfifoa(jme);
 476                                 gpreg1 |= GPREG1_RSSPATCH;
 477                                 break;
 478                         case PHY_LINK_SPEED_100M:
 479                                 jme_set_phyfifob(jme);
 480                                 gpreg1 |= GPREG1_RSSPATCH;
 481                                 break;
 482                         case PHY_LINK_SPEED_1000M:
 483                                 jme_set_phyfifoa(jme);
 484                                 break;
 485                         default:
 486                                 break;
 487                         }
 488                 }
 489
 490                 jwrite32(jme, JME_GPREG1, gpreg1);
 491                 jwrite32(jme, JME_GHC, ghc);
 492                 jme->reg_ghc = ghc;
 493
 494                 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
 495                                         "Full-Duplex, " :
 496                                         "Half-Duplex, ");
 497                 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
 498                                         "MDI-X" :
 499                                         "MDI");
 500                 msg_link(jme, "Link is up at %s.\n", linkmsg);
 501                 netif_carrier_on(netdev);
 502         } else {
 503                 if (testonly)
 504                         goto out;
 505
 506                 msg_link(jme, "Link is down.\n");
 507                 jme->phylink = 0;
 508                 netif_carrier_off(netdev);
 509         }
 510
 511 out:
 512         return rc;
 513 }
 514
 515 static int
 516 jme_setup_tx_resources(struct jme_adapter *jme)
 517 {
 518         struct jme_ring *txring = &(jme->txring[0]);
 519
 520         txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
 521                                    TX_RING_ALLOC_SIZE(jme->tx_ring_size),
 522                                    &(txring->dmaalloc),
 523                                    GFP_ATOMIC);
 524
 525         if (!txring->alloc) {
 526                 txring->desc = NULL;
 527                 txring->dmaalloc = 0;
 528                 txring->dma = 0;
 529                 return -ENOMEM;
 530         }
 531
 532         /*
 533          * 16 Bytes align
 534          */
 535         txring->desc            = (void *)ALIGN((unsigned long)(txring->alloc),
 536                                                 RING_DESC_ALIGN);
 537         txring->dma             = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
 538         txring->next_to_use     = 0;
 539         atomic_set(&txring->next_to_clean, 0);
 540         atomic_set(&txring->nr_free, jme->tx_ring_size);
 541
 542         /*
 543          * Initialize Transmit Descriptors
 544          */
 545         memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
 546         memset(txring->bufinf, 0,
 547                 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
 548
 549         return 0;
 550 }
 551
 552 static void
 553 jme_free_tx_resources(struct jme_adapter *jme)
 554 {
 555         int i;
 556         struct jme_ring *txring = &(jme->txring[0]);
 557         struct jme_buffer_info *txbi = txring->bufinf;
 558
 559         if (txring->alloc) {
 560                 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
 561                         txbi = txring->bufinf + i;
 562                         if (txbi->skb) {
 563                                 dev_kfree_skb(txbi->skb);
 564                                 txbi->skb = NULL;
 565                         }
 566                         txbi->mapping           = 0;
 567                         txbi->len               = 0;
 568                         txbi->nr_desc           = 0;
 569                         txbi->start_xmit        = 0;
 570                 }
 571
 572                 dma_free_coherent(&(jme->pdev->dev),
 573                                   TX_RING_ALLOC_SIZE(jme->tx_ring_size),
 574                                   txring->alloc,
 575                                   txring->dmaalloc);
 576
 577                 txring->alloc           = NULL;
 578                 txring->desc            = NULL;
 579                 txring->dmaalloc        = 0;
 580                 txring->dma             = 0;
 581         }
 582         txring->next_to_use     = 0;
 583         atomic_set(&txring->next_to_clean, 0);
 584         atomic_set(&txring->nr_free, 0);
 585
 586 }
 587
 588 static inline void
 589 jme_enable_tx_engine(struct jme_adapter *jme)
 590 {
 591         /*
 592          * Select Queue 0
 593          */
 594         jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
 595         wmb();
 596
 597         /*
 598          * Setup TX Queue 0 DMA Bass Address
 599          */
 600         jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
 601         jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
 602         jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
 603
 604         /*
 605          * Setup TX Descptor Count
 606          */
 607         jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
 608
 609         /*
 610          * Enable TX Engine
 611          */
 612         wmb();
 613         jwrite32(jme, JME_TXCS, jme->reg_txcs |
 614                                 TXCS_SELECT_QUEUE0 |
 615                                 TXCS_ENABLE);
 616
 617 }
 618
 619 static inline void
 620 jme_restart_tx_engine(struct jme_adapter *jme)
 621 {
 622         /*
 623          * Restart TX Engine
 624          */
 625         jwrite32(jme, JME_TXCS, jme->reg_txcs |
 626                                 TXCS_SELECT_QUEUE0 |
 627                                 TXCS_ENABLE);
 628 }
 629
 630 static inline void
 631 jme_disable_tx_engine(struct jme_adapter *jme)
 632 {
 633         int i;
 634         u32 val;
 635
 636         /*
 637          * Disable TX Engine
 638          */
 639         jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
 640         wmb();
 641
 642         val = jread32(jme, JME_TXCS);
 643         for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
 644                 mdelay(1);
 645                 val = jread32(jme, JME_TXCS);
 646                 rmb();
 647         }
 648
 649         if (!i)
 650                 jeprintk(jme->pdev, "Disable TX engine timeout.\n");
 651 }
 652
 653 static void
 654 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
 655 {
 656         struct jme_ring *rxring = jme->rxring;
 657         register struct rxdesc *rxdesc = rxring->desc;
 658         struct jme_buffer_info *rxbi = rxring->bufinf;
 659         rxdesc += i;
 660         rxbi += i;
 661
 662         rxdesc->dw[0] = 0;
 663         rxdesc->dw[1] = 0;
 664         rxdesc->desc1.bufaddrh  = cpu_to_le32((__u64)rxbi->mapping >> 32);
 665         rxdesc->desc1.bufaddrl  = cpu_to_le32(
 666                                         (__u64)rxbi->mapping & 0xFFFFFFFFUL);
 667         rxdesc->desc1.datalen   = cpu_to_le16(rxbi->len);
 668         if (jme->dev->features & NETIF_F_HIGHDMA)
 669                 rxdesc->desc1.flags = RXFLAG_64BIT;
 670         wmb();
 671         rxdesc->desc1.flags     |= RXFLAG_OWN | RXFLAG_INT;
 672 }
 673
 674 static int
 675 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
 676 {
 677         struct jme_ring *rxring = &(jme->rxring[0]);
 678         struct jme_buffer_info *rxbi = rxring->bufinf + i;
 679         struct sk_buff *skb;
 680
 681         skb = netdev_alloc_skb(jme->dev,
 682                 jme->dev->mtu + RX_EXTRA_LEN);
 683         if (unlikely(!skb))
 684                 return -ENOMEM;
 685
 686         rxbi->skb = skb;
 687         rxbi->len = skb_tailroom(skb);
 688         rxbi->mapping = pci_map_page(jme->pdev,
 689                                         virt_to_page(skb->data),
 690                                         offset_in_page(skb->data),
 691                                         rxbi->len,
 692                                         PCI_DMA_FROMDEVICE);
 693
 694         return 0;
 695 }
 696
 697 static void
 698 jme_free_rx_buf(struct jme_adapter *jme, int i)
 699 {
 700         struct jme_ring *rxring = &(jme->rxring[0]);
 701         struct jme_buffer_info *rxbi = rxring->bufinf;
 702         rxbi += i;
 703
 704         if (rxbi->skb) {
 705                 pci_unmap_page(jme->pdev,
 706                                  rxbi->mapping,
 707                                  rxbi->len,
 708                                  PCI_DMA_FROMDEVICE);
 709                 dev_kfree_skb(rxbi->skb);
 710                 rxbi->skb = NULL;
 711                 rxbi->mapping = 0;
 712                 rxbi->len = 0;
 713         }
 714 }
 715
 716 static void
 717 jme_free_rx_resources(struct jme_adapter *jme)
 718 {
 719         int i;
 720         struct jme_ring *rxring = &(jme->rxring[0]);
 721
 722         if (rxring->alloc) {
 723                 for (i = 0 ; i < jme->rx_ring_size ; ++i)
 724                         jme_free_rx_buf(jme, i);
 725
 726                 dma_free_coherent(&(jme->pdev->dev),
 727                                   RX_RING_ALLOC_SIZE(jme->rx_ring_size),
 728                                   rxring->alloc,
 729                                   rxring->dmaalloc);
 730                 rxring->alloc    = NULL;
 731                 rxring->desc     = NULL;
 732                 rxring->dmaalloc = 0;
 733                 rxring->dma      = 0;
 734         }
 735         rxring->next_to_use   = 0;
 736         atomic_set(&rxring->next_to_clean, 0);
 737 }
 738
 739 static int
 740 jme_setup_rx_resources(struct jme_adapter *jme)
 741 {
 742         int i;
 743         struct jme_ring *rxring = &(jme->rxring[0]);
 744
 745         rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
 746                                    RX_RING_ALLOC_SIZE(jme->rx_ring_size),
 747                                    &(rxring->dmaalloc),
 748                                    GFP_ATOMIC);
 749         if (!rxring->alloc) {
 750                 rxring->desc = NULL;
 751                 rxring->dmaalloc = 0;
 752                 rxring->dma = 0;
 753                 return -ENOMEM;
 754         }
 755
 756         /*
 757          * 16 Bytes align
 758          */
 759         rxring->desc            = (void *)ALIGN((unsigned long)(rxring->alloc),
 760                                                 RING_DESC_ALIGN);
 761         rxring->dma             = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
 762         rxring->next_to_use     = 0;
 763         atomic_set(&rxring->next_to_clean, 0);
 764
 765         /*
 766          * Initiallize Receive Descriptors
 767          */
 768         for (i = 0 ; i < jme->rx_ring_size ; ++i) {
 769                 if (unlikely(jme_make_new_rx_buf(jme, i))) {
 770                         jme_free_rx_resources(jme);
 771                         return -ENOMEM;
 772                 }
 773
 774                 jme_set_clean_rxdesc(jme, i);
 775         }
 776
 777         return 0;
 778 }
 779
 780 static inline void
 781 jme_enable_rx_engine(struct jme_adapter *jme)
 782 {
 783         /*
 784          * Select Queue 0
 785          */
 786         jwrite32(jme, JME_RXCS, jme->reg_rxcs |
 787                                 RXCS_QUEUESEL_Q0);
 788         wmb();
 789
 790         /*
 791          * Setup RX DMA Bass Address
 792          */
 793         jwrite32(jme, JME_RXDBA_LO, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
 794         jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
 795         jwrite32(jme, JME_RXNDA, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
 796
 797         /*
 798          * Setup RX Descriptor Count
 799          */
 800         jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
 801
 802         /*
 803          * Setup Unicast Filter
 804          */
 805         jme_set_multi(jme->dev);
 806
 807         /*
 808          * Enable RX Engine
 809          */
 810         wmb();
 811         jwrite32(jme, JME_RXCS, jme->reg_rxcs |
 812                                 RXCS_QUEUESEL_Q0 |
 813                                 RXCS_ENABLE |
 814                                 RXCS_QST);
 815 }
 816
 817 static inline void
 818 jme_restart_rx_engine(struct jme_adapter *jme)
 819 {
 820         /*
 821          * Start RX Engine
 822          */
 823         jwrite32(jme, JME_RXCS, jme->reg_rxcs |
 824                                 RXCS_QUEUESEL_Q0 |
 825                                 RXCS_ENABLE |
 826                                 RXCS_QST);
 827 }
 828
 829 static inline void
 830 jme_disable_rx_engine(struct jme_adapter *jme)
 831 {
 832         int i;
 833         u32 val;
 834
 835         /*
 836          * Disable RX Engine
 837          */
 838         jwrite32(jme, JME_RXCS, jme->reg_rxcs);
 839         wmb();
 840
 841         val = jread32(jme, JME_RXCS);
 842         for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
 843                 mdelay(1);
 844                 val = jread32(jme, JME_RXCS);
 845                 rmb();
 846         }
 847
 848         if (!i)
 849                 jeprintk(jme->pdev, "Disable RX engine timeout.\n");
 850
 851 }
 852
 853 static int
 854 jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
 855 {
 856         if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
 857                 return false;
 858
 859         if (unlikely(!(flags & RXWBFLAG_MF) &&
 860         (flags & RXWBFLAG_TCPON) && !(flags & RXWBFLAG_TCPCS))) {
 861                 msg_rx_err(jme, "TCP Checksum error.\n");
 862                 goto out_sumerr;
 863         }
 864
 865         if (unlikely(!(flags & RXWBFLAG_MF) &&
 866         (flags & RXWBFLAG_UDPON) && !(flags & RXWBFLAG_UDPCS))) {
 867                 msg_rx_err(jme, "UDP Checksum error.\n");
 868                 goto out_sumerr;
 869         }
 870
 871         if (unlikely((flags & RXWBFLAG_IPV4) && !(flags & RXWBFLAG_IPCS))) {
 872                 msg_rx_err(jme, "IPv4 Checksum error.\n");
 873                 goto out_sumerr;
 874         }
 875
 876         return true;
 877
 878 out_sumerr:
 879         return false;
 880 }
 881
 882 static void
 883 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
 884 {
 885         struct jme_ring *rxring = &(jme->rxring[0]);
 886         struct rxdesc *rxdesc = rxring->desc;
 887         struct jme_buffer_info *rxbi = rxring->bufinf;
 888         struct sk_buff *skb;
 889         int framesize;
 890
 891         rxdesc += idx;
 892         rxbi += idx;
 893
 894         skb = rxbi->skb;
 895         pci_dma_sync_single_for_cpu(jme->pdev,
 896                                         rxbi->mapping,
 897                                         rxbi->len,
 898                                         PCI_DMA_FROMDEVICE);
 899
 900         if (unlikely(jme_make_new_rx_buf(jme, idx))) {
 901                 pci_dma_sync_single_for_device(jme->pdev,
 902                                                 rxbi->mapping,
 903                                                 rxbi->len,
 904                                                 PCI_DMA_FROMDEVICE);
 905
 906                 ++(NET_STAT(jme).rx_dropped);
 907         } else {
 908                 framesize = le16_to_cpu(rxdesc->descwb.framesize)
 909                                 - RX_PREPAD_SIZE;
 910
 911                 skb_reserve(skb, RX_PREPAD_SIZE);
 912                 skb_put(skb, framesize);
 913                 skb->protocol = eth_type_trans(skb, jme->dev);
 914
 915                 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
 916                         skb->ip_summed = CHECKSUM_UNNECESSARY;
 917                 else
 918                         skb->ip_summed = CHECKSUM_NONE;
 919
 920                 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
 921                         if (jme->vlgrp) {
 922                                 jme->jme_vlan_rx(skb, jme->vlgrp,
 923                                         le16_to_cpu(rxdesc->descwb.vlan));
 924                                 NET_STAT(jme).rx_bytes += 4;
 925                         }
 926                 } else {
 927                         jme->jme_rx(skb);
 928                 }
 929
 930                 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
 931                     cpu_to_le16(RXWBFLAG_DEST_MUL))
 932                         ++(NET_STAT(jme).multicast);
 933
 934                 NET_STAT(jme).rx_bytes += framesize;
 935                 ++(NET_STAT(jme).rx_packets);
 936         }
 937
 938         jme_set_clean_rxdesc(jme, idx);
 939
 940 }
 941
 942 static int
 943 jme_process_receive(struct jme_adapter *jme, int limit)
 944 {
 945         struct jme_ring *rxring = &(jme->rxring[0]);
 946         struct rxdesc *rxdesc = rxring->desc;
 947         int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
 948
 949         if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
 950                 goto out_inc;
 951
 952         if (unlikely(atomic_read(&jme->link_changing) != 1))
 953                 goto out_inc;
 954
 955         if (unlikely(!netif_carrier_ok(jme->dev)))
 956                 goto out_inc;
 957
 958         i = atomic_read(&rxring->next_to_clean);
 959         while (limit-- > 0) {
 960                 rxdesc = rxring->desc;
 961                 rxdesc += i;
 962
 963                 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
 964                 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
 965                         goto out;
 966
 967                 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
 968
 969                 if (unlikely(desccnt > 1 ||
 970                 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
 971
 972                         if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
 973                                 ++(NET_STAT(jme).rx_crc_errors);
 974                         else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
 975                                 ++(NET_STAT(jme).rx_fifo_errors);
 976                         else
 977                                 ++(NET_STAT(jme).rx_errors);
 978
 979                         if (desccnt > 1)
 980                                 limit -= desccnt - 1;
 981
 982                         for (j = i, ccnt = desccnt ; ccnt-- ; ) {
 983                                 jme_set_clean_rxdesc(jme, j);
 984                                 j = (j + 1) & (mask);
 985                         }
 986
 987                 } else {
 988                         jme_alloc_and_feed_skb(jme, i);
 989                 }
 990
 991                 i = (i + desccnt) & (mask);
 992         }
 993
 994 out:
 995         atomic_set(&rxring->next_to_clean, i);
 996
 997 out_inc:
 998         atomic_inc(&jme->rx_cleaning);
 999
1000         return limit > 0 ? limit : 0;
1001
1002 }
1003
1004 static void
1005 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1006 {
1007         if (likely(atmp == dpi->cur)) {
1008                 dpi->cnt = 0;
1009                 return;
1010         }
1011
1012         if (dpi->attempt == atmp) {
1013                 ++(dpi->cnt);
1014         } else {
1015                 dpi->attempt = atmp;
1016                 dpi->cnt = 0;
1017         }
1018
1019 }
1020
1021 static void
1022 jme_dynamic_pcc(struct jme_adapter *jme)
1023 {
1024         register struct dynpcc_info *dpi = &(jme->dpi);
1025
1026         if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1027                 jme_attempt_pcc(dpi, PCC_P3);
1028         else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD
1029         || dpi->intr_cnt > PCC_INTR_THRESHOLD)
1030                 jme_attempt_pcc(dpi, PCC_P2);
1031         else
1032                 jme_attempt_pcc(dpi, PCC_P1);
1033
1034         if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1035                 if (dpi->attempt < dpi->cur)
1036                         tasklet_schedule(&jme->rxclean_task);
1037                 jme_set_rx_pcc(jme, dpi->attempt);
1038                 dpi->cur = dpi->attempt;
1039                 dpi->cnt = 0;
1040         }
1041 }
1042
1043 static void
1044 jme_start_pcc_timer(struct jme_adapter *jme)
1045 {
1046         struct dynpcc_info *dpi = &(jme->dpi);
1047         dpi->last_bytes         = NET_STAT(jme).rx_bytes;
1048         dpi->last_pkts          = NET_STAT(jme).rx_packets;
1049         dpi->intr_cnt           = 0;
1050         jwrite32(jme, JME_TMCSR,
1051                 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1052 }
1053
1054 static inline void
1055 jme_stop_pcc_timer(struct jme_adapter *jme)
1056 {
1057         jwrite32(jme, JME_TMCSR, 0);
1058 }
1059
1060 static void
1061 jme_shutdown_nic(struct jme_adapter *jme)
1062 {
1063         u32 phylink;
1064
1065         phylink = jme_linkstat_from_phy(jme);
1066
1067         if (!(phylink & PHY_LINK_UP)) {
1068                 /*
1069                  * Disable all interrupt before issue timer
1070                  */
1071                 jme_stop_irq(jme);
1072                 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1073         }
1074 }
1075
1076 static void
1077 jme_pcc_tasklet(unsigned long arg)
1078 {
1079         struct jme_adapter *jme = (struct jme_adapter *)arg;
1080         struct net_device *netdev = jme->dev;
1081
1082         if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1083                 jme_shutdown_nic(jme);
1084                 return;
1085         }
1086
1087         if (unlikely(!netif_carrier_ok(netdev) ||
1088                 (atomic_read(&jme->link_changing) != 1)
1089         )) {
1090                 jme_stop_pcc_timer(jme);
1091                 return;
1092         }
1093
1094         if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1095                 jme_dynamic_pcc(jme);
1096
1097         jme_start_pcc_timer(jme);
1098 }
1099
1100 static inline void
1101 jme_polling_mode(struct jme_adapter *jme)
1102 {
1103         jme_set_rx_pcc(jme, PCC_OFF);
1104 }
1105
1106 static inline void
1107 jme_interrupt_mode(struct jme_adapter *jme)
1108 {
1109         jme_set_rx_pcc(jme, PCC_P1);
1110 }
1111
1112 static inline int
1113 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1114 {
1115         u32 apmc;
1116         apmc = jread32(jme, JME_APMC);
1117         return apmc & JME_APMC_PSEUDO_HP_EN;
1118 }
1119
1120 static void
1121 jme_start_shutdown_timer(struct jme_adapter *jme)
1122 {
1123         u32 apmc;
1124
1125         apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1126         apmc &= ~JME_APMC_EPIEN_CTRL;
1127         if (!no_extplug) {
1128                 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1129                 wmb();
1130         }
1131         jwrite32f(jme, JME_APMC, apmc);
1132
1133         jwrite32f(jme, JME_TIMER2, 0);
1134         set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1135         jwrite32(jme, JME_TMCSR,
1136                 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1137 }
1138
1139 static void
1140 jme_stop_shutdown_timer(struct jme_adapter *jme)
1141 {
1142         u32 apmc;
1143
1144         jwrite32f(jme, JME_TMCSR, 0);
1145         jwrite32f(jme, JME_TIMER2, 0);
1146         clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1147
1148         apmc = jread32(jme, JME_APMC);
1149         apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1150         jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1151         wmb();
1152         jwrite32f(jme, JME_APMC, apmc);
1153 }
1154
1155 static void
1156 jme_link_change_tasklet(unsigned long arg)
1157 {
1158         struct jme_adapter *jme = (struct jme_adapter *)arg;
1159         struct net_device *netdev = jme->dev;
1160         int rc;
1161
1162         while (!atomic_dec_and_test(&jme->link_changing)) {
1163                 atomic_inc(&jme->link_changing);
1164                 msg_intr(jme, "Get link change lock failed.\n");
1165                 while (atomic_read(&jme->link_changing) != 1)
1166                         msg_intr(jme, "Waiting link change lock.\n");
1167         }
1168
1169         if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1170                 goto out;
1171
1172         jme->old_mtu = netdev->mtu;
1173         netif_stop_queue(netdev);
1174         if (jme_pseudo_hotplug_enabled(jme))
1175                 jme_stop_shutdown_timer(jme);
1176
1177         jme_stop_pcc_timer(jme);
1178         tasklet_disable(&jme->txclean_task);
1179         tasklet_disable(&jme->rxclean_task);
1180         tasklet_disable(&jme->rxempty_task);
1181
1182         if (netif_carrier_ok(netdev)) {
1183                 jme_reset_ghc_speed(jme);
1184                 jme_disable_rx_engine(jme);
1185                 jme_disable_tx_engine(jme);
1186                 jme_reset_mac_processor(jme);
1187                 jme_free_rx_resources(jme);
1188                 jme_free_tx_resources(jme);
1189
1190                 if (test_bit(JME_FLAG_POLL, &jme->flags))
1191                         jme_polling_mode(jme);
1192
1193                 netif_carrier_off(netdev);
1194         }
1195
1196         jme_check_link(netdev, 0);
1197         if (netif_carrier_ok(netdev)) {
1198                 rc = jme_setup_rx_resources(jme);
1199                 if (rc) {
1200                         jeprintk(jme->pdev, "Allocating resources for RX error"
1201                                 ", Device STOPPED!\n");
1202                         goto out_enable_tasklet;
1203                 }
1204
1205                 rc = jme_setup_tx_resources(jme);
1206                 if (rc) {
1207                         jeprintk(jme->pdev, "Allocating resources for TX error"
1208                                 ", Device STOPPED!\n");
1209                         goto err_out_free_rx_resources;
1210                 }
1211
1212                 jme_enable_rx_engine(jme);
1213                 jme_enable_tx_engine(jme);
1214
1215                 netif_start_queue(netdev);
1216
1217                 if (test_bit(JME_FLAG_POLL, &jme->flags))
1218                         jme_interrupt_mode(jme);
1219
1220                 jme_start_pcc_timer(jme);
1221         } else if (jme_pseudo_hotplug_enabled(jme)) {
1222                 jme_start_shutdown_timer(jme);
1223         }
1224
1225         goto out_enable_tasklet;
1226
1227 err_out_free_rx_resources:
1228         jme_free_rx_resources(jme);
1229 out_enable_tasklet:
1230         tasklet_enable(&jme->txclean_task);
1231         tasklet_hi_enable(&jme->rxclean_task);
1232         tasklet_hi_enable(&jme->rxempty_task);
1233 out:
1234         atomic_inc(&jme->link_changing);
1235 }
1236
1237 static void
1238 jme_rx_clean_tasklet(unsigned long arg)
1239 {
1240         struct jme_adapter *jme = (struct jme_adapter *)arg;
1241         struct dynpcc_info *dpi = &(jme->dpi);
1242
1243         jme_process_receive(jme, jme->rx_ring_size);
1244         ++(dpi->intr_cnt);
1245
1246 }
1247
1248 static int
1249 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1250 {
1251         struct jme_adapter *jme = jme_napi_priv(holder);
1252         int rest;
1253
1254         rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1255
1256         while (atomic_read(&jme->rx_empty) > 0) {
1257                 atomic_dec(&jme->rx_empty);
1258                 ++(NET_STAT(jme).rx_dropped);
1259                 jme_restart_rx_engine(jme);
1260         }
1261         atomic_inc(&jme->rx_empty);
1262
1263         if (rest) {
1264                 JME_RX_COMPLETE(netdev, holder);
1265                 jme_interrupt_mode(jme);
1266         }
1267
1268         JME_NAPI_WEIGHT_SET(budget, rest);
1269         return JME_NAPI_WEIGHT_VAL(budget) - rest;
1270 }
1271
1272 static void
1273 jme_rx_empty_tasklet(unsigned long arg)
1274 {
1275         struct jme_adapter *jme = (struct jme_adapter *)arg;
1276
1277         if (unlikely(atomic_read(&jme->link_changing) != 1))
1278                 return;
1279
1280         if (unlikely(!netif_carrier_ok(jme->dev)))
1281                 return;
1282
1283         msg_rx_status(jme, "RX Queue Full!\n");
1284
1285         jme_rx_clean_tasklet(arg);
1286
1287         while (atomic_read(&jme->rx_empty) > 0) {
1288                 atomic_dec(&jme->rx_empty);
1289                 ++(NET_STAT(jme).rx_dropped);
1290                 jme_restart_rx_engine(jme);
1291         }
1292         atomic_inc(&jme->rx_empty);
1293 }
1294
1295 static void
1296 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1297 {
1298         struct jme_ring *txring = jme->txring;
1299
1300         smp_wmb();
1301         if (unlikely(netif_queue_stopped(jme->dev) &&
1302         atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1303                 msg_tx_done(jme, "TX Queue Waked.\n");
1304                 netif_wake_queue(jme->dev);
1305         }
1306
1307 }
1308
1309 static void
1310 jme_tx_clean_tasklet(unsigned long arg)
1311 {
1312         struct jme_adapter *jme = (struct jme_adapter *)arg;
1313         struct jme_ring *txring = &(jme->txring[0]);
1314         struct txdesc *txdesc = txring->desc;
1315         struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1316         int i, j, cnt = 0, max, err, mask;
1317
1318         tx_dbg(jme, "Into txclean.\n");
1319
1320         if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1321                 goto out;
1322
1323         if (unlikely(atomic_read(&jme->link_changing) != 1))
1324                 goto out;
1325
1326         if (unlikely(!netif_carrier_ok(jme->dev)))
1327                 goto out;
1328
1329         max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1330         mask = jme->tx_ring_mask;
1331
1332         for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1333
1334                 ctxbi = txbi + i;
1335
1336                 if (likely(ctxbi->skb &&
1337                 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1338
1339                         tx_dbg(jme, "txclean: %d+%d@%lu\n",
1340                                         i, ctxbi->nr_desc, jiffies);
1341
1342                         err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1343
1344                         for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1345                                 ttxbi = txbi + ((i + j) & (mask));
1346                                 txdesc[(i + j) & (mask)].dw[0] = 0;
1347
1348                                 pci_unmap_page(jme->pdev,
1349                                                  ttxbi->mapping,
1350                                                  ttxbi->len,
1351                                                  PCI_DMA_TODEVICE);
1352
1353                                 ttxbi->mapping = 0;
1354                                 ttxbi->len = 0;
1355                         }
1356
1357                         dev_kfree_skb(ctxbi->skb);
1358
1359                         cnt += ctxbi->nr_desc;
1360
1361                         if (unlikely(err)) {
1362                                 ++(NET_STAT(jme).tx_carrier_errors);
1363                         } else {
1364                                 ++(NET_STAT(jme).tx_packets);
1365                                 NET_STAT(jme).tx_bytes += ctxbi->len;
1366                         }
1367
1368                         ctxbi->skb = NULL;
1369                         ctxbi->len = 0;
1370                         ctxbi->start_xmit = 0;
1371
1372                 } else {
1373                         break;
1374                 }
1375
1376                 i = (i + ctxbi->nr_desc) & mask;
1377
1378                 ctxbi->nr_desc = 0;
1379         }
1380
1381         tx_dbg(jme, "txclean: done %d@%lu.\n", i, jiffies);
1382         atomic_set(&txring->next_to_clean, i);
1383         atomic_add(cnt, &txring->nr_free);
1384
1385         jme_wake_queue_if_stopped(jme);
1386
1387 out:
1388         atomic_inc(&jme->tx_cleaning);
1389 }
1390
1391 static void
1392 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1393 {
1394         /*
1395          * Disable interrupt
1396          */
1397         jwrite32f(jme, JME_IENC, INTR_ENABLE);
1398
1399         if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1400                 /*
1401                  * Link change event is critical
1402                  * all other events are ignored
1403                  */
1404                 jwrite32(jme, JME_IEVE, intrstat);
1405                 tasklet_schedule(&jme->linkch_task);
1406                 goto out_reenable;
1407         }
1408
1409         if (intrstat & INTR_TMINTR) {
1410                 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1411                 tasklet_schedule(&jme->pcc_task);
1412         }
1413
1414         if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1415                 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1416                 tasklet_schedule(&jme->txclean_task);
1417         }
1418
1419         if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1420                 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1421                                                      INTR_PCCRX0 |
1422                                                      INTR_RX0EMP)) |
1423                                         INTR_RX0);
1424         }
1425
1426         if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1427                 if (intrstat & INTR_RX0EMP)
1428                         atomic_inc(&jme->rx_empty);
1429
1430                 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1431                         if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1432                                 jme_polling_mode(jme);
1433                                 JME_RX_SCHEDULE(jme);
1434                         }
1435                 }
1436         } else {
1437                 if (intrstat & INTR_RX0EMP) {
1438                         atomic_inc(&jme->rx_empty);
1439                         tasklet_hi_schedule(&jme->rxempty_task);
1440                 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1441                         tasklet_hi_schedule(&jme->rxclean_task);
1442                 }
1443         }
1444
1445 out_reenable:
1446         /*
1447          * Re-enable interrupt
1448          */
1449         jwrite32f(jme, JME_IENS, INTR_ENABLE);
1450 }
1451
1452 static irqreturn_t
1453 jme_intr(int irq, void *dev_id)
1454 {
1455         struct net_device *netdev = dev_id;
1456         struct jme_adapter *jme = netdev_priv(netdev);
1457         u32 intrstat;
1458
1459         intrstat = jread32(jme, JME_IEVE);
1460
1461         /*
1462          * Check if it's really an interrupt for us
1463          */
1464         if (unlikely((intrstat & INTR_ENABLE) == 0))
1465                 return IRQ_NONE;
1466
1467         /*
1468          * Check if the device still exist
1469          */
1470         if (unlikely(intrstat == ~((typeof(intrstat))0)))
1471                 return IRQ_NONE;
1472
1473         jme_intr_msi(jme, intrstat);
1474
1475         return IRQ_HANDLED;
1476 }
1477
1478 static irqreturn_t
1479 jme_msi(int irq, void *dev_id)
1480 {
1481         struct net_device *netdev = dev_id;
1482         struct jme_adapter *jme = netdev_priv(netdev);
1483         u32 intrstat;
1484
1485         pci_dma_sync_single_for_cpu(jme->pdev,
1486                                     jme->shadow_dma,
1487                                     sizeof(u32) * SHADOW_REG_NR,
1488                                     PCI_DMA_FROMDEVICE);
1489         intrstat = jme->shadow_regs[SHADOW_IEVE];
1490         jme->shadow_regs[SHADOW_IEVE] = 0;
1491
1492         jme_intr_msi(jme, intrstat);
1493
1494         return IRQ_HANDLED;
1495 }
1496
1497 static void
1498 jme_reset_link(struct jme_adapter *jme)
1499 {
1500         jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1501 }
1502
1503 static void
1504 jme_restart_an(struct jme_adapter *jme)
1505 {
1506         u32 bmcr;
1507
1508         spin_lock_bh(&jme->phy_lock);
1509         bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1510         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1511         jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1512         spin_unlock_bh(&jme->phy_lock);
1513 }
1514
1515 static int
1516 jme_request_irq(struct jme_adapter *jme)
1517 {
1518         int rc;
1519         struct net_device *netdev = jme->dev;
1520         irq_handler_t handler = jme_intr;
1521         int irq_flags = IRQF_SHARED;
1522
1523         if (!pci_enable_msi(jme->pdev)) {
1524                 set_bit(JME_FLAG_MSI, &jme->flags);
1525                 handler = jme_msi;
1526                 irq_flags = 0;
1527         }
1528
1529         rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1530                           netdev);
1531         if (rc) {
1532                 jeprintk(jme->pdev,
1533                         "Unable to request %s interrupt (return: %d)\n",
1534                         test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1535                         rc);
1536
1537                 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1538                         pci_disable_msi(jme->pdev);
1539                         clear_bit(JME_FLAG_MSI, &jme->flags);
1540                 }
1541         } else {
1542                 netdev->irq = jme->pdev->irq;
1543         }
1544
1545         return rc;
1546 }
1547
1548 static void
1549 jme_free_irq(struct jme_adapter *jme)
1550 {
1551         free_irq(jme->pdev->irq, jme->dev);
1552         if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1553                 pci_disable_msi(jme->pdev);
1554                 clear_bit(JME_FLAG_MSI, &jme->flags);
1555                 jme->dev->irq = jme->pdev->irq;
1556         }
1557 }
1558
1559 static int
1560 jme_open(struct net_device *netdev)
1561 {
1562         struct jme_adapter *jme = netdev_priv(netdev);
1563         int rc;
1564
1565         jme_clear_pm(jme);
1566         JME_NAPI_ENABLE(jme);
1567
1568         tasklet_enable(&jme->txclean_task);
1569         tasklet_hi_enable(&jme->rxclean_task);
1570         tasklet_hi_enable(&jme->rxempty_task);
1571
1572         rc = jme_request_irq(jme);
1573         if (rc)
1574                 goto err_out;
1575
1576         jme_enable_shadow(jme);
1577         jme_start_irq(jme);
1578
1579         if (test_bit(JME_FLAG_SSET, &jme->flags))
1580                 jme_set_settings(netdev, &jme->old_ecmd);
1581         else
1582                 jme_reset_phy_processor(jme);
1583
1584         jme_reset_link(jme);
1585
1586         return 0;
1587
1588 err_out:
1589         netif_stop_queue(netdev);
1590         netif_carrier_off(netdev);
1591         return rc;
1592 }
1593
1594 #ifdef CONFIG_PM
1595 static void
1596 jme_set_100m_half(struct jme_adapter *jme)
1597 {
1598         u32 bmcr, tmp;
1599
1600         bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1601         tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1602                        BMCR_SPEED1000 | BMCR_FULLDPLX);
1603         tmp |= BMCR_SPEED100;
1604
1605         if (bmcr != tmp)
1606                 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1607
1608         if (jme->fpgaver)
1609                 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1610         else
1611                 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1612 }
1613
1614 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1615 static void
1616 jme_wait_link(struct jme_adapter *jme)
1617 {
1618         u32 phylink, to = JME_WAIT_LINK_TIME;
1619
1620         mdelay(1000);
1621         phylink = jme_linkstat_from_phy(jme);
1622         while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1623                 mdelay(10);
1624                 phylink = jme_linkstat_from_phy(jme);
1625         }
1626 }
1627 #endif
1628
1629 static inline void
1630 jme_phy_off(struct jme_adapter *jme)
1631 {
1632         jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1633 }
1634
1635 static int
1636 jme_close(struct net_device *netdev)
1637 {
1638         struct jme_adapter *jme = netdev_priv(netdev);
1639
1640         netif_stop_queue(netdev);
1641         netif_carrier_off(netdev);
1642
1643         jme_stop_irq(jme);
1644         jme_disable_shadow(jme);
1645         jme_free_irq(jme);
1646
1647         JME_NAPI_DISABLE(jme);
1648
1649         tasklet_kill(&jme->linkch_task);
1650         tasklet_kill(&jme->txclean_task);
1651         tasklet_kill(&jme->rxclean_task);
1652         tasklet_kill(&jme->rxempty_task);
1653
1654         jme_reset_ghc_speed(jme);
1655         jme_disable_rx_engine(jme);
1656         jme_disable_tx_engine(jme);
1657         jme_reset_mac_processor(jme);
1658         jme_free_rx_resources(jme);
1659         jme_free_tx_resources(jme);
1660         jme->phylink = 0;
1661         jme_phy_off(jme);
1662
1663         return 0;
1664 }
1665
1666 static int
1667 jme_alloc_txdesc(struct jme_adapter *jme,
1668                         struct sk_buff *skb)
1669 {
1670         struct jme_ring *txring = jme->txring;
1671         int idx, nr_alloc, mask = jme->tx_ring_mask;
1672
1673         idx = txring->next_to_use;
1674         nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1675
1676         if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1677                 return -1;
1678
1679         atomic_sub(nr_alloc, &txring->nr_free);
1680
1681         txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1682
1683         return idx;
1684 }
1685
1686 static void
1687 jme_fill_tx_map(struct pci_dev *pdev,
1688                 struct txdesc *txdesc,
1689                 struct jme_buffer_info *txbi,
1690                 struct page *page,
1691                 u32 page_offset,
1692                 u32 len,
1693                 u8 hidma)
1694 {
1695         dma_addr_t dmaaddr;
1696
1697         dmaaddr = pci_map_page(pdev,
1698                                 page,
1699                                 page_offset,
1700                                 len,
1701                                 PCI_DMA_TODEVICE);
1702
1703         pci_dma_sync_single_for_device(pdev,
1704                                        dmaaddr,
1705                                        len,
1706                                        PCI_DMA_TODEVICE);
1707
1708         txdesc->dw[0] = 0;
1709         txdesc->dw[1] = 0;
1710         txdesc->desc2.flags     = TXFLAG_OWN;
1711         txdesc->desc2.flags     |= (hidma) ? TXFLAG_64BIT : 0;
1712         txdesc->desc2.datalen   = cpu_to_le16(len);
1713         txdesc->desc2.bufaddrh  = cpu_to_le32((__u64)dmaaddr >> 32);
1714         txdesc->desc2.bufaddrl  = cpu_to_le32(
1715                                         (__u64)dmaaddr & 0xFFFFFFFFUL);
1716
1717         txbi->mapping = dmaaddr;
1718         txbi->len = len;
1719 }
1720
1721 static void
1722 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1723 {
1724         struct jme_ring *txring = jme->txring;
1725         struct txdesc *txdesc = txring->desc, *ctxdesc;
1726         struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1727         u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1728         int i, nr_frags = skb_shinfo(skb)->nr_frags;
1729         int mask = jme->tx_ring_mask;
1730         struct skb_frag_struct *frag;
1731         u32 len;
1732
1733         for (i = 0 ; i < nr_frags ; ++i) {
1734                 frag = &skb_shinfo(skb)->frags[i];
1735                 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1736                 ctxbi = txbi + ((idx + i + 2) & (mask));
1737
1738                 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1739                                  frag->page_offset, frag->size, hidma);
1740         }
1741
1742         len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1743         ctxdesc = txdesc + ((idx + 1) & (mask));
1744         ctxbi = txbi + ((idx + 1) & (mask));
1745         jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1746                         offset_in_page(skb->data), len, hidma);
1747
1748 }
1749
1750 static int
1751 jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1752 {
1753         if (unlikely(skb_shinfo(skb)->gso_size &&
1754                         skb_header_cloned(skb) &&
1755                         pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1756                 dev_kfree_skb(skb);
1757                 return -1;
1758         }
1759
1760         return 0;
1761 }
1762
1763 static int
1764 jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
1765 {
1766         *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
1767         if (*mss) {
1768                 *flags |= TXFLAG_LSEN;
1769
1770                 if (skb->protocol == htons(ETH_P_IP)) {
1771                         struct iphdr *iph = ip_hdr(skb);
1772
1773                         iph->check = 0;
1774                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1775                                                                 iph->daddr, 0,
1776                                                                 IPPROTO_TCP,
1777                                                                 0);
1778                 } else {
1779                         struct ipv6hdr *ip6h = ipv6_hdr(skb);
1780
1781                         tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1782                                                                 &ip6h->daddr, 0,
1783                                                                 IPPROTO_TCP,
1784                                                                 0);
1785                 }
1786
1787                 return 0;
1788         }
1789
1790         return 1;
1791 }
1792
1793 static void
1794 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1795 {
1796         if (skb->ip_summed == CHECKSUM_PARTIAL) {
1797                 u8 ip_proto;
1798
1799                 switch (skb->protocol) {
1800                 case htons(ETH_P_IP):
1801                         ip_proto = ip_hdr(skb)->protocol;
1802                         break;
1803                 case htons(ETH_P_IPV6):
1804                         ip_proto = ipv6_hdr(skb)->nexthdr;
1805                         break;
1806                 default:
1807                         ip_proto = 0;
1808                         break;
1809                 }
1810
1811                 switch (ip_proto) {
1812                 case IPPROTO_TCP:
1813                         *flags |= TXFLAG_TCPCS;
1814                         break;
1815                 case IPPROTO_UDP:
1816                         *flags |= TXFLAG_UDPCS;
1817                         break;
1818                 default:
1819                         msg_tx_err(jme, "Error upper layer protocol.\n");
1820                         break;
1821                 }
1822         }
1823 }
1824
1825 static inline void
1826 jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
1827 {
1828         if (vlan_tx_tag_present(skb)) {
1829                 *flags |= TXFLAG_TAGON;
1830                 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
1831         }
1832 }
1833
1834 static int
1835 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1836 {
1837         struct jme_ring *txring = jme->txring;
1838         struct txdesc *txdesc;
1839         struct jme_buffer_info *txbi;
1840         u8 flags;
1841
1842         txdesc = (struct txdesc *)txring->desc + idx;
1843         txbi = txring->bufinf + idx;
1844
1845         txdesc->dw[0] = 0;
1846         txdesc->dw[1] = 0;
1847         txdesc->dw[2] = 0;
1848         txdesc->dw[3] = 0;
1849         txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1850         /*
1851          * Set OWN bit at final.
1852          * When kernel transmit faster than NIC.
1853          * And NIC trying to send this descriptor before we tell
1854          * it to start sending this TX queue.
1855          * Other fields are already filled correctly.
1856          */
1857         wmb();
1858         flags = TXFLAG_OWN | TXFLAG_INT;
1859         /*
1860          * Set checksum flags while not tso
1861          */
1862         if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1863                 jme_tx_csum(jme, skb, &flags);
1864         jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
1865         jme_map_tx_skb(jme, skb, idx);
1866         txdesc->desc1.flags = flags;
1867         /*
1868          * Set tx buffer info after telling NIC to send
1869          * For better tx_clean timing
1870          */
1871         wmb();
1872         txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1873         txbi->skb = skb;
1874         txbi->len = skb->len;
1875         txbi->start_xmit = jiffies;
1876         if (!txbi->start_xmit)
1877                 txbi->start_xmit = (0UL-1);
1878
1879         return 0;
1880 }
1881
1882 static void
1883 jme_stop_queue_if_full(struct jme_adapter *jme)
1884 {
1885         struct jme_ring *txring = jme->txring;
1886         struct jme_buffer_info *txbi = txring->bufinf;
1887         int idx = atomic_read(&txring->next_to_clean);
1888
1889         txbi += idx;
1890
1891         smp_wmb();
1892         if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
1893                 netif_stop_queue(jme->dev);
1894                 msg_tx_queued(jme, "TX Queue Paused.\n");
1895                 smp_wmb();
1896                 if (atomic_read(&txring->nr_free)
1897                         >= (jme->tx_wake_threshold)) {
1898                         netif_wake_queue(jme->dev);
1899                         msg_tx_queued(jme, "TX Queue Fast Waked.\n");
1900                 }
1901         }
1902
1903         if (unlikely(txbi->start_xmit &&
1904                         (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
1905                         txbi->skb)) {
1906                 netif_stop_queue(jme->dev);
1907                 msg_tx_queued(jme, "TX Queue Stopped %d@%lu.\n", idx, jiffies);
1908         }
1909 }
1910
1911 /*
1912  * This function is already protected by netif_tx_lock()
1913  */
1914
1915 static int
1916 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1917 {
1918         struct jme_adapter *jme = netdev_priv(netdev);
1919         int idx;
1920
1921         if (unlikely(jme_expand_header(jme, skb))) {
1922                 ++(NET_STAT(jme).tx_dropped);
1923                 return NETDEV_TX_OK;
1924         }
1925
1926         idx = jme_alloc_txdesc(jme, skb);
1927
1928         if (unlikely(idx < 0)) {
1929                 netif_stop_queue(netdev);
1930                 msg_tx_err(jme, "BUG! Tx ring full when queue awake!\n");
1931
1932                 return NETDEV_TX_BUSY;
1933         }
1934
1935         jme_fill_tx_desc(jme, skb, idx);
1936
1937         jwrite32(jme, JME_TXCS, jme->reg_txcs |
1938                                 TXCS_SELECT_QUEUE0 |
1939                                 TXCS_QUEUE0S |
1940                                 TXCS_ENABLE);
1941         netdev->trans_start = jiffies;
1942
1943         tx_dbg(jme, "xmit: %d+%d@%lu\n", idx,
1944                         skb_shinfo(skb)->nr_frags + 2,
1945                         jiffies);
1946         jme_stop_queue_if_full(jme);
1947
1948         return NETDEV_TX_OK;
1949 }
1950
1951 static int
1952 jme_set_macaddr(struct net_device *netdev, void *p)
1953 {
1954         struct jme_adapter *jme = netdev_priv(netdev);
1955         struct sockaddr *addr = p;
1956         u32 val;
1957
1958         if (netif_running(netdev))
1959                 return -EBUSY;
1960
1961         spin_lock_bh(&jme->macaddr_lock);
1962         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1963
1964         val = (addr->sa_data[3] & 0xff) << 24 |
1965               (addr->sa_data[2] & 0xff) << 16 |
1966               (addr->sa_data[1] & 0xff) <<  8 |
1967               (addr->sa_data[0] & 0xff);
1968         jwrite32(jme, JME_RXUMA_LO, val);
1969         val = (addr->sa_data[5] & 0xff) << 8 |
1970               (addr->sa_data[4] & 0xff);
1971         jwrite32(jme, JME_RXUMA_HI, val);
1972         spin_unlock_bh(&jme->macaddr_lock);
1973
1974         return 0;
1975 }
1976
1977 static void
1978 jme_set_multi(struct net_device *netdev)
1979 {
1980         struct jme_adapter *jme = netdev_priv(netdev);
1981         u32 mc_hash[2] = {};
1982         int i;
1983
1984         spin_lock_bh(&jme->rxmcs_lock);
1985
1986         jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
1987
1988         if (netdev->flags & IFF_PROMISC) {
1989                 jme->reg_rxmcs |= RXMCS_ALLFRAME;
1990         } else if (netdev->flags & IFF_ALLMULTI) {
1991                 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
1992         } else if (netdev->flags & IFF_MULTICAST) {
1993                 struct dev_mc_list *mclist;
1994                 int bit_nr;
1995
1996                 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
1997                 for (i = 0, mclist = netdev->mc_list;
1998                         mclist && i < netdev->mc_count;
1999                         ++i, mclist = mclist->next) {
2000
2001                         bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
2002                         mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2003                 }
2004
2005                 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2006                 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2007         }
2008
2009         wmb();
2010         jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2011
2012         spin_unlock_bh(&jme->rxmcs_lock);
2013 }
2014
2015 static int
2016 jme_change_mtu(struct net_device *netdev, int new_mtu)
2017 {
2018         struct jme_adapter *jme = netdev_priv(netdev);
2019
2020         if (new_mtu == jme->old_mtu)
2021                 return 0;
2022
2023         if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2024                 ((new_mtu) < IPV6_MIN_MTU))
2025                 return -EINVAL;
2026
2027         if (new_mtu > 4000) {
2028                 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2029                 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2030                 jme_restart_rx_engine(jme);
2031         } else {
2032                 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2033                 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2034                 jme_restart_rx_engine(jme);
2035         }
2036
2037         if (new_mtu > 1900) {
2038                 netdev->features &= ~(NETIF_F_HW_CSUM |
2039                                 NETIF_F_TSO |
2040                                 NETIF_F_TSO6);
2041         } else {
2042                 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2043                         netdev->features |= NETIF_F_HW_CSUM;
2044                 if (test_bit(JME_FLAG_TSO, &jme->flags))
2045                         netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2046         }
2047
2048         netdev->mtu = new_mtu;
2049         jme_reset_link(jme);
2050
2051         return 0;
2052 }
2053
2054 static void
2055 jme_tx_timeout(struct net_device *netdev)
2056 {
2057         struct jme_adapter *jme = netdev_priv(netdev);
2058
2059         jme->phylink = 0;
2060         jme_reset_phy_processor(jme);
2061         if (test_bit(JME_FLAG_SSET, &jme->flags))
2062                 jme_set_settings(netdev, &jme->old_ecmd);
2063
2064         /*
2065          * Force to Reset the link again
2066          */
2067         jme_reset_link(jme);
2068 }
2069
2070 static void
2071 jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2072 {
2073         struct jme_adapter *jme = netdev_priv(netdev);
2074
2075         jme->vlgrp = grp;
2076 }
2077
2078 static void
2079 jme_get_drvinfo(struct net_device *netdev,
2080                      struct ethtool_drvinfo *info)
2081 {
2082         struct jme_adapter *jme = netdev_priv(netdev);
2083
2084         strcpy(info->driver, DRV_NAME);
2085         strcpy(info->version, DRV_VERSION);
2086         strcpy(info->bus_info, pci_name(jme->pdev));
2087 }
2088
2089 static int
2090 jme_get_regs_len(struct net_device *netdev)
2091 {
2092         return JME_REG_LEN;
2093 }
2094
2095 static void
2096 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2097 {
2098         int i;
2099
2100         for (i = 0 ; i < len ; i += 4)
2101                 p[i >> 2] = jread32(jme, reg + i);
2102 }
2103
2104 static void
2105 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2106 {
2107         int i;
2108         u16 *p16 = (u16 *)p;
2109
2110         for (i = 0 ; i < reg_nr ; ++i)
2111                 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2112 }
2113
2114 static void
2115 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2116 {
2117         struct jme_adapter *jme = netdev_priv(netdev);
2118         u32 *p32 = (u32 *)p;
2119
2120         memset(p, 0xFF, JME_REG_LEN);
2121
2122         regs->version = 1;
2123         mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2124
2125         p32 += 0x100 >> 2;
2126         mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2127
2128         p32 += 0x100 >> 2;
2129         mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2130
2131         p32 += 0x100 >> 2;
2132         mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2133
2134         p32 += 0x100 >> 2;
2135         mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2136 }
2137
2138 static int
2139 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2140 {
2141         struct jme_adapter *jme = netdev_priv(netdev);
2142
2143         ecmd->tx_coalesce_usecs = PCC_TX_TO;
2144         ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2145
2146         if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2147                 ecmd->use_adaptive_rx_coalesce = false;
2148                 ecmd->rx_coalesce_usecs = 0;
2149                 ecmd->rx_max_coalesced_frames = 0;
2150                 return 0;
2151         }
2152
2153         ecmd->use_adaptive_rx_coalesce = true;
2154
2155         switch (jme->dpi.cur) {
2156         case PCC_P1:
2157                 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2158                 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2159                 break;
2160         case PCC_P2:
2161                 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2162                 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2163                 break;
2164         case PCC_P3:
2165                 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2166                 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2167                 break;
2168         default:
2169                 break;
2170         }
2171
2172         return 0;
2173 }
2174
2175 static int
2176 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2177 {
2178         struct jme_adapter *jme = netdev_priv(netdev);
2179         struct dynpcc_info *dpi = &(jme->dpi);
2180
2181         if (netif_running(netdev))
2182                 return -EBUSY;
2183
2184         if (ecmd->use_adaptive_rx_coalesce
2185         && test_bit(JME_FLAG_POLL, &jme->flags)) {
2186                 clear_bit(JME_FLAG_POLL, &jme->flags);
2187                 jme->jme_rx = netif_rx;
2188                 jme->jme_vlan_rx = vlan_hwaccel_rx;
2189                 dpi->cur                = PCC_P1;
2190                 dpi->attempt            = PCC_P1;
2191                 dpi->cnt                = 0;
2192                 jme_set_rx_pcc(jme, PCC_P1);
2193                 jme_interrupt_mode(jme);
2194         } else if (!(ecmd->use_adaptive_rx_coalesce)
2195         && !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2196                 set_bit(JME_FLAG_POLL, &jme->flags);
2197                 jme->jme_rx = netif_receive_skb;
2198                 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2199                 jme_interrupt_mode(jme);
2200         }
2201
2202         return 0;
2203 }
2204
2205 static void
2206 jme_get_pauseparam(struct net_device *netdev,
2207                         struct ethtool_pauseparam *ecmd)
2208 {
2209         struct jme_adapter *jme = netdev_priv(netdev);
2210         u32 val;
2211
2212         ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2213         ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2214
2215         spin_lock_bh(&jme->phy_lock);
2216         val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2217         spin_unlock_bh(&jme->phy_lock);
2218
2219         ecmd->autoneg =
2220                 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2221 }
2222
2223 static int
2224 jme_set_pauseparam(struct net_device *netdev,
2225                         struct ethtool_pauseparam *ecmd)
2226 {
2227         struct jme_adapter *jme = netdev_priv(netdev);
2228         u32 val;
2229
2230         if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2231                 (ecmd->tx_pause != 0)) {
2232
2233                 if (ecmd->tx_pause)
2234                         jme->reg_txpfc |= TXPFC_PF_EN;
2235                 else
2236                         jme->reg_txpfc &= ~TXPFC_PF_EN;
2237
2238                 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2239         }
2240
2241         spin_lock_bh(&jme->rxmcs_lock);
2242         if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2243                 (ecmd->rx_pause != 0)) {
2244
2245                 if (ecmd->rx_pause)
2246                         jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2247                 else
2248                         jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2249
2250                 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2251         }
2252         spin_unlock_bh(&jme->rxmcs_lock);
2253
2254         spin_lock_bh(&jme->phy_lock);
2255         val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2256         if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2257                 (ecmd->autoneg != 0)) {
2258
2259                 if (ecmd->autoneg)
2260                         val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2261                 else
2262                         val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2263
2264                 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2265                                 MII_ADVERTISE, val);
2266         }
2267         spin_unlock_bh(&jme->phy_lock);
2268
2269         return 0;
2270 }
2271
2272 static void
2273 jme_get_wol(struct net_device *netdev,
2274                 struct ethtool_wolinfo *wol)
2275 {
2276         struct jme_adapter *jme = netdev_priv(netdev);
2277
2278         wol->supported = WAKE_MAGIC | WAKE_PHY;
2279
2280         wol->wolopts = 0;
2281
2282         if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2283                 wol->wolopts |= WAKE_PHY;
2284
2285         if (jme->reg_pmcs & PMCS_MFEN)
2286                 wol->wolopts |= WAKE_MAGIC;
2287
2288 }
2289
2290 static int
2291 jme_set_wol(struct net_device *netdev,
2292                 struct ethtool_wolinfo *wol)
2293 {
2294         struct jme_adapter *jme = netdev_priv(netdev);
2295
2296         if (wol->wolopts & (WAKE_MAGICSECURE |
2297                                 WAKE_UCAST |
2298                                 WAKE_MCAST |
2299                                 WAKE_BCAST |
2300                                 WAKE_ARP))
2301                 return -EOPNOTSUPP;
2302
2303         jme->reg_pmcs = 0;
2304
2305         if (wol->wolopts & WAKE_PHY)
2306                 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2307
2308         if (wol->wolopts & WAKE_MAGIC)
2309                 jme->reg_pmcs |= PMCS_MFEN;
2310
2311         jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2312
2313         return 0;
2314 }
2315
2316 static int
2317 jme_get_settings(struct net_device *netdev,
2318                      struct ethtool_cmd *ecmd)
2319 {
2320         struct jme_adapter *jme = netdev_priv(netdev);
2321         int rc;
2322
2323         spin_lock_bh(&jme->phy_lock);
2324         rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2325         spin_unlock_bh(&jme->phy_lock);
2326         return rc;
2327 }
2328
2329 static int
2330 jme_set_settings(struct net_device *netdev,
2331                      struct ethtool_cmd *ecmd)
2332 {
2333         struct jme_adapter *jme = netdev_priv(netdev);
2334         int rc, fdc = 0;
2335
2336         if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2337                 return -EINVAL;
2338
2339         if (jme->mii_if.force_media &&
2340         ecmd->autoneg != AUTONEG_ENABLE &&
2341         (jme->mii_if.full_duplex != ecmd->duplex))
2342                 fdc = 1;
2343
2344         spin_lock_bh(&jme->phy_lock);
2345         rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2346         spin_unlock_bh(&jme->phy_lock);
2347
2348         if (!rc && fdc)
2349                 jme_reset_link(jme);
2350
2351         if (!rc) {
2352                 set_bit(JME_FLAG_SSET, &jme->flags);
2353                 jme->old_ecmd = *ecmd;
2354         }
2355
2356         return rc;
2357 }
2358
2359 static u32
2360 jme_get_link(struct net_device *netdev)
2361 {
2362         struct jme_adapter *jme = netdev_priv(netdev);
2363         return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2364 }
2365
2366 static u32
2367 jme_get_msglevel(struct net_device *netdev)
2368 {
2369         struct jme_adapter *jme = netdev_priv(netdev);
2370         return jme->msg_enable;
2371 }
2372
2373 static void
2374 jme_set_msglevel(struct net_device *netdev, u32 value)
2375 {
2376         struct jme_adapter *jme = netdev_priv(netdev);
2377         jme->msg_enable = value;
2378 }
2379
2380 static u32
2381 jme_get_rx_csum(struct net_device *netdev)
2382 {
2383         struct jme_adapter *jme = netdev_priv(netdev);
2384         return jme->reg_rxmcs & RXMCS_CHECKSUM;
2385 }
2386
2387 static int
2388 jme_set_rx_csum(struct net_device *netdev, u32 on)
2389 {
2390         struct jme_adapter *jme = netdev_priv(netdev);
2391
2392         spin_lock_bh(&jme->rxmcs_lock);
2393         if (on)
2394                 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2395         else
2396                 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2397         jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2398         spin_unlock_bh(&jme->rxmcs_lock);
2399
2400         return 0;
2401 }
2402
2403 static int
2404 jme_set_tx_csum(struct net_device *netdev, u32 on)
2405 {
2406         struct jme_adapter *jme = netdev_priv(netdev);
2407
2408         if (on) {
2409                 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2410                 if (netdev->mtu <= 1900)
2411                         netdev->features |= NETIF_F_HW_CSUM;
2412         } else {
2413                 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2414                 netdev->features &= ~NETIF_F_HW_CSUM;
2415         }
2416
2417         return 0;
2418 }
2419
2420 static int
2421 jme_set_tso(struct net_device *netdev, u32 on)
2422 {
2423         struct jme_adapter *jme = netdev_priv(netdev);
2424
2425         if (on) {
2426                 set_bit(JME_FLAG_TSO, &jme->flags);
2427                 if (netdev->mtu <= 1900)
2428                         netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2429         } else {
2430                 clear_bit(JME_FLAG_TSO, &jme->flags);
2431                 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2432         }
2433
2434         return 0;
2435 }
2436
2437 static int
2438 jme_nway_reset(struct net_device *netdev)
2439 {
2440         struct jme_adapter *jme = netdev_priv(netdev);
2441         jme_restart_an(jme);
2442         return 0;
2443 }
2444
2445 static u8
2446 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2447 {
2448         u32 val;
2449         int to;
2450
2451         val = jread32(jme, JME_SMBCSR);
2452         to = JME_SMB_BUSY_TIMEOUT;
2453         while ((val & SMBCSR_BUSY) && --to) {
2454                 msleep(1);
2455                 val = jread32(jme, JME_SMBCSR);
2456         }
2457         if (!to) {
2458                 msg_hw(jme, "SMB Bus Busy.\n");
2459                 return 0xFF;
2460         }
2461
2462         jwrite32(jme, JME_SMBINTF,
2463                 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2464                 SMBINTF_HWRWN_READ |
2465                 SMBINTF_HWCMD);
2466
2467         val = jread32(jme, JME_SMBINTF);
2468         to = JME_SMB_BUSY_TIMEOUT;
2469         while ((val & SMBINTF_HWCMD) && --to) {
2470                 msleep(1);
2471                 val = jread32(jme, JME_SMBINTF);
2472         }
2473         if (!to) {
2474                 msg_hw(jme, "SMB Bus Busy.\n");
2475                 return 0xFF;
2476         }
2477
2478         return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2479 }
2480
2481 static void
2482 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2483 {
2484         u32 val;
2485         int to;
2486
2487         val = jread32(jme, JME_SMBCSR);
2488         to = JME_SMB_BUSY_TIMEOUT;
2489         while ((val & SMBCSR_BUSY) && --to) {
2490                 msleep(1);
2491                 val = jread32(jme, JME_SMBCSR);
2492         }
2493         if (!to) {
2494                 msg_hw(jme, "SMB Bus Busy.\n");
2495                 return;
2496         }
2497
2498         jwrite32(jme, JME_SMBINTF,
2499                 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2500                 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2501                 SMBINTF_HWRWN_WRITE |
2502                 SMBINTF_HWCMD);
2503
2504         val = jread32(jme, JME_SMBINTF);
2505         to = JME_SMB_BUSY_TIMEOUT;
2506         while ((val & SMBINTF_HWCMD) && --to) {
2507                 msleep(1);
2508                 val = jread32(jme, JME_SMBINTF);
2509         }
2510         if (!to) {
2511                 msg_hw(jme, "SMB Bus Busy.\n");
2512                 return;
2513         }
2514
2515         mdelay(2);
2516 }
2517
2518 static int
2519 jme_get_eeprom_len(struct net_device *netdev)
2520 {
2521         struct jme_adapter *jme = netdev_priv(netdev);
2522         u32 val;
2523         val = jread32(jme, JME_SMBCSR);
2524         return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2525 }
2526
2527 static int
2528 jme_get_eeprom(struct net_device *netdev,
2529                 struct ethtool_eeprom *eeprom, u8 *data)
2530 {
2531         struct jme_adapter *jme = netdev_priv(netdev);
2532         int i, offset = eeprom->offset, len = eeprom->len;
2533
2534         /*
2535          * ethtool will check the boundary for us
2536          */
2537         eeprom->magic = JME_EEPROM_MAGIC;
2538         for (i = 0 ; i < len ; ++i)
2539                 data[i] = jme_smb_read(jme, i + offset);
2540
2541         return 0;
2542 }
2543
2544 static int
2545 jme_set_eeprom(struct net_device *netdev,
2546                 struct ethtool_eeprom *eeprom, u8 *data)
2547 {
2548         struct jme_adapter *jme = netdev_priv(netdev);
2549         int i, offset = eeprom->offset, len = eeprom->len;
2550
2551         if (eeprom->magic != JME_EEPROM_MAGIC)
2552                 return -EINVAL;
2553
2554         /*
2555          * ethtool will check the boundary for us
2556          */
2557         for (i = 0 ; i < len ; ++i)
2558                 jme_smb_write(jme, i + offset, data[i]);
2559
2560         return 0;
2561 }
2562
2563 static const struct ethtool_ops jme_ethtool_ops = {
2564         .get_drvinfo            = jme_get_drvinfo,
2565         .get_regs_len           = jme_get_regs_len,
2566         .get_regs               = jme_get_regs,
2567         .get_coalesce           = jme_get_coalesce,
2568         .set_coalesce           = jme_set_coalesce,
2569         .get_pauseparam         = jme_get_pauseparam,
2570         .set_pauseparam         = jme_set_pauseparam,
2571         .get_wol                = jme_get_wol,
2572         .set_wol                = jme_set_wol,
2573         .get_settings           = jme_get_settings,
2574         .set_settings           = jme_set_settings,
2575         .get_link               = jme_get_link,
2576         .get_msglevel           = jme_get_msglevel,
2577         .set_msglevel           = jme_set_msglevel,
2578         .get_rx_csum            = jme_get_rx_csum,
2579         .set_rx_csum            = jme_set_rx_csum,
2580         .set_tx_csum            = jme_set_tx_csum,
2581         .set_tso                = jme_set_tso,
2582         .set_sg                 = ethtool_op_set_sg,
2583         .nway_reset             = jme_nway_reset,
2584         .get_eeprom_len         = jme_get_eeprom_len,
2585         .get_eeprom             = jme_get_eeprom,
2586         .set_eeprom             = jme_set_eeprom,
2587 };
2588
2589 static int
2590 jme_pci_dma64(struct pci_dev *pdev)
2591 {
2592         if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2593             !pci_set_dma_mask(pdev, DMA_64BIT_MASK))
2594                 if (!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
2595                         return 1;
2596
2597         if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2598             !pci_set_dma_mask(pdev, DMA_40BIT_MASK))
2599                 if (!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
2600                         return 1;
2601
2602         if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
2603                 if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
2604                         return 0;
2605
2606         return -1;
2607 }
2608
2609 static inline void
2610 jme_phy_init(struct jme_adapter *jme)
2611 {
2612         u16 reg26;
2613
2614         reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2615         jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2616 }
2617
2618 static inline void
2619 jme_check_hw_ver(struct jme_adapter *jme)
2620 {
2621         u32 chipmode;
2622
2623         chipmode = jread32(jme, JME_CHIPMODE);
2624
2625         jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2626         jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2627 }
2628
2629 static const struct net_device_ops jme_netdev_ops = {
2630         .ndo_open               = jme_open,
2631         .ndo_stop               = jme_close,
2632         .ndo_validate_addr      = eth_validate_addr,
2633         .ndo_start_xmit         = jme_start_xmit,
2634         .ndo_set_mac_address    = jme_set_macaddr,
2635         .ndo_set_multicast_list = jme_set_multi,
2636         .ndo_change_mtu         = jme_change_mtu,
2637         .ndo_tx_timeout         = jme_tx_timeout,
2638         .ndo_vlan_rx_register   = jme_vlan_rx_register,
2639 };
2640
2641 static int __devinit
2642 jme_init_one(struct pci_dev *pdev,
2643              const struct pci_device_id *ent)
2644 {
2645         int rc = 0, using_dac, i;
2646         struct net_device *netdev;
2647         struct jme_adapter *jme;
2648         u16 bmcr, bmsr;
2649         u32 apmc;
2650
2651         /*
2652          * set up PCI device basics
2653          */
2654         rc = pci_enable_device(pdev);
2655         if (rc) {
2656                 jeprintk(pdev, "Cannot enable PCI device.\n");
2657                 goto err_out;
2658         }
2659
2660         using_dac = jme_pci_dma64(pdev);
2661         if (using_dac < 0) {
2662                 jeprintk(pdev, "Cannot set PCI DMA Mask.\n");
2663                 rc = -EIO;
2664                 goto err_out_disable_pdev;
2665         }
2666
2667         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2668                 jeprintk(pdev, "No PCI resource region found.\n");
2669                 rc = -ENOMEM;
2670                 goto err_out_disable_pdev;
2671         }
2672
2673         rc = pci_request_regions(pdev, DRV_NAME);
2674         if (rc) {
2675                 jeprintk(pdev, "Cannot obtain PCI resource region.\n");
2676                 goto err_out_disable_pdev;
2677         }
2678
2679         pci_set_master(pdev);
2680
2681         /*
2682          * alloc and init net device
2683          */
2684         netdev = alloc_etherdev(sizeof(*jme));
2685         if (!netdev) {
2686                 jeprintk(pdev, "Cannot allocate netdev structure.\n");
2687                 rc = -ENOMEM;
2688                 goto err_out_release_regions;
2689         }
2690         netdev->netdev_ops = &jme_netdev_ops;
2691         netdev->ethtool_ops             = &jme_ethtool_ops;
2692         netdev->watchdog_timeo          = TX_TIMEOUT;
2693         netdev->features                =       NETIF_F_HW_CSUM |
2694                                                 NETIF_F_SG |
2695                                                 NETIF_F_TSO |
2696                                                 NETIF_F_TSO6 |
2697                                                 NETIF_F_HW_VLAN_TX |
2698                                                 NETIF_F_HW_VLAN_RX;
2699         if (using_dac)
2700                 netdev->features        |=      NETIF_F_HIGHDMA;
2701
2702         SET_NETDEV_DEV(netdev, &pdev->dev);
2703         pci_set_drvdata(pdev, netdev);
2704
2705         /*
2706          * init adapter info
2707          */
2708         jme = netdev_priv(netdev);
2709         jme->pdev = pdev;
2710         jme->dev = netdev;
2711         jme->jme_rx = netif_rx;
2712         jme->jme_vlan_rx = vlan_hwaccel_rx;
2713         jme->old_mtu = netdev->mtu = 1500;
2714         jme->phylink = 0;
2715         jme->tx_ring_size = 1 << 10;
2716         jme->tx_ring_mask = jme->tx_ring_size - 1;
2717         jme->tx_wake_threshold = 1 << 9;
2718         jme->rx_ring_size = 1 << 9;
2719         jme->rx_ring_mask = jme->rx_ring_size - 1;
2720         jme->msg_enable = JME_DEF_MSG_ENABLE;
2721         jme->regs = ioremap(pci_resource_start(pdev, 0),
2722                              pci_resource_len(pdev, 0));
2723         if (!(jme->regs)) {
2724                 jeprintk(pdev, "Mapping PCI resource region error.\n");
2725                 rc = -ENOMEM;
2726                 goto err_out_free_netdev;
2727         }
2728         jme->shadow_regs = pci_alloc_consistent(pdev,
2729                                                 sizeof(u32) * SHADOW_REG_NR,
2730                                                 &(jme->shadow_dma));
2731         if (!(jme->shadow_regs)) {
2732                 jeprintk(pdev, "Allocating shadow register mapping error.\n");
2733                 rc = -ENOMEM;
2734                 goto err_out_unmap;
2735         }
2736
2737         if (no_pseudohp) {
2738                 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2739                 jwrite32(jme, JME_APMC, apmc);
2740         } else if (force_pseudohp) {
2741                 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2742                 jwrite32(jme, JME_APMC, apmc);
2743         }
2744
2745         NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
2746
2747         spin_lock_init(&jme->phy_lock);
2748         spin_lock_init(&jme->macaddr_lock);
2749         spin_lock_init(&jme->rxmcs_lock);
2750
2751         atomic_set(&jme->link_changing, 1);
2752         atomic_set(&jme->rx_cleaning, 1);
2753         atomic_set(&jme->tx_cleaning, 1);
2754         atomic_set(&jme->rx_empty, 1);
2755
2756         tasklet_init(&jme->pcc_task,
2757                      &jme_pcc_tasklet,
2758                      (unsigned long) jme);
2759         tasklet_init(&jme->linkch_task,
2760                      &jme_link_change_tasklet,
2761                      (unsigned long) jme);
2762         tasklet_init(&jme->txclean_task,
2763                      &jme_tx_clean_tasklet,
2764                      (unsigned long) jme);
2765         tasklet_init(&jme->rxclean_task,
2766                      &jme_rx_clean_tasklet,
2767                      (unsigned long) jme);
2768         tasklet_init(&jme->rxempty_task,
2769                      &jme_rx_empty_tasklet,
2770                      (unsigned long) jme);
2771         tasklet_disable_nosync(&jme->txclean_task);
2772         tasklet_disable_nosync(&jme->rxclean_task);
2773         tasklet_disable_nosync(&jme->rxempty_task);
2774         jme->dpi.cur = PCC_P1;
2775
2776         jme->reg_ghc = 0;
2777         jme->reg_rxcs = RXCS_DEFAULT;
2778         jme->reg_rxmcs = RXMCS_DEFAULT;
2779         jme->reg_txpfc = 0;
2780         jme->reg_pmcs = PMCS_MFEN;
2781         set_bit(JME_FLAG_TXCSUM, &jme->flags);
2782         set_bit(JME_FLAG_TSO, &jme->flags);
2783
2784         /*
2785          * Get Max Read Req Size from PCI Config Space
2786          */
2787         pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
2788         jme->mrrs &= PCI_DCSR_MRRS_MASK;
2789         switch (jme->mrrs) {
2790         case MRRS_128B:
2791                 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2792                 break;
2793         case MRRS_256B:
2794                 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2795                 break;
2796         default:
2797                 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2798                 break;
2799         };
2800
2801         /*
2802          * Must check before reset_mac_processor
2803          */
2804         jme_check_hw_ver(jme);
2805         jme->mii_if.dev = netdev;
2806         if (jme->fpgaver) {
2807                 jme->mii_if.phy_id = 0;
2808                 for (i = 1 ; i < 32 ; ++i) {
2809                         bmcr = jme_mdio_read(netdev, i, MII_BMCR);
2810                         bmsr = jme_mdio_read(netdev, i, MII_BMSR);
2811                         if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
2812                                 jme->mii_if.phy_id = i;
2813                                 break;
2814                         }
2815                 }
2816
2817                 if (!jme->mii_if.phy_id) {
2818                         rc = -EIO;
2819                         jeprintk(pdev, "Can not find phy_id.\n");
2820                          goto err_out_free_shadow;
2821                 }
2822
2823                 jme->reg_ghc |= GHC_LINK_POLL;
2824         } else {
2825                 jme->mii_if.phy_id = 1;
2826         }
2827         if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
2828                 jme->mii_if.supports_gmii = true;
2829         else
2830                 jme->mii_if.supports_gmii = false;
2831         jme->mii_if.mdio_read = jme_mdio_read;
2832         jme->mii_if.mdio_write = jme_mdio_write;
2833
2834         jme_clear_pm(jme);
2835         jme_set_phyfifoa(jme);
2836         pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev);
2837         if (!jme->fpgaver)
2838                 jme_phy_init(jme);
2839         jme_phy_off(jme);
2840
2841         /*
2842          * Reset MAC processor and reload EEPROM for MAC Address
2843          */
2844         jme_reset_mac_processor(jme);
2845         rc = jme_reload_eeprom(jme);
2846         if (rc) {
2847                 jeprintk(pdev,
2848                         "Reload eeprom for reading MAC Address error.\n");
2849                 goto err_out_free_shadow;
2850         }
2851         jme_load_macaddr(netdev);
2852
2853         /*
2854          * Tell stack that we are not ready to work until open()
2855          */
2856         netif_carrier_off(netdev);
2857         netif_stop_queue(netdev);
2858
2859         /*
2860          * Register netdev
2861          */
2862         rc = register_netdev(netdev);
2863         if (rc) {
2864                 jeprintk(pdev, "Cannot register net device.\n");
2865                 goto err_out_free_shadow;
2866         }
2867
2868         msg_probe(jme, "%s%s ver:%x rev:%x macaddr:%pM\n",
2869                 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
2870                         "JMC250 Gigabit Ethernet" :
2871                         (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
2872                                 "JMC260 Fast Ethernet" : "Unknown",
2873                 (jme->fpgaver != 0) ? " (FPGA)" : "",
2874                 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
2875                 jme->rev, netdev->dev_addr);
2876
2877         return 0;
2878
2879 err_out_free_shadow:
2880         pci_free_consistent(pdev,
2881                             sizeof(u32) * SHADOW_REG_NR,
2882                             jme->shadow_regs,
2883                             jme->shadow_dma);
2884 err_out_unmap:
2885         iounmap(jme->regs);
2886 err_out_free_netdev:
2887         pci_set_drvdata(pdev, NULL);
2888         free_netdev(netdev);
2889 err_out_release_regions:
2890         pci_release_regions(pdev);
2891 err_out_disable_pdev:
2892         pci_disable_device(pdev);
2893 err_out:
2894         return rc;
2895 }
2896
2897 static void __devexit
2898 jme_remove_one(struct pci_dev *pdev)
2899 {
2900         struct net_device *netdev = pci_get_drvdata(pdev);
2901         struct jme_adapter *jme = netdev_priv(netdev);
2902
2903         unregister_netdev(netdev);
2904         pci_free_consistent(pdev,
2905                             sizeof(u32) * SHADOW_REG_NR,
2906                             jme->shadow_regs,
2907                             jme->shadow_dma);
2908         iounmap(jme->regs);
2909         pci_set_drvdata(pdev, NULL);
2910         free_netdev(netdev);
2911         pci_release_regions(pdev);
2912         pci_disable_device(pdev);
2913
2914 }
2915
2916 #ifdef CONFIG_PM
2917 static int
2918 jme_suspend(struct pci_dev *pdev, pm_message_t state)
2919 {
2920         struct net_device *netdev = pci_get_drvdata(pdev);
2921         struct jme_adapter *jme = netdev_priv(netdev);
2922
2923         atomic_dec(&jme->link_changing);
2924
2925         netif_device_detach(netdev);
2926         netif_stop_queue(netdev);
2927         jme_stop_irq(jme);
2928
2929         tasklet_disable(&jme->txclean_task);
2930         tasklet_disable(&jme->rxclean_task);
2931         tasklet_disable(&jme->rxempty_task);
2932
2933         jme_disable_shadow(jme);
2934
2935         if (netif_carrier_ok(netdev)) {
2936                 if (test_bit(JME_FLAG_POLL, &jme->flags))
2937                         jme_polling_mode(jme);
2938
2939                 jme_stop_pcc_timer(jme);
2940                 jme_reset_ghc_speed(jme);
2941                 jme_disable_rx_engine(jme);
2942                 jme_disable_tx_engine(jme);
2943                 jme_reset_mac_processor(jme);
2944                 jme_free_rx_resources(jme);
2945                 jme_free_tx_resources(jme);
2946                 netif_carrier_off(netdev);
2947                 jme->phylink = 0;
2948         }
2949
2950         tasklet_enable(&jme->txclean_task);
2951         tasklet_hi_enable(&jme->rxclean_task);
2952         tasklet_hi_enable(&jme->rxempty_task);
2953
2954         pci_save_state(pdev);
2955         if (jme->reg_pmcs) {
2956                 jme_set_100m_half(jme);
2957
2958                 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2959                         jme_wait_link(jme);
2960
2961                 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2962
2963                 pci_enable_wake(pdev, PCI_D3cold, true);
2964         } else {
2965                 jme_phy_off(jme);
2966         }
2967         pci_set_power_state(pdev, PCI_D3cold);
2968
2969         return 0;
2970 }
2971
2972 static int
2973 jme_resume(struct pci_dev *pdev)
2974 {
2975         struct net_device *netdev = pci_get_drvdata(pdev);
2976         struct jme_adapter *jme = netdev_priv(netdev);
2977
2978         jme_clear_pm(jme);
2979         pci_restore_state(pdev);
2980
2981         if (test_bit(JME_FLAG_SSET, &jme->flags))
2982                 jme_set_settings(netdev, &jme->old_ecmd);
2983         else
2984                 jme_reset_phy_processor(jme);
2985
2986         jme_enable_shadow(jme);
2987         jme_start_irq(jme);
2988         netif_device_attach(netdev);
2989
2990         atomic_inc(&jme->link_changing);
2991
2992         jme_reset_link(jme);
2993
2994         return 0;
2995 }
2996 #endif
2997
2998 static struct pci_device_id jme_pci_tbl[] = {
2999         { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3000         { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3001         { }
3002 };
3003
3004 static struct pci_driver jme_driver = {
3005         .name           = DRV_NAME,
3006         .id_table       = jme_pci_tbl,
3007         .probe          = jme_init_one,
3008         .remove         = __devexit_p(jme_remove_one),
3009 #ifdef CONFIG_PM
3010         .suspend        = jme_suspend,
3011         .resume         = jme_resume,
3012 #endif /* CONFIG_PM */
3013 };
3014
3015 static int __init
3016 jme_init_module(void)
3017 {
3018         printk(KERN_INFO PFX "JMicron JMC2XX ethernet "
3019                "driver version %s\n", DRV_VERSION);
3020         return pci_register_driver(&jme_driver);
3021 }
3022
3023 static void __exit
3024 jme_cleanup_module(void)
3025 {
3026         pci_unregister_driver(&jme_driver);
3027 }
3028
3029 module_init(jme_init_module);
3030 module_exit(jme_cleanup_module);
3031
3032 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3033 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3034 MODULE_LICENSE("GPL");
3035 MODULE_VERSION(DRV_VERSION);
3036 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3037