include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[jme.git] / jme.c
1 /*
2  * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3  *
4  * Copyright 2008 JMicron Technology Corporation
5  * http://www.jmicron.com/
6  *
7  * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2 of the License.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21  *
22  */
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/pci.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
29 #include <linux/ethtool.h>
30 #include <linux/mii.h>
31 #include <linux/crc32.h>
32 #include <linux/delay.h>
33 #include <linux/spinlock.h>
34 #include <linux/in.h>
35 #include <linux/ip.h>
36 #include <linux/ipv6.h>
37 #include <linux/tcp.h>
38 #include <linux/udp.h>
39 #include <linux/if_vlan.h>
40 #include <linux/slab.h>
41 #include <net/ip6_checksum.h>
42 #include "jme.h"
43
44 static int force_pseudohp = -1;
45 static int no_pseudohp = -1;
46 static int no_extplug = -1;
47 module_param(force_pseudohp, int, 0);
48 MODULE_PARM_DESC(force_pseudohp,
49         "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
50 module_param(no_pseudohp, int, 0);
51 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
52 module_param(no_extplug, int, 0);
53 MODULE_PARM_DESC(no_extplug,
54         "Do not use external plug signal for pseudo hot-plug.");
55
56 static int
57 jme_mdio_read(struct net_device *netdev, int phy, int reg)
58 {
59         struct jme_adapter *jme = netdev_priv(netdev);
60         int i, val, again = (reg == MII_BMSR) ? 1 : 0;
61
62 read_again:
63         jwrite32(jme, JME_SMI, SMI_OP_REQ |
64                                 smi_phy_addr(phy) |
65                                 smi_reg_addr(reg));
66
67         wmb();
68         for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
69                 udelay(20);
70                 val = jread32(jme, JME_SMI);
71                 if ((val & SMI_OP_REQ) == 0)
72                         break;
73         }
74
75         if (i == 0) {
76                 jeprintk(jme->pdev, "phy(%d) read timeout : %d\n", phy, reg);
77                 return 0;
78         }
79
80         if (again--)
81                 goto read_again;
82
83         return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
84 }
85
86 static void
87 jme_mdio_write(struct net_device *netdev,
88                                 int phy, int reg, int val)
89 {
90         struct jme_adapter *jme = netdev_priv(netdev);
91         int i;
92
93         jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
94                 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
95                 smi_phy_addr(phy) | smi_reg_addr(reg));
96
97         wmb();
98         for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
99                 udelay(20);
100                 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
101                         break;
102         }
103
104         if (i == 0)
105                 jeprintk(jme->pdev, "phy(%d) write timeout : %d\n", phy, reg);
106
107         return;
108 }
109
110 static inline void
111 jme_reset_phy_processor(struct jme_adapter *jme)
112 {
113         u32 val;
114
115         jme_mdio_write(jme->dev,
116                         jme->mii_if.phy_id,
117                         MII_ADVERTISE, ADVERTISE_ALL |
118                         ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
119
120         if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
121                 jme_mdio_write(jme->dev,
122                                 jme->mii_if.phy_id,
123                                 MII_CTRL1000,
124                                 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
125
126         val = jme_mdio_read(jme->dev,
127                                 jme->mii_if.phy_id,
128                                 MII_BMCR);
129
130         jme_mdio_write(jme->dev,
131                         jme->mii_if.phy_id,
132                         MII_BMCR, val | BMCR_RESET);
133
134         return;
135 }
136
137 static void
138 jme_setup_wakeup_frame(struct jme_adapter *jme,
139                 u32 *mask, u32 crc, int fnr)
140 {
141         int i;
142
143         /*
144          * Setup CRC pattern
145          */
146         jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
147         wmb();
148         jwrite32(jme, JME_WFODP, crc);
149         wmb();
150
151         /*
152          * Setup Mask
153          */
154         for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
155                 jwrite32(jme, JME_WFOI,
156                                 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
157                                 (fnr & WFOI_FRAME_SEL));
158                 wmb();
159                 jwrite32(jme, JME_WFODP, mask[i]);
160                 wmb();
161         }
162 }
163
164 static inline void
165 jme_reset_mac_processor(struct jme_adapter *jme)
166 {
167         u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
168         u32 crc = 0xCDCDCDCD;
169         u32 gpreg0;
170         int i;
171
172         jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
173         udelay(2);
174         jwrite32(jme, JME_GHC, jme->reg_ghc);
175
176         jwrite32(jme, JME_RXDBA_LO, 0x00000000);
177         jwrite32(jme, JME_RXDBA_HI, 0x00000000);
178         jwrite32(jme, JME_RXQDC, 0x00000000);
179         jwrite32(jme, JME_RXNDA, 0x00000000);
180         jwrite32(jme, JME_TXDBA_LO, 0x00000000);
181         jwrite32(jme, JME_TXDBA_HI, 0x00000000);
182         jwrite32(jme, JME_TXQDC, 0x00000000);
183         jwrite32(jme, JME_TXNDA, 0x00000000);
184
185         jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
186         jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
187         for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
188                 jme_setup_wakeup_frame(jme, mask, crc, i);
189         if (jme->fpgaver)
190                 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
191         else
192                 gpreg0 = GPREG0_DEFAULT;
193         jwrite32(jme, JME_GPREG0, gpreg0);
194         jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
195 }
196
197 static inline void
198 jme_reset_ghc_speed(struct jme_adapter *jme)
199 {
200         jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
201         jwrite32(jme, JME_GHC, jme->reg_ghc);
202 }
203
204 static inline void
205 jme_clear_pm(struct jme_adapter *jme)
206 {
207         jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
208         pci_set_power_state(jme->pdev, PCI_D0);
209         pci_enable_wake(jme->pdev, PCI_D0, false);
210 }
211
212 static int
213 jme_reload_eeprom(struct jme_adapter *jme)
214 {
215         u32 val;
216         int i;
217
218         val = jread32(jme, JME_SMBCSR);
219
220         if (val & SMBCSR_EEPROMD) {
221                 val |= SMBCSR_CNACK;
222                 jwrite32(jme, JME_SMBCSR, val);
223                 val |= SMBCSR_RELOAD;
224                 jwrite32(jme, JME_SMBCSR, val);
225                 mdelay(12);
226
227                 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
228                         mdelay(1);
229                         if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
230                                 break;
231                 }
232
233                 if (i == 0) {
234                         jeprintk(jme->pdev, "eeprom reload timeout\n");
235                         return -EIO;
236                 }
237         }
238
239         return 0;
240 }
241
242 static void
243 jme_load_macaddr(struct net_device *netdev)
244 {
245         struct jme_adapter *jme = netdev_priv(netdev);
246         unsigned char macaddr[6];
247         u32 val;
248
249         spin_lock_bh(&jme->macaddr_lock);
250         val = jread32(jme, JME_RXUMA_LO);
251         macaddr[0] = (val >>  0) & 0xFF;
252         macaddr[1] = (val >>  8) & 0xFF;
253         macaddr[2] = (val >> 16) & 0xFF;
254         macaddr[3] = (val >> 24) & 0xFF;
255         val = jread32(jme, JME_RXUMA_HI);
256         macaddr[4] = (val >>  0) & 0xFF;
257         macaddr[5] = (val >>  8) & 0xFF;
258         memcpy(netdev->dev_addr, macaddr, 6);
259         spin_unlock_bh(&jme->macaddr_lock);
260 }
261
262 static inline void
263 jme_set_rx_pcc(struct jme_adapter *jme, int p)
264 {
265         switch (p) {
266         case PCC_OFF:
267                 jwrite32(jme, JME_PCCRX0,
268                         ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
269                         ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
270                 break;
271         case PCC_P1:
272                 jwrite32(jme, JME_PCCRX0,
273                         ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
274                         ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
275                 break;
276         case PCC_P2:
277                 jwrite32(jme, JME_PCCRX0,
278                         ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
279                         ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
280                 break;
281         case PCC_P3:
282                 jwrite32(jme, JME_PCCRX0,
283                         ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
284                         ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
285                 break;
286         default:
287                 break;
288         }
289         wmb();
290
291         if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
292                 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
293 }
294
295 static void
296 jme_start_irq(struct jme_adapter *jme)
297 {
298         register struct dynpcc_info *dpi = &(jme->dpi);
299
300         jme_set_rx_pcc(jme, PCC_P1);
301         dpi->cur                = PCC_P1;
302         dpi->attempt            = PCC_P1;
303         dpi->cnt                = 0;
304
305         jwrite32(jme, JME_PCCTX,
306                         ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
307                         ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
308                         PCCTXQ0_EN
309                 );
310
311         /*
312          * Enable Interrupts
313          */
314         jwrite32(jme, JME_IENS, INTR_ENABLE);
315 }
316
317 static inline void
318 jme_stop_irq(struct jme_adapter *jme)
319 {
320         /*
321          * Disable Interrupts
322          */
323         jwrite32f(jme, JME_IENC, INTR_ENABLE);
324 }
325
326 static u32
327 jme_linkstat_from_phy(struct jme_adapter *jme)
328 {
329         u32 phylink, bmsr;
330
331         phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
332         bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
333         if (bmsr & BMSR_ANCOMP)
334                 phylink |= PHY_LINK_AUTONEG_COMPLETE;
335
336         return phylink;
337 }
338
339 static inline void
340 jme_set_phyfifoa(struct jme_adapter *jme)
341 {
342         jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
343 }
344
345 static inline void
346 jme_set_phyfifob(struct jme_adapter *jme)
347 {
348         jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
349 }
350
351 static int
352 jme_check_link(struct net_device *netdev, int testonly)
353 {
354         struct jme_adapter *jme = netdev_priv(netdev);
355         u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
356         char linkmsg[64];
357         int rc = 0;
358
359         linkmsg[0] = '\0';
360
361         if (jme->fpgaver)
362                 phylink = jme_linkstat_from_phy(jme);
363         else
364                 phylink = jread32(jme, JME_PHY_LINK);
365
366         if (phylink & PHY_LINK_UP) {
367                 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
368                         /*
369                          * If we did not enable AN
370                          * Speed/Duplex Info should be obtained from SMI
371                          */
372                         phylink = PHY_LINK_UP;
373
374                         bmcr = jme_mdio_read(jme->dev,
375                                                 jme->mii_if.phy_id,
376                                                 MII_BMCR);
377
378                         phylink |= ((bmcr & BMCR_SPEED1000) &&
379                                         (bmcr & BMCR_SPEED100) == 0) ?
380                                         PHY_LINK_SPEED_1000M :
381                                         (bmcr & BMCR_SPEED100) ?
382                                         PHY_LINK_SPEED_100M :
383                                         PHY_LINK_SPEED_10M;
384
385                         phylink |= (bmcr & BMCR_FULLDPLX) ?
386                                          PHY_LINK_DUPLEX : 0;
387
388                         strcat(linkmsg, "Forced: ");
389                 } else {
390                         /*
391                          * Keep polling for speed/duplex resolve complete
392                          */
393                         while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
394                                 --cnt) {
395
396                                 udelay(1);
397
398                                 if (jme->fpgaver)
399                                         phylink = jme_linkstat_from_phy(jme);
400                                 else
401                                         phylink = jread32(jme, JME_PHY_LINK);
402                         }
403                         if (!cnt)
404                                 jeprintk(jme->pdev,
405                                         "Waiting speed resolve timeout.\n");
406
407                         strcat(linkmsg, "ANed: ");
408                 }
409
410                 if (jme->phylink == phylink) {
411                         rc = 1;
412                         goto out;
413                 }
414                 if (testonly)
415                         goto out;
416
417                 jme->phylink = phylink;
418
419                 ghc = jme->reg_ghc & ~(GHC_SPEED | GHC_DPX |
420                                 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE |
421                                 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY);
422                 switch (phylink & PHY_LINK_SPEED_MASK) {
423                 case PHY_LINK_SPEED_10M:
424                         ghc |= GHC_SPEED_10M |
425                                 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
426                         strcat(linkmsg, "10 Mbps, ");
427                         break;
428                 case PHY_LINK_SPEED_100M:
429                         ghc |= GHC_SPEED_100M |
430                                 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
431                         strcat(linkmsg, "100 Mbps, ");
432                         break;
433                 case PHY_LINK_SPEED_1000M:
434                         ghc |= GHC_SPEED_1000M |
435                                 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
436                         strcat(linkmsg, "1000 Mbps, ");
437                         break;
438                 default:
439                         break;
440                 }
441
442                 if (phylink & PHY_LINK_DUPLEX) {
443                         jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
444                         ghc |= GHC_DPX;
445                 } else {
446                         jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
447                                                 TXMCS_BACKOFF |
448                                                 TXMCS_CARRIERSENSE |
449                                                 TXMCS_COLLISION);
450                         jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
451                                 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
452                                 TXTRHD_TXREN |
453                                 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
454                 }
455
456                 gpreg1 = GPREG1_DEFAULT;
457                 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
458                         if (!(phylink & PHY_LINK_DUPLEX))
459                                 gpreg1 |= GPREG1_HALFMODEPATCH;
460                         switch (phylink & PHY_LINK_SPEED_MASK) {
461                         case PHY_LINK_SPEED_10M:
462                                 jme_set_phyfifoa(jme);
463                                 gpreg1 |= GPREG1_RSSPATCH;
464                                 break;
465                         case PHY_LINK_SPEED_100M:
466                                 jme_set_phyfifob(jme);
467                                 gpreg1 |= GPREG1_RSSPATCH;
468                                 break;
469                         case PHY_LINK_SPEED_1000M:
470                                 jme_set_phyfifoa(jme);
471                                 break;
472                         default:
473                                 break;
474                         }
475                 }
476
477                 jwrite32(jme, JME_GPREG1, gpreg1);
478                 jwrite32(jme, JME_GHC, ghc);
479                 jme->reg_ghc = ghc;
480
481                 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
482                                         "Full-Duplex, " :
483                                         "Half-Duplex, ");
484                 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
485                                         "MDI-X" :
486                                         "MDI");
487                 netif_info(jme, link, jme->dev, "Link is up at %s.\n", linkmsg);
488                 netif_carrier_on(netdev);
489         } else {
490                 if (testonly)
491                         goto out;
492
493                 netif_info(jme, link, jme->dev, "Link is down.\n");
494                 jme->phylink = 0;
495                 netif_carrier_off(netdev);
496         }
497
498 out:
499         return rc;
500 }
501
502 static int
503 jme_setup_tx_resources(struct jme_adapter *jme)
504 {
505         struct jme_ring *txring = &(jme->txring[0]);
506
507         txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
508                                    TX_RING_ALLOC_SIZE(jme->tx_ring_size),
509                                    &(txring->dmaalloc),
510                                    GFP_ATOMIC);
511
512         if (!txring->alloc)
513                 goto err_set_null;
514
515         /*
516          * 16 Bytes align
517          */
518         txring->desc            = (void *)ALIGN((unsigned long)(txring->alloc),
519                                                 RING_DESC_ALIGN);
520         txring->dma             = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
521         txring->next_to_use     = 0;
522         atomic_set(&txring->next_to_clean, 0);
523         atomic_set(&txring->nr_free, jme->tx_ring_size);
524
525         txring->bufinf          = kmalloc(sizeof(struct jme_buffer_info) *
526                                         jme->tx_ring_size, GFP_ATOMIC);
527         if (unlikely(!(txring->bufinf)))
528                 goto err_free_txring;
529
530         /*
531          * Initialize Transmit Descriptors
532          */
533         memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
534         memset(txring->bufinf, 0,
535                 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
536
537         return 0;
538
539 err_free_txring:
540         dma_free_coherent(&(jme->pdev->dev),
541                           TX_RING_ALLOC_SIZE(jme->tx_ring_size),
542                           txring->alloc,
543                           txring->dmaalloc);
544
545 err_set_null:
546         txring->desc = NULL;
547         txring->dmaalloc = 0;
548         txring->dma = 0;
549         txring->bufinf = NULL;
550
551         return -ENOMEM;
552 }
553
554 static void
555 jme_free_tx_resources(struct jme_adapter *jme)
556 {
557         int i;
558         struct jme_ring *txring = &(jme->txring[0]);
559         struct jme_buffer_info *txbi;
560
561         if (txring->alloc) {
562                 if (txring->bufinf) {
563                         for (i = 0 ; i < jme->tx_ring_size ; ++i) {
564                                 txbi = txring->bufinf + i;
565                                 if (txbi->skb) {
566                                         dev_kfree_skb(txbi->skb);
567                                         txbi->skb = NULL;
568                                 }
569                                 txbi->mapping           = 0;
570                                 txbi->len               = 0;
571                                 txbi->nr_desc           = 0;
572                                 txbi->start_xmit        = 0;
573                         }
574                         kfree(txring->bufinf);
575                 }
576
577                 dma_free_coherent(&(jme->pdev->dev),
578                                   TX_RING_ALLOC_SIZE(jme->tx_ring_size),
579                                   txring->alloc,
580                                   txring->dmaalloc);
581
582                 txring->alloc           = NULL;
583                 txring->desc            = NULL;
584                 txring->dmaalloc        = 0;
585                 txring->dma             = 0;
586                 txring->bufinf          = NULL;
587         }
588         txring->next_to_use     = 0;
589         atomic_set(&txring->next_to_clean, 0);
590         atomic_set(&txring->nr_free, 0);
591 }
592
593 static inline void
594 jme_enable_tx_engine(struct jme_adapter *jme)
595 {
596         /*
597          * Select Queue 0
598          */
599         jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
600         wmb();
601
602         /*
603          * Setup TX Queue 0 DMA Bass Address
604          */
605         jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
606         jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
607         jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
608
609         /*
610          * Setup TX Descptor Count
611          */
612         jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
613
614         /*
615          * Enable TX Engine
616          */
617         wmb();
618         jwrite32(jme, JME_TXCS, jme->reg_txcs |
619                                 TXCS_SELECT_QUEUE0 |
620                                 TXCS_ENABLE);
621
622 }
623
624 static inline void
625 jme_restart_tx_engine(struct jme_adapter *jme)
626 {
627         /*
628          * Restart TX Engine
629          */
630         jwrite32(jme, JME_TXCS, jme->reg_txcs |
631                                 TXCS_SELECT_QUEUE0 |
632                                 TXCS_ENABLE);
633 }
634
635 static inline void
636 jme_disable_tx_engine(struct jme_adapter *jme)
637 {
638         int i;
639         u32 val;
640
641         /*
642          * Disable TX Engine
643          */
644         jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
645         wmb();
646
647         val = jread32(jme, JME_TXCS);
648         for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
649                 mdelay(1);
650                 val = jread32(jme, JME_TXCS);
651                 rmb();
652         }
653
654         if (!i)
655                 jeprintk(jme->pdev, "Disable TX engine timeout.\n");
656 }
657
658 static void
659 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
660 {
661         struct jme_ring *rxring = &(jme->rxring[0]);
662         register struct rxdesc *rxdesc = rxring->desc;
663         struct jme_buffer_info *rxbi = rxring->bufinf;
664         rxdesc += i;
665         rxbi += i;
666
667         rxdesc->dw[0] = 0;
668         rxdesc->dw[1] = 0;
669         rxdesc->desc1.bufaddrh  = cpu_to_le32((__u64)rxbi->mapping >> 32);
670         rxdesc->desc1.bufaddrl  = cpu_to_le32(
671                                         (__u64)rxbi->mapping & 0xFFFFFFFFUL);
672         rxdesc->desc1.datalen   = cpu_to_le16(rxbi->len);
673         if (jme->dev->features & NETIF_F_HIGHDMA)
674                 rxdesc->desc1.flags = RXFLAG_64BIT;
675         wmb();
676         rxdesc->desc1.flags     |= RXFLAG_OWN | RXFLAG_INT;
677 }
678
679 static int
680 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
681 {
682         struct jme_ring *rxring = &(jme->rxring[0]);
683         struct jme_buffer_info *rxbi = rxring->bufinf + i;
684         struct sk_buff *skb;
685
686         skb = netdev_alloc_skb(jme->dev,
687                 jme->dev->mtu + RX_EXTRA_LEN);
688         if (unlikely(!skb))
689                 return -ENOMEM;
690
691         rxbi->skb = skb;
692         rxbi->len = skb_tailroom(skb);
693         rxbi->mapping = pci_map_page(jme->pdev,
694                                         virt_to_page(skb->data),
695                                         offset_in_page(skb->data),
696                                         rxbi->len,
697                                         PCI_DMA_FROMDEVICE);
698
699         return 0;
700 }
701
702 static void
703 jme_free_rx_buf(struct jme_adapter *jme, int i)
704 {
705         struct jme_ring *rxring = &(jme->rxring[0]);
706         struct jme_buffer_info *rxbi = rxring->bufinf;
707         rxbi += i;
708
709         if (rxbi->skb) {
710                 pci_unmap_page(jme->pdev,
711                                  rxbi->mapping,
712                                  rxbi->len,
713                                  PCI_DMA_FROMDEVICE);
714                 dev_kfree_skb(rxbi->skb);
715                 rxbi->skb = NULL;
716                 rxbi->mapping = 0;
717                 rxbi->len = 0;
718         }
719 }
720
721 static void
722 jme_free_rx_resources(struct jme_adapter *jme)
723 {
724         int i;
725         struct jme_ring *rxring = &(jme->rxring[0]);
726
727         if (rxring->alloc) {
728                 if (rxring->bufinf) {
729                         for (i = 0 ; i < jme->rx_ring_size ; ++i)
730                                 jme_free_rx_buf(jme, i);
731                         kfree(rxring->bufinf);
732                 }
733
734                 dma_free_coherent(&(jme->pdev->dev),
735                                   RX_RING_ALLOC_SIZE(jme->rx_ring_size),
736                                   rxring->alloc,
737                                   rxring->dmaalloc);
738                 rxring->alloc    = NULL;
739                 rxring->desc     = NULL;
740                 rxring->dmaalloc = 0;
741                 rxring->dma      = 0;
742                 rxring->bufinf   = NULL;
743         }
744         rxring->next_to_use   = 0;
745         atomic_set(&rxring->next_to_clean, 0);
746 }
747
748 static int
749 jme_setup_rx_resources(struct jme_adapter *jme)
750 {
751         int i;
752         struct jme_ring *rxring = &(jme->rxring[0]);
753
754         rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
755                                    RX_RING_ALLOC_SIZE(jme->rx_ring_size),
756                                    &(rxring->dmaalloc),
757                                    GFP_ATOMIC);
758         if (!rxring->alloc)
759                 goto err_set_null;
760
761         /*
762          * 16 Bytes align
763          */
764         rxring->desc            = (void *)ALIGN((unsigned long)(rxring->alloc),
765                                                 RING_DESC_ALIGN);
766         rxring->dma             = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
767         rxring->next_to_use     = 0;
768         atomic_set(&rxring->next_to_clean, 0);
769
770         rxring->bufinf          = kmalloc(sizeof(struct jme_buffer_info) *
771                                         jme->rx_ring_size, GFP_ATOMIC);
772         if (unlikely(!(rxring->bufinf)))
773                 goto err_free_rxring;
774
775         /*
776          * Initiallize Receive Descriptors
777          */
778         memset(rxring->bufinf, 0,
779                 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
780         for (i = 0 ; i < jme->rx_ring_size ; ++i) {
781                 if (unlikely(jme_make_new_rx_buf(jme, i))) {
782                         jme_free_rx_resources(jme);
783                         return -ENOMEM;
784                 }
785
786                 jme_set_clean_rxdesc(jme, i);
787         }
788
789         return 0;
790
791 err_free_rxring:
792         dma_free_coherent(&(jme->pdev->dev),
793                           RX_RING_ALLOC_SIZE(jme->rx_ring_size),
794                           rxring->alloc,
795                           rxring->dmaalloc);
796 err_set_null:
797         rxring->desc = NULL;
798         rxring->dmaalloc = 0;
799         rxring->dma = 0;
800         rxring->bufinf = NULL;
801
802         return -ENOMEM;
803 }
804
805 static inline void
806 jme_enable_rx_engine(struct jme_adapter *jme)
807 {
808         /*
809          * Select Queue 0
810          */
811         jwrite32(jme, JME_RXCS, jme->reg_rxcs |
812                                 RXCS_QUEUESEL_Q0);
813         wmb();
814
815         /*
816          * Setup RX DMA Bass Address
817          */
818         jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
819         jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
820         jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
821
822         /*
823          * Setup RX Descriptor Count
824          */
825         jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
826
827         /*
828          * Setup Unicast Filter
829          */
830         jme_set_multi(jme->dev);
831
832         /*
833          * Enable RX Engine
834          */
835         wmb();
836         jwrite32(jme, JME_RXCS, jme->reg_rxcs |
837                                 RXCS_QUEUESEL_Q0 |
838                                 RXCS_ENABLE |
839                                 RXCS_QST);
840 }
841
842 static inline void
843 jme_restart_rx_engine(struct jme_adapter *jme)
844 {
845         /*
846          * Start RX Engine
847          */
848         jwrite32(jme, JME_RXCS, jme->reg_rxcs |
849                                 RXCS_QUEUESEL_Q0 |
850                                 RXCS_ENABLE |
851                                 RXCS_QST);
852 }
853
854 static inline void
855 jme_disable_rx_engine(struct jme_adapter *jme)
856 {
857         int i;
858         u32 val;
859
860         /*
861          * Disable RX Engine
862          */
863         jwrite32(jme, JME_RXCS, jme->reg_rxcs);
864         wmb();
865
866         val = jread32(jme, JME_RXCS);
867         for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
868                 mdelay(1);
869                 val = jread32(jme, JME_RXCS);
870                 rmb();
871         }
872
873         if (!i)
874                 jeprintk(jme->pdev, "Disable RX engine timeout.\n");
875
876 }
877
878 static int
879 jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
880 {
881         if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
882                 return false;
883
884         if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
885                         == RXWBFLAG_TCPON)) {
886                 if (flags & RXWBFLAG_IPV4)
887                         netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
888                 return false;
889         }
890
891         if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
892                         == RXWBFLAG_UDPON)) {
893                 if (flags & RXWBFLAG_IPV4)
894                         netif_err(jme, rx_err, jme->dev, "UDP Checksum error.\n");
895                 return false;
896         }
897
898         if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
899                         == RXWBFLAG_IPV4)) {
900                 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error.\n");
901                 return false;
902         }
903
904         return true;
905 }
906
907 static void
908 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
909 {
910         struct jme_ring *rxring = &(jme->rxring[0]);
911         struct rxdesc *rxdesc = rxring->desc;
912         struct jme_buffer_info *rxbi = rxring->bufinf;
913         struct sk_buff *skb;
914         int framesize;
915
916         rxdesc += idx;
917         rxbi += idx;
918
919         skb = rxbi->skb;
920         pci_dma_sync_single_for_cpu(jme->pdev,
921                                         rxbi->mapping,
922                                         rxbi->len,
923                                         PCI_DMA_FROMDEVICE);
924
925         if (unlikely(jme_make_new_rx_buf(jme, idx))) {
926                 pci_dma_sync_single_for_device(jme->pdev,
927                                                 rxbi->mapping,
928                                                 rxbi->len,
929                                                 PCI_DMA_FROMDEVICE);
930
931                 ++(NET_STAT(jme).rx_dropped);
932         } else {
933                 framesize = le16_to_cpu(rxdesc->descwb.framesize)
934                                 - RX_PREPAD_SIZE;
935
936                 skb_reserve(skb, RX_PREPAD_SIZE);
937                 skb_put(skb, framesize);
938                 skb->protocol = eth_type_trans(skb, jme->dev);
939
940                 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
941                         skb->ip_summed = CHECKSUM_UNNECESSARY;
942                 else
943                         skb->ip_summed = CHECKSUM_NONE;
944
945                 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
946                         if (jme->vlgrp) {
947                                 jme->jme_vlan_rx(skb, jme->vlgrp,
948                                         le16_to_cpu(rxdesc->descwb.vlan));
949                                 NET_STAT(jme).rx_bytes += 4;
950                         } else {
951                                 dev_kfree_skb(skb);
952                         }
953                 } else {
954                         jme->jme_rx(skb);
955                 }
956
957                 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
958                     cpu_to_le16(RXWBFLAG_DEST_MUL))
959                         ++(NET_STAT(jme).multicast);
960
961                 NET_STAT(jme).rx_bytes += framesize;
962                 ++(NET_STAT(jme).rx_packets);
963         }
964
965         jme_set_clean_rxdesc(jme, idx);
966
967 }
968
969 static int
970 jme_process_receive(struct jme_adapter *jme, int limit)
971 {
972         struct jme_ring *rxring = &(jme->rxring[0]);
973         struct rxdesc *rxdesc = rxring->desc;
974         int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
975
976         if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
977                 goto out_inc;
978
979         if (unlikely(atomic_read(&jme->link_changing) != 1))
980                 goto out_inc;
981
982         if (unlikely(!netif_carrier_ok(jme->dev)))
983                 goto out_inc;
984
985         i = atomic_read(&rxring->next_to_clean);
986         while (limit > 0) {
987                 rxdesc = rxring->desc;
988                 rxdesc += i;
989
990                 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
991                 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
992                         goto out;
993                 --limit;
994
995                 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
996
997                 if (unlikely(desccnt > 1 ||
998                 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
999
1000                         if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1001                                 ++(NET_STAT(jme).rx_crc_errors);
1002                         else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1003                                 ++(NET_STAT(jme).rx_fifo_errors);
1004                         else
1005                                 ++(NET_STAT(jme).rx_errors);
1006
1007                         if (desccnt > 1)
1008                                 limit -= desccnt - 1;
1009
1010                         for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1011                                 jme_set_clean_rxdesc(jme, j);
1012                                 j = (j + 1) & (mask);
1013                         }
1014
1015                 } else {
1016                         jme_alloc_and_feed_skb(jme, i);
1017                 }
1018
1019                 i = (i + desccnt) & (mask);
1020         }
1021
1022 out:
1023         atomic_set(&rxring->next_to_clean, i);
1024
1025 out_inc:
1026         atomic_inc(&jme->rx_cleaning);
1027
1028         return limit > 0 ? limit : 0;
1029
1030 }
1031
1032 static void
1033 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1034 {
1035         if (likely(atmp == dpi->cur)) {
1036                 dpi->cnt = 0;
1037                 return;
1038         }
1039
1040         if (dpi->attempt == atmp) {
1041                 ++(dpi->cnt);
1042         } else {
1043                 dpi->attempt = atmp;
1044                 dpi->cnt = 0;
1045         }
1046
1047 }
1048
1049 static void
1050 jme_dynamic_pcc(struct jme_adapter *jme)
1051 {
1052         register struct dynpcc_info *dpi = &(jme->dpi);
1053
1054         if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1055                 jme_attempt_pcc(dpi, PCC_P3);
1056         else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1057                  dpi->intr_cnt > PCC_INTR_THRESHOLD)
1058                 jme_attempt_pcc(dpi, PCC_P2);
1059         else
1060                 jme_attempt_pcc(dpi, PCC_P1);
1061
1062         if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1063                 if (dpi->attempt < dpi->cur)
1064                         tasklet_schedule(&jme->rxclean_task);
1065                 jme_set_rx_pcc(jme, dpi->attempt);
1066                 dpi->cur = dpi->attempt;
1067                 dpi->cnt = 0;
1068         }
1069 }
1070
1071 static void
1072 jme_start_pcc_timer(struct jme_adapter *jme)
1073 {
1074         struct dynpcc_info *dpi = &(jme->dpi);
1075         dpi->last_bytes         = NET_STAT(jme).rx_bytes;
1076         dpi->last_pkts          = NET_STAT(jme).rx_packets;
1077         dpi->intr_cnt           = 0;
1078         jwrite32(jme, JME_TMCSR,
1079                 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1080 }
1081
1082 static inline void
1083 jme_stop_pcc_timer(struct jme_adapter *jme)
1084 {
1085         jwrite32(jme, JME_TMCSR, 0);
1086 }
1087
1088 static void
1089 jme_shutdown_nic(struct jme_adapter *jme)
1090 {
1091         u32 phylink;
1092
1093         phylink = jme_linkstat_from_phy(jme);
1094
1095         if (!(phylink & PHY_LINK_UP)) {
1096                 /*
1097                  * Disable all interrupt before issue timer
1098                  */
1099                 jme_stop_irq(jme);
1100                 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1101         }
1102 }
1103
1104 static void
1105 jme_pcc_tasklet(unsigned long arg)
1106 {
1107         struct jme_adapter *jme = (struct jme_adapter *)arg;
1108         struct net_device *netdev = jme->dev;
1109
1110         if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1111                 jme_shutdown_nic(jme);
1112                 return;
1113         }
1114
1115         if (unlikely(!netif_carrier_ok(netdev) ||
1116                 (atomic_read(&jme->link_changing) != 1)
1117         )) {
1118                 jme_stop_pcc_timer(jme);
1119                 return;
1120         }
1121
1122         if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1123                 jme_dynamic_pcc(jme);
1124
1125         jme_start_pcc_timer(jme);
1126 }
1127
1128 static inline void
1129 jme_polling_mode(struct jme_adapter *jme)
1130 {
1131         jme_set_rx_pcc(jme, PCC_OFF);
1132 }
1133
1134 static inline void
1135 jme_interrupt_mode(struct jme_adapter *jme)
1136 {
1137         jme_set_rx_pcc(jme, PCC_P1);
1138 }
1139
1140 static inline int
1141 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1142 {
1143         u32 apmc;
1144         apmc = jread32(jme, JME_APMC);
1145         return apmc & JME_APMC_PSEUDO_HP_EN;
1146 }
1147
1148 static void
1149 jme_start_shutdown_timer(struct jme_adapter *jme)
1150 {
1151         u32 apmc;
1152
1153         apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1154         apmc &= ~JME_APMC_EPIEN_CTRL;
1155         if (!no_extplug) {
1156                 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1157                 wmb();
1158         }
1159         jwrite32f(jme, JME_APMC, apmc);
1160
1161         jwrite32f(jme, JME_TIMER2, 0);
1162         set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1163         jwrite32(jme, JME_TMCSR,
1164                 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1165 }
1166
1167 static void
1168 jme_stop_shutdown_timer(struct jme_adapter *jme)
1169 {
1170         u32 apmc;
1171
1172         jwrite32f(jme, JME_TMCSR, 0);
1173         jwrite32f(jme, JME_TIMER2, 0);
1174         clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1175
1176         apmc = jread32(jme, JME_APMC);
1177         apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1178         jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1179         wmb();
1180         jwrite32f(jme, JME_APMC, apmc);
1181 }
1182
1183 static void
1184 jme_link_change_tasklet(unsigned long arg)
1185 {
1186         struct jme_adapter *jme = (struct jme_adapter *)arg;
1187         struct net_device *netdev = jme->dev;
1188         int rc;
1189
1190         while (!atomic_dec_and_test(&jme->link_changing)) {
1191                 atomic_inc(&jme->link_changing);
1192                 netif_info(jme, intr, jme->dev, "Get link change lock failed.\n");
1193                 while (atomic_read(&jme->link_changing) != 1)
1194                         netif_info(jme, intr, jme->dev, "Waiting link change lock.\n");
1195         }
1196
1197         if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1198                 goto out;
1199
1200         jme->old_mtu = netdev->mtu;
1201         netif_stop_queue(netdev);
1202         if (jme_pseudo_hotplug_enabled(jme))
1203                 jme_stop_shutdown_timer(jme);
1204
1205         jme_stop_pcc_timer(jme);
1206         tasklet_disable(&jme->txclean_task);
1207         tasklet_disable(&jme->rxclean_task);
1208         tasklet_disable(&jme->rxempty_task);
1209
1210         if (netif_carrier_ok(netdev)) {
1211                 jme_reset_ghc_speed(jme);
1212                 jme_disable_rx_engine(jme);
1213                 jme_disable_tx_engine(jme);
1214                 jme_reset_mac_processor(jme);
1215                 jme_free_rx_resources(jme);
1216                 jme_free_tx_resources(jme);
1217
1218                 if (test_bit(JME_FLAG_POLL, &jme->flags))
1219                         jme_polling_mode(jme);
1220
1221                 netif_carrier_off(netdev);
1222         }
1223
1224         jme_check_link(netdev, 0);
1225         if (netif_carrier_ok(netdev)) {
1226                 rc = jme_setup_rx_resources(jme);
1227                 if (rc) {
1228                         jeprintk(jme->pdev, "Allocating resources for RX error"
1229                                 ", Device STOPPED!\n");
1230                         goto out_enable_tasklet;
1231                 }
1232
1233                 rc = jme_setup_tx_resources(jme);
1234                 if (rc) {
1235                         jeprintk(jme->pdev, "Allocating resources for TX error"
1236                                 ", Device STOPPED!\n");
1237                         goto err_out_free_rx_resources;
1238                 }
1239
1240                 jme_enable_rx_engine(jme);
1241                 jme_enable_tx_engine(jme);
1242
1243                 netif_start_queue(netdev);
1244
1245                 if (test_bit(JME_FLAG_POLL, &jme->flags))
1246                         jme_interrupt_mode(jme);
1247
1248                 jme_start_pcc_timer(jme);
1249         } else if (jme_pseudo_hotplug_enabled(jme)) {
1250                 jme_start_shutdown_timer(jme);
1251         }
1252
1253         goto out_enable_tasklet;
1254
1255 err_out_free_rx_resources:
1256         jme_free_rx_resources(jme);
1257 out_enable_tasklet:
1258         tasklet_enable(&jme->txclean_task);
1259         tasklet_hi_enable(&jme->rxclean_task);
1260         tasklet_hi_enable(&jme->rxempty_task);
1261 out:
1262         atomic_inc(&jme->link_changing);
1263 }
1264
1265 static void
1266 jme_rx_clean_tasklet(unsigned long arg)
1267 {
1268         struct jme_adapter *jme = (struct jme_adapter *)arg;
1269         struct dynpcc_info *dpi = &(jme->dpi);
1270
1271         jme_process_receive(jme, jme->rx_ring_size);
1272         ++(dpi->intr_cnt);
1273
1274 }
1275
1276 static int
1277 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1278 {
1279         struct jme_adapter *jme = jme_napi_priv(holder);
1280         int rest;
1281
1282         rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1283
1284         while (atomic_read(&jme->rx_empty) > 0) {
1285                 atomic_dec(&jme->rx_empty);
1286                 ++(NET_STAT(jme).rx_dropped);
1287                 jme_restart_rx_engine(jme);
1288         }
1289         atomic_inc(&jme->rx_empty);
1290
1291         if (rest) {
1292                 JME_RX_COMPLETE(netdev, holder);
1293                 jme_interrupt_mode(jme);
1294         }
1295
1296         JME_NAPI_WEIGHT_SET(budget, rest);
1297         return JME_NAPI_WEIGHT_VAL(budget) - rest;
1298 }
1299
1300 static void
1301 jme_rx_empty_tasklet(unsigned long arg)
1302 {
1303         struct jme_adapter *jme = (struct jme_adapter *)arg;
1304
1305         if (unlikely(atomic_read(&jme->link_changing) != 1))
1306                 return;
1307
1308         if (unlikely(!netif_carrier_ok(jme->dev)))
1309                 return;
1310
1311         netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1312
1313         jme_rx_clean_tasklet(arg);
1314
1315         while (atomic_read(&jme->rx_empty) > 0) {
1316                 atomic_dec(&jme->rx_empty);
1317                 ++(NET_STAT(jme).rx_dropped);
1318                 jme_restart_rx_engine(jme);
1319         }
1320         atomic_inc(&jme->rx_empty);
1321 }
1322
1323 static void
1324 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1325 {
1326         struct jme_ring *txring = &(jme->txring[0]);
1327
1328         smp_wmb();
1329         if (unlikely(netif_queue_stopped(jme->dev) &&
1330         atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1331                 netif_info(jme, tx_done, jme->dev, "TX Queue Waked.\n");
1332                 netif_wake_queue(jme->dev);
1333         }
1334
1335 }
1336
1337 static void
1338 jme_tx_clean_tasklet(unsigned long arg)
1339 {
1340         struct jme_adapter *jme = (struct jme_adapter *)arg;
1341         struct jme_ring *txring = &(jme->txring[0]);
1342         struct txdesc *txdesc = txring->desc;
1343         struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1344         int i, j, cnt = 0, max, err, mask;
1345
1346         tx_dbg(jme, "Into txclean.\n");
1347
1348         if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1349                 goto out;
1350
1351         if (unlikely(atomic_read(&jme->link_changing) != 1))
1352                 goto out;
1353
1354         if (unlikely(!netif_carrier_ok(jme->dev)))
1355                 goto out;
1356
1357         max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1358         mask = jme->tx_ring_mask;
1359
1360         for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1361
1362                 ctxbi = txbi + i;
1363
1364                 if (likely(ctxbi->skb &&
1365                 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1366
1367                         tx_dbg(jme, "txclean: %d+%d@%lu\n",
1368                                         i, ctxbi->nr_desc, jiffies);
1369
1370                         err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1371
1372                         for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1373                                 ttxbi = txbi + ((i + j) & (mask));
1374                                 txdesc[(i + j) & (mask)].dw[0] = 0;
1375
1376                                 pci_unmap_page(jme->pdev,
1377                                                  ttxbi->mapping,
1378                                                  ttxbi->len,
1379                                                  PCI_DMA_TODEVICE);
1380
1381                                 ttxbi->mapping = 0;
1382                                 ttxbi->len = 0;
1383                         }
1384
1385                         dev_kfree_skb(ctxbi->skb);
1386
1387                         cnt += ctxbi->nr_desc;
1388
1389                         if (unlikely(err)) {
1390                                 ++(NET_STAT(jme).tx_carrier_errors);
1391                         } else {
1392                                 ++(NET_STAT(jme).tx_packets);
1393                                 NET_STAT(jme).tx_bytes += ctxbi->len;
1394                         }
1395
1396                         ctxbi->skb = NULL;
1397                         ctxbi->len = 0;
1398                         ctxbi->start_xmit = 0;
1399
1400                 } else {
1401                         break;
1402                 }
1403
1404                 i = (i + ctxbi->nr_desc) & mask;
1405
1406                 ctxbi->nr_desc = 0;
1407         }
1408
1409         tx_dbg(jme, "txclean: done %d@%lu.\n", i, jiffies);
1410         atomic_set(&txring->next_to_clean, i);
1411         atomic_add(cnt, &txring->nr_free);
1412
1413         jme_wake_queue_if_stopped(jme);
1414
1415 out:
1416         atomic_inc(&jme->tx_cleaning);
1417 }
1418
1419 static void
1420 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1421 {
1422         /*
1423          * Disable interrupt
1424          */
1425         jwrite32f(jme, JME_IENC, INTR_ENABLE);
1426
1427         if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1428                 /*
1429                  * Link change event is critical
1430                  * all other events are ignored
1431                  */
1432                 jwrite32(jme, JME_IEVE, intrstat);
1433                 tasklet_schedule(&jme->linkch_task);
1434                 goto out_reenable;
1435         }
1436
1437         if (intrstat & INTR_TMINTR) {
1438                 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1439                 tasklet_schedule(&jme->pcc_task);
1440         }
1441
1442         if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1443                 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1444                 tasklet_schedule(&jme->txclean_task);
1445         }
1446
1447         if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1448                 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1449                                                      INTR_PCCRX0 |
1450                                                      INTR_RX0EMP)) |
1451                                         INTR_RX0);
1452         }
1453
1454         if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1455                 if (intrstat & INTR_RX0EMP)
1456                         atomic_inc(&jme->rx_empty);
1457
1458                 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1459                         if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1460                                 jme_polling_mode(jme);
1461                                 JME_RX_SCHEDULE(jme);
1462                         }
1463                 }
1464         } else {
1465                 if (intrstat & INTR_RX0EMP) {
1466                         atomic_inc(&jme->rx_empty);
1467                         tasklet_hi_schedule(&jme->rxempty_task);
1468                 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1469                         tasklet_hi_schedule(&jme->rxclean_task);
1470                 }
1471         }
1472
1473 out_reenable:
1474         /*
1475          * Re-enable interrupt
1476          */
1477         jwrite32f(jme, JME_IENS, INTR_ENABLE);
1478 }
1479
1480 static irqreturn_t
1481 jme_intr(int irq, void *dev_id)
1482 {
1483         struct net_device *netdev = dev_id;
1484         struct jme_adapter *jme = netdev_priv(netdev);
1485         u32 intrstat;
1486
1487         intrstat = jread32(jme, JME_IEVE);
1488
1489         /*
1490          * Check if it's really an interrupt for us
1491          */
1492         if (unlikely((intrstat & INTR_ENABLE) == 0))
1493                 return IRQ_NONE;
1494
1495         /*
1496          * Check if the device still exist
1497          */
1498         if (unlikely(intrstat == ~((typeof(intrstat))0)))
1499                 return IRQ_NONE;
1500
1501         jme_intr_msi(jme, intrstat);
1502
1503         return IRQ_HANDLED;
1504 }
1505
1506 static irqreturn_t
1507 jme_msi(int irq, void *dev_id)
1508 {
1509         struct net_device *netdev = dev_id;
1510         struct jme_adapter *jme = netdev_priv(netdev);
1511         u32 intrstat;
1512
1513         intrstat = jread32(jme, JME_IEVE);
1514
1515         jme_intr_msi(jme, intrstat);
1516
1517         return IRQ_HANDLED;
1518 }
1519
1520 static void
1521 jme_reset_link(struct jme_adapter *jme)
1522 {
1523         jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1524 }
1525
1526 static void
1527 jme_restart_an(struct jme_adapter *jme)
1528 {
1529         u32 bmcr;
1530
1531         spin_lock_bh(&jme->phy_lock);
1532         bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1533         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1534         jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1535         spin_unlock_bh(&jme->phy_lock);
1536 }
1537
1538 static int
1539 jme_request_irq(struct jme_adapter *jme)
1540 {
1541         int rc;
1542         struct net_device *netdev = jme->dev;
1543         irq_handler_t handler = jme_intr;
1544         int irq_flags = IRQF_SHARED;
1545
1546         if (!pci_enable_msi(jme->pdev)) {
1547                 set_bit(JME_FLAG_MSI, &jme->flags);
1548                 handler = jme_msi;
1549                 irq_flags = 0;
1550         }
1551
1552         rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1553                           netdev);
1554         if (rc) {
1555                 jeprintk(jme->pdev,
1556                         "Unable to request %s interrupt (return: %d)\n",
1557                         test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1558                         rc);
1559
1560                 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1561                         pci_disable_msi(jme->pdev);
1562                         clear_bit(JME_FLAG_MSI, &jme->flags);
1563                 }
1564         } else {
1565                 netdev->irq = jme->pdev->irq;
1566         }
1567
1568         return rc;
1569 }
1570
1571 static void
1572 jme_free_irq(struct jme_adapter *jme)
1573 {
1574         free_irq(jme->pdev->irq, jme->dev);
1575         if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1576                 pci_disable_msi(jme->pdev);
1577                 clear_bit(JME_FLAG_MSI, &jme->flags);
1578                 jme->dev->irq = jme->pdev->irq;
1579         }
1580 }
1581
1582 static int
1583 jme_open(struct net_device *netdev)
1584 {
1585         struct jme_adapter *jme = netdev_priv(netdev);
1586         int rc;
1587
1588         jme_clear_pm(jme);
1589         JME_NAPI_ENABLE(jme);
1590
1591         tasklet_enable(&jme->linkch_task);
1592         tasklet_enable(&jme->txclean_task);
1593         tasklet_hi_enable(&jme->rxclean_task);
1594         tasklet_hi_enable(&jme->rxempty_task);
1595
1596         rc = jme_request_irq(jme);
1597         if (rc)
1598                 goto err_out;
1599
1600         jme_start_irq(jme);
1601
1602         if (test_bit(JME_FLAG_SSET, &jme->flags))
1603                 jme_set_settings(netdev, &jme->old_ecmd);
1604         else
1605                 jme_reset_phy_processor(jme);
1606
1607         jme_reset_link(jme);
1608
1609         return 0;
1610
1611 err_out:
1612         netif_stop_queue(netdev);
1613         netif_carrier_off(netdev);
1614         return rc;
1615 }
1616
1617 #ifdef CONFIG_PM
1618 static void
1619 jme_set_100m_half(struct jme_adapter *jme)
1620 {
1621         u32 bmcr, tmp;
1622
1623         bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1624         tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1625                        BMCR_SPEED1000 | BMCR_FULLDPLX);
1626         tmp |= BMCR_SPEED100;
1627
1628         if (bmcr != tmp)
1629                 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1630
1631         if (jme->fpgaver)
1632                 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1633         else
1634                 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1635 }
1636
1637 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1638 static void
1639 jme_wait_link(struct jme_adapter *jme)
1640 {
1641         u32 phylink, to = JME_WAIT_LINK_TIME;
1642
1643         mdelay(1000);
1644         phylink = jme_linkstat_from_phy(jme);
1645         while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1646                 mdelay(10);
1647                 phylink = jme_linkstat_from_phy(jme);
1648         }
1649 }
1650 #endif
1651
1652 static inline void
1653 jme_phy_off(struct jme_adapter *jme)
1654 {
1655         jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1656 }
1657
1658 static int
1659 jme_close(struct net_device *netdev)
1660 {
1661         struct jme_adapter *jme = netdev_priv(netdev);
1662
1663         netif_stop_queue(netdev);
1664         netif_carrier_off(netdev);
1665
1666         jme_stop_irq(jme);
1667         jme_free_irq(jme);
1668
1669         JME_NAPI_DISABLE(jme);
1670
1671         tasklet_disable(&jme->linkch_task);
1672         tasklet_disable(&jme->txclean_task);
1673         tasklet_disable(&jme->rxclean_task);
1674         tasklet_disable(&jme->rxempty_task);
1675
1676         jme_reset_ghc_speed(jme);
1677         jme_disable_rx_engine(jme);
1678         jme_disable_tx_engine(jme);
1679         jme_reset_mac_processor(jme);
1680         jme_free_rx_resources(jme);
1681         jme_free_tx_resources(jme);
1682         jme->phylink = 0;
1683         jme_phy_off(jme);
1684
1685         return 0;
1686 }
1687
1688 static int
1689 jme_alloc_txdesc(struct jme_adapter *jme,
1690                         struct sk_buff *skb)
1691 {
1692         struct jme_ring *txring = &(jme->txring[0]);
1693         int idx, nr_alloc, mask = jme->tx_ring_mask;
1694
1695         idx = txring->next_to_use;
1696         nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1697
1698         if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1699                 return -1;
1700
1701         atomic_sub(nr_alloc, &txring->nr_free);
1702
1703         txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1704
1705         return idx;
1706 }
1707
1708 static void
1709 jme_fill_tx_map(struct pci_dev *pdev,
1710                 struct txdesc *txdesc,
1711                 struct jme_buffer_info *txbi,
1712                 struct page *page,
1713                 u32 page_offset,
1714                 u32 len,
1715                 u8 hidma)
1716 {
1717         dma_addr_t dmaaddr;
1718
1719         dmaaddr = pci_map_page(pdev,
1720                                 page,
1721                                 page_offset,
1722                                 len,
1723                                 PCI_DMA_TODEVICE);
1724
1725         pci_dma_sync_single_for_device(pdev,
1726                                        dmaaddr,
1727                                        len,
1728                                        PCI_DMA_TODEVICE);
1729
1730         txdesc->dw[0] = 0;
1731         txdesc->dw[1] = 0;
1732         txdesc->desc2.flags     = TXFLAG_OWN;
1733         txdesc->desc2.flags     |= (hidma) ? TXFLAG_64BIT : 0;
1734         txdesc->desc2.datalen   = cpu_to_le16(len);
1735         txdesc->desc2.bufaddrh  = cpu_to_le32((__u64)dmaaddr >> 32);
1736         txdesc->desc2.bufaddrl  = cpu_to_le32(
1737                                         (__u64)dmaaddr & 0xFFFFFFFFUL);
1738
1739         txbi->mapping = dmaaddr;
1740         txbi->len = len;
1741 }
1742
1743 static void
1744 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1745 {
1746         struct jme_ring *txring = &(jme->txring[0]);
1747         struct txdesc *txdesc = txring->desc, *ctxdesc;
1748         struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1749         u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1750         int i, nr_frags = skb_shinfo(skb)->nr_frags;
1751         int mask = jme->tx_ring_mask;
1752         struct skb_frag_struct *frag;
1753         u32 len;
1754
1755         for (i = 0 ; i < nr_frags ; ++i) {
1756                 frag = &skb_shinfo(skb)->frags[i];
1757                 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1758                 ctxbi = txbi + ((idx + i + 2) & (mask));
1759
1760                 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1761                                  frag->page_offset, frag->size, hidma);
1762         }
1763
1764         len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1765         ctxdesc = txdesc + ((idx + 1) & (mask));
1766         ctxbi = txbi + ((idx + 1) & (mask));
1767         jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1768                         offset_in_page(skb->data), len, hidma);
1769
1770 }
1771
1772 static int
1773 jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1774 {
1775         if (unlikely(skb_shinfo(skb)->gso_size &&
1776                         skb_header_cloned(skb) &&
1777                         pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1778                 dev_kfree_skb(skb);
1779                 return -1;
1780         }
1781
1782         return 0;
1783 }
1784
1785 static int
1786 jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
1787 {
1788         *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
1789         if (*mss) {
1790                 *flags |= TXFLAG_LSEN;
1791
1792                 if (skb->protocol == htons(ETH_P_IP)) {
1793                         struct iphdr *iph = ip_hdr(skb);
1794
1795                         iph->check = 0;
1796                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1797                                                                 iph->daddr, 0,
1798                                                                 IPPROTO_TCP,
1799                                                                 0);
1800                 } else {
1801                         struct ipv6hdr *ip6h = ipv6_hdr(skb);
1802
1803                         tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1804                                                                 &ip6h->daddr, 0,
1805                                                                 IPPROTO_TCP,
1806                                                                 0);
1807                 }
1808
1809                 return 0;
1810         }
1811
1812         return 1;
1813 }
1814
1815 static void
1816 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1817 {
1818         if (skb->ip_summed == CHECKSUM_PARTIAL) {
1819                 u8 ip_proto;
1820
1821                 switch (skb->protocol) {
1822                 case htons(ETH_P_IP):
1823                         ip_proto = ip_hdr(skb)->protocol;
1824                         break;
1825                 case htons(ETH_P_IPV6):
1826                         ip_proto = ipv6_hdr(skb)->nexthdr;
1827                         break;
1828                 default:
1829                         ip_proto = 0;
1830                         break;
1831                 }
1832
1833                 switch (ip_proto) {
1834                 case IPPROTO_TCP:
1835                         *flags |= TXFLAG_TCPCS;
1836                         break;
1837                 case IPPROTO_UDP:
1838                         *flags |= TXFLAG_UDPCS;
1839                         break;
1840                 default:
1841                         netif_err(jme, tx_err, jme->dev, "Error upper layer protocol.\n");
1842                         break;
1843                 }
1844         }
1845 }
1846
1847 static inline void
1848 jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
1849 {
1850         if (vlan_tx_tag_present(skb)) {
1851                 *flags |= TXFLAG_TAGON;
1852                 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
1853         }
1854 }
1855
1856 static int
1857 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1858 {
1859         struct jme_ring *txring = &(jme->txring[0]);
1860         struct txdesc *txdesc;
1861         struct jme_buffer_info *txbi;
1862         u8 flags;
1863
1864         txdesc = (struct txdesc *)txring->desc + idx;
1865         txbi = txring->bufinf + idx;
1866
1867         txdesc->dw[0] = 0;
1868         txdesc->dw[1] = 0;
1869         txdesc->dw[2] = 0;
1870         txdesc->dw[3] = 0;
1871         txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1872         /*
1873          * Set OWN bit at final.
1874          * When kernel transmit faster than NIC.
1875          * And NIC trying to send this descriptor before we tell
1876          * it to start sending this TX queue.
1877          * Other fields are already filled correctly.
1878          */
1879         wmb();
1880         flags = TXFLAG_OWN | TXFLAG_INT;
1881         /*
1882          * Set checksum flags while not tso
1883          */
1884         if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1885                 jme_tx_csum(jme, skb, &flags);
1886         jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
1887         jme_map_tx_skb(jme, skb, idx);
1888         txdesc->desc1.flags = flags;
1889         /*
1890          * Set tx buffer info after telling NIC to send
1891          * For better tx_clean timing
1892          */
1893         wmb();
1894         txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1895         txbi->skb = skb;
1896         txbi->len = skb->len;
1897         txbi->start_xmit = jiffies;
1898         if (!txbi->start_xmit)
1899                 txbi->start_xmit = (0UL-1);
1900
1901         return 0;
1902 }
1903
1904 static void
1905 jme_stop_queue_if_full(struct jme_adapter *jme)
1906 {
1907         struct jme_ring *txring = &(jme->txring[0]);
1908         struct jme_buffer_info *txbi = txring->bufinf;
1909         int idx = atomic_read(&txring->next_to_clean);
1910
1911         txbi += idx;
1912
1913         smp_wmb();
1914         if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
1915                 netif_stop_queue(jme->dev);
1916                 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused.\n");
1917                 smp_wmb();
1918                 if (atomic_read(&txring->nr_free)
1919                         >= (jme->tx_wake_threshold)) {
1920                         netif_wake_queue(jme->dev);
1921                         netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked.\n");
1922                 }
1923         }
1924
1925         if (unlikely(txbi->start_xmit &&
1926                         (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
1927                         txbi->skb)) {
1928                 netif_stop_queue(jme->dev);
1929                 netif_info(jme, tx_queued, jme->dev, "TX Queue Stopped %d@%lu.\n", idx, jiffies);
1930         }
1931 }
1932
1933 /*
1934  * This function is already protected by netif_tx_lock()
1935  */
1936
1937 static netdev_tx_t
1938 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1939 {
1940         struct jme_adapter *jme = netdev_priv(netdev);
1941         int idx;
1942
1943         if (unlikely(jme_expand_header(jme, skb))) {
1944                 ++(NET_STAT(jme).tx_dropped);
1945                 return NETDEV_TX_OK;
1946         }
1947
1948         idx = jme_alloc_txdesc(jme, skb);
1949
1950         if (unlikely(idx < 0)) {
1951                 netif_stop_queue(netdev);
1952                 netif_err(jme, tx_err, jme->dev, "BUG! Tx ring full when queue awake!\n");
1953
1954                 return NETDEV_TX_BUSY;
1955         }
1956
1957         jme_fill_tx_desc(jme, skb, idx);
1958
1959         jwrite32(jme, JME_TXCS, jme->reg_txcs |
1960                                 TXCS_SELECT_QUEUE0 |
1961                                 TXCS_QUEUE0S |
1962                                 TXCS_ENABLE);
1963
1964         tx_dbg(jme, "xmit: %d+%d@%lu\n", idx,
1965                         skb_shinfo(skb)->nr_frags + 2,
1966                         jiffies);
1967         jme_stop_queue_if_full(jme);
1968
1969         return NETDEV_TX_OK;
1970 }
1971
1972 static int
1973 jme_set_macaddr(struct net_device *netdev, void *p)
1974 {
1975         struct jme_adapter *jme = netdev_priv(netdev);
1976         struct sockaddr *addr = p;
1977         u32 val;
1978
1979         if (netif_running(netdev))
1980                 return -EBUSY;
1981
1982         spin_lock_bh(&jme->macaddr_lock);
1983         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1984
1985         val = (addr->sa_data[3] & 0xff) << 24 |
1986               (addr->sa_data[2] & 0xff) << 16 |
1987               (addr->sa_data[1] & 0xff) <<  8 |
1988               (addr->sa_data[0] & 0xff);
1989         jwrite32(jme, JME_RXUMA_LO, val);
1990         val = (addr->sa_data[5] & 0xff) << 8 |
1991               (addr->sa_data[4] & 0xff);
1992         jwrite32(jme, JME_RXUMA_HI, val);
1993         spin_unlock_bh(&jme->macaddr_lock);
1994
1995         return 0;
1996 }
1997
1998 static void
1999 jme_set_multi(struct net_device *netdev)
2000 {
2001         struct jme_adapter *jme = netdev_priv(netdev);
2002         u32 mc_hash[2] = {};
2003
2004         spin_lock_bh(&jme->rxmcs_lock);
2005
2006         jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2007
2008         if (netdev->flags & IFF_PROMISC) {
2009                 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2010         } else if (netdev->flags & IFF_ALLMULTI) {
2011                 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2012         } else if (netdev->flags & IFF_MULTICAST) {
2013                 struct dev_mc_list *mclist;
2014                 int bit_nr;
2015
2016                 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2017                 netdev_for_each_mc_addr(mclist, netdev) {
2018                         bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
2019                         mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2020                 }
2021
2022                 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2023                 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2024         }
2025
2026         wmb();
2027         jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2028
2029         spin_unlock_bh(&jme->rxmcs_lock);
2030 }
2031
2032 static int
2033 jme_change_mtu(struct net_device *netdev, int new_mtu)
2034 {
2035         struct jme_adapter *jme = netdev_priv(netdev);
2036
2037         if (new_mtu == jme->old_mtu)
2038                 return 0;
2039
2040         if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2041                 ((new_mtu) < IPV6_MIN_MTU))
2042                 return -EINVAL;
2043
2044         if (new_mtu > 4000) {
2045                 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2046                 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2047                 jme_restart_rx_engine(jme);
2048         } else {
2049                 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2050                 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2051                 jme_restart_rx_engine(jme);
2052         }
2053
2054         if (new_mtu > 1900) {
2055                 netdev->features &= ~(NETIF_F_HW_CSUM |
2056                                 NETIF_F_TSO |
2057                                 NETIF_F_TSO6);
2058         } else {
2059                 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2060                         netdev->features |= NETIF_F_HW_CSUM;
2061                 if (test_bit(JME_FLAG_TSO, &jme->flags))
2062                         netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2063         }
2064
2065         netdev->mtu = new_mtu;
2066         jme_reset_link(jme);
2067
2068         return 0;
2069 }
2070
2071 static void
2072 jme_tx_timeout(struct net_device *netdev)
2073 {
2074         struct jme_adapter *jme = netdev_priv(netdev);
2075
2076         jme->phylink = 0;
2077         jme_reset_phy_processor(jme);
2078         if (test_bit(JME_FLAG_SSET, &jme->flags))
2079                 jme_set_settings(netdev, &jme->old_ecmd);
2080
2081         /*
2082          * Force to Reset the link again
2083          */
2084         jme_reset_link(jme);
2085 }
2086
2087 static inline void jme_pause_rx(struct jme_adapter *jme)
2088 {
2089         atomic_dec(&jme->link_changing);
2090
2091         jme_set_rx_pcc(jme, PCC_OFF);
2092         if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2093                 JME_NAPI_DISABLE(jme);
2094         } else {
2095                 tasklet_disable(&jme->rxclean_task);
2096                 tasklet_disable(&jme->rxempty_task);
2097         }
2098 }
2099
2100 static inline void jme_resume_rx(struct jme_adapter *jme)
2101 {
2102         struct dynpcc_info *dpi = &(jme->dpi);
2103
2104         if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2105                 JME_NAPI_ENABLE(jme);
2106         } else {
2107                 tasklet_hi_enable(&jme->rxclean_task);
2108                 tasklet_hi_enable(&jme->rxempty_task);
2109         }
2110         dpi->cur                = PCC_P1;
2111         dpi->attempt            = PCC_P1;
2112         dpi->cnt                = 0;
2113         jme_set_rx_pcc(jme, PCC_P1);
2114
2115         atomic_inc(&jme->link_changing);
2116 }
2117
2118 static void
2119 jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2120 {
2121         struct jme_adapter *jme = netdev_priv(netdev);
2122
2123         jme_pause_rx(jme);
2124         jme->vlgrp = grp;
2125         jme_resume_rx(jme);
2126 }
2127
2128 static void
2129 jme_get_drvinfo(struct net_device *netdev,
2130                      struct ethtool_drvinfo *info)
2131 {
2132         struct jme_adapter *jme = netdev_priv(netdev);
2133
2134         strcpy(info->driver, DRV_NAME);
2135         strcpy(info->version, DRV_VERSION);
2136         strcpy(info->bus_info, pci_name(jme->pdev));
2137 }
2138
2139 static int
2140 jme_get_regs_len(struct net_device *netdev)
2141 {
2142         return JME_REG_LEN;
2143 }
2144
2145 static void
2146 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2147 {
2148         int i;
2149
2150         for (i = 0 ; i < len ; i += 4)
2151                 p[i >> 2] = jread32(jme, reg + i);
2152 }
2153
2154 static void
2155 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2156 {
2157         int i;
2158         u16 *p16 = (u16 *)p;
2159
2160         for (i = 0 ; i < reg_nr ; ++i)
2161                 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2162 }
2163
2164 static void
2165 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2166 {
2167         struct jme_adapter *jme = netdev_priv(netdev);
2168         u32 *p32 = (u32 *)p;
2169
2170         memset(p, 0xFF, JME_REG_LEN);
2171
2172         regs->version = 1;
2173         mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2174
2175         p32 += 0x100 >> 2;
2176         mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2177
2178         p32 += 0x100 >> 2;
2179         mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2180
2181         p32 += 0x100 >> 2;
2182         mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2183
2184         p32 += 0x100 >> 2;
2185         mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2186 }
2187
2188 static int
2189 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2190 {
2191         struct jme_adapter *jme = netdev_priv(netdev);
2192
2193         ecmd->tx_coalesce_usecs = PCC_TX_TO;
2194         ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2195
2196         if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2197                 ecmd->use_adaptive_rx_coalesce = false;
2198                 ecmd->rx_coalesce_usecs = 0;
2199                 ecmd->rx_max_coalesced_frames = 0;
2200                 return 0;
2201         }
2202
2203         ecmd->use_adaptive_rx_coalesce = true;
2204
2205         switch (jme->dpi.cur) {
2206         case PCC_P1:
2207                 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2208                 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2209                 break;
2210         case PCC_P2:
2211                 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2212                 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2213                 break;
2214         case PCC_P3:
2215                 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2216                 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2217                 break;
2218         default:
2219                 break;
2220         }
2221
2222         return 0;
2223 }
2224
2225 static int
2226 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2227 {
2228         struct jme_adapter *jme = netdev_priv(netdev);
2229         struct dynpcc_info *dpi = &(jme->dpi);
2230
2231         if (netif_running(netdev))
2232                 return -EBUSY;
2233
2234         if (ecmd->use_adaptive_rx_coalesce &&
2235             test_bit(JME_FLAG_POLL, &jme->flags)) {
2236                 clear_bit(JME_FLAG_POLL, &jme->flags);
2237                 jme->jme_rx = netif_rx;
2238                 jme->jme_vlan_rx = vlan_hwaccel_rx;
2239                 dpi->cur                = PCC_P1;
2240                 dpi->attempt            = PCC_P1;
2241                 dpi->cnt                = 0;
2242                 jme_set_rx_pcc(jme, PCC_P1);
2243                 jme_interrupt_mode(jme);
2244         } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2245                    !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2246                 set_bit(JME_FLAG_POLL, &jme->flags);
2247                 jme->jme_rx = netif_receive_skb;
2248                 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2249                 jme_interrupt_mode(jme);
2250         }
2251
2252         return 0;
2253 }
2254
2255 static void
2256 jme_get_pauseparam(struct net_device *netdev,
2257                         struct ethtool_pauseparam *ecmd)
2258 {
2259         struct jme_adapter *jme = netdev_priv(netdev);
2260         u32 val;
2261
2262         ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2263         ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2264
2265         spin_lock_bh(&jme->phy_lock);
2266         val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2267         spin_unlock_bh(&jme->phy_lock);
2268
2269         ecmd->autoneg =
2270                 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2271 }
2272
2273 static int
2274 jme_set_pauseparam(struct net_device *netdev,
2275                         struct ethtool_pauseparam *ecmd)
2276 {
2277         struct jme_adapter *jme = netdev_priv(netdev);
2278         u32 val;
2279
2280         if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2281                 (ecmd->tx_pause != 0)) {
2282
2283                 if (ecmd->tx_pause)
2284                         jme->reg_txpfc |= TXPFC_PF_EN;
2285                 else
2286                         jme->reg_txpfc &= ~TXPFC_PF_EN;
2287
2288                 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2289         }
2290
2291         spin_lock_bh(&jme->rxmcs_lock);
2292         if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2293                 (ecmd->rx_pause != 0)) {
2294
2295                 if (ecmd->rx_pause)
2296                         jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2297                 else
2298                         jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2299
2300                 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2301         }
2302         spin_unlock_bh(&jme->rxmcs_lock);
2303
2304         spin_lock_bh(&jme->phy_lock);
2305         val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2306         if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2307                 (ecmd->autoneg != 0)) {
2308
2309                 if (ecmd->autoneg)
2310                         val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2311                 else
2312                         val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2313
2314                 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2315                                 MII_ADVERTISE, val);
2316         }
2317         spin_unlock_bh(&jme->phy_lock);
2318
2319         return 0;
2320 }
2321
2322 static void
2323 jme_get_wol(struct net_device *netdev,
2324                 struct ethtool_wolinfo *wol)
2325 {
2326         struct jme_adapter *jme = netdev_priv(netdev);
2327
2328         wol->supported = WAKE_MAGIC | WAKE_PHY;
2329
2330         wol->wolopts = 0;
2331
2332         if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2333                 wol->wolopts |= WAKE_PHY;
2334
2335         if (jme->reg_pmcs & PMCS_MFEN)
2336                 wol->wolopts |= WAKE_MAGIC;
2337
2338 }
2339
2340 static int
2341 jme_set_wol(struct net_device *netdev,
2342                 struct ethtool_wolinfo *wol)
2343 {
2344         struct jme_adapter *jme = netdev_priv(netdev);
2345
2346         if (wol->wolopts & (WAKE_MAGICSECURE |
2347                                 WAKE_UCAST |
2348                                 WAKE_MCAST |
2349                                 WAKE_BCAST |
2350                                 WAKE_ARP))
2351                 return -EOPNOTSUPP;
2352
2353         jme->reg_pmcs = 0;
2354
2355         if (wol->wolopts & WAKE_PHY)
2356                 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2357
2358         if (wol->wolopts & WAKE_MAGIC)
2359                 jme->reg_pmcs |= PMCS_MFEN;
2360
2361         jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2362
2363         return 0;
2364 }
2365
2366 static int
2367 jme_get_settings(struct net_device *netdev,
2368                      struct ethtool_cmd *ecmd)
2369 {
2370         struct jme_adapter *jme = netdev_priv(netdev);
2371         int rc;
2372
2373         spin_lock_bh(&jme->phy_lock);
2374         rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2375         spin_unlock_bh(&jme->phy_lock);
2376         return rc;
2377 }
2378
2379 static int
2380 jme_set_settings(struct net_device *netdev,
2381                      struct ethtool_cmd *ecmd)
2382 {
2383         struct jme_adapter *jme = netdev_priv(netdev);
2384         int rc, fdc = 0;
2385
2386         if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2387                 return -EINVAL;
2388
2389         if (jme->mii_if.force_media &&
2390         ecmd->autoneg != AUTONEG_ENABLE &&
2391         (jme->mii_if.full_duplex != ecmd->duplex))
2392                 fdc = 1;
2393
2394         spin_lock_bh(&jme->phy_lock);
2395         rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2396         spin_unlock_bh(&jme->phy_lock);
2397
2398         if (!rc && fdc)
2399                 jme_reset_link(jme);
2400
2401         if (!rc) {
2402                 set_bit(JME_FLAG_SSET, &jme->flags);
2403                 jme->old_ecmd = *ecmd;
2404         }
2405
2406         return rc;
2407 }
2408
2409 static u32
2410 jme_get_link(struct net_device *netdev)
2411 {
2412         struct jme_adapter *jme = netdev_priv(netdev);
2413         return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2414 }
2415
2416 static u32
2417 jme_get_msglevel(struct net_device *netdev)
2418 {
2419         struct jme_adapter *jme = netdev_priv(netdev);
2420         return jme->msg_enable;
2421 }
2422
2423 static void
2424 jme_set_msglevel(struct net_device *netdev, u32 value)
2425 {
2426         struct jme_adapter *jme = netdev_priv(netdev);
2427         jme->msg_enable = value;
2428 }
2429
2430 static u32
2431 jme_get_rx_csum(struct net_device *netdev)
2432 {
2433         struct jme_adapter *jme = netdev_priv(netdev);
2434         return jme->reg_rxmcs & RXMCS_CHECKSUM;
2435 }
2436
2437 static int
2438 jme_set_rx_csum(struct net_device *netdev, u32 on)
2439 {
2440         struct jme_adapter *jme = netdev_priv(netdev);
2441
2442         spin_lock_bh(&jme->rxmcs_lock);
2443         if (on)
2444                 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2445         else
2446                 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2447         jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2448         spin_unlock_bh(&jme->rxmcs_lock);
2449
2450         return 0;
2451 }
2452
2453 static int
2454 jme_set_tx_csum(struct net_device *netdev, u32 on)
2455 {
2456         struct jme_adapter *jme = netdev_priv(netdev);
2457
2458         if (on) {
2459                 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2460                 if (netdev->mtu <= 1900)
2461                         netdev->features |= NETIF_F_HW_CSUM;
2462         } else {
2463                 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2464                 netdev->features &= ~NETIF_F_HW_CSUM;
2465         }
2466
2467         return 0;
2468 }
2469
2470 static int
2471 jme_set_tso(struct net_device *netdev, u32 on)
2472 {
2473         struct jme_adapter *jme = netdev_priv(netdev);
2474
2475         if (on) {
2476                 set_bit(JME_FLAG_TSO, &jme->flags);
2477                 if (netdev->mtu <= 1900)
2478                         netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2479         } else {
2480                 clear_bit(JME_FLAG_TSO, &jme->flags);
2481                 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2482         }
2483
2484         return 0;
2485 }
2486
2487 static int
2488 jme_nway_reset(struct net_device *netdev)
2489 {
2490         struct jme_adapter *jme = netdev_priv(netdev);
2491         jme_restart_an(jme);
2492         return 0;
2493 }
2494
2495 static u8
2496 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2497 {
2498         u32 val;
2499         int to;
2500
2501         val = jread32(jme, JME_SMBCSR);
2502         to = JME_SMB_BUSY_TIMEOUT;
2503         while ((val & SMBCSR_BUSY) && --to) {
2504                 msleep(1);
2505                 val = jread32(jme, JME_SMBCSR);
2506         }
2507         if (!to) {
2508                 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n");
2509                 return 0xFF;
2510         }
2511
2512         jwrite32(jme, JME_SMBINTF,
2513                 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2514                 SMBINTF_HWRWN_READ |
2515                 SMBINTF_HWCMD);
2516
2517         val = jread32(jme, JME_SMBINTF);
2518         to = JME_SMB_BUSY_TIMEOUT;
2519         while ((val & SMBINTF_HWCMD) && --to) {
2520                 msleep(1);
2521                 val = jread32(jme, JME_SMBINTF);
2522         }
2523         if (!to) {
2524                 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n");
2525                 return 0xFF;
2526         }
2527
2528         return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2529 }
2530
2531 static void
2532 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2533 {
2534         u32 val;
2535         int to;
2536
2537         val = jread32(jme, JME_SMBCSR);
2538         to = JME_SMB_BUSY_TIMEOUT;
2539         while ((val & SMBCSR_BUSY) && --to) {
2540                 msleep(1);
2541                 val = jread32(jme, JME_SMBCSR);
2542         }
2543         if (!to) {
2544                 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n");
2545                 return;
2546         }
2547
2548         jwrite32(jme, JME_SMBINTF,
2549                 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2550                 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2551                 SMBINTF_HWRWN_WRITE |
2552                 SMBINTF_HWCMD);
2553
2554         val = jread32(jme, JME_SMBINTF);
2555         to = JME_SMB_BUSY_TIMEOUT;
2556         while ((val & SMBINTF_HWCMD) && --to) {
2557                 msleep(1);
2558                 val = jread32(jme, JME_SMBINTF);
2559         }
2560         if (!to) {
2561                 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n");
2562                 return;
2563         }
2564
2565         mdelay(2);
2566 }
2567
2568 static int
2569 jme_get_eeprom_len(struct net_device *netdev)
2570 {
2571         struct jme_adapter *jme = netdev_priv(netdev);
2572         u32 val;
2573         val = jread32(jme, JME_SMBCSR);
2574         return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2575 }
2576
2577 static int
2578 jme_get_eeprom(struct net_device *netdev,
2579                 struct ethtool_eeprom *eeprom, u8 *data)
2580 {
2581         struct jme_adapter *jme = netdev_priv(netdev);
2582         int i, offset = eeprom->offset, len = eeprom->len;
2583
2584         /*
2585          * ethtool will check the boundary for us
2586          */
2587         eeprom->magic = JME_EEPROM_MAGIC;
2588         for (i = 0 ; i < len ; ++i)
2589                 data[i] = jme_smb_read(jme, i + offset);
2590
2591         return 0;
2592 }
2593
2594 static int
2595 jme_set_eeprom(struct net_device *netdev,
2596                 struct ethtool_eeprom *eeprom, u8 *data)
2597 {
2598         struct jme_adapter *jme = netdev_priv(netdev);
2599         int i, offset = eeprom->offset, len = eeprom->len;
2600
2601         if (eeprom->magic != JME_EEPROM_MAGIC)
2602                 return -EINVAL;
2603
2604         /*
2605          * ethtool will check the boundary for us
2606          */
2607         for (i = 0 ; i < len ; ++i)
2608                 jme_smb_write(jme, i + offset, data[i]);
2609
2610         return 0;
2611 }
2612
2613 static const struct ethtool_ops jme_ethtool_ops = {
2614         .get_drvinfo            = jme_get_drvinfo,
2615         .get_regs_len           = jme_get_regs_len,
2616         .get_regs               = jme_get_regs,
2617         .get_coalesce           = jme_get_coalesce,
2618         .set_coalesce           = jme_set_coalesce,
2619         .get_pauseparam         = jme_get_pauseparam,
2620         .set_pauseparam         = jme_set_pauseparam,
2621         .get_wol                = jme_get_wol,
2622         .set_wol                = jme_set_wol,
2623         .get_settings           = jme_get_settings,
2624         .set_settings           = jme_set_settings,
2625         .get_link               = jme_get_link,
2626         .get_msglevel           = jme_get_msglevel,
2627         .set_msglevel           = jme_set_msglevel,
2628         .get_rx_csum            = jme_get_rx_csum,
2629         .set_rx_csum            = jme_set_rx_csum,
2630         .set_tx_csum            = jme_set_tx_csum,
2631         .set_tso                = jme_set_tso,
2632         .set_sg                 = ethtool_op_set_sg,
2633         .nway_reset             = jme_nway_reset,
2634         .get_eeprom_len         = jme_get_eeprom_len,
2635         .get_eeprom             = jme_get_eeprom,
2636         .set_eeprom             = jme_set_eeprom,
2637 };
2638
2639 static int
2640 jme_pci_dma64(struct pci_dev *pdev)
2641 {
2642         if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2643             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
2644                 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2645                         return 1;
2646
2647         if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2648             !pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
2649                 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2650                         return 1;
2651
2652         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2653                 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2654                         return 0;
2655
2656         return -1;
2657 }
2658
2659 static inline void
2660 jme_phy_init(struct jme_adapter *jme)
2661 {
2662         u16 reg26;
2663
2664         reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2665         jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2666 }
2667
2668 static inline void
2669 jme_check_hw_ver(struct jme_adapter *jme)
2670 {
2671         u32 chipmode;
2672
2673         chipmode = jread32(jme, JME_CHIPMODE);
2674
2675         jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2676         jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2677 }
2678
2679 static const struct net_device_ops jme_netdev_ops = {
2680         .ndo_open               = jme_open,
2681         .ndo_stop               = jme_close,
2682         .ndo_validate_addr      = eth_validate_addr,
2683         .ndo_start_xmit         = jme_start_xmit,
2684         .ndo_set_mac_address    = jme_set_macaddr,
2685         .ndo_set_multicast_list = jme_set_multi,
2686         .ndo_change_mtu         = jme_change_mtu,
2687         .ndo_tx_timeout         = jme_tx_timeout,
2688         .ndo_vlan_rx_register   = jme_vlan_rx_register,
2689 };
2690
2691 static int __devinit
2692 jme_init_one(struct pci_dev *pdev,
2693              const struct pci_device_id *ent)
2694 {
2695         int rc = 0, using_dac, i;
2696         struct net_device *netdev;
2697         struct jme_adapter *jme;
2698         u16 bmcr, bmsr;
2699         u32 apmc;
2700
2701         /*
2702          * set up PCI device basics
2703          */
2704         rc = pci_enable_device(pdev);
2705         if (rc) {
2706                 jeprintk(pdev, "Cannot enable PCI device.\n");
2707                 goto err_out;
2708         }
2709
2710         using_dac = jme_pci_dma64(pdev);
2711         if (using_dac < 0) {
2712                 jeprintk(pdev, "Cannot set PCI DMA Mask.\n");
2713                 rc = -EIO;
2714                 goto err_out_disable_pdev;
2715         }
2716
2717         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2718                 jeprintk(pdev, "No PCI resource region found.\n");
2719                 rc = -ENOMEM;
2720                 goto err_out_disable_pdev;
2721         }
2722
2723         rc = pci_request_regions(pdev, DRV_NAME);
2724         if (rc) {
2725                 jeprintk(pdev, "Cannot obtain PCI resource region.\n");
2726                 goto err_out_disable_pdev;
2727         }
2728
2729         pci_set_master(pdev);
2730
2731         /*
2732          * alloc and init net device
2733          */
2734         netdev = alloc_etherdev(sizeof(*jme));
2735         if (!netdev) {
2736                 jeprintk(pdev, "Cannot allocate netdev structure.\n");
2737                 rc = -ENOMEM;
2738                 goto err_out_release_regions;
2739         }
2740         netdev->netdev_ops = &jme_netdev_ops;
2741         netdev->ethtool_ops             = &jme_ethtool_ops;
2742         netdev->watchdog_timeo          = TX_TIMEOUT;
2743         netdev->features                =       NETIF_F_HW_CSUM |
2744                                                 NETIF_F_SG |
2745                                                 NETIF_F_TSO |
2746                                                 NETIF_F_TSO6 |
2747                                                 NETIF_F_HW_VLAN_TX |
2748                                                 NETIF_F_HW_VLAN_RX;
2749         if (using_dac)
2750                 netdev->features        |=      NETIF_F_HIGHDMA;
2751
2752         SET_NETDEV_DEV(netdev, &pdev->dev);
2753         pci_set_drvdata(pdev, netdev);
2754
2755         /*
2756          * init adapter info
2757          */
2758         jme = netdev_priv(netdev);
2759         jme->pdev = pdev;
2760         jme->dev = netdev;
2761         jme->jme_rx = netif_rx;
2762         jme->jme_vlan_rx = vlan_hwaccel_rx;
2763         jme->old_mtu = netdev->mtu = 1500;
2764         jme->phylink = 0;
2765         jme->tx_ring_size = 1 << 10;
2766         jme->tx_ring_mask = jme->tx_ring_size - 1;
2767         jme->tx_wake_threshold = 1 << 9;
2768         jme->rx_ring_size = 1 << 9;
2769         jme->rx_ring_mask = jme->rx_ring_size - 1;
2770         jme->msg_enable = JME_DEF_MSG_ENABLE;
2771         jme->regs = ioremap(pci_resource_start(pdev, 0),
2772                              pci_resource_len(pdev, 0));
2773         if (!(jme->regs)) {
2774                 jeprintk(pdev, "Mapping PCI resource region error.\n");
2775                 rc = -ENOMEM;
2776                 goto err_out_free_netdev;
2777         }
2778
2779         if (no_pseudohp) {
2780                 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2781                 jwrite32(jme, JME_APMC, apmc);
2782         } else if (force_pseudohp) {
2783                 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2784                 jwrite32(jme, JME_APMC, apmc);
2785         }
2786
2787         NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
2788
2789         spin_lock_init(&jme->phy_lock);
2790         spin_lock_init(&jme->macaddr_lock);
2791         spin_lock_init(&jme->rxmcs_lock);
2792
2793         atomic_set(&jme->link_changing, 1);
2794         atomic_set(&jme->rx_cleaning, 1);
2795         atomic_set(&jme->tx_cleaning, 1);
2796         atomic_set(&jme->rx_empty, 1);
2797
2798         tasklet_init(&jme->pcc_task,
2799                      jme_pcc_tasklet,
2800                      (unsigned long) jme);
2801         tasklet_init(&jme->linkch_task,
2802                      jme_link_change_tasklet,
2803                      (unsigned long) jme);
2804         tasklet_init(&jme->txclean_task,
2805                      jme_tx_clean_tasklet,
2806                      (unsigned long) jme);
2807         tasklet_init(&jme->rxclean_task,
2808                      jme_rx_clean_tasklet,
2809                      (unsigned long) jme);
2810         tasklet_init(&jme->rxempty_task,
2811                      jme_rx_empty_tasklet,
2812                      (unsigned long) jme);
2813         tasklet_disable_nosync(&jme->linkch_task);
2814         tasklet_disable_nosync(&jme->txclean_task);
2815         tasklet_disable_nosync(&jme->rxclean_task);
2816         tasklet_disable_nosync(&jme->rxempty_task);
2817         jme->dpi.cur = PCC_P1;
2818
2819         jme->reg_ghc = 0;
2820         jme->reg_rxcs = RXCS_DEFAULT;
2821         jme->reg_rxmcs = RXMCS_DEFAULT;
2822         jme->reg_txpfc = 0;
2823         jme->reg_pmcs = PMCS_MFEN;
2824         set_bit(JME_FLAG_TXCSUM, &jme->flags);
2825         set_bit(JME_FLAG_TSO, &jme->flags);
2826
2827         /*
2828          * Get Max Read Req Size from PCI Config Space
2829          */
2830         pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
2831         jme->mrrs &= PCI_DCSR_MRRS_MASK;
2832         switch (jme->mrrs) {
2833         case MRRS_128B:
2834                 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2835                 break;
2836         case MRRS_256B:
2837                 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2838                 break;
2839         default:
2840                 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2841                 break;
2842         };
2843
2844         /*
2845          * Must check before reset_mac_processor
2846          */
2847         jme_check_hw_ver(jme);
2848         jme->mii_if.dev = netdev;
2849         if (jme->fpgaver) {
2850                 jme->mii_if.phy_id = 0;
2851                 for (i = 1 ; i < 32 ; ++i) {
2852                         bmcr = jme_mdio_read(netdev, i, MII_BMCR);
2853                         bmsr = jme_mdio_read(netdev, i, MII_BMSR);
2854                         if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
2855                                 jme->mii_if.phy_id = i;
2856                                 break;
2857                         }
2858                 }
2859
2860                 if (!jme->mii_if.phy_id) {
2861                         rc = -EIO;
2862                         jeprintk(pdev, "Can not find phy_id.\n");
2863                          goto err_out_unmap;
2864                 }
2865
2866                 jme->reg_ghc |= GHC_LINK_POLL;
2867         } else {
2868                 jme->mii_if.phy_id = 1;
2869         }
2870         if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
2871                 jme->mii_if.supports_gmii = true;
2872         else
2873                 jme->mii_if.supports_gmii = false;
2874         jme->mii_if.mdio_read = jme_mdio_read;
2875         jme->mii_if.mdio_write = jme_mdio_write;
2876
2877         jme_clear_pm(jme);
2878         jme_set_phyfifoa(jme);
2879         pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev);
2880         if (!jme->fpgaver)
2881                 jme_phy_init(jme);
2882         jme_phy_off(jme);
2883
2884         /*
2885          * Reset MAC processor and reload EEPROM for MAC Address
2886          */
2887         jme_reset_mac_processor(jme);
2888         rc = jme_reload_eeprom(jme);
2889         if (rc) {
2890                 jeprintk(pdev,
2891                         "Reload eeprom for reading MAC Address error.\n");
2892                 goto err_out_unmap;
2893         }
2894         jme_load_macaddr(netdev);
2895
2896         /*
2897          * Tell stack that we are not ready to work until open()
2898          */
2899         netif_carrier_off(netdev);
2900         netif_stop_queue(netdev);
2901
2902         /*
2903          * Register netdev
2904          */
2905         rc = register_netdev(netdev);
2906         if (rc) {
2907                 jeprintk(pdev, "Cannot register net device.\n");
2908                 goto err_out_unmap;
2909         }
2910
2911         netif_info(jme, probe, jme->dev, "%s%s ver:%x rev:%x macaddr:%pM\n",
2912                    (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
2913                    "JMC250 Gigabit Ethernet" :
2914                    (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
2915                    "JMC260 Fast Ethernet" : "Unknown",
2916                    (jme->fpgaver != 0) ? " (FPGA)" : "",
2917                    (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
2918                    jme->rev, netdev->dev_addr);
2919
2920         return 0;
2921
2922 err_out_unmap:
2923         iounmap(jme->regs);
2924 err_out_free_netdev:
2925         pci_set_drvdata(pdev, NULL);
2926         free_netdev(netdev);
2927 err_out_release_regions:
2928         pci_release_regions(pdev);
2929 err_out_disable_pdev:
2930         pci_disable_device(pdev);
2931 err_out:
2932         return rc;
2933 }
2934
2935 static void __devexit
2936 jme_remove_one(struct pci_dev *pdev)
2937 {
2938         struct net_device *netdev = pci_get_drvdata(pdev);
2939         struct jme_adapter *jme = netdev_priv(netdev);
2940
2941         unregister_netdev(netdev);
2942         iounmap(jme->regs);
2943         pci_set_drvdata(pdev, NULL);
2944         free_netdev(netdev);
2945         pci_release_regions(pdev);
2946         pci_disable_device(pdev);
2947
2948 }
2949
2950 #ifdef CONFIG_PM
2951 static int
2952 jme_suspend(struct pci_dev *pdev, pm_message_t state)
2953 {
2954         struct net_device *netdev = pci_get_drvdata(pdev);
2955         struct jme_adapter *jme = netdev_priv(netdev);
2956
2957         atomic_dec(&jme->link_changing);
2958
2959         netif_device_detach(netdev);
2960         netif_stop_queue(netdev);
2961         jme_stop_irq(jme);
2962
2963         tasklet_disable(&jme->txclean_task);
2964         tasklet_disable(&jme->rxclean_task);
2965         tasklet_disable(&jme->rxempty_task);
2966
2967         if (netif_carrier_ok(netdev)) {
2968                 if (test_bit(JME_FLAG_POLL, &jme->flags))
2969                         jme_polling_mode(jme);
2970
2971                 jme_stop_pcc_timer(jme);
2972                 jme_reset_ghc_speed(jme);
2973                 jme_disable_rx_engine(jme);
2974                 jme_disable_tx_engine(jme);
2975                 jme_reset_mac_processor(jme);
2976                 jme_free_rx_resources(jme);
2977                 jme_free_tx_resources(jme);
2978                 netif_carrier_off(netdev);
2979                 jme->phylink = 0;
2980         }
2981
2982         tasklet_enable(&jme->txclean_task);
2983         tasklet_hi_enable(&jme->rxclean_task);
2984         tasklet_hi_enable(&jme->rxempty_task);
2985
2986         pci_save_state(pdev);
2987         if (jme->reg_pmcs) {
2988                 jme_set_100m_half(jme);
2989
2990                 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2991                         jme_wait_link(jme);
2992
2993                 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2994
2995                 pci_enable_wake(pdev, PCI_D3cold, true);
2996         } else {
2997                 jme_phy_off(jme);
2998         }
2999         pci_set_power_state(pdev, PCI_D3cold);
3000
3001         return 0;
3002 }
3003
3004 static int
3005 jme_resume(struct pci_dev *pdev)
3006 {
3007         struct net_device *netdev = pci_get_drvdata(pdev);
3008         struct jme_adapter *jme = netdev_priv(netdev);
3009
3010         jme_clear_pm(jme);
3011         pci_restore_state(pdev);
3012
3013         if (test_bit(JME_FLAG_SSET, &jme->flags))
3014                 jme_set_settings(netdev, &jme->old_ecmd);
3015         else
3016                 jme_reset_phy_processor(jme);
3017
3018         jme_start_irq(jme);
3019         netif_device_attach(netdev);
3020
3021         atomic_inc(&jme->link_changing);
3022
3023         jme_reset_link(jme);
3024
3025         return 0;
3026 }
3027 #endif
3028
3029 static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3030         { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3031         { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3032         { }
3033 };
3034
3035 static struct pci_driver jme_driver = {
3036         .name           = DRV_NAME,
3037         .id_table       = jme_pci_tbl,
3038         .probe          = jme_init_one,
3039         .remove         = __devexit_p(jme_remove_one),
3040 #ifdef CONFIG_PM
3041         .suspend        = jme_suspend,
3042         .resume         = jme_resume,
3043 #endif /* CONFIG_PM */
3044 };
3045
3046 static int __init
3047 jme_init_module(void)
3048 {
3049         printk(KERN_INFO PFX "JMicron JMC2XX ethernet "
3050                "driver version %s\n", DRV_VERSION);
3051         return pci_register_driver(&jme_driver);
3052 }
3053
3054 static void __exit
3055 jme_cleanup_module(void)
3056 {
3057         pci_unregister_driver(&jme_driver);
3058 }
3059
3060 module_init(jme_init_module);
3061 module_exit(jme_cleanup_module);
3062
3063 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3064 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3065 MODULE_LICENSE("GPL");
3066 MODULE_VERSION(DRV_VERSION);
3067 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3068